MSC1201
SBAS317 – APRIL 2004
www.ti.com
Copyright © 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Precision Analog-to-Digital Converter (ADC)
and Digital-to-Analog Converter (DAC)
with 8051 Microcontroller and Flash Memory
FEATURES
ANALOG FEATURES
●24-BITS NO MISSING CODES
●22-BITS EFFECTIVE RESOLUTION AT 10Hz
Low Noise: 75nV
●PGA FROM 1 TO 128
●PRECISION ON-CHIP VOLTAGE REFERENCE
●6 DIFFERENTIAL/SINGLE-ENDED CHANNELS
●ON-CHIP OFFSET/GAIN CALIBRATION
●OFFSET DRIFT: 0.02ppm/°C
●GAIN DRIFT: 0.5ppm/°C
●ON-CHIP TEMPERATURE SENSOR
●SELECTABLE BUFFER INPUT
●BURNOUT DETECT
●8-BIT CURRENT DAC
DIGITAL FEATURES
Microcontroller Core
●8051-COMPATIBLE
●HIGH-SPEED CORE:
4 Clocks per Instruction Cycle
●DC TO 33MHz
●ON-CHIP OSCILLATOR
●PLL WITH 32kHz CAPABILITY
●SINGLE INSTRUCTION 121ns
●DUAL DATA POINTER
Memory
●4kB OR 8kB OF FLASH MEMORY
●FLASH MEMORY PARTITIONING
●ENDURANCE 1M ERASE/WRITE CYCLES,
100 YEAR DATA RETENTION
●128 BYTES DATA SRAM
●IN-SYSTEM SERIALLY PROGRAMMABLE
●FLASH MEMORY SECURITY
●1kB BOOT ROM
Peripheral Features
●16 DIGITAL I/O PINS
●ADDITIONAL 32-BIT ACCUMULATOR
●TWO 16-BIT TIMER/COUNTERS
●SYSTEM TIMERS
●PROGRAMMABLE WATCHDOG TIMER
●FULL DUPLEX UART
●BASIC SPI™
●BASIC I2C™
●POWER MANAGEMENT CONTROL
●INTERNAL CLOCK DIVIDER
●IDLE MODE CURRENT < 200µA
●STOP MODE CURRENT < 100nA
●DIGITAL BROWNOUT RESET
●ANALOG LOW VOLTAGE DETECT
●20 INTERRUPT SOURCES
GENERAL FEATURES
●PACKAGE: QFN-36
●LOW POWER: 3mW
●INDUSTRIAL TEMPERATURE RANGE:
–40°C to +85°C
●POWER SUPPLY: 2.7V to 5.25V
APPLICATIONS
●INDUSTRIAL PROCESS CONTROL
●INSTRUMENTATION
●LIQUID/GAS CHROMATOGRAPHY
●BLOOD ANALYSIS
●SMART TRANSMITTERS
●PORTABLE INSTRUMENTS
●WEIGH SCALES
●PRESSURE TRANSDUCERS
●INTELLIGENT SENSORS
●PORTABLE APPLICATIONS
●DAS SYSTEMS
MSC1201
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PRODUCT PREVIEW
MSC1201
2SBAS317
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PRODUCT PREVIEW
PACKAGE/ORDERING INFORMATION
SPECIFIED
FLASH PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT MEMORY PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY
MSC1201Y2 4k QFN-36 RHH –40°C to +85°C MSC1201Y2 MSC1201Y2RHHT Tape and Reel, TBD
MSC1201Y2 4k "" " "MSC1201Y2RHHR Tape and Reel, TBD
MSC1201Y3 8k QFN-36 RHH –40°C to +85°C MSC1201Y3 MSC1201Y3RHHT Tape and Reel, TBD
MSC1201Y3 8k "" " "MSC1201Y3RHHR Tape and Reel, TBD
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com/msc.
ABSOLUTE MAXIMUM RATINGS(1)
Analog Inputs
Input Current ............................................................ 100mA, Momentary
Input Current ..............................................................10mA, Continuous
Input Voltage.............................................AGND – 0.5V to AVDD + 0.5V
Power Supply
DVDD to DGND......................................................................–0.3V to 6V
AVDD to AGND ......................................................................–0.3V to 6V
AGND to DGND .............................................................. –0.3V to +0.3V
VREF to AGND ....................................................... –0.3V to AVDD + 0.3V
Digital Input Voltage to DGND ..............................–0.3V to DVDD + 0.3V
Digital Output Voltage to DGND ...........................–0.3V to DVDD + 0.3V
Maximum Junction Temperature ................................................ +150°C
Operating Temperature Range ...................................... –40°C to +85°C
Storage Temperature Range ....................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................ +300°C
Package Power Dissipation ...................................................... 2038mW
Output Current All Pins ................................................................ 200mA
Output Pin Short Circuit .....................................................................10s
Thermal Resistance, Junction-to-Ambient
(
θ
JA)....................... 31.9°C/W
Thermal Resistance, Junction-to-Case (
θ
JC) ............................. 0.9°C/W
Digital Outputs
Output Current .........................................................100mA, Continuous
I/O Source/Sink Current............................................................... 100mA
Power Pin Maximum .................................................................... 300mA
NOTE: (1) Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute-maximum-
rated conditions for extended periods may affect device reliability.
FEATURES(1) MSC1201Y2(2) MSC1201Y3(2)
Flash Program Memory (Bytes) Up to 4k Up to 8k
Flash Data Memory (Bytes) Up to 2k Up to 4k
Internal Scratchpad RAM (Bytes) 128 128
NOTES: (1) All peripheral features are the same on all devices; the flash
memory size is the only difference. (2) The last digit of the part number (N)
represents the onboard flash size = (2N)kBytes.
MSC1201Yx FAMILY FEATURES
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V,
unless otherwise noted.
MSC1201Yx
PARAMETER CONDITION MIN TYP MAX UNITS
ANALOG INPUT (AIN0-AIN5, AINCOM)
Analog Input Range Buffer OFF AGND – 0.1 AVDD + 0.1 V
Buffer ON AGND + 50mV A VDD – 1.5 V
Full-Scale Input Voltage Range (In+) – (In–)±VREF/PGA V
Differential Input Impedance Buffer OFF 7/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • fDATA
Sinc2 Filter –3dB 0.318 • fDATA
Sinc3 Filter –3dB 0.262 • fDATA
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance Buffer ON 7 pF
Input Leakage Current Multiplexer Channel Off, T = +25°C 0.5 pA
Burnout Current Sources Buffer ON ±2µA
ADC OFFSET DAC
Offset DAC Range
±V
REF
/(2 • PGA)
V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±1.0 % of Range
Offset DAC Gain Error Drift 0.6 ppm/°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
MSC1201 3
SBAS317 www.ti.com
PRODUCT PREVIEW
SYSTEM PERFORMANCE
Resolution 24 Bits
ENOB 22 Bits
Output Noise See Typical Characteristics
No Missing Codes Sinc3 Filter 24 Bits
Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 %FSR
Offset Error After Calibration 1.5 ppm of FS
Offset Drift(1) Before Calibration 0.02 ppm of FS/°C
Gain Error(2) After Calibration 0.005 %
Gain Error Drift(1) Before Calibration 0.5 ppm/°C
System Gain Calibration Range 80 120 % of FS
System Offset Calibration Range –50 50 % of FS
Common-Mode Rejection At DC 100 120 dB
fCM = 60Hz, fDATA = 10Hz 130 dB
fCM = 50Hz, fDATA = 50Hz 120 dB
fCM = 60Hz, fDATA = 60Hz 120 dB
Normal Mode Rejection fSIG = 50Hz, fDATA = 50Hz 100 dB
fSIG = 60Hz, fDATA = 60Hz 100 dB
Power-Supply Rejection At DC, dB = –20log(∆VOUT/∆VDD)(3) 100 dB
VOLTAGE REFERENCE INPUTS
Reference Input Range REF IN+, REF IN–AGND AVDD(2) V
VREF VREF ≡ (REF IN+) – (REF IN–) 0.3 2.5 AVDD V
Common-Mode Rejection At DC 115 dB
Input Current VREF = 2.5V, PGA = 1 1 µA
ON-CHIP VOLTAGE REFERENCE
Output Voltage VREFH = 1 at +25°C 2.5 V
VREFH = 0 1.25 V
Short-Circuit Current Source 9mA
Short-Circuit Current Sink 10 mA
Short-Circuit Duration Sink or Source Indefinite
Startup Time from Power ON 0.4 ms
Temperature Sensor
Temperature Sensor Voltage T = +25°C115mV
Temperature Sensor Coefficient 375 µV/°C
IDAC OUTPUT CHARACTERISTICS
Full-Scale Output Current 1mA
Maximum Short-Circuit Current Duration Indefinite
Compliance Voltage AVDD – 1.5 V
ANALOG POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AVDD 4.75 5.0 5.25 V
Analog Current Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 < 1 nA
ADC Current IADC PGA = 1, Buffer OFF 170 µA
PGA = 128, Buffer OFF 430 µA
PGA = 1, Buffer ON 230 µA
PGA = 128, Buffer ON 770 µA
VREF Supply Current IVREF ADC ON 360 µA
IDAC Supply Current IIDAC IDAC = 00H230 µA
NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD – 1.5V with buffer ON. To calibrate gain,
turn buffer off. (3) DVOUT is change in digital result.
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V,
unless otherwise noted.
MSC1201Yx
PARAMETER CONDITION MIN TYP MAX UNITS
MSC1201
4SBAS317
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PRODUCT PREVIEW
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications from T
MIN
to T
MAX
, AV
DD
= +3V, DV
DD
= +2.7V to 5.25V, f
MOD
= 15.625kHz, PGA = 1, Buffer ON, f
DATA
= 10Hz, Bipolar, and V
REF
≡ (REF IN+) – (REF IN–) = +1.25V,
unless otherwise no ted.
MSC1201Yx
PARAMETER CONDITION MIN TYP MAX UNITS
ANALOG INPUT (AIN0-AIN5, AINCOM)
Analog Input Range Buffer OFF AGND – 0.1 AVDD + 0.1 V
Buffer ON AGND + 50mV A VDD – 1.5 V
Full-Scale Input Voltage Range (In+) – (In–)±VREF/PGA V
Differential Input Impedance Buffer OFF 7/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • fDATA
Sinc2 Filter –3dB 0.318 • fDATA
Sinc3 Filter –3dB 0.262 • fDATA
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance Buffer On 7 pF
Input Leakage Current Multiplexer Channel Off, T = +25°C 0.5 pA
Burnout Current Sources Buffer ON ±2µA
ADC OFFSET DAC
Offset DAC Range
±V
REF
/(2 • PGA)
V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±1.5 % of Range
Offset DAC Gain Error Drift 0.6 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
ENOB 22 Bits
Output Noise See Typical Characteristics
No Missing Codes Sinc3 Filter 24 Bits
Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 %FSR
Offset Error After Calibration 1.3 ppm of FS
Offset Drift(1) Before Calibration 0.02 ppm of FS/°C
Gain Error(2) After Calibration 0.005 %
Gain Error Drift(1) Before Calibration 0.5 ppm/°C
System Gain Calibration Range 80 120 % of FS
System Offset Calibration Range –50 50 % of FS
Common-Mode Rejection At DC 100 130 dB
fCM = 60Hz, fDATA = 10Hz 130 dB
fCM = 50Hz, fDATA = 50Hz 120 dB
fCM = 60Hz, fDATA = 60Hz 120 dB
Normal Mode Rejection fSIG = 50Hz, fDATA = 50Hz 100 dB
fSIG = 60Hz, fDATA = 60Hz 100 dB
Power-Supply Rejection At DC, dB = –20log(DVOUT/DVDD)(3) 88 dB
VOLTAGE REFERENCE INPUTS
Reference Input Range REF IN+, REF IN–AGND AVDD(2) V
VREF VREF ≡ (REF IN+) – (REF IN–) 0.3 1.25 AVDD V
Common-Mode Rejection At DC 110 dB
Input Current VREF = 1.25V, PGA = 1 0.5 µA
ON-CHIP VOLTAGE REFERENCE
Output Voltage VREFH = 0 at +25°C 1.25 V
Short-Circuit Current Source 4mA
Short-Circuit Current Sink 5µA
Short-Circuit Duration Sink or Source Indefinite
Startup Time from Power ON 0.2 ms
Temperature Sensor
Temperature Sensor Voltage T = +25°C 115 mV
Temperature Sensor Coefficient 375 µV/°C
IDAC OUTPUT CHARACTERISTICS
Full-Scale Output Current 1mA
Maximum Short-Circuit Current Duration Indefinite
Compliance Voltage AVDD – 1.5 V
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage AVDD 2.7 3.0 3.6 V
Analog Current Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 < 1 n A
ADC Current IADC PGA = 1, Buffer OFF 150 µA
PGA = 128, Buffer OFF 380 µA
PGA = 1, Buffer ON 200 µA
PGA = 128, Buffer ON 610 µA
VREF Supply Current IVREF ADC ON 330 µA
IDAC Supply Current IIDAC IDAC = 00H220 µA
NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD – 1.5V with buffer ON. To calibrate gain,
turn buffer off. (3) DVOUT is change in digital result.
MSC1201 5
SBAS317 www.ti.com
PRODUCT PREVIEW
DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V
All specifications from TMIN to TMAX, unless otherwise specified.
MSC1201Yx
PARAMETER CONDITION MIN TYP MAX UNITS
POWER-SUPPLY REQUIREMENTS
Digital Supply Current DVDD 2.7 3.0 3.6 V
Normal Mode, fOSC = 1MHz 0.6 mA
Normal Mode, fOSC = 8MHz, All Peripherals ON 5 mA
Internal Oscillator LF Mode (12.8MHz nominal) 7.1 mA
Stop Mode, DBOR OFF 100 nA
DVDD 4.75 5.0 5.25 V
Normal Mode, fOSC = 1MHz 1.2 mA
Normal Mode, fOSC = 8MHz, All Peripherals ON 9 mA
Internal Oscillator LF Mode (12.8MHz nominal) 15 mA
Internal Oscillator HF Mode (25.6MHz nominal) 29 mA
Stop Mode, DBOR OFF 100 nA
DIGITAL INPUT/OUTPUT (CMOS)
Logic Level: VIH (except XIN pin) 0.6 • DVDD DVDD V
VIL (except XIN pin) DGND 0.2 • DVDD V
Ports 1 and 3, Input Leakage Current, Input Mode VIH = DVDD or VIH = 0V 0 µA
Pin XIN Input Leakage Current 0µA
I/O Pin Hysteresis 700 mV
VOL, Ports 1 and 3, All Output Modes IOL = 1mA DGND 0.4 V
VOL, Ports 1 and 3, All Output Modes IOL = 30mA, 3V (20mA) 1.5 V
VOH, Ports 1 and 3, Strong Drive Output IOH = 1mA DVDD – 0.4 DVDD – 0.1 DVDD V
VOH, Ports 1 and 3, Strong Drive Output IOH = 30mA, 3V (20mA) DVDD – 1.5 V
Ports 1 and 3 Pull-Up Resistors 11 kΩ
FLASH MEMORY CHARACTERISTICS: DVDD = 2.7V to 5.25V
tUSEC = 1µs, tMSEC = 1ms
MSC1201Yx
PARAMETER CONDITION MIN TYP MAX UNITS
Flash Memory Endurance 100,000 1,000,000 cycles
Flash Memory Data Retention 100 Years
Mass and Page Erase Time Set with FER Value in FTCON 10 ms
Flash Memory Write Time Set with FWR Value in FTCON 30 40 µs
MSC1201
6SBAS317
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PRODUCT PREVIEW
2.7V to 3.6V 4.75V to 5.25V
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNITS
External Clock Mode
fOSC(1) A External Crystal Frequency (fOSC)120133MHz
1/tOSC(1) A External Clock Frequency (fOSC)020033MHz
fOSC(1) A External Ceramic Resonator Frequency (fOSC)1 12 1 12 MHz
tHIGH A HIGH Time(2) 15 10 ns
tLOW A LOW Time(2) 15 10 ns
tRA Rise Time(2) 55ns
tFA Fall Time(2) 55ns
NOTES: (1) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1. (2) These values are characterized but not 100% production tested.
AC ELECTRICAL CHARACTERISTICS(1): DVDD = 2.7V to 5.25V
FIGURE A. External Clock Drive CLK.
FIGURE B. Serial Flash Programming Power-On Timing.
SYMBOL FIGURE PARAMETER MIN MAX UNIT
tRW B RST width 2 tOSC —ns
tRRD B RST rise to P1.0 internal pull high —5µs
tRFD B RST falling to CPU start —18 ms
tRS B Input signal to RST falling setup time tOSC —ns
tRH B RST falling to P1.0 hold time 18 —ms
NOTE: P1.0 is internally pulled-up with ~11kΩ during RST high.
P1.0/PROG
RST
t
RFD
, t
RH
t
RS
t
RRD
t
RW
tR
tHIGH
VIH VIH
0.8V 0.8V VIH VIH
0.8V 0.8V
tLOW
tOSC
tF
MSC1201Yx
PARAMETER CONDITION MIN TYP MAX UNITS
PHASE LOCK LOOP (PLL)
Input Frequency Range External Crystal/Clock Frequency (fOSC) 32.768 kHz
PLL LF Mode PLLDIV = 449 (default) 14.7456 MHz
PLL HF Mode PLLDIV = 899 (must be set by user) 29.4912 MHz
PLL Lock Time Within 1% 2 ms
INTERNAL OSCILLATOR (IO) See Typical Characteristics
IO LF Mode 12.8 MHz
IO HF Mode 25.6 MHz
Internal Oscillator Settling Time Within 1% 1 ms
NOTE: (1) Parameters are valid over operating temperature range, unless otherwise specified.
EXTERNAL CLOCK DRIVE CLK TIMING
SERIAL FLASH PROGRAMMING TIMING
MSC1201 7
SBAS317 www.ti.com
PRODUCT PREVIEW
PIN CONFIGURATION
Top View QFN
P3.7
P3.6/SCK/SCL/CLKS
P3.5/T1
P3.4/T0
P3.3/INT1
P3.2/INT0
P3.1/TxD0
P3.0/RxD0
P1.7/INT5
DV
DD
DGND
P1.6/INT4
P1.5/INT3
P1.4/INT2/SS
P1.3/DIN
P1.2/DOUT
P1.1
P1.0/PROG
IDAC
REFOUT/REFIN+
REFIN–
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
XIN
XOUT
DGND
RST
CAP
AV
DD
AGND
AGND
AINCOM
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
36 35 34 33 32 31 30 29 28
10 11 12 13 14 15 16 17 18
MSC1201
MSC1201
8SBAS317
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PRODUCT PREVIEW
PIN # NAME DESCRIPTION
1 XIN The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators.
XIN can also be an input if there is an external clock source instead of a crystal.
2 XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators.
XOUT serves as the output of the crystal amplifier.
3, 26 DGND Digital Ground
4 RST A HIGH on the reset input for two tOSC periods will reset the device.
5 CAP Capacitor (220pF ceramic)
6AV
DD Analog Power Supply
7, 8 AGND Analog Ground
9 AINCOM Analog Input (can be analog common for single-ended inputs or analog input for differential inputs)
10 IDAC IDAC Output
1 1 REFOUT/REF IN+ Internal Voltage Reference Output/Voltage Reference Positive Input
12 REF IN–Voltage Reference Negative Input (tie to AGND for internal voltage reference)
13 AIN5 Analog Input Channel 5
14 AIN4 Analog Input Channel 4
15 AIN3 Analog Input Channel 3
16 AIN2 Analog Input Channel 2
17 AIN1 Analog Input Channel 1
18 AIN0 Analog Input Channel 0
19-25, 28 P1.0-P1.7 Port 1 is a bidirectional I/O port (refer to P1DDRL, SFR AEH, and P1DDRH, SFR AFH, for port pin configuration control).
Port 1—Alternate Functions:
PIN DESCRIPTIONS
PORT ALTERNATE MODE
P3.0 RxD0 Serial Port 0 Input
P3.1 TxD0 Serial Port 0 Output
P3.2
INT0
External Interrupt 0
P3.3
INT1
External Interrupt 1
P3.4 T0 Timer 0 External Input
P3.5 T1 Timer 1 External Input
P3.6 SCK/SCL/CLKS SCK/SCL/Various Clocks (refer to PASEL, SFR F2H)
P3.7 N/A
PORT ALTERNATE MODE
P1.0
PROG
Serial Programming Mode
P1.1 N/A
P1.2 DOUT Serial Data Out
P1.3 DIN Serial Data In
P1.4 INT2/
SS
External Interrupt 2/Slave Select
P1.5
INT3
External Interrupt 3
P1.6 INT4 External Interrupt 4
P1.7
INT5
External Interrupt 5
27 DVDD Digital Power Supply
29-36 P3.0-P3.7 Port 3 is a bidirectional I/O port (refer to P3DDRL, SFR B3H, and P3DDRH, SFR B4 H, for port pin configuration control).
Port 3—Alternate Functions:
MSC1201 9
SBAS317 www.ti.com
PRODUCT PREVIEW
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
Decimation Ratio = f
MOD
f
DATA
0 500 1000 1500 2000
PGA4
ENOB (rms)
PGA1 PGA2
PGA16
PGA8
PGA32 PGA64 PGA128
Sinc
3
Filter, Buffer OFF
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
0 500 1000 1500 2000
ENOB (rms)
PGA4 PGA8
PGA1
PGA2
PGA16
PGA32 PGA64 PGA128
Decimation Ratio = f
MOD
f
DATA
Sinc
3
Filter, Buffer ON
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
0 500 1000 1500 2000
ENOB (rms)
PGA4 PGA8
PGA1 PGA2
PGA16 PGA32 PGA64 PGA128
Decimation Ratio = f
MOD
f
DATA
AV
DD
= 3V, Sinc
3
Filter,
V
REF
= 1.25V, Buffer OFF
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
0 500 1000 1500 2000
ENOB (rms)
PGA4 PGA8
PGA1
PGA2
PGA16 PGA32 PGA64 PGA128
AV
DD
= 3V, Sinc
3
Filter,
V
REF
= 1.25V, Buffer ON
Decimation Ratio = f
MOD
f
DATA
22
21
20
19
18
17
16
15
14
13
12
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
0 500 1000 1500 2000
ENOB (rms)
PGA4 PGA8
PGA1
PGA2
PGA32 PGA128
PGA16 PGA64
Decimation Ratio = f
MOD
f
DATA
Sinc
2
Filter
EFFECTIVE NUMBER OF BITS vs DATA RATE
23
22
21
20
19
18
17
16
15
14
13
12
11
10
ENOB (rms)
Data Rate (SPS)
1 10 100 1000
Sinc3 Filter, Buffer OFF
PGA1
PGA8
PGA32
PGA64
PGA128
MSC1201
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PRODUCT PREVIEW
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
22
21
20
19
18
17
16
15
14
13
12
FAST SETTLING FILTER
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
0 500 1000 1500 2000
ENOB (rms)
1500
Decimation Ratio = f
MOD
f
DATA
Fast Settling Filter
EFFECTIVE NUMBER OF BITS vs fMOD
(set with ACLK)
25
20
15
10
5
0
ENOB (rms)
Data Rate (SPS)
1 10 100 1k 10k 100k
fMOD = 15.6kHz
fMOD = 62.5kHz
fMOD = 203kHz
fMOD = 110kHz
fMOD = 31.25kHz
EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK)
WITH FIXED DECIMATION
25
20
15
10
5
0
ENOB (rms)
Data Rate (SPS)
10 100 1k 10k 100k
DEC = 2020
DEC = 255
DEC = 500
DEC = 50
DEC = 20
DEC = 10
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
NOISE vs INPUT SIGNAL
V
IN
(V)
–2.5 –1.5 0.5–0.5 1.5 2.5
Noise (rms, ppm of FS)
10
8
6
4
2
0
−2
−4
−6
−8
−10
INTEGRAL NONLINEARITY vs INPUT SIGNAL
V
IN
(V)
−2.5 −2.0 −1.0 −0.5−1.5 0 0.5 1.0 1.5 2.0 2.5
INL (ppm of FS)
–40°C
+25°C
V
REF
= 2.5V
+85°C
15
10
5
0
−5
−10
−15
INTEGRAL NONLINEARITY vs INPUT SIGNAL
V
IN
(V)
V
IN
= −V
REF
0V
IN
= +V
REF
INL (ppm of FS)
V
REF
= AV
DD
= 5V
Buffer OFF
MSC1201 11
SBAS317 www.ti.com
PRODUCT PREVIEW
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
ADC CURRENT vs PGA
PGA Setting
1824 3216 12864
I
ADC
(µA)
AV
DD
= 5V, Buffer = ON
AV
DD
= 5V, Buffer = OFF
AV
DD
= 3V, Buffer = ON
AV
DD
= 3V, Buffer = OFF
4500
4000
3500
3000
2500
2000
1500
1000
500
0
HISTOGRAM OF OUTPUT DATA
ppm of FS
–2
Number of Occurrences
–1.5 –1–0.5 0 0.5 1 1.5 2
30
25
20
15
10
5
0
ADC INTEGRAL NONLINEARITY vs V
REF
V
REF
(V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
INL (ppm of FS)
V
IN
= V
REF
Buffer OFF
AV
DD
= 3V
AV
DD
= 5V
INL ERROR vs PGA
PGA Setting
INL (ppm of FS)
142168 1286432
50
45
40
35
30
25
20
15
10
5
0
AV
DD
= 5V
V
REF
= 2.5V
1.3
1.3
1.2
1.2
1.1
1.1
1.0
1.0
0.9
ANALOG SUPPLY CURRENT
Analog Supply Voltage (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Analog Supply Current (mA)
–40°C
+25°C
+85°C
PGA = 128, ADC = ON
V
REF
= ON, DBOR = ON
ALVD = ON, IDAC = ON
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
OFFSET DAC: OFFSET vs TEMPERATURE
Offset (ppm of FSR)
Temperature (°C)
–40 +25 +85
MSC1201
12 SBAS317
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PRODUCT PREVIEW
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
1.00006
1.00004
1.00002
1
0.99998
0.99996
0.99994
OFFSET DAC: GAIN vs TEMPERATURE
Normalized Gain
Temperature (°C)
–40 +25 +85
DIGITAL SUPPLY CURRENT vs FREQUENCY
Clock Frequency (MHz)
Digital Supply Current (mA)
1 10 100
100
10
1
0.1 DVDD = 5V
DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER
Clock Frequency (MHz)
Digital Supply Current (mA)
1 10 100
100
10
1
0.1
1024
Divider Values
2
1
4
8
16
32
DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE
Supply Voltage (V)
Digital Supply Current (mA)
2.7 3.1 3.5 3.9 4.3 4.7 5.1
10
8
6
4
2
0
–40°C
+85°C
+25°C
CMOS DIGITAL OUTPUT
Output Current (mA)
Output Voltage (V)
02010 4030 706050
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3V
Low
Output
5V
Low
Output
5V
3V
NORMALIZED GAIN vs PGA
PGA Setting
Normalized Gain (%)
142168 1286432
101
100
99
98
97
96
95
Buffer ON
MSC1201 13
SBAS317 www.ti.com
PRODUCT PREVIEW
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
IO LF MODE vs TEMPERATURE
Temperature (°C)
IO Frequency (MHz)
−40 25 85
14
13
12
11
10
2.7V
5.25V
3.3V
4.75V
AVDD = DVDD
IO HF MODE vs FREQUENCY
Temperature (°C)
IO Frequency (MHz)
−40 25 85
28
27
26
25
24
23
4.75V
5.25V
AVDD = DVDD
MSC1201
14 SBAS317
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PRODUCT PREVIEW
The MSC1201Yx allows the user to uniquely configure the
Flash memory map to meet the needs of their application.
The Flash is programmable down to 2.7V using serial pro-
gramming. Flash endurance is typically 1M Erase/Write cycles.
The part has separate analog and digital supplies, which can
be independently powered from 2.7V to +5.25V. At +3V
operation, the power dissipation for the part is typically less
than 3mW. The MSC1201Yx is packaged in a QFN -36 pack-
age.
The MSC1201Yx is designed for high-resolution measurement
applications in smart transmitters, industrial process control,
weigh scales, chromatography, and portable instrumentation.
ENHANCED 8051 CORE
All instructions in the MSC1201 family perform exactly the same
functions as they would in a standard 8051. The effect on bits,
flags, and registers is the same. However, the timing is different.
The MSC1201 family utilizes an efficient 8051 core which results
in an improved instruction execution speed of between 1.5 and
3 times faster than the original core for the same external clock
speed (4 clock cycles per instruction versus 12 clock cycles per
instruction, as shown in Figure 2). This translates into an effective
throughput improvement of more than 2.5 times, using the same
code and same external clock speed. Therefore, a device
frequency of 33MHz for the MSC1201Yx actually performs at an
equivalent execution speed of 82.5MHz compared to the
DESCRIPTION
The MSC1201Yx is a completely integrated family of mixed-
signal devices incorporating a high-resolution delta-sigma
ADC, 8-bit IDAC, 8-channel multiplexer, burnout detect cur-
rent sources, selectable buffered input, offset DAC, program-
mable gain amplifier (PGA), temperature sensor, voltage
reference, 8-bit microcontroller, Flash Program Memory, Flash
Data Memory, and Data SRAM, as shown in Figure 1.
On-chip peripherals include an additional 32-bit accumulator,
basic SPI, basic I2C, UART, multiple digital input/output
ports, watchdog timer, low-voltage detect, on-chip power-on
reset, brownout reset, timer/counters, system clock divider,
PLL, on-chip oscillator, and external interrupts.
The device accepts low-level differential or single-ended
signals directly from a transducer. The ADC provides 24 bits
of resolution and 24 bits of no-missing-code performance
using a Sinc3 filter with a programmable sample rate. The
ADC also has a selectable filter that allows for high-resolu-
tion single-cycle conversion.
The microcontroller core is 8051 instruction set compatible. The
microcontroller core is an optimized 8051 core that executes up
to three times faster than the standard 8051 core, given the
same clock source. This makes it possible to run the device at
a lower external clock frequency and achieve the same perfor-
mance at lower power than the standard 8051 core.
ACC
MUX
AV
DD
BUF PGA
V
REF
Modulator
4K or 8K
FLASH
128 Bytes
SRAM
Digital
Filter
8051
SFR
ALVD
DBOR
System
Clock
Divider
POR
PORT1
WDT
Alternate
Functions
Timers/
Counters
PLL
PORT3
DIN
DOUT
SS
EXT (4)
PROG
UART
EXT (2)
T0
T1
SCK/SCL/CLKS
On-Chip
Oscillator
8-Bit
Offset DAC
8-Bit IDAC
Burnout
Detect
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AINCOM
IDAC
AGND REFOUT/REFIN+ REFIN–DV
DD
DGND
XIN XOUT
Temperature
Sensor
Burnout
Detect
RST
CAP
220pF Ceramic
AGND
AV
DD
FIGURE 1. Block Diagram.
FIGURE 2. Instruction Cycle Timing.
CLK
instr_cycle
cpu_cycle C1 C2 C3 C4 C1 C2 C3 C4 C1
n + 1 n + 2
MSC1201 15
SBAS317 www.ti.com
PRODUCT PREVIEW
FIGURE 3. Comparison of MSC1201 Timing to Standard
8051 Timing.
FIGURE 4. MSC1201 Timing Chain and Clock Control.
ALE
PSEN
Internal
AD0-AD7
Internal
A8-A15
ALE
PSEN
AD0-AD7
PORT 2
CLK
Standard 8051 Timing MSC1201 Timing
Single-Byte, Single-Cycle
Instruction
Single-Byte, Single-Cycle
Instruction
12 Cycles
4 Cycles
standard 8051 core. This allows the user to run the device at
slower clock speeds, which reduces system noise and power
consumption, but provides greater throughput. This performance
difference can be seen in Figure 3. The timing of software loops
will be faster with the MSC1201. However, the timer/counter
operation of the MSC1201 may be maintained at 12 clocks per
increment or optionally run at 4 clocks per increment.
The MSC1201 also provides dual data pointers (DPTRs).
Furthermore, improvements were made to peripheral fea-
tures that off-load processing from the core and the user, to
further improve efficiency. For instance, a 32-bit accumulator
was added to significantly reduce the processing overhead
for the multiple byte data from the ADC or other sources. This
allows for 24-bit addition and shifting to be accomplished in
a few instruction cycles, compared to hundreds of instruction
cycles through software implementation.
Family Device Compatibility
The hardware functionality and pin configuration across the
MSC1201 family is fully compatible. To the user, the only
difference between family members is the memory configuration.
This makes migration between family members simple. Code
written for the MSC1201Y2 can be executed directly on an
MSC1201Y3. This gives the user the ability to add or subtract
software functions and to freely migrate between family mem-
bers. Thus, the MSC1201 can become a standard device used
across several application platforms.
Family Development Tools
The MSC1201 is fully compatible with the standard 8051
instruction set. This means that the user can develop soft-
ware for the MSC1201 with existing 8051 development tools.
Additionally, a complete, integrated development environ-
ment is provided with each demo board, and third-party
developers also provide support.
Power Down Modes
The MSC1201 can power several of the peripherals and put
the CPU into IDLE. This is accomplished by shutting off the
clocks to those sections, as shown in Figure 4.
USEC FB
MSECH
HMSEC FE
MSINT FA
ACLK F6 divide
by 64
MSECL
FD FC ms
µs
100ms
Flash Write
Timing
Flash Erase
Timing
WDTCON
SECINT F9
FF
FTCON
[3:0]
FTCON
[7:4]
EF
EF
seconds
interrupt
watchdog
milliseconds
interrupt
ADC Output Rate
ADCON3 ADCON2
DF DE
Decimation Ratio
SPICON/
I2CCON 9A
C7
SCL/SCK
tCLK
tSYS
(30µs to 40µs)
(5ms to 11ms)
PDCON.0
PDCON.1
Modulator Clock
PDCON.2
PDCON.3
IDLE CPU Clock
Timers 0/1
SYS Clock
Divider
ADC Power Down
UART
MSC1201
16 SBAS317
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PRODUCT PREVIEW
OVERVIEW
The MSC1201 ADC structure is shown in Figure 5. The figure lists the components that make up the ADC, along with the
corresponding special function register (SFR) associated with each component.
FIGURE 5. MSC1201 ADC Structure.
Σ
ΣX
Input
Multiplexer
Temperature
Sensor
Buffer PGA
Sample
and Hold
ADMUXD7
H
REFIN+
REFIN−
REFIN+ f
MOD
REFIN−
ADCON1DD
H
ADCON2DE
H
ADCON3DF
H
OCR GCR ADRES
SUMR
D3
H
D2
H
D1
H
D6
H
D5
H
D4
H
DB
H
DA
H
D9
H
E5
H
E4
H
E3
H
E2
H
Offset
Calibration
Register
ADCON0DC
H
ACLKF6
H
SSCON
E1
H
ODACE6
H
Offset
DAC
∆Σ ADC
Modulator
FAST
SINC2
SINC3
AUTO
ADC
Result Register
Σ
Summation
Block
V
IN
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AINCOM
f
SAMP
f
DATA
Gain
Calibration
Register
Burnout
Detect
AV
DD
In+
AGND
In−
Burnout
Detect
MSC1201 17
SBAS317 www.ti.com
PRODUCT PREVIEW
FIGURE 6. Input Multiplexer Configuration.
FIGURE 7. Analog Input Structure (without buffer).
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differential
inputs to be selected as the input channel, as shown in Figure 6.
If AIN0 is selected as the positive differential input channel, any
other channel can be selected as the negative differential input
channel. With this method, it is possible to have up to six fully
differential input channels. It is also possible to switch the polarity
of the differential input pair to negate any offset voltages.
In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the pins.
TEMPERATURE SENSOR
On-chip diodes provide temperature sensing capability. When
the configuration register for the input MUX is set to all 1s,
the diodes are connected to the input of the ADC. All other
channels are open.
BURNOUT DETECT
When the Burnout Detect (BOD) bit is set in the ADC control
configuration register (ADCON0 DCH), two current sources are
enabled. The current source on the positive input channel sources
approximately 2µA of current. The current source on the negative
input channel sinks approximately 2µA. This allows for the
detection of an open circuit (full-scale reading) or short circuit
(small differential reading) on the selected input differential pair.
Enabling the buffer is recommended when BOD is enabled.
INPUT BUFFER
The analog input impedance is always high, regardless of
PGA setting (when the buffer is enabled). With the buffer
enabled, the input voltage range is reduced and the analog
power-supply current is higher. If the limitation of input
voltage range is acceptable, then the buffer is always pre-
ferred.
The input impedance of the MSC1201 without the buffer
is 7MΩ/PGA. The buffer is controlled by the state of the BUF
bit in the ADC control register (ADCON0 DCH).
ANALOG INPUT
When the buffer is not selected, the input impedance of the
analog input changes with ACLK clock frequency (ACLK
F6H) and gain (PGA). The relationship is:
A pedance MHz
ACLKFrequency M
PGA
IN Im ( )Ω=
•Ω
17
where ACLK frequency (fACLK) =
f
ACLK
CLK
+1
and fMOD = fACLK
64 .
Figure 7 shows the basic input structure of the MSC1201.
R
SWITCH
(3kΩ typical)
Sampling Frequency = f
SAMP
High Impedance
> 1GΩ
C
S
AGND
A
IN
PGA f
SAMP
1, 2, 4 f
MOD
82 × f
MOD
16 4 × f
MOD
32 8 × f
MOD
64, 128 16 × f
MOD
PGA C
S
1 9pF
2 18pF
4 to 128 36pF
AIN3
AIN4
AIN5
AIN0
AIN1
AIN2
AINCOM
Burnout Detect (2µA)
Burnout Detect (2µA)
AGND
Buffer
Temperature Sensor
I
80 • I
AVDD
AVDD AVDD
In+
In–
MSC1201
18 SBAS317
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PRODUCT PREVIEW
FIGURE 8. Filter Step Responses.
SETTLING TIME
FILTER (Conversion Cycles)
Sinc33(1)
Sinc22(1)
Fast 1(1)
NOTE: (1) With Synchronized Channel Changes.
CONVERSION CYCLE
1234+
Discard Fast Sinc2Sinc3
AUTO MODE FILTER SELECTION
FILTER SETTLING TIME
Adjustable Digital Filter
Data Out
Modulator
Fast Settling
Sinc2
Sinc3
RMS
FULL-SCALE ENOB MEASUREMENT
PGA RANGE AT 10Hz RESOLUTION
SETTING (V) (BITS) (nV)
1±2.5 21.7 1468
2±1.25 21.5 843
4±0.625 21.4 452
8±0.313 21.2 259
16 ±0.156 20.8 171
32 ±0.0781 20.4 113
64 ±0.039 20 74.5
128 ±0.019 19 74.5
TABLE I. ENOB Versus PGA.
PGA
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can actually improve the effective resolution
of the ADC. For instance, with a PGA of 1 on a ±2.5V full-
scale range, the ADC can resolve to 1.5µV. With a PGA of
128 on a ±19mV full-scale range, the ADC can resolve to
75nV. With a PGA of 1 on a ±2.5V full-scale range, it would
require a 26-bit ADC to resolve 75nV, as shown in Table I.
OFFSET DAC
The analog output from the PGA can be offset by up to half
the full-scale input range of the PGA by using the ODAC
register (SFR E6H). The ODAC (Offset DAC) register is an 8-
bit value; the MSB is the sign and the seven LSBs provide
the magnitude of the offset. Since the ODAC introduces an
analog (instead of digital) offset to the PGA, using the ODAC
does not reduce the range of the ADC.
MODULATOR
The modulator is a single-loop 2nd-order system. The modu-
lator runs at a clock speed (fMOD) that is derived from the CLK
using the value in the Analog Clock register (ACLK, F6H).
The data output rate is:
Data Rate = fDATA =
f
DecimationRatio
MOD
where fMOD = f
ACLK f
CLK ACLK
()+• =
164 64
CALIBRATION
The offset and gain errors in the MSC1201, or the complete
system, can be reduced with calibration. Calibration is con-
trolled through the ADCON1 register (SFR DDH), bits
CAL2:CAL0. Each calibration process takes seven tDATA
periods (data conversion time) to complete. Therefore, it
takes 14 tDATA periods to complete both an offset and gain
calibration.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset calibration requires a
zero-differential input signal. It then computes an offset val ue
that will nullify offset in the system. The system gain calibration
requires a positive full-scale differential input signal. It then
computes a gain value to nullify gain errors in the system.
Each of these calibrations will take seven tDATA periods to
complete.
Calibration should be performed after power on, a change in
temperature, power supply, voltage reference, decimation
ratio, buffer, or a change of the PGA. Calibration will remove
the effects of the Offset DAC; therefore, changes to the
Offset DAC register should be done after calibration.
At the completion of calibration, the ADC Interrupt bit goes
high, which indicates the calibration is finished and valid data
is available.
DIGITAL FILTER
The Digital Filter can use either the Fast Settling, Sinc2, or
Sinc3 filter, as shown in Figure 8. In addition, the Auto mode
changes the Sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the
Fast Settling filter, for the next two conversions the first of
which should be discarded. It will then use the Sinc2 followed
by the Sinc3 filter to improve noise performance. This com-
bines the low-noise advantage of the Sinc3 filter with the
quick response of the Fast Settling Time filter. The frequency
response of each filter is shown in Figure 9.
MSC1201 19
SBAS317 www.ti.com
PRODUCT PREVIEW
FIGURE 9. Filter Frequency Responses.
SINC3 FILTER RESPONSE
fDATA
0
–20
–40
–60
–80
–100
–120 012345
012345
012345
Gain (dB)
SINC2 FILTER RESPONSE
fDATA
0
–20
–40
–60
–80
–100
–120
Gain (dB)
FAST SETTLING FILTER RESPONSE
fDATA
0
–20
–40
–60
–80
–100
–120
NOTE: fDATA = Data Output Rate = 1/tDATA
Gain (dB)
(–3dB = 0.318 • fDATA)
(–3dB = 0.469 • fDATA)
(–3dB = 0.262 • fDATA)
The external voltage reference is differential and is repre-
sented by the voltage difference between the pins: REFIN+
and REFIN–. The absolute voltage on either pin (REFIN+
and REFIN–) can range from AGND to AVDD; however, the
differential voltage must not exceed AVDD. The differential
voltage reference provides easy means of performing
ratiometric measurement.
IDAC
The 8-bit IDAC in the MSC1201 can be used to provide a
current source that can be used for ratiometric measure-
ments. The full-scale output current of the IDAC is approxi-
mately 1mA. The equation for the IDAC output current is:
IDACOUT = IDAC • 3.8µA
DIGITAL BROWNOUT RESET
The MSC1201 contains a programmable digital brownout
reset (DBOR). When the digital supply drops below the value
programmed in HCR1, the device is held in a reset state until
the supply rises above this value. Once the supply rises
above this value, the device is released from reset and
executes a normal POR sequence. The digital supply voltage
comparison is performed against an analog reference, and
therefore, the analog supply must be within the valid operat-
ing range in order to use DBOR.
ANALOG LOW VOLTAGE DETECT
The MSC1201 contains an analog low-voltage detect. When
the analog supply drops below the value programmed in
LVDCON (SFR E7H), an interrupt is generated.
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The built-in (on-chip) power-on reset circuitry was designed
to accommodate analog or digital supply ramp rates as slow
as 1V/10ms. To ensure proper operation, the power supply
should ramp monotonically at the specified rate. If DBOR is
enabled, the ramp rate can be slower.
RESET
A typical reset circuit is shown in Figure 10.
FIGURE 10. Typical Reset Circuit.
VOLTAGE REFERENCE
The voltage reference used for the MSC1201 can either be
internal or external. The power-up configuration for the volt-
age reference is 2.5V internal. The selection for the voltage
reference is made through the ADCON0 register (SFR DCH).
The internal voltage reference is selectable as either 1.25V
(AVDD = 2.7V to 5.25V) or 2.5V (AVDD = 4.1V to 5.25V). If the
internal VREF is not used, it should be turned off. The
REFOUT/REFIN+ pin should have a 0.1µF capacitor to AGND.
MSC1201
DVDD DVDD
RST
5
MSC1201
20 SBAS317
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PRODUCT PREVIEW
CLOCKS
The MSC1201 can operate in three separate clock modes:
internal oscillator mode (IOM), external clock mode (ECM),
and PLL mode. A block diagram is shown in Figure 11. The
clock mode for the MSC1201 is selected via the CLKSEL bits
in HCR2. IOM is the default mode for the device.
Serial Flash Programming mode uses IO LF mode (the
HCR2 and CLKSEL bits have no effect). Table II shows the
active clock mode for the various startup conditions.
Internal Oscillator
In IOM, the CPU executes either in LF mode (if HCR2,
CLKSEL = 111) or HF mode (if HCR2, CLKSEL = 110).
External Clock
In ECM (HCR2, CLKSEL = 011), the CPU can execute from
an external crystal, external ceramic resonator, external
clock, or external oscillator. If an external clock is detected at
startup, then the CPU will begin execution in ECM after
startup. If an external clock is not detected at startup, then
the device will revert to the mode shown in Table II.
PLL
In Phase Lock Loop (PLL) mode (HCR2, CLKSEL = 101 or
HCR2, CLKSEL = 100), the CPU can execute from an
external 32.768 kHz crystal. This mode enables the use of a
phase-lock loop (PLL) circuit that synthesizes the selected
clock frequencies (PLL LF mode or PLL HF mode). If an
external clock is detected at startup, then the CPU will begin
execution in PLL mode after startup. If an external clock is
not detected at startup, then the device will revert to the
mode shown in Table II. The status of the PLL can be
determined by first writing the PLLLOCK bit (enable) and
then reading the PLLLOCK status bit in the PLLH SFR.
The frequency of the PLL is preloaded with default trimmed
values. However, the PLL frequency can be fine-tuned by
writing to the PLLDIV1 and PLLDIV0 SFRs. The equation for
the PLL frequency is:
PLL Frequency = ((PLLDIV9:PLLDIV0) + 1) • fOSC
where fOSC = 32.768kHz.
The default value for PLL LF mode is automatically loaded
into the PLLDIV SFR. For PLL HF mode, the user must load
PLLDIV with the appropriate value (0383H).
For different connections to external clocks, see Figures 12,
13, and 14.
FIGURE 11. Clock Block Diagram.
100kΩ
Int Osc
LF/HF Mode
220pF
Ceramic
CAP
(1)
STOP
Phase
Detector
XIN
XOUT
Charge
Pump
NOTE: (1) The trace length connecting the CAP pin to the 220pF ceramic capacitor should be as short as possible.
VCO
PLL DAC
PLLDIV
SYSDIV
t
OSC
t
PLL
/t
IOM
t
SYS
t
CLK
SELECTED CLOCK MODE (HCR2, CLKCON2:0) STARTUP CONDITION(1) ACTIVE CLOCK MODE (fSYS)
External Clock Mode (ECM) Active Clock Present at XIN External Clock Mode
No Clock Present at XIN IO LF Mode
Internal Oscillator Mode (IOM)
IO LF Mode N/A IO LF Mode
IO HF Mode N/A IO HF Mode
PLL(2)
PLL LF Mode Active 32.768kHz Clock at XIN PLL LF Mode
No Clock Present at XIN Nominal: 50% of IO LF Mode Rate
PLL HF Mode Active 32.768kHz Clock at XIN PLL HF Mode
No Clock Present at XIN Nominal: 50% of IO HF Mode Rate
NOTES: (1) Clock detection is only done at startup; refer to Electrical Characteristics parameter tRFD in Figure B.
(2) PLL operation requires that both AVDD and DVDD are within their specified operating range.
TABLE II. Active Clock Modes.
MSC1201 21
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PRODUCT PREVIEW
FIGURE 12. External Crystal Connection.
XIN
XOUT
C1
C2
NOTE: Refer to the crystal manufacturer's specification
for C1 and C2 values.
FIGURE 13. External Clock Connection.
XINExternal Clock
FIGURE 14. PLL Connection.
XOUT
XIN
C
1
R
S
C
2
32.768kHz
NOTE: Typical configuration is shown.
SPI
The MSC1201 implements a basic SPI interface which in-
cludes the hardware for simple serial data transfers. Figure 15
shows a block digram of the SPI. The peripheral supports
master and slave mode, full duplex data transfers, both clock
polarities, both clock phases, bit order, and slave select.
The timing diagram for supported SPI data transfers is
shown in Figure 16.
The I/O pins needed for data transfer are Data In (DIN), Data
Out (DOUT) and serial clock (SCK). The slave select (
SS
)
pin can also be used to control the output of data on DOUT.
The DIN pin is used for shifting data in for both master and
slave modes.
The DOUT pin is used for shifting data out for both master
and slave modes.
The SCK pin is used to synchronize the transfer of data for
both master and slave modes. SCK is always generated by
the master. The generation of SCK in master mode can be
done in SW by simply toggling the port pin, or the generation
of SCK can be accomplished by configuring the output on the
SCK pin via PASEL (SFR F2H). A list of the most common
methods of generating SCK follows, but the complete list of
clock sources can be found by referring to the PASEL SFR.
• Toggle SCK by setting and clearing the port pin.
• Memory Write Pulse (
WR
) which is idle high. Whenever a
external memory write command (MOVX) is executed then a
pulse is seen on P3.6. This method can be used only if CPOL
is set to ‘1’.
• Memory Write Pulse toggle version: In this mode, SCK
toggles whenever an external write command (MOVX) is
executed.
• T0_Out signal can be used as a clock. A pulse is generated
on SCK whenever Timer 0 expires. The idle state of the
signal is low, so this can be used only if CPOL is cleared to
‘0’.
• T0_Out Toggle: SCK toggles whenever Timer 0 expires.
FIGURE 15. SPI/I2C Block Diagram.
SPI /I
2
C
Data Write
SPICON
I2CCON
I
2
C
Stretch
Control
Counter
Start/Stop
Detect
SPI /I
2
C
Data Read
Pad Control
DOUT
P1.2
P1.4
P3.6
P1.3
Logic
DOUT
TX_CLK
RX_CLK
SS
SCK/SCL
CNT_CLK
CNT INT
I2C INT
DIN
CLKS
(refer to PASEL, SFR F2
H
)
SS
SCK
DIN
MSC1201
22 SBAS317
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PRODUCT PREVIEW
• T1_Out signal can be used as a clock. A pulse is generated
whenever Timer 1 expires. The idle state of the signal is low,
so this can be used only if CPOL is cleared to ‘0’.
• T1_Out Toggle: SCK toggles whenever Timer 1 expires.
The
SS
pin can be used to control the output of data on
DOUT when the MSC1201 is in slave mode. The
SS
function
is enabled or disabled by the ESS bit of the SPICON SFR.
When enabled, the
SS
input of a slave device must be
externally asserted before a master device can exchange
data with the slave device.
SS
must be low before data
transactions and must stay low for the duration of the
transaction. When
SS
is high then data will not be shifted into
the shift register nor will the counter increment. When SPI is
enabled,
SS
also controls the drive of the line DOUT (P1.2).
When
SS
is low in slave mode, the DOUT pin will be driven
and when
SS
is high then DOUT will be high impedance.
The SPI generates an interrupt ECNT (AIE.2) to indicate that
the transfer/reception of the byte is complete. The interrupt
goes high whenever the counter value is equal to 8 (indicat-
ing that 8 SCKs have occurred). The interrupt is cleared on
reading or writing to the SPIDATA register. During the data
transfer, the actual counter value can be read from the
SPICON SFR.
Power Down
The SPI is powered down by the PDSPI bit in the power
control register (PDCON). This bit needs to be cleared to
enable the SPI function. When the SPI is powered down the
pins P1.2, P1.3, P1.4, and P3.6 revert to general-purpose
I/O pins.
Application Flow
Explained below are the steps of the typical application
usage flow of SPI in master and slave mode:
Master Mode Application Flow
1. Configure the port pins.
2. Configure the SPI.
3. Assert
SS
to enable slave communications (if applicable).
4. Write data to SPIDATA.
5. Generate 8 SCKs.
6. Read the received data from SPIDATA.
Slave Mode Application Flow
1. Configure the ports pins.
2. Enable
SS
(if applicable).
3. Configure the SPI.
4. Write data to SPIDATA.
5. Wait for the Count Interrupt (8 SCKs).
6. Read the data from SPIDATA.
Warning: If SPIDATA is not read before the next SPI
transaction the ECNT interrupt will be removed and the
previous data will be lost.
FIGURE 16. SPI Timing Diagram.
1) SS Asserted
2) First SCK Edge
3) CNTIF Set (dependent on CPHA bit)
4) SS Negated
SCK Cycle #
MSB654321LSB
MSB654321 LSB
Slave CPHA = 0 Transfer in Progress
2
43
1
12345678
Slave CPHA = 1 Transfer in Progress
Sample Input
(CPHA = 0) Data Out
(CPHA = 1) Data Out
Sample Input
SS to Slave
SCK (CPOL = 0)
SCK (CPOL = 1)
MSC1201 23
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PRODUCT PREVIEW
I2C
The I/O pins needed for I2C transfer are: serial clock (SCL)
and serial data (SDA—implemented by connecting DIN and
DOUT externally).
The MSC1201 I2C supports:
1) Master or slave I2C operation (control in software)
2) Standard or fast modes of transfer
3) Clock stretching
4) General call
When used in I2C mode, pins DIN (P1.3) and DOUT (P1.2)
should be tied together externally. The DIN pin should be
configured as an input pin and the DOUT pin should be config-
ured as open drain or standard 8051 by setting the P1DDR
(DOUT should be set high so that the bus is not pulled low).
The MSC1201 I2C can generate two interrupts:
1) I2C interrupt for START/STOP interrupt (AIE.3)
2) CNT interrupt for bit counter interrupt (AIE.2)
The START/STOP interrupt is generated when a START
condition or STOP condition is detected on the bus. The bit
counter generates an interrupt on a complete (8-bit) data
transfer and also after the transfer of the ACK/NACK.
The bit counter for serial transfer is always incremented on the
falling edge of SCL and can be reset by reading or writing to
I2CDATA (SFR 9BH) or when a START/STOP condition is
detected. The bit counter can be polled or used as an interrupt.
The bit counter interrupt occurs when the bit counter value is
equal to 8, indicating that eight bits of data have been
transferred. I2C mode also allows for interrupt generation on
one bit of data transfer (I2CCON.CNTSEL). This can be used
for ACK/NACK interrupt generation. For instance, the I2C
interrupt can be configured for 8-bit interrupt detection, on the
eighth bit the interrupt is generated. Following this interrupt,
the clock will be stretched (SCL held low). The interrupt can
then be configured for 1-bit detection. The ACK/NACK can be
written by the software, which will terminate clock stretching.
The next interrupt will be generated after the ACK/NACK has
been latched by the receiving device. The interrupt is cleared
on reading or writing to the I2CDATA register. If I2CDATA is
not read before the next data transfer, the interrupt will be
removed and the previous data will be lost.
Master Operation
The source for the SCL is controlled in the PASEL register or
can be generated in software.
Transmit
The serial data must be stable on the bus while SCL is high.
Therefore, the writing of serial data to I2CDATA must be
coordinated with the generation of the SCL, since SDA
transitions on the bus may be interpreted as a START or
STOP while SCL is high. The START and STOP conditions
on the bus must be generated in software. After the serial
data has been transmitted, the generation of the ACK/NACK
clock must be enabled by writing 0xFFH to I2CDATA. This
allows the master to read the state of ACK/NACK.
Receive
The serial data is latched into the receive buffer on the rising
edge of SCL. After the serial data has been received,
ACK/NACK is generated by writing 0x7FH (for ACK) or 0xFFH
(for NACK) to I2CDATA.
Slave Operation
Slave operation is supported, but address recognition, R/W
determination, and ACK/NACK must be done under software
control.
Transmit
Once address recognition, R/W determination, and
ACK/NACK are complete, the serial data to be transferred
can be written to I2CDATA. The data is automatically shifted
out based on the master SCL. After data transmission,
CNTIF is generated and SCL is stretched by the MSC1201
until the I2CDATA register is written with a 0xFFH. The
ACK/NACK from the master can then be read.
Receive
Once address recognition, R/W determination, and
ACK/NACK are complete, I2CDATA must be written with
0xFFH to enable data reception. Upon completion of the data
shift, the MSC1201 generates the CNT interrupt and stretches
SCL. Received data can then be read from I2CDATA. After
the serial data has been received, ACK/NACK is generated
by writing 0x7FH (for ACK) or 0xFFH (for NACK) to I2CDATA.
The write to I2CDATA clears the CNT interrupt and clock
stretch.
SDA
SCL 1-7 8
PS
STOP
Condition
(4)
START
Condition
(1)
ACK
(3)
ACK
(3)
ACK
(3)
R/W
(2)
DATA
(2)
DATA
(2)
ADDRESS
(2)
9 1-7 8 9 1-7 8 9
(1) Generate in software; write 0x7F to I2CDATA.
(2) I2CDATA register.
(3) Generate in software. Can enable bit count = 1 interrupt prior to ACK/NACK for interrupt use.
Generate ACK by writing 0x7F to I2CDATA; generate NACK by writing 0xFF to I2CDATA.
(4) Generate in software; write 0xFF to I2CDATA.
NOTES:
FIGURE 17. Timing Diagram for I2C Transmission and Reception.
MSC1201
24 SBAS317
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PRODUCT PREVIEW
MEMORY MAP
The MSC1201 contains on-chip SFR, Flash Memory,
Scratchpad RAM Memory, and Boot ROM. The SFR regis-
ters are primarily used for control and status. The standard
8051 features and additional peripheral features of the
MSC1201 are controlled through the SFR. Reading from
undefined SFR will return zero; writing to undefined SFR
registers is not recommended and may have indeterminate
effects.
Flash Memory is used for both Program Memory and Data
Memory. The user has the ability to select the partition size
of Program and Data Memories. The partition size is set
through hardware configuration bits, which are programmed
through serial programming. Both Program and Data Flash
Memories are erasable and writable (programmable) in user
application mode. However, program execution can only
occur from Program Memory. As an added precaution, a lock
feature can be activated through the hardware configuration
bits, which disables erase and writes to the first 4kB of
Program Flash Memory or the entire Program Flash Memory
in user application mode.
FLASH MEMORY
The MSC1201 uses a memory addressing scheme that
separates Program Memory from Data Memory. The program
and data segments can overlap since they are accessed by
different instructions. Program Memory is fetched by the
microcontroller automatically. There is one instruction (MOVC)
that is used to explicitly read the program area. This is commonly
used to read lookup tables.
The MSC1201 has three Hardware (HW) Configuration
registers (HCR0, HCR1, and HCR2) that are programmable
only during Flash Memory Programming mode.
The MSC1201 allows the user to partition the Flash Memory
between Program Memory and Data Memory. For instance,
the MSC1201Y3 contains 8kB of Flash Memory on-chip.
Through the HW configuration registers, the user can define
the partition between Program Memory (PM) and Data
Memory (DM), as shown in Tables III and IV and Figure 18.
The MSC1201 family offers two memory configurations.
FIGURE 18. Memory Map.
HCR0 MSC1201Y2 MSC1201Y3
DFSEL PM DM PM DM
00 0000-07FF 0400-0BFF 0000-0FFF 0400-13FF
01 0000-07FF 0400-0BFF 0000-17FF 0400-0BFF
10 0000-0BFF 0400-07FF 0000-1BFF 0400-07FF
11 (default) 0000-0FFF 0000 0000-1FFF 0000
TABLE IV. Flash Memory Partitioning Addresses.
HCR0 MSC1201Y2 MSC1201Y3
DFSEL PM DM PM DM
00 2kB 2kB 4kB 4kB
01 2kB 2kB 6kB 2kB
10 3kB 1kB 7kB 1kB
11 (default) 4kB 0kB 8kB 0kB
TABLE III. MSC1201Y Flash Partitioning.
Unused
Unused
Unused
1K Internal Boot ROM
Select in
HCR0
0000
H
, 0k
2000
H
, 8k (Y3)
1000
H
, 4k (Y2)
FC00
H
F800
H
FFFF
H
FFFF
H
On-Chip Flash
Program
Memory
0400
H
, 1k
1400
H
, 5k (Y3)
0C00
H
, 3k (Y2)
On-Chip Flash
Data
Memory
MSC1201 25
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PRODUCT PREVIEW
FIGURE 20. Scratchpad Register Addressing.
7FH
2FH
2DH
2EH
2CH
2BH
2AH
29H
28H
27H
26H
25H
24H
23H
22H
21H
20H
1FH
18H
17H
10H
0FH
08H
07H
7F 7E 7D 7C 7B 7A 79 78
77 76 75 74 73 72 71 70
6F 6E 6D 6C 6B 6A 69 68
67 66 65 64 63 62 61 60
5F 5E 5D 5C 5B 5A 59 58
57 56 55 54 53 52 51 50
4F 4E 4D 4C 4B 4A 49 48
47 46 45 44 43 42 41 40
3F 3E 3D 3C 3B 3A 39 38
37 36 35 34 33 32 31 30
2F 2E 2D 2C 2B 2A 29 28
27 26 25 24 23 22 21 20
1F 1E 1D 1C 1B 1A 19 18
17 16 15 14 13 12 11 10
0F 0E 0D 0C 0B 0A 09 08
07 06 05 04 03 02 01 00
00H
Direct
RAM
Bank 3
Bit Addressable
Bank 2
Bank 1
Bank 0
MSB LSB
It is important to note that the Flash Memory is readable and
writable (depending on the MXWS bit in the MWS SFR) by
the user through the MOVX instruction when configured as
either Program or Data Memory. This means that the user
may partition the device for maximum Flash Program Memory
size (no Flash Data Memory) and use Flash Program Memory
as Flash Data Memory. This may lead to undesirable behav-
ior if the PC points to an area of Flash Program Memory that
is being used for data storage. Therefore, it is recommended
to use Flash partitioning when Flash Memory is used for data
storage. Flash partitioning prohibits execution of code from
Data Flash Memory. Additionally, the Program Memory erase/
write can be disabled through hardware configuration bits
(HCR0), while still providing access (read/write/erase) to
Data Flash Memory.
The effect of memory mapping on Program and Data Memory
is straightforward. The Program Memory is decreased in size
from the top of Flash Memory. To maintain compatibility with
the MSC121x, the Flash Data Memory maps to addresses
0400H. Therefore, access to Data Memory (through MOVX)
will access Flash Memory for the addresses shown in
Table IV.
Data Memory
The MSC1201 has on-chip Flash Data Memory, which is
readable and writable (depending on Memory Write Select
register) during normal operation (full VDD range). This memory
is mapped into the external Data Memory space, which
requires the use of the MOVX instruction to program. Note
that the page size is 64 bytes for both Program and Data
Memory and the page must be erased before it can be
written.
REGISTER MAP
The Register Map is illustrated in Figure 19. It is entirely
separate from the Program and Data Memory areas men-
tioned before. A separate class of instructions is used to
access the registers. There are 128 register locations. In
practice, the MSC1201 has 128 bytes of Scratchpad RAM
and up to 128 SFRs. Thus, a direct reference to one of the
upper 128 locations will be an SFR access. Direct RAM is
reached at locations 0 to 7FH (0 to 127).
SFRs are accessed directly between 80H and FFH (128 to
255). Scratchpad RAM is available for general-purpose data
storage. It is commonly used in place of off-chip RAM when
the total data contents are small. Within the 128 bytes of
RAM, there are several special-purpose areas.
Bit Addressable Locations
In addition to direct register access, some individual bits are
also accessible. These are individually addressable bits in
both the RAM and SFR area. In the Scratchpad RAM area,
registers 20H to 2FH are bit addressable. This provides 128
(16 • 8) individual bits available to software. A bit access is
distinguished from a full-register access by the type of
instruction. In the SFR area, any register location ending in
a 0H or 8H is bit addressable. Figure 20 shows details of the
on-chip RAM addressing including the locations of individual
RAM bits.
FIGURE 19. Register Map.
FF
H
255
128
127
0
80
H
7F
H
00
H
Direct
Scratchpad
RAM
Direct
Special Function
Registers
MSC1201
26 SBAS317
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PRODUCT PREVIEW
Working Registers
As part of the lower 128 bytes of RAM, there are four banks
of Working Registers, as shown in Figure 20. The Working
Registers are general-purpose RAM locations that can be
addressed in a special way. They are designated R0 through
R7. Since there are four banks, the currently selected bank will
be used by any instruction using R0-R7. This allows software
to change context by simply switching banks. This is controlled
via the Program Status Word register (PSW; 0D0H) in the SFR
area described below. The 16 bytes immediately above the
R0-R7 registers are bit addressable. So any of the 128 bits in
this area can be directly accessed using bit addressable
instructions.
Stack
Another use of the Scratchpad area is for the programmer’s
stack. This area is selected using the Stack Pointer (SP; 81H)
SFR. Whenever a call or interrupt is invoked, the return
address is placed on the Stack. It also is available to the
programmer for variables, etc., since the Stack can be
moved and there is no fixed location within the RAM desig-
nated as Stack. The Stack Pointer will default to 07H on reset.
The user can then move it as needed. The SP will point to the
last used value. Therefore, the next value placed on the
Stack is put at SP + 1. Each PUSH or CALL will increment
the SP by the appropriate value. Each POP or RET will
decrement as well.
Program Memory
After reset, the CPU begins execution from Program Memory
location 0000H. The standard internal Program Memory size for
MSC1201 family members is shown in Table V. If enabled the
Boot ROM will appear from address F800H to FBFFH.
STANDARD INTERNAL
MODEL NUMBER PROGRAM MEMORY SIZE (BYTES)
MSC1201Y3 8k
MSC1201Y2 4k
TABLE V. MSC120 1 Maximum Internal Program Memory Sizes.
Boot ROM
There is a 1kB Boot ROM that controls operation during serial
programming. Additionally, the Boot ROM routines shown in
Table VI can be accessed during the user mode if it is enabled.
When enabled, the Boot ROM routines will be located at
memory addresses F800H-FBFFH during user mode.
HEX ADDRESS ROUTINE C DECLARATIONS DESCRIPTION
F802 sfr_rd char sfr_rd(void); Return SFR value pointed to by CADDR(1)
F805 sfr_wr void sfr_wr(char d); Write to SFR pointed to by CADDR(1)
FBD8 monitor_isr void monitor_isr() interrupt 6; Push registers and call cmd_parser
FBDA cmd_parser void cmd_parser(void); See SBAA076B.pdf
FBDC put_string void put_string(char code *string); Output string
FBDE page_erase char page_erase (int faddr, char fdata, char fdm); Erase flash page
FBE0 write_flash Assembly only; DPTR = address, ACC = data Flash write(2)
FBE2 write_flash_chk char write_flash_chk (int faddr, char fdata, char fdm); Write flash byte, verify
FBE4 write_flash_byte void write_flash_byte (int faddr, char fdata); Write flash byte(2)
FBE6 faddr_data_read char faddr_data_read(char faddr); Read HW config byte from faddr
FBE8 data_x_c_read char data_x_c_read(int faddr, char fdm); Read xdata or code byte
FBEA tx_byte void tx_byte(char); Send byte to UART0
FBEC tx_hex void tx_hex(char); Send hex value to UART0
FBEE putx void putx(char); Send “x” to UART0 on R7 = 1
FBF0 rx_byte char rx_byte(void); Read byte from UART0
FBF2 rx_byte_echo char rx_byte_echo(void); Read and echo byte on UART0
FBF4 rx_hex_echo char rx_hex_echo(void); Read and echo hex on UART0
FBF6 rx_hex_dbl_echo int rx_hex_dbl_echo(void); Read int as hex and echo: UART0
FBF8 rx_hex_word_echo int rx_hex_word_echo(void); Read int reversed as hex and echo: UART0
FBFA autobaud void autobaud(void); Set baud with received CR(3)
FBFC putspace1 void putspace1(void); Output 1 space to UART0
FBFE putcr void putcr(void); Output CR, LF to UART0
NOTES: (1) CADDR must be set using the faddr_data_read routine.
(2) MWS register (SFR 8FH) defines Data Memory or Program Memory write.
(3) SFR registers CKCON and TCON must be initialized: CKCON = 0x10 and TCON = 0x00.
TABLE VI. MSC1201 Boot ROM Routines.
MSC1201 27
SBAS317 www.ti.com
PRODUCT PREVIEW
Serial Flash Programming Mode
Two methods of programming are available: serial program-
ming mode and user application mode. Serial programming
mode is initiated by holding the P1.0/PROG pin low during
POR, as shown in Figure 21. User Application mode also
allows for Flash programming. Code execution from Flash
Memory cannot occur in this mode while programming, but
code execution can occur from Boot ROM while programming.
INTERRUPT
INTERRUPT/EVENT ADDR NUM PRIORITY FLAG ENABLE CONTROL
HIGH
AVDD Low Voltage Detect 33H6 0 ALVDIP (AIPOL.1)(1) EALV (AIE.1)(1) N/A
Count (SPI / I2C) 33H6 0 CNTIP (AIPOL.2)(1) ECNT (AIE.2)(1) N/A
I2C Start/Stop 33H6 0 I2CIP (AIPOL.3)(1) EI2C (AIE.3)(1) N/A
Milliseconds Timer 33H6 0 MSECIP (AAIPOLIE.4)(1) EMSEC (AIE.4)(1) N/A
ADC 33H6 0 ADCIP (AIPOL.5)(1) EADC (AIE .5)(1) N/A
Summation Register 33H6 0 SUMIP (AIPOL.6)(1) ESUM (AIE.6)(1) N/A
Seconds Timer 33H6 0 SECIP (AIPOL.7)(1) ESEC (AIE.7)(1) N/A
External Interrupt 0 03H0 1 IE0 (TCON.1)(2) EX0 (IE.0)(4) PX0 (IP.0)
Timer 0 Overflow 0BH1 2 TF0 (TCON.5)(3) ET0 (IE.1)(4) PT0 (IP.1)
External Interrupt 1 13H2 3 IE1 (TCON.3)(2) EX1 (IE.2)(4) PX1 (IP.2)
Timer 1 Overflow 1BH3 4 TF1 (TCON.7)(3) ET1 (IE.3)(4) PT1 (IP.3)
Serial Port 0 23H4 5 RI_0 (SCON0.0) ES0 (IE.4)(4) PS0 (IP.4)
TI_0 (SCON0.1)
External Interrupt 2 43H8 6 IE2 (EXIF.4) EX2 (EIE.0)(4) PX2 (IP.0)
External Interrupt 3 4BH9 7 IE3 (EXIF.5) EX3 (EIE.1)(4) PX3 (IP.1)
External Interrupt 4 53H10 8 IE4 (EXIF.6) EX4 (EIE.2)(4) PX4 (IP.2)
External Interrupt 5 5BH11 9 IE5 (EXIF.7) EX5 (EIE.3)(4) PX5 (IP.3)
Watchdog 63H12 10 WDTI (EICON.3) EWDI (EIE.4)(4) PWDI (IP.4)
LOW
NOTES: (1) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2) If edge triggered, cleared automatically by hardware when the
service routine is vectored to. If level triggered, the flag follows the state of the pin. (3) Cleared automatically by hardware when interrupt vector occurs.
(4) Globally enabled by EA (IE.7).
TABLE VII. Interrupt Summary.
INTERRUPT
INTERRUPTS
The MSC1201 uses a three-priority interrupt system. As
shown in Table VII, each interrupt source has an indepen-
dent priority bit, flag, interrupt vector, and enable (except that
nine interrupts share the Auxiliary Interrupt (AI) at the highest
priority). In addition, interrupts can be globally enabled or
disabled. The interrupt structure is compatible with the origi-
nal 8051 family. All of the standard interrupts are available.
HARDWARE CONFIGURATION MEMORY
The 64 configuration bytes can only be written during the
program mode. The bytes are accessed through SFR regis-
ters CADDR (SFR 93H) and CDATA (SFR 94H). Three of the
configuration bytes control Flash partitioning and system
control. If the security bit is set, these bits cannot be changed
except with a Mass Erase command that erases all of the
Flash Memory including the 64 configuration bytes.
FIGURE 21. Serial Programming Mode.
MSC1201
Programmer
P3.0/RxD0
P3.1/TxD0
P1.0/PROG
NOTE: For user application mode, avoid heavy loading on
P1.0/PROG, which may result in erroneously entering serial
programming mode on power-up.
MSC1201
28 SBAS317
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PRODUCT PREVIEW
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
CADDR 3FHEPMA PML RSL EBR EWDR 1 DFSEL1 DFSEL0
Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA.
To read this register during normal operation, refer to the register descriptions for CADDR and CDATA.
EPMA Enable Programming Memory Access (Security Bit).
bit 7 0: After reset in programming modes, Flash Memory can only be accessed in UAM mode until a mass erase is done.
1: Fully Accessible (default)
PML Program Memory Lock (PML has Priority Over RSL).
bit 6 0: Enable all Flash Programming Modes in Program Memory; can be written in UAM.
1: Enable read only for Program Memory; cannot be written in UAM (default).
RSL Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming. This
bit 5 will allow Program Memory updates without changing the jumpers for in-circuit code updates or program
development. The code in this boot sector would then provide the monitor and programming routines with the ability
to jump into the main Flash code when programming is finished.
0: Enable Reset Sector Writing
1: Enable Read Only Mode for Reset Sector (4kB) (default)
EBR Enable Boot ROM. Boot ROM is 1kB of code located in ROM, not to be confused with the 4kB Boot Sector located
bit 4 in Flash Memory.
0: Disable Internal Boot ROM
1: Enable Internal Boot ROM (default)
EWDR Enable Watchdog Reset.
bit 3 0: Disable Watchdog Reset
1: Enable Watchdog Reset (default)
DFSEL1-0 Data Flash Memory Size (see Table II).
bits 1-0 00: 4kB Data Flash Memory (MSC1201Y3 Only)
01: 2kB Data Flash Memory
10: 1kB Data Flash Memory
11: No Data Flash Memory (default)
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7654321 0
CADDR 3EH11111DDB1 1
Hardware Configuration Register 1 (HCR1)
To read this register during normal operation, refer to the register descriptions for CADDR and CDATA.
DDB Disable Digital Brownout Detection
bit 2 0: Enable Digital Brownout Detection (2.7V)
1: Disable Digital Brownout Detection (default)
Hardware Configuration Register 2 (HCR2)
7654321 0
CADDR 3DH0 0 0 0 0 CLKSEL2 CLKSEL1 CLKSEL0
To read this register during normal operation, refer to the register descriptions for CADDR and CDATA.
CLKSEL2-0 Clock Select
bits 2-0 000: Reserved
001: Reserved
010: Reserved
011: External Clock Mode
100: PLL High-Frequency (HF) Mode
101: PLL Low-Frequency (LF) Mode
110: Internal Oscillator High-Frequency (HF) Mode
111: Internal Oscillator Low-Frequency (LF) Mode
Configuration Memory Programming
Certain key functions such as Brownout Reset and Watchdog Timer are controlled by the hardware configuration bits. These
bits are nonvolatile and can only be changed through serial flash programming. Other peripheral control and status functions,
such as ADC configuration timer setup, and Flash control are controlled through the SFRs.
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SFR Definitions
ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES
80H
81HSP 07H
82HDPL0 00H
83HDPH0 00H
84HDPL1 00H
85HDPH1 00H
86HDPS 0000000SEL 00
H
87HPCON SMOD 011GF1GF0STOP IDLE 30H
88HTCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
89HTMOD |---------------------------Timer 1 --------------------------| |--------------------------Timer 0 ---------------------------| 00H
GATE C/T M1 M0 GATE C/T M1 M0
8AHTL0 00H
8BHTL1 00H
8CHTH0 00H
8DHTH1 00H
8EHCKCON 0 0 0 T1M T0M MD2 MD1 MD0 01H
8FHMWS0000000MXWS 00
H
90HP1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 FFH
INT5
INT4
INT3
INT2/
SS
DIN DOUT
91HEXIFIE5IE4IE3IE21000 08
H
92H
93HCADDR 00H
94HCDATA 00H
95H
96H
97H
98HSCON0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00H
99HSBUF0 00H
9AHSPICON SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA ESS CPOL 00H
I2CCON SBIT3 SBIT2 SBIT1 SBIT0 STOP START DCS CNTSEL
9BHSPIDATA 00H
I2CDATA
9CH
9DH
9EH
9FH
A0H
A1H
A2H
A3H
A4HAIPOL SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP 0 00H
A5HPAI 0000PAI3PAI2PAI1PAI0 00
H
A6HAIE ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00H
A7HAISTAT SEC SUM ADC MSEC I2C CNT ALVD 0 00H
A8HIE EA 0 0 ES0 ET1 EX1 ET0 EX0 00H
A9H
AAH
ABH
ACH
ADH
AEHP1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00H
AFHP1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00H
B0HP3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 FFH
SCK/SCL/CLKS
T1 T0
INT1 INT0
TXD0 RXD0
B1H
B2H
B3HP3DDRL P33H P33L P32H P32L P31H P31L P30H P30L 00H
B4HP3DDRH P37H P37L P36H P36L P35H P35L P34H P34L 00H
B5HIDAC 00H
B6H
B7H
B8HIP 1 0 0 PS0 PT1 PX1 PT0 PX0 80H
B9H
BAH
BBH
BCH
BDH
BEH
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ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES
BFH
C0H
C1H
C2H
C3H
C4H
C5H
C6HEWU EWUWDT EWUEX1 EWUEX0 00H
C7HSYSCLK 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00H
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
D0HPSW CY AC F0 RS1 RS0 OV F1 P 00H
D1HOCL LSB 00H
D2HOCM 00H
D3HOCH MSB 00H
D4HGCL LSB 5AH
D5HGCM ECH
D6HGCH MSB 5FH
D7HADMUX INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01H
D8HEICON 0 1 EAI AI WDTI 0 0 0 40H
D9HADRESL LSB 00H
DAHADRESM 00H
DBHADRESH MSB 00H
DCHADCON0 —BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30H
DDHADCON1 —POL SM1 SM0 —CAL2 CAL1 CAL0 00H
DEHADCON2 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1BH
DFHADCON3 00000DR10DR9DR8 06
H
E0HACC 00H
E1HSSCON SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00H
E2HSUMR0 LSB 00H
E3HSUMR1 00H
E4HSUMR2 00H
E5HSUMR3 MSB 00H
E6HODAC 00H
E7HLVDCON ALVDIS 0001111 8F
H
E8HEIE 111EWDIEX5EX4EX3EX2 E0
H
E9HHWPC00000000MEMORY0000_000xB
EAHHWPC100100000 20
H
EBHHWVER
ECHReserved
EDHReserved
EEHFMCON 0 PGERA 0 FRCM 0 BUSY 1 0 02H
EFHFTCON FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5H
F0HB00H
F1HPDCON PDICLK PDIDAC PDI2C 0 PDADC PDWDT
PDST
PDSPI 6FH
F2HPASEL PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00H
F3HReserved
F4HPLLL PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 C1H
F5HPLLH
CLKSTAT2 CLKSTAT1
CLKSTAT0 PLLLOCK 0 0 PLL9 PLL8 x1H
F6HACLK 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03H
F7HSRST 0000000RSTREQ 00H
F8HEIP 111PWDIPX5PX4PX3PX2 E0
H
F9HSECINT WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7FH
FAHMSINT WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7FH
FBHUSEC 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03H
FCHMSECL MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9FH
FDHMSECH MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0FH
FEHHMSEC HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63H
FFHWDTCON EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00H
SFR Definitions (Cont.)
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7 6 5 4 3 2 1 0 Reset Value
SFR 81HSP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 07H
SP.7-0 Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before
b i ts 7- 0 every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07H after reset.
Data Pointer Low 0 (DPL0)
Stack Pointer (SP)
DPL0.7-0 Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0
bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H).
Data Pointer High 0 (DPH0)
7 6 5 4 3 2 1 0 Reset Value
SFR 82HDPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 00H
DPH0.7-0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0
bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H).
Data Pointer Low 1 (DPL1)
7 6 5 4 3 2 1 0 Reset Value
SFR 83HDPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 00H
DPL1.7-0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0)
bits 7-0 (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
Data Pointer High 1 (DPH1)
7 6 5 4 3 2 1 0 Reset Value
SFR 84HDPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 00H
DPH1.7-0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0)
bits 7-0 (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
Data Pointer Select (DPS)
7 6 5 4 3 2 1 0 Reset Value
SFR 85HDPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 00H
7 6 5 4 3 2 1 0 Reset Value
SFR 86H0 0 0 0 0 0 0 SEL 00H
SEL Data Pointer Select. This bit selects the active data pointer.
bit 0 0: Instructions that use the DPTR will use DPL0 and DPH0.
1: Instructions that use the DPTR will use DPL1 and DPH1.
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SMOD Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0.
bit 7 0: Serial Port 0 baud rate will be a standard baud rate.
1: Serial Port 0 baud rate will be double that defined by baud rate generation equation.
GF1 General-Purpose User Flag 1. This is a general-purpose flag for software control.
bit 3
GF0 General-Purpose User Flag 0. This is a general-purpose flag for software control.
bit 2
STOP Stop Mode Select. Setting this bit will halt the oscillator and block external clocks. This bit will always read as a 0.
bit 1 Exit with RESET. In this mode, internal peripherals are frozen and I/O pins are held in their current state. The ADC
is frozen, but IDAC and VREF remain active.
IDLE Idle Mode Select. Setting this bit will freeze the CPU, Timer 0 and 1, and the UART; other peripherals remain
bit 0 active. This bit will always be read as a 0. Exit with AIE (A6H) and EWU (C6H) interrupts (refer to Figure 4 for clocks
affected during IDLE).
Timer/Counter Control (TCON)
7 6 5 4 3 2 1 0 Reset Value
SFR 87HSMOD 0 1 1 GF1 GF0 STOP IDLE 30H
TF1 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current
bit 7 mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1
interrupt service routine.
0: No Timer 1 overflow has been detected.
1: Timer 1 has overflowed its maximum count.
TR1 Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the
current bit 6 count in TH1, TL1.
0: Timer is halted.
1: Timer is enabled.
TF0 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current
bit 5 mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0
interrupt service routine.
0: No Timer 0 overflow has been detected.
1: Timer 0 has overflowed its maximum count.
TR0 Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the
bit 4 current count in TH0, TL0.
0: Timer is halted.
1: Timer is enabled.
IE1 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this
bit 3 bit will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this
bit will inversely reflect the state of the
INT1
pin.
IT1 Interrupt 1 Type Select. This bit selects whether the
INT1
pin will detect edge or level triggered interrupts.
bit 2 0:
INT1
is level triggered.
1:
INT1
is edge triggered.
IE0 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this
bit 3 bit will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this
bit will inversely reflect the state of the
INT0
pin.
IT0 Interrupt 0 Type Select. This bit selects whether the
INT0
pin will detect edge or level triggered interrupts.
bit 2 0:
INT0
is level triggered.
1:
INT0
is edge triggered.
Power Control (PCON)
7 6 5 4 3 2 1 0 Reset Value
SFR 88HTF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
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Timer Mode Control (TMOD)
765432 10
TIMER 1 TIMER 0 Reset Value
SFR 89HGATE C/T M1 M0 GATE C/T M1 M0 00H
GATE Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment.
bit 7 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin
INT1
.
1: Timer 1 will clock only when TR1 = 1 and pin
INT1
= 1.
C/T
Timer 1 Counter/Timer Select.
bit 6 0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88H) is 1.
M1, M0 Timer 1 Mode Select. These bits select the operating mode of Timer 1.
bits 5-4
TL0.7-0 Timer 0 LSB. This register contains the least significant byte of Timer 0.
bits 7-0
Timer 1 LSB (TL1)
7 6 5 4 3 2 1 0 Reset Value
SFR 8AHTL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 00H
TL1.7-0 Timer 1 LSB. This register contains the least significant byte of Timer 1.
bits 7-0
Timer 0 MSB (TH0)
7 6 5 4 3 2 1 0 Reset Value
SFR 8BHTL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 00H
TH0.7-0 Timer 0 MSB. This register contains the most significant byte of Timer 0.
bits 7-0
7 6 5 4 3 2 1 0 Reset Value
SFR 8CHTH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00H
GATE Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment.
bit 3 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin
INT0
(software control).
1: Timer 0 will clock only when TR0 = 1 and pin
INT0
= 1 (hardware control).
C/T
Timer 0 Counter/Timer Select.
bit 2 0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88H) is 1.
M1, M0 Timer 0 Mode Select. These bits select the operating mode of Timer 0.
bits 1-0
M1 M0 MODE
0 0 Mode 0: 8-bit counter with 5-bit prescale.
0 1 Mode 1: 16 bits.
1 0 Mode 2: 8-bit counter with auto reload.
1 1 Mode 3: Timer 1 is halted, but holds its count.
M1 M0 MODE
0 0 Mode 0: 8-bit counter with 5-bit prescale.
0 1 Mode 1: 16 bits.
1 0 Mode 2: 8-bit counter with auto reload.
1 1 Mode 3: Timer 1 is halted, but holds its count.
Timer 0 LSB (TL0)
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Port 1 (P1)
7 6 5 4 3 2 1 0 Reset Value
SFR 90HP1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 FFH
INT5
INT4
INT3
INT2/
SS
DIN DOUT
PROG
P1.7-0 General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have
bit s 7 - 0 an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port
1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate
function, set the appropriate mode in P1DDRL (SFR AE
H
), P1DDRH (SFR AF
H
).
INT5
External Interrupt 5.A falling edge on this pin will cause an external interrupt 5 if enabled.
bit 7
INT4 External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled.
bit 6
INT3
External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled.
bit 5
INT2/
SS
External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. This pin can be used
bit 4 as slave select (
SS
) in SPI slave mode.
DIN Serial Data In. This pin receives serial data in SPI and I2C modes (in I2C mode, this pin should be configured
bit 3 as an input) or standard 8051.
DOUT Serial Data Out. This pin transmits serial data in SPI and I2C modes (in I2C mode, this pin should be configured
bit 2 as an open drain) or standard 8051.
PROG Program Mode. When this pin is pulled low at power-up, the device enters Serial Programming mode (refer to
bit 0 Figure B).
Timer 1 MSB (TH1)
7 6 5 4 3 2 1 0 Reset Value
SFR 8DHTH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00H
7 6 5 4 3 2 1 0 Reset Value
SFR 8EH0 0 0 T1M T0M MD2 MD1 MD0 01H
TH1.7-0 Timer 1 MSB. This register contains the most significant byte of Timer 1.
bits 7-0
Clock Control (CKCON)
T1M Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0
bit 4 maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 1 uses a divide by 12 of the crystal frequency.
1: Timer 1 uses a divide by 4 of the crystal frequency.
T0M Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0
bit 3 maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 0 uses a divide by 12 of the crystal frequency.
1: Timer 0 uses a divide by 4 of the crystal frequency.
MD2, MD1, MD0
Stretch MOVX Select. These bits select the time by which MOVX cycles are to be stretched. Since the MSC1201
bit 3 does not allow external memory access, these bits should be set to 000B to allow for the fastest flash data memory
access.
Memory Write Select (MWS)
MXWS MOVX Write Select. This allows writing to the internal Flash program memory.
bit 0 0: No writes are allowed to the internal Flash program memory.
1: Writing is allowed to the internal Flash program memory, unless PML (HCR0) or RSL (HCR0) are on.
7 6 5 4 3 2 1 0 Reset Value
SFR 8FH00 0 0 0 0 0MXWS 00
H
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IE5 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on
INT5
. This bit must be
bit 7 cleared manually by software. Setting this bit in software will cause an interrupt if enabled.
IE4 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared
bit 6 manually by software. Setting this bit in software will cause an interrupt if enabled.
IE3 External Interrupt 3 Flag. This bit will be set when a falling edge is detected on
INT3
. This bit must be cleared
bit 5 manually by software. Setting this bit in software will cause an interrupt if enabled.
IE2 External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared
bit 4 manually by software. Setting this bit in software will cause an interrupt if enabled.
Configuration Address Register (CADDR) (write only)
7 6 5 4 3 2 1 0 Reset Value
SFR 94H00H
7 6 5 4 3 2 1 0 Reset Value
SFR 93H00H
CADDR Configuration Address Register. This register supplies the address for reading bytes in the 64 bytes of Flash Configuration
bi ts 7- 0 Memory. Al ways use the Boot ROM CADDR access routine. This register is also used for SFR read and write
routines.
WARNING: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.
Configuration Data Register (CDATA)
CDATA Configuration Data Register. This register will contain the data in the 64 bytes of Flash Configuration Memory
bits 7-0 that is located at the last written address in the CADDR register. This is a read-only register.
7 6 5 4 3 2 1 0 Reset Value
SFR 91HIE5 IE4 IE3 IE2 1 0 0 0 08H
External Interrupt Flag (EXIF)
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7 6 5 4 3 2 1 0 Reset Value
SFR 99H00H
SBUF0 Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and
bits 7-0 receive buffers are separate registers, but both are addressed at this location.
Serial Data Buffer 0 (SBUF0)
SM0-2 Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit
bits 7-5 in addition to the 8 or 9 data bits.
7 6 5 4 3 2 1 0 Reset Value
SFR 98HSM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00H
REN_0 Receive Enable. This bit enables/disables the serial Port 0 received shift register.
bit 4 0: Serial Port 0 reception disabled.
1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).
TB8_0 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3.
bit 3
RB8_0 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes
bit 2 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.
TI_0 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted
bit 1 out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end
of the last data bit. This bit must be manually cleared by software.
RI_0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In
bit 0 serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample
of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of
RB8_0. This bit must be manually cleared by software.
MODE SM0 SM1 SM2 FUNCTION LENGTH PERIOD
0 0 0 0 Synchronous 8 bits 12 pCLK(1)
0 0 0 1 Synchronous 8 bits 4 pCLK(1)
1 0 1 0 Asynchronous 10 bits Timer 1 Baud Rate Equation
1 0 1 1 Asynchronous—Valid Stop Required(2) 10 bits Timer 1 Baud Rate Equation
2 1 0 0 Asynchronous 11 bits 64 pCLK(1) (SMOD = 0)
32 pCLK(1) (SMOD = 1)
2 1 0 1 Asynchronous with Multiprocessor Communication 11 bits 64 pCLK(1) (SMOD = 0)
32 pCLK(1) (SMOD = 1)
3 1 1 0 Asynchronous 11 bits Timer 1 Baud Rate Equation
3 1 1 1 Asynchronous with Multiprocessor Communication(3) 11 bits Timer 1 Baud Rate Equation
NOTES: (1) pCLK will be equal to tCLK, except that pCLK will stop for IDLE. (2) R I_0 will only be activated when a valid stop
is received. (3) RI_0 will not be activated if bit 9 = 0.
Serial Port 0 Control (SCON0)
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SPI Control (SPICON) (SERSEL bit determines SPICON control)
SBIT3-0 Serial Bit Count. Number of bits transferred (read only).
bits 7-4 SBIT3:0 COUNT
0x00 0
0x01 1
0x03 2
0x02 3
0x06 4
0x07 5
0x05 6
0x04 7
0x0C 8
7 6 5 4 3 2 1 0 Reset Value
SFR 9AHSBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA ESS CPOL 00H
ORDER Set Bit Order for Transmit and Receive.
bit 3 0: Most Significant Bits First
1: Least Significant Bits First
CPHA Serial Clock Phase Control.
bit 2 0: Valid data starting from half SCK period before the first edge of SCK
1: Valid data starting from the first edge of SCK
ESS Enable Slave Select.
bit 1 0:
SS
(P1.4) is configured as a general-purpose I/O (default).
1:
SS
(P1.4) is configured as
SS
for SPI mode. DOUT (P1.2) drives when
SS
is low, and DOUT (P1.2) is high-
impedance when
SS
is high.
CPOL Serial Clock Polarity.
bit 0 0: SCK idle at logic LOW
1: SCK idle at logic HIGH
7 6 5 4 3 2 1 0 Reset Value
SFR 9AHSBIT3 SBIT2 SBIT1 SBIT0 STOP START DCS CNTSEL 00H
I2C Control (I2CCON) (SERSEL bit determines I2CCON control)
SBIT3-0 Serial Bit Count. Number of bits transferred (read only).
bits 7-4 SBIT3:0 COUNT
0x00 0
0x01 1
0x03 2
0x02 3
0x06 4
0x07 5
0x05 6
0x04 7
0x0C 8
STOP Stop-Bit Status.
bit 3 0: No Stop
1: Stop Condition Received and I2CCNT set (cleared on write to I2CDATA)
START Start-Bit Status.
bit 2 0: No Stop
1: Start or Repeated Start Condition Received and I2CCNT set (cleared on write to I2CDATA)
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7 6 5 4 3 2 1 0 Reset Value
SFR A4HSECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP Unused 00H
SECIP Second System Timer Interrupt Poll (before IRQ masking).
bit 7 0 = Seconds System Timer Interrupt Poll Inactive
1 = Seconds System Timer Interrupt Poll Active
SUMIP Accumulator Interrupt Poll (before IRQ masking).
bits 6 0 = Accumulator Interrupt Poll Inactive
1 = Accumulator Interrupt Poll Active
ADCIP ADC Interrupt Poll (before IRQ masking).
bits 5 0 = ADC Interrupt Poll Inactive
1 = ADC Interrupt Poll Active
MSECIP Millisecond System Timer Interrupt Poll (before IRQ masking).
bits 4 0 = Millisecond System Timer Interrupt Poll Inactive
1 = Millisecond System Timer Interrupt Poll Active
I2CIP I2C Interrupt Poll (before IRQ masking).
bits 3 0 = I2C Interrupt Poll Inactive
1 = I2C Interrupt Poll Active
CNTIP Serial Bit Count Interrupt Poll (before IRQ masking).
bits 2 0 = Serial Bit Count Interrupt Poll Inactive
1 = Serial Bit Count Interrupt Poll Active
ALVDIP Analog Low Voltage Detect Interrupt Poll (before IRQ masking).
bits 1 0 = Analog Low Voltage Detect Interrupt Poll Inactive
1 = Analog Low Voltage Detect Interrupt Poll Active
Auxilliary Interrupt Poll (AIPOL)
7 6 5 4 3 2 1 0 Reset Value
SFR 9BH00H
SPIDATA SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers
bits 7-0 are separate registers, but both are addressed at this location.
I2CDATA I2C Data Register. Data for I2C is read from or written to this location. The I2C transmit and receive buffers
bits 7-0 are separate registers, but both are addressed at this location.
SPI Data Register (SPIDATA) / I2C Data Register (I2CDATA)
DCS Disable Serial Clock Stretch.
bit 1 0: Enable SCL Stretch (cleared by firmware or START condition)
1: Disable SCL Stretch
CNTSEL Counter Select.
bit 0 0: Counter IRQ Set for Bit Counter = 8 (default)
1: Counter IRQ Set for Bit Counter = 1
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7 6 5 4 3 2 1 0 Reset Value
SFR A6HESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00H
Auxiliary Interrupt Enable (AIE)
Interrupts are enabled by EICON.4 (SFR D8H). The other interrupts are controlled by the IE and EIE registers.
ESEC Enable Second System Timer Interrupt (lowest priority auxiliary interrupt).
bit 7 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Second Timer Interrupt mask.
ESUM Enable Summation Interrupt.
bit 6 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Summation Interrupt mask.
EADC Enable ADC Interrupt.
bit 5 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: ADC Interrupt mask.
EMSEC Enable Millisecond System Timer Interrupt.
bit 4 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Millisecond System Timer Interrupt mask.
EI2C Enable I2C Start/Stop Bit.
bit 3 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: I2C Start/Stop Bit mask.
ECNT Enable Serial Bit Count Interrupt.
bit 2 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Serial Bit Count Interrupt mask.
EALV Enable Analog Low Voltage Interrupt.
bit 1 Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: Analog Low Voltage Detect Interrupt mask.
7 6 5 4 3 2 1 0 Reset Value
SFR A5H0 0 0 0 PAI3 PAI2 PAI1 PAI0 00H
PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS
0 0 0 0 No Pending Auxiliary IRQ
0 0 0 1 Reserved
0 0 1 0 Analog Low Voltage Detect IRQ and Possible Lower Priority Pending
0011I
2C IRQ and Possible Lower Priority Pending
0 1 0 0 Serial Bit Count Interrupt and Possible Lower Priority Pending
0 1 0 1 Millisecond System Timer IRQ and Possible Lower Priority Pending
0 1 1 0 ADC IRQ and Possible Lower Priority Pending
0 1 1 1 Accumulator IRQ and Possible Lower Priority Pending
1 0 0 0 Second System Timer IRQ and Possible Lower Priority Pending
Pending Auxiliary Interrupt (PAI)
PAI Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the appropriate
bits 3-0 interrupt routine. All of these interrupts vector through address 0033H.
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Interrupt Enable (IE)
EA Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6H).
bit 7 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register.
1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled.
ES0 Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt.
bit 4 0: Disable all serial Port 0 interrupts.
1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98H) or TI_0 (SCON0.1, SFR 98H) flags.
ET1 Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt.
bit 3 0: Disable Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88H).
EX1 Enable External Interrupt 1. This bit controls the masking of external interrupt 1.
bit 2 0: Disable external interrupt 1.
1: Enable interrupt requests generated by the
INT1
pin.
ET0 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt.
bit 1 0: Disable all Timer 0 interrupts.
1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88H).
EX0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0.
bit 0 0: Disable external interrupt 0.
1: Enable interrupt requests generated by the
INT0
pin.
Auxiliary Interrupt Status Register (AISTAT)
7 6 5 4 3 2 1 0 Reset Value
SFR A7HSEC SUM ADC MSEC I2C CNT ALVD 0 00H
SEC Second System Timer Interrupt Status Flag (lowest priority AI).
bit 7 0: SEC Interrupt cleared or masked.
1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9H).
SUM Summation Register Interrupt Status Flag.
bit 6 0: SUM Interrupt cleared or masked.
1: SUM Interrupt active (it is cleared by reading the lowest byte of SUMR0, SFR E2H).
ADC ADC Interrupt Status Flag.
bit 5 0: ADC Interrupt cleared or masked.
1: ADC Interrupt active (it is cleared by reading the lowest byte of ADRESL, SFR D9H; if active, no new data will be
written to the ADC Results registers).
MSEC Millisecond System Timer Interrupt Status Flag.
bit 4 0: MSEC Interrupt cleared or masked.
1: MSEC Interrupt active (it is cleared by reading MSINT, SFR FAH).
I2C I2C Start/Stop Interrupt Status Flag.
bit 3 0: I2C Start/stop Interrupt cleared or masked.
1: I2C Start/stop Interrupt active (it is cleared by writing to I2CDATA, SFR 9BH).
CNT CNT Interrupt Status Flag.
bit 2 0: CNT Interrupt cleared or masked.
1: CNT Interrupt active (it is cleared by reading from or writing to SPIDATA/I2CDATA, SFR 9BH).
ALVD Analog Low Voltage Detect Interrupt Status Flag.
bit 1 0: ALVD Interrupt cleared or masked.
1: ALVD Interrupt active (cleared in HW if AVDD exceeds ALVD threshold).
NOTE: If an interrupt is masked, the status can be read in AIPOL, SFR A4H.
7 6 5 4 3 2 1 0 Reset Value
SFR A8HEA 0 0 ES0 ET1 EX1 ET0 EX0 00H
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P1.1 Port 1 bit 1 control.
bits 3-2
Port 1 Data Direction High Register (P1DDRH)
P1.0 Port 1 bit 0 control.
bits 1-0
P11H P11L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P1.7 Port 1 bit 7 control.
bits 7-6
7 6 5 4 3 2 1 0 Reset Value
SFR AFHP17H P17L P16H P16L P15H P15L P14H P14L 00H
P17H P17L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P1.6 Port 1 bit 6 control.
bits 5-4 P16H P16L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P1.5 Port 1 bit 5 control.
bits 3-2 P15H P15L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P1.4 Port 1 bit 4 control.
bits 1-0 P14H P14L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
Port 1 Data Direction Low Register (P1DDRL)
P1.3 Port 1 bit 3 control.
bits 7-6
7 6 5 4 3 2 1 0 Reset Value
SFR AEHP13H P13L P12H P12L P11H P11L P10H P10L 00H
P13H P13L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P1.2 Port 1 bit 2 control.
bits 5-4 P12H P12L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P10H P10L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
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7 6 5 4 3 2 1 0 Reset Value
SFR B3HP33H P33L P32H P32L P31H P31L P30H P30L 00H
P33H P33L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P32H P32L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P31H P31L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P30H P30L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
7 6 5 4 3 2 1 0 Reset Value
SFR B0HP3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 FFH
SCK/SCL/CLKS
T1 T0
INT1
INT0
TXD0 RXD0
Port 3 (P3)
P3.7-0 General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have
bits 7-0 an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated
Port 3 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity.
SCK/SCL/CLKS
Clock Source Select. Refer to PASEL (SFR F2H).
bit 6
T1 Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1.
bit 5
T0 Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0.
bit 4
INT1
External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled.
bit 3
INT0
External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled.
bit 2
TXD0 Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the
bit 1 synchronizing clock in serial port mode 0.
RXD0 Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional
bit 0 data transfer pin in serial port mode 0.
Port 3 Data Direction Low Register (P3DDRL)
P3.3 Port 3 bit 3 control.
bits 7-6
P3.2 Port 3 bit 2 control.
bits 5-4
P3.1 Port 3 bit 1 control.
bits 3-2
P3.0 Port 3 bit 0 control.
bits 1-0
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Port 3 Data Direction High Register (P3DDRH)
7 6 5 4 3 2 1 0 Reset Value
SFR B4HP37H P37L P36H P36L P35H P35L P34H P34L 00H
P3.7 Port 3 bit 7 control.
bits 7-6
P3.6 Port 3 bit 6 control.
bits 5-4
P3.5 Port 3 bit 5 control.
bits 3-2
P3.4 Port 3 bit 4 control.
bits 1-0
P36H P36L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P35H P35L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P34H P34L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
P37H P37L
0 0 Standard 8051
0 1 CMOS Output
1 0 Open Drain Output
1 1 Input
7 6 5 4 3 2 1 0 Reset Value
SFR B5H00H
NOTE: Port 3.7 also controlled by
EA
and Memory Access Control HCR1.1.
NOTE: Port 3.6 also controlled by
EA
and Memory Access Control HCR1.1.
IDAC Register
IDAC IDAC Register.
bits 7-0 IDACOUT = IDAC • 3.8µA (~1mA full-scale). Setting (PDCON.PDIDAC) will shut down IDAC and float the IDAC pin.
Interrupt Priority (IP)
PS0 Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt.
bit 4 0 = Serial Port 0 priority is determined by the natural priority order.
1 = Serial Port 0 is a high priority interrupt.
PT1 Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt.
bit 3 0 = Timer 1 priority is determined by the natural priority order.
1 = Timer 1 priority is a high priority interrupt.
PX1 External Interrupt 1. This bit controls the priority of external interrupt 1.
bit 2 0 = External interrupt 1 priority is determined by the natural priority order.
1 = External interrupt 1 is a high priority interrupt.
PT0 Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt.
bit 1 0 = Timer 0 priority is determined by the natural priority order.
1 = Timer 0 priority is a high priority interrupt.
PX0 External Interrupt 0. This bit controls the priority of external interrupt 0.
bit 0 0 = External interrupt 0 priority is determined by the natural priority order.
1 = External interrupt 0 is a high priority interrupt.
7 6 5 4 3 2 1 0 Reset Value
SFR B8H1 0 0 PS0 PT1 PX1 PT0 PX0 80H
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Auxiliary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5).
EWUWDT Enable Wake Up Watchdog Timer. Wake up using watchdog timer interrupt.
bit 2 0 = Don’t wake up on watchdog timer interrupt.
1 = Wake up on watchdog timer interrupt.
EWUEX1 Enable Wake Up External 1. Wake up using external interrupt source 1.
bit 1 0 = Don’t wake up on external interrupt source 1.
1 = Wake up on external interrupt source 1.
EWUEX0 Enable Wake Up External 0. Wake up using external interrupt source 0.
bit 0 0 = Don’t wake up on external interrupt source 0.
1 = Wake up on external interrupt source 0.
System Clock Divider Register (SYSCLK)
Enable Wake Up (EWU) Waking Up from IDLE Mode
7 6 5 4 3 2 1 0 Reset Value
SFR C6H—— — — —EWUWDT EWUEX1 EWUEX0 00H
7 6 5 4 3 2 1 0 Reset Value
SFR C7H0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00H
DIVMOD DIVIDE MODE
00 Normal mode (default, no divide)
01 Immediate mode: start divide immediately, return to Normal mode on IDLE wakeup condition or Normal mode write.
10 Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is
enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not
enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the
MSINT counter overflows, which follows a wakeup condition. Can exit on Normal mode write.
11 Manual mode: start divide immediately; exit mode only on write to DIVMOD.
DIVMOD DIVISION MODE STATUS
00 No divide
01 Divider is in Immediate mode
10 Divider is in Delay mode
11 Reserved
DIV DIVISOR
000 Divide by 2 (default) fCLK = fSYS/2
001 Divide by 4 fCLK = fSYS/4
010 Divide by 8 fCLK = fSYS/8
011 Divide by 16 fCLK = fSYS/16
100 Divide by 32 fCLK = fSYS/32
101 Divide by 1024 fCLK = fSYS/1024
110 Divide by 2048 fCLK = fSYS/2048
111 Divide by 4096 fCLK = fSYS/4096
DIVMOD1-0 Clock Divide Mode
bits 5-4 Write:
Read:
DIV2-0 Divide Mode
bit 2-0
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ADC Offset Calibration Register Middle Byte (OCM)
7 6 5 4 3 2 1 0 Reset Value
SFR D2H00H
OCM ADC Offset Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC
bits 7-0 offset calibration. A value which is written to this location will set the ADC offset calibration value.
ADC Offset Calibration Register High Byte (OCH)
7 6 5 4 3 2 1 0 Reset Value
SFR D3HMSB 00H
OCH ADC Offset Calibration Register High Byte. This is the high byte of the 24-bit word that contains the
bits 7-0 ADC offset calibration. A value which is written to this location will set the ADC offset calibration value.
Program Status Word (PSW)
CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow
bit 7 (during subtraction). Otherwise it is cleared to 0 by all arithmetic operations.
AC Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into (during addition),
bit 6 or a borrow (during substraction) from the high order nibble. Otherwise it is cleared to 0 by all arithmetic
operations.
F0 User Flag 0. This is a bit-addressable, general-purpose flag for software control.
bit 5
RS1, RS0 Register Bank Select 1-0. These bits select which register bank is addressed during register accesses.
bits 4-3
OV Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow
bit 2 (subtraction), or overflow (multiply or divide). Otherwise it is cleared to 0 by all arithmetic operations.
F1 User Flag 1. This is a bit-addressable, general-purpose flag for software control.
bit 1
P Parity Flag. This bit is set to 1 if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity); and
bit 0 cleared to 0 on even parity.
ADC Offset Calibration Register Low Byte (OCL)
7 6 5 4 3 2 1 0 Reset Value
SFR D0HCY AC F0 RS1 RS0 OV F1 P 00H
RS1 RS0 REGISTER BANK ADDRESS
00 0 00
H-07H
01 1 08
H-0FH
10 2 10
H-17H
11 3 18
H-1FH
OCL ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the
bits 7-0 ADC offset calibration. A value which is written to this location will set the ADC offset calibration value.
7 6 5 4 3 2 1 0 Reset Value
SFR D1HLSB 00H
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GCM ADC Gain Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains
bits 7-0 the ADC gain calibration. A value which is written to this location will set the ADC gain calibration value.
ADC Gain Calibration Register High Byte (GCH)
7 6 5 4 3 2 1 0 Reset Value
SFR D5HECH
GCH ADC Gain Calibration Register High Byte. This is the high byte of the 24-bit word that contains the
bits 7-0 ADC gain calibration. A value which is written to this location will set the ADC gain calibration value.
ADC Multiplexer Register (ADMUX)
7 6 5 4 3 2 1 0 Reset Value
SFR D6HMSB 5FH
INP3-0 Input Multiplexer Positive Channel. This selects the positive signal input.
bits 7-4
7 6 5 4 3 2 1 0 Reset Value
SFR D7HINP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01H
INP3 INP2 INP1 INP0 POSITIVE INPUT
0000AIN0 (default)
0001AIN1
0010AIN2
0011AIN3
0100AIN4
0101AIN5
0110REFIN–
0111REFIN–
1000AINCOM
1111Temperature Sensor (requires ADMUX = FFH)
INN3-0 Input Multiplexer Negative Channel. This selects the negative signal input.
bits 3-0 INN3 INN2 INN1 INN0 NEGATIVE INPUT
0000AIN0
0001AIN1 (default)
0010AIN2
0011AIN3
0100AIN4
0101AIN5
0110REFIN–
0111REFIN–
1000AINCOM
1111Temperature Sensor (requires ADMUX = FFH)
ADC Gain Calibration Register Middle Byte (GCM)
GCL ADC Gain Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC
bits 7-0 gain calibration. A value which is written to this location will set the ADC gain calibration value.
7 6 5 4 3 2 1 0 Reset Value
SFR D4HLSB 5AH
ADC Gain Calibration Register Low Byte (GCL)
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ADRESL The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC
bits 7-0 Results. Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared.
ADC Results Register Middle Byte (ADRESM)
7 6 5 4 3 2 1 0 Reset Value
SFR D9HLSB 00H
7 6 5 4 3 2 1 0 Reset Value
SFR DAH00H
ADRESM The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the ADC
bits 7-0 Results.
ADC Results Register High Byte (ADRESH)
ADRESH The ADC Results High Byte. This is the high byte of the 24-bit word that contains the ADC
bits 7-0 Results.
7 6 5 4 3 2 1 0 Reset Value
SFR DBHMSB 00H
7 6 5 4 3 2 1 0 Reset Value
SFR D8H0 1 EAI AI WDTI 0 0 0 40H
Enable Interrupt Control (EICON)
EAI Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and
bit 5 identified by SFR registers PAI (SFR A5H), AIE (SFR A6H), and AISTAT (SFR A7H).
0 = Auxiliary Interrupt disabled (default).
1 = Auxiliary Interrupt enabled.
AI Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine,
bit 4 after the source of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates
an Auxiliary Interrupt, if enabled.
0 = No Auxiliary Interrupt detected (default).
1 = Auxiliary Interrupt detected.
WDTI Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine.
bi t 3 Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The
Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabledin HCR0.
0 = No Watchdog Timer Interrupt Detected (default).
1 = Watchdog Timer Interrupt Detected.
ADC Results Register Low Byte (ADRESL)
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ADC Control Register 0 (ADCON0)
7 6 5 4 3 2 1 0 Reset Value
SFR DCH—BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30H
BOD Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative current
bit 6 source to the negative channel. If the channel is open circuit then the ADC results will be full-scale (buffer must be enabled).
0 = Burnout Current Sources Off (default).
1 = Burnout Current Sources On.
EVREF Enable Internal Voltage Reference. If an external voltage reference is used, the internal voltage reference should
bit 5 be disabled.
0 = Internal Voltage Reference Off.
1 = Internal Voltage Reference On (default).
VREFH Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V.
bit 4 0 = REFOUT/REFIN+ is 1.25V.
1 = REFOUT/REFIN+ is 2.5V (default).
EBUF Enable Buffer. Enable the input buffer to provide higher input impedance but limits the input voltage range and
bit 3 dissipates more power.
0 = Buffer disabled (default).
1 = Buffer enabled.
PGA2-0 Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128.
bits 2-0 PGA2 PGA1 PGA0 GAIN
0 0 0 1 (default)
00 1 2
01 0 4
01 1 8
10 016
10 132
11 064
1 1 1 128
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SM1 SM0 SETTLING MODE
0 0 Auto
0 1 Fast Settling Filter
1 0 Sinc2 Filter
1 1 Sinc3 Filter
ADC Control Register 1 (ADCON1)
POL Polarity. Polarity of the ADC result and Summation register.
bit 6 0 = Bipolar.
1 = Unipolar.
7 6 5 4 3 2 1 0 Reset Value
SFR DDH—POL SM1 SM0 —CAL2 CAL1 CAL0 x000 0000B
POL ANALOG INPUT DIGITAL OUTPUT
+FSR 0x7FFFFF
0ZERO 0x000000
–FSR 0x800000
+FSR 0xFFFFFF
1ZERO 0x000000
–FSR 0x000000
SM1-0 Settling Mode. Selects the type of filter or auto select which defines the digital filter settling characteristics.
bits 5-4
CAL2-0 Calibration Mode Control Bits. Writing to this register initiates calibration.
bits 2-0
ADC Control Register 2 (ADCON2)
CAL2 CAL1 CAL0 CALIBRATION MODE
0 0 0 No Calibration (default)
0 0 1 Self Calibration, Offset and Gain
0 1 0 Self Calibration, Offset Only
0 1 1 Self Calibration, Gain Only
1 0 0 System Calibration, Offset Only
1 0 1 System Calibration, Gain Only
1 1 0 Reserved
1 1 1 Reserved
DR7-0 Decimation Ratio LSB (refer to ADCON3, SFR DFH).
bits 7-0
ADC Control Register 3 (ADCON3)
7 6 5 4 3 2 1 0 Reset Value
SFR DEHDR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1BH
DR10-8 Decimation Ratio Most Significant 3 Bits. The output data rate =
f
DecimationRatio
MOD
where f
MOD
=
f
ACLK
CLK
()+•164
.
bits 2-0
Accumulator (A or ACC)
7 6 5 4 3 2 1 0 Reset Value
SFR E0HACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00H
ACC.7-0 Accumulator. This register serves as the accumulator for arithmetic and logic operations.
bits 7-0
7 6 5 4 3 2 1 0 Reset Value
SFR E1HSSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00H
Read Value—000B.
7 6 5 4 3 2 1 0 Reset Value
SFR DFH—— — — —DR10 DR9 DR8 06H
Summation/Shifter Control (SSCON)
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit
SUMR3-0 registers will be cleared. The Summation registers will do sign extend if Bipolar is selected in ADCON1.
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SHF2-0 Shift Count.
bits 2-0
SUMR0 Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7.
bits 7-0 Write: will cause values in SUMR3-0 to be added to or subtracted from the summation register.
Read: will clear the Summation Interrupt.
Summation Register 1 (SUMR1)
SHF2 SHF1 SHF0 SHIFT DIVIDE
000 1 2
001 2 4
010 3 8
011 4 16
100 5 32
101 6 64
1 1 0 7 128
1 1 1 8 256
7 6 5 4 3 2 1 0 Reset Value
SFR E2HLSB 00H
SU MR 1 Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8-15.
bits 7-0
Summation Register 2 (SUMR2)
7 6 5 4 3 2 1 0 Reset Value
SFR E3H00H
SUM R2 Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16-23.
bits 7-0
7 6 5 4 3 2 1 0 Reset Value
SFR E4H00H
SSCON1-0 Summation/Shift Control.
bits 7-6
SCNT2-0 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the
bits 5-3 SUMR0 register clears the interrupt.
SCNT2 SCNT1 SCNT0 SUMMATION COUNT
000 2
001 4
010 8
011 16
100 32
101 64
1 1 0 128
1 1 1 256
SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 DESCRIPTION
0 0 0 0 0 0 0 0 Clear Summation Register
0 0 0 1 0 0 0 0 CPU Summation on Write to SUMR0
0 0 1 0 0 0 0 0 CPU Subtraction on Write to SUMR0
1 0 x x x Note (1) Note (1) Note (1) CPU Shift Only
0 1 Note (1) Note (1) Note (1) x x x ADC Summation Only
1 1 Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) ADC Summation Completes then Shift Completes
NOTES: (1) Refer to register bit definition.
7 6 5 4 3 2 1 0 Reset Value
SFR E5HMSB 00H
Summation Register 3 (SUMR3)
SUMR3 Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24-31.
bits 7-0
Summation Register 0 (SUMR0)
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PRODUCT PREVIEW
Low Voltage Detect Control (LVDCON)
ALVDIS Analog Low Voltage Detect Disable.
bit 7 0 = Enable Detection of Low Analog Supply Voltage (ALVD interrupt set when AVDD < 2.8V).
1 = Disable Detection of Low Analog Supply Voltage.
7 6 5 4 3 2 1 0 Reset Value
SFR E7HALVDIS 0 0 0 1 1 1 1 8FH
Extended Interrupt Enable (EIE)
7 6 5 4 3 2 1 0 Reset Value
SFR E8H1 1 1 EWDI EX5 EX4 EX3 EX2 E0H
EWDI Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by
the WDTCON (SFR FFH) and PDCON (SFR F1H) registers.
bit 4 0 = Disable the Watchdog Interrupt
1 = Enable Interrupt Request Generated by the Watchdog Timer
EX5 External Interrupt 5 Enable. This bit enables/disables external interrupt 5.
bit 3 0 = Disable External Interrupt 5
1 = Enable External Interrupt 5
EX4 External Interrupt 4 Enable. This bit enables/disables external interrupt 4.
bit 2 0 = Disable External Interrupt 4
1 = Enable External Interrupt 4
EX3 External Interrupt 3 Enable. This bit enables/disables external interrupt 3.
bit 1 0 = Disable External Interrupt 3
1 = Enable External Interrupt 3
EX2 External Interrupt 2 Enable. This bit enables/disables external interrupt 2.
bit 0 0 = Disable External Interrupt 2
1 = Enable External Interrupt 2
Offset DAC Register (ODAC)
ODAC Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The offset
bit7-0 DAC value is summed from the ADC input prior to conversion. Writing 00H or 80H to ODAC turns off the Offset DAC.
bit 7 Offset DAC Sign bit.
0 = Positive
1 = Negative
bit 6-0 Offset =
VPGA ODAC
REF bit
260
127 17
••
•−
[:] ()
NOTE: The offset must be used after calibration or the calibration will nullify the effects.
7 6 5 4 3 2 1 0 Reset Value
SFR E6H00H
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PRODUCT PREVIEW
Hardware Product Code Register 0 (HWPC0)
HWPC0.7-0 Hardware Product Code LSB. Read only.
bits 7-0
7 6 5 4 3 2 1 0 Reset Value
SFR E9H0 0 0 0 0 0 0 MEMORY 0000_000xB
7 6 5 4 3 2 1 0 Reset Value
SFR EAH00 1000 00 20
H
HWPC1.7-0 Hardware Product Code MSB. Read only.
bits 7-0
Hardware Version Register (HWVER)
PGERA Page Erase. Available in both user and program modes.
bit 6 0 = Disable Page Erase Mode
1 = Enable Page Erase Mode
FRCM Frequency Control Mode. The bypass is only used for slow clocks to save power.
bit 4 0 = Bypass (default)
1 = Use Delay Line. Saves power (Recommended).
BUSY Write/Erase BUSY Signal.
bit 2 0 = Idle or Available
1 = Busy
Flash Memory Timing Control Register (FTCON)
7 6 5 4 3 2 1 0 Reset Value
SFR EEH0 PGERA 0 FRCM 0 BUSY 1 0 02H
7 6 5 4 3 2 1 0 Reset Value
SFR EFHFER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5H
MEMORY SIZE MODEL FLASH MEMORY
0 MSC1201Y2 4kB
1 MSC1201Y3 8kB
Hardware Product Code Register 1 (HWPC1)
Refer to Flash Timing Characteristics
FER3-0 Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • tCLK.
bits 7-4 11ms industrial temperature range.
5ms commercial temperature range.
FWR3-0 Set Write. Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK.
bits 3-0 30µs to 40µs.
7 6 5 4 3 2 1 0 Reset Value
SFR EBH
Flash Memory Control (FMCON)
B Register (B)
B B Register. This register serves as a second accumulator for certain arithmetic operations.
bits 7-0
7 6 5 4 3 2 1 0 Reset Value
SFR F0H00H
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PSEN4-0
PSEN
Mode Select. Defines the output on P3.6 in User Application mode or Serial Flash Programming mode.
bits 7-3 00000: General-Purpose I/O (default)
00001: SYSCLK
00011: Internal
PSEN
(refer to Figure 3 for timing)
00101: Internal ALE (refer to Figure 3 for timing)
00111: fOSC(buffered XIN oscillator clock)
01001: Memory
WR
(MOVX write)
01011: T0 Out (overflow)(1)
01101: T1 Out (overflow)(1)
01111: fMOD(2)
10001: SYSCLK/2 (toggles on rising edge)(2)
10011: Internal
PSEN
/2(2)
10101: Internal ALE/2(2)
10111: fOSC/2(2)
11001: Memory
WR
/2 (MOVX write)(2)
11011: T0 Out/2 (overflow)(2)
11101: T1 Out/2 (overflow)(2)
11111: fMOD/2(2)
NOTES: (1) On period of these signals equal to tCLK. (2) Duty cycle is 50%.
7 6 5 4 3 2 1 0 Reset Value
SFR F1HPDICLK PDIDAC PDI2C 0 PDADC PDWDT PDSPI PDSPI 6FH
Turning peripheral modules off puts the MSC1201 in the lowest power mode.
PDICLK Internal Clock Control.
bit 7 0 = Internal Oscillator and PLL On (Internal Oscillator or PLL mode)
1 = Internal Oscillator and PLL Power Down (External Clock mode)
PDIDAC IDAC Control.
bit 6 0 = IDAC On
1 = IDAC Power Down (default)
PDI2C I2C Control.
bit 5 0 = I2C On (only when PDSPI = 1)
1 = I2C Power Down (default)
PDADC ADC Control.
bit 3 0 = ADC On
1 = ADC, VREF, and Summation registers are powered down (default).
PDWDT Watchdog Timer Control.
bit 2 0 = Watchdog Timer On
1 = Watchdog Timer Power Down (default)
PDST System Timer Control.
bit 1 0 = System Timer On
1 = System Timer Power Down (default)
PDSPI SPI Control.
bit 0 0 = SPI System On
1 = SPI System Power Down (default)
PSEN
/ALE Select (PASEL)
7 6 5 4 3 2 1 0 Reset Value
SFR F2HPSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00H
Power-Down Control Register (PDCON)
MSC1201 55
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PRODUCT PREVIEW
Analog Clock (ACLK)
FREQ6-0 Clock Frequency – 1. This value + 1 divides the system clock to create the ADC clock.
bits 6-0 fACLK =
f
ACLK
CLK
()+1
, where fCLK =
f
SYSCLKDivider
OSC
.
fMOD = fACLK
64
ADC Data Rate = fDATA =
f
DecimationRatio
MOD
System Reset Register (SRST)
7 6 5 4 3 2 1 0 Reset Value
SFR F7H0 0 0 0 0 0 0 RSTREQ 00H
7 6 5 4 3 2 1 0 Reset Value
SFR F6H0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03H
RSTREQ Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset.
bit 0
PLL7-0 PLL Counter Value Least Significant Bit.
bits 7-0
PLL Frequency = External Crystal Frequency • PLL9:0
Phase Lock Loop High Register (PLLH)
7 6 5 4 3 2 1 0 Reset Value
SFR F4HPLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 C1H
Phase Lock Loop Low Register (PLLL)
7 6 5 4 3 2 1 0 Reset Value
SFR F5HCLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK 0 0 PLL9 PLL8 x1H
CLKSTAT2-0 Active Clock Status (read only). Derived from HCR2 setting; refer to Table II.
bits 7-5 000: Reserved
001: Reserved
010: Reserved
011: External Clock Mode
100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status)
101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status)
110: Internal Oscillator High-Frequency (HF) Mode
111: Internal Oscillator Low-Frequency (LF) Mode
PLLLOCK PLL Lock Status and Status Enable.
bit 4 For Write (PLL Lock Status Enable):
0 = No Effect
1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid).
For Read (PLL Lock Status):
0 = PLL Not Locked (PLL may be inactive; refer to Table II for active clock mode)
1 = PLL Locked (PLL is active clock)
PLL9-8 PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4H)
bits 1-0
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The clock used for this timer is the 1ms clock which results from dividing the system clock by the values in registers MSECH:MSECL.
Reading this register will clear MSINT.
W RT Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0.
bit 7 0 = Delay Write Operation. The MSINT value is loaded when the current count expires.
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.
MSINT6-0 Seconds Count. Normal operation would use 1ms as the clock interval.
bits 6-0 MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • tCLK
7 6 5 4 3 2 1 0 Reset Value
SFR FAHWRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7FH
Milliseconds Interrupt (MSINT)
7 6 5 4 3 2 1 0 Reset Value
SFR F8H1 1 1 PWDI PX5 PX4 PX3 PX2 E0H
7 6 5 4 3 2 1 0 Reset Value
SFR F9HWRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7FH
This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then that 1ms timer tick is divided by the register
HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt
which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt. This Interrupt can be monitored
in the AIE register.
WRT Write Control. Determines whether to write the value immediately or wait until the current count is finished.
bit 7 Read = 0.
0 = Delay Write Operation. The SEC value is loaded when the current count expires.
1 = Write Immediately. The counter is loaded once the CPU completes the write operation.
SECINT6-0 Seconds Count. Normal operation would use 100ms as the clock interval.
bits 6-0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • tCLK.
PWDI Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt.
bit 4 0 = The watchdog interrupt is low priority.
1 = The watchdog interrupt is high priority.
PX5 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5.
bit 3 0 = External interrupt 5 is low priority.
1 = External interrupt 5 is high priority.
PX4 External Interrupt 4 Priority. This bit controls the priority of external interrupt 4.
bit 2 0 = External interrupt 4 is low priority.
1 = External interrupt 4 is high priority.
PX3 External Interrupt 3 Priority. This bit controls the priority of external interrupt 3.
bit 1 0 = External interrupt 3 is low priority.
1 = External interrupt 3 is high priority.
PX2 External Interrupt 2 Priority. This bit controls the priority of external interrupt 2.
bit 0 0 = External interrupt 2 is low priority.
1 = External interrupt 2 is high priority.
Seconds Timer Interrupt (SECINT)
Extended Interrupt Priority (EIP)
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FREQ5-0 Clock Frequency – 1. This value + 1 divides the system clock to create a 1µs Clock.
bits 5-0 USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFH).
One Millisecond Low Register (MSECL)
MSECL7-0 One Millisecond Low. This value in combination with the next register is used to create a 1ms Clock.
bits 7-0 1ms Clock = (MSECH • 256 + MSECL + 1) • tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFH).
One Millisecond High Register (MSECH)
7 6 5 4 3 2 1 0 Reset Value
SFR FBH0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03H
7 6 5 4 3 2 1 0 Reset Value
SFR FDHMSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0FH
7 6 5 4 3 2 1 0 Reset Value
SFR FCHMSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9FH
MSECH7-0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock.
bits 7-0 1ms = (MSECH • 256 + MSECL + 1) • tCLK.
One Hundred Millisecond Register (HMSEC)
7 6 5 4 3 2 1 0 Reset Value
SFR FEHHMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63H
7 6 5 4 3 2 1 0 Reset Value
SFR FFHEWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00H
HMSEC7-0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock.
bits 7-0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • tCLK.
Watchdog Timer Register (WDTCON)
EWDT Enable Watchdog (R/W).
bit 7 Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.
DWDT Disable Watchdog (R/W).
bit 6 Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.
RWDT Reset Watchdog (R/W).
bit 5 Write 1/Write 0 sequence restarts the Watchdog Counter.
WDCNT4-0 Watchdog Count (R/W).
bits 4-0 Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There
is an uncertainty of 1 count.
NOTE: If HCR0.3 (EWDR) is set and the watchdog timer expires, a system reset is generated. If HCR0.3 (EWDR) is cleared
and the watchdog timer expires, an interrupt is generated (see Table VII).
One Microsecond Register (USEC)
PACKAGING INFORMATION
ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY
MSC1201Y2RHHR PREVIEW QFN RHH 36 2500
MSC1201Y2RHHT PREVIEW QFN RHH 36 250
MSC1201Y3RHHR PREVIEW QFN RHH 36 2500
MSC1201Y3RHHT PREVIEW QFN RHH 36 250
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Aug-2004
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