© Semiconductor Components Industries, LLC, 2014
March, 2017 − Rev. 2
1Publication Order Number:
KAI−4021/D
KAI-4021
2048 (H) x 2048 (V) Interline
CCD Image Sensor
Description
The KAI−4021 Image Sensor is a high-performance 4-million pixel
sensor designed for a wide range of medical, scientific and machine
vision applications. The 7.4 mm square pixels with microlenses
provide high sensitivity and the large full well capacity results in high
dynamic range. The two high-speed outputs and binning capabilities
allow for 16−50 frames per second (fps) video rate for the
progressively scanned images. The vertical overflow drain structure
provides antiblooming protection and enables electronic shuttering for
precise exposure control. Other features include low dark current,
negligible lag and low smear.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture Interline CCD, Progressive Scan
Total Number of Pixels 2112 (H) × 2072 (V) = approx. 4.38M
Number of Effective Pixels 2056 (H) × 2062 (V) = approx. 4.24M
Number of Active Pixels 2048 (H) × 2048 (V) = approx. 4.19M
Pixel Size 7.4 mm (H) × 7.4 mm (V)
Imager Size 21.43 mm (Diagonal),
Chip Size 16.67 mm (H) × 16.05 mm (V)
Aspect Ratio 1:1
Number of Outputs 1 or 2
Saturation Signal 40,000 e−
Peak Quantum Efficiency
−ABA
−CBA (BGR)
55%
45%, 42%, 35%
Output Sensitivity 31 mV/e−
Total System Noise
40 MHz
20 MHz
25 e−
12 e−
Dark Current < 0.5 nA/cm2
Dark Current Doubling
Temperature
7°C
Dynamic Range 60 dB
Charge Transfer Efficiency > 0.99999
Blooming Suppression 300X
Smear 80 dB
Image Lag < 10 e−
Maximum Data Rate 40 MHz
Package 34-pin, cerDIP
Cover Glass AR Coated, 2 Sides
NOTE: All parameters above are specified at T = 40°C.
Features
•High Resolution
•High Sensitivity
•High Dynamic Range
•Low Noise Architecture
•High Frame Rate
•Binning Capability for Higher Frame Rate
•Electronic Shutter
Applications
•Machine Vision
www.onsemi.com
Figure 1. KAI−4021 Interline CCD
Image Sensor
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
KAI−4021
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2
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−4021 IMAGE SENSOR
Part Number Description Marking Code
KAI−4021−AAA−CR−BA Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade
KAI−4021
Serial Number
KAI−4021−AAA−CR−AE Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
KAI−4021−ABA−CD−BA Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−4021M
Serial Number
KAI−4021−ABA−CD−AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−4021−ABA−CR−BA Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade
KAI−4021−ABA−CR−AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
KAI−4021−CBA−CD−BA* Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−4021CM
Serial Number
KAI−4021−CBA−CD−AE* Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−4021−CBA−CR−BA* Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−4021−CBA−CR−AE* Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (Both Sides), Engineering Grade
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number Description
KAI−4011−10−40−A−EVK Evaluation Board, (Complete Kit)
KAI−4021−10−40−A−EVK Evaluation Board, (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
KAI−4021
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3
DEVICE DESCRIPTION
Architecture
Figure 2. Sensor Architecture
4Buffer Rows
2048 (H) x 2048 (H)
Active Pixels
6 Buffer Rows
10 Dark Rows
8 Buffer Rows
4 Buffer Columns
28 Dark Columns
28 Dark Columns
12 Dummy Pixels
12 Dummy Pixels
4 Buffer Columns
Pixel
1,1
Dual
Output
or
Video L Video R
12 28 4 2048 4 28 12
Single
12 28 4 1024 1024 4 28 12
G
G
R
B
G
G
R
B
G
G
R
B
G
G
R
B
G
G
R
B
G
G
R
B
G
G
R
B
G
G
R
B
There are 10 light shielded rows followed 2062
photoactive rows. The first 6 and the last 8 photoactive rows
are buffer rows giving a total of 2048 lines of image data.
In the single output mode all pixels are clocked out of the
Video L output in the lower left corner of the sensor. The first
12 empty pixels of each line do not receive charge from the
vertical shift register. The next 28 pixels receive charge from
the left light−shielded edge followed by 2056
photo−sensitive pixels and finally 28 more light shielded
pixels from the right edge of the sensor. The first and last 4
photosensitive pixels are buffer pixels giving a total of 2048
pixels of image data.
In the dual output mode the clocking of the right half of the
horizontal CCD is reversed. The left half of the image is
clocked out Video L and the right half of the image is clocked
out Video R. Each row consists of 12 empty pixels followed
by 28 light shielded pixels followed by 1028 photosensitive
pixels. When reconstructing the image, data from Video R
will have to be reversed in a line buffer and appended to the
Video L data.
There are no dark reference rows at the top and 10 dark
rows at the bottom of the image sensor. The 10 dark rows are
not entirely dark and so should not be used for a dark
reference level. Use the 28 dark columns on the left or right
side of the image sensor as a dark reference.
Of the 28 dark columns, the first and last dark columns
should not be used for determining the zero signal level.
Some light does leak into the first and last dark columns.
Only use the center 26 columns of the 28 column dark
reference.
KAI−4021
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4
Pixel
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
Figure 3. Pixel Architecture
Top View
Direction
of
Charge
Transfer
True Two Phase Burried Channel VCCD
Lightshield over VCCD not shown
V1
Photodiode
V2
Transfer
Gate
ËËËËË
ËËËËË
Direction of
Charge
Transfer
ÉÉ
ÉÉ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
É
V1
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
V2
É
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ËËËËË
ËËËËË
V1
n−
n
n−n−
p Well (GND)
Cross Section Down Through VCCD
n Substrate
p
V1
n
p+
Light Shield
p
p
n
p
Cross Section Through
Photodiode and VCCD Phase 1
Photodiode
pp
V2
n
p+
Light Shield
p
p
n
n Substrate
p
Cross Section Through Photodiode
and VCCD Phase 2 at Transfer Gate
Transfer
Gate
Cross Section Showing Lenslet
Lenslet
VCCD VCCD
Light Shield Light Shield
Photodiode
Red Color Filter
NOTE: Drawings not scale.
7.4 mm
7.4 mm
n Substrate
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non−linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
KAI−4021
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5
Vertical to Horizontal Transfer
Figure 4. Vertical to Horizontal Transfer Architecture
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
Top View
Direction of
Vertical
Charge
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
Transfer
V1
ËËËËËË
ËËËËËË
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
V2
V1
Photodiode
ËËËËËË
ËËËËËË
V2
Transfer
Gate
ËËËËËË
ËËËËËË
Fast
Line
Dump
H1S
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
Direction of
Horizontal
Charge Transfer
Lightshield
Not Shown
H2B
H2S
H1B
When the V1 and V2 timing inputs are pulsed, charge in
every pixel of the VCCD is shifted one row towards the
HCCD. The last row next to the HCCD is shifted into the
HCCD. When the VCCD is shifted, the timing signals to the
HCCD must be stopped. H1 must be stopped in the high state
and H2 must be stopped in the low state. The HCCD
clocking may begin THD ms after the falling edge of the V1
and V2 pulse.
Charge is transferred from the last vertical CCD phase into
the H1S horizontal CCD phase. Refer to Figure 36 for an
example of timing that accomplishes the vertical to
horizontal transfer of charge.
If the fast line dump is held at the high level (FDH) during
a vertical to horizontal transfer, then the entire line is
removed and not transferred into the horizontal register.
KAI−4021
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6
Horizontal Register to Floating Diffusion
Figure 5. Horizontal Register to Floating Diffusion Architecture
n+
R OG H2S H1S H1B H2S H2B H1S
n−n−n−
RD
Floating
Diffusion
n (burried channel)
n
n+
p (GND)
n (SUB)
H2B
The HCCD has a total of 2124 pixels. The 2112 vertical
shift registers (columns) are shifted into the center 2112
pixels of the HCCD. There are 12 pixels at both ends of the
HCCD, which receive no charge from a vertical shift
register. The first 12 clock cycles of the HCCD will be empty
pixels (containing no electrons). The next 28 clock cycles
will contain only electrons generated by dark current in the
VCCD and photodiodes. The next 2056 clock cycles will
contain photo−electrons (image data). Finally, the last 28
clock cycles will contain only electrons generated by dark
current in the VCCD and photodiodes. Of the 28 dark
columns, the first and last dark columns should not be used
for determining the zero signal level. Some light does leak
into the first and last dark columns. Only use the center 26
columns of the 28 column dark reference.
When the HCCD is shifting valid image data, the timing
inputs to the electronic shutter (SUB), VCCD (V1, V2), and
fast line dump (FD) should be not be pulsed. This prevents
unwanted noise from being introduced. The HCCD is a type
of charge coupled device known as a pseudo−two phase
CCD. This type of CCD has the ability to shift charge in two
directions. This allows the entire image to be shifted out to
the video L output, or to the video R output (left/right image
reversal). The HCCD is split into two equal halves of 1068
pixels each. When operating the sensor in single output
mode the two halves of the HCCD are shifted in the same
direction. When operating the sensor in dual output mode
the two halves of the HCCD are shifted in opposite
directions. The direction of charge transfer in each half is
controlled by the H1BL, H2BL, H1BR, and H2BR timing
inputs.
KAI−4021
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7
Horizontal Register Split
Figure 6. Horizontal Register
Single Output
H2SL
H1SL H1BL H2SRH1SR H2BR
H1BR
Pixel
1068
Pixel
1069
H2SL H2BLH1BL
H1 H1 H1 H1 H1H2 H2 H2 H2 H2
H2SL
H1SL H1BL H2SRH1SR H2BR
H1BR
Pixel
1068
Pixel
1069
H2SL H2BLH1BL
H1 H1 H1 H1 H2H2 H2 H2 H1 H2
Dual Output
Single Output Operation
When operating the sensor in single output mode all pixels
of the image sensor will be shifted out the Video L output
(pin 12). To conserve power and lower heat generation the
output amplifier for Video R may be turned off by
connecting VDDR (pin 24) and VOUTR (pin 23) to GND
(zero volts).
The H1 timing from the timing diagrams should be
applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing
should be applied to H2SL, H2BL, H2SR, and H1BR. In
other words, the clock driver generating the H1 timing
should be connected to pins 16, 15, 19, and 21. The clock
driver generating the H2 timing should be connected to pins
17, 14, 18, and 20. The horizontal CCD should be clocked
for 12 empty pixels plus 28 light shielded pixels plus 2056
photoactive pixels plus 28 light shielded pixels for a total of
2124 pixels.
Dual Output Operation
In dual output mode the connections to the H1BR and
H2BR pins are swapped from the single output mode to
change the direction of charge transfer of the right side
horizontal shift register. In dual output mode both VDDL
and VDDR (pins 11, 24) should be connected to 15 V. The
H1 timing from the timing diagrams should be applied to
H1SL, H1BL, H1SR, H1BR, and the H2 timing should be
applied to H2SL, H2BL, H2SR, and H2BR. The clock driver
generating the H1 timing should be connected to pins 16, 15,
19, and 20. The clock driver generating the H2 timing should
be connected to pins 17, 14, 18, and 21. The horizontal CCD
should be clocked for 12 empty pixels plus 28 light shielded
pixels plus 1028 photoactive pixels for a total of 1068 pixels.
If the camera is to have the option of dual or single output
mode, the clock driver signals sent to H1BR and H2BR may
be swapped by using a relay. Another alternative is to have
two extra clock drivers for H1BR and H2BR and invert the
signals in the timing logic generator. If two extra clock
drivers are used, care must be taken to ensure the rising and
falling edges of the H1BR and H2BR clocks occur at the
same time (within 3 ns) as the other HCCD clocks.
KAI−4021
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8
Output
Figure 7. Output Architecture
Floating
Diffusion
HCCD
Charge
Transfer
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
RD
R
OG
H2S
H1S
H1B
H2S
H2B
VDD
VOUT
H2B
Charge packets contained in the horizontal register are
dumped pixel by pixel onto the floating diffusion (FD)
output node whose potential varies linearly with the quantity
of charge in each packet. The amount of potential charge is
determined by the expression DVFD =DQ/C
FD.
A three-stage source-follower amplifier is used to buffer
this signal voltage off chip with slightly less than unity gain.
The translation from the charge domain to the voltage
domain is quantified by the output sensitivity or charge to
voltage conversion in terms of microvolts per electron
(mV/e−). After the signal has been sampled off chip, the reset
clock (R) removes the charge from the floating diffusion and
resets its potential to the reset drain voltage (RD).
When the image sensor is operated in the binned or
summed interlaced modes there will be more than 20,000 e−
in the output signal. The image sensor is designed with
a31mV/e− charge to voltage conversion on the output. This
means a full signal of 20,000 electrons will produce
a 640 mV change on the output amplifier. The output
amplifier was designed to handle an output swing of 640 mV
at a pixel rate of 40 MHz. If 40,000 electron charge packets
are generated in the binned or summed interlaced modes
then the output amplifier output will have to swing
1,280 mV. The output amplifier does not have enough
bandwidth (slew rate) to handle 1,280 mV at 40 MHz.
Hence, the pixel rate will have to be reduced to 20 MHz if
the full dynamic range of 40,000 electrons is desired.
The charge handling capacity of the output amplifier is
also set by the reset clock voltage levels. The reset clock
driver circuit is very simple, if an amplitude of 5 V is used.
But the 5 V amplitude restricts the output amplifier charge
capacity to 20,000 electrons. If the full dynamic range of
40,000 electrons is desired then the reset clock amplitude
will have to be increased to 7 V.
If you only want a maximum signal of 20,000 electrons in
binned or summed interlaced modes, then a 40 MHz pixel
rate with a 5 V reset clock may be used. The output of the
amplifier will be unpredictable above 20,000 electrons so be
sure to set the maximum input signal level of your analog to
digital converter to the equivalent of 20,000 electrons
(640 mV).
The following table summarizes the previous explanation
on the output amplifier’s operation. Certain trade−offs can
be made based on application needs such as Dynamic Range
or Pixel frequency.
KAI−4021
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9
Table 4.
Pixel Frequency
(MHz)
Reset Clock
Amplitude (V) Output Gate (V)
Saturation Signal
(mV)
Saturation Signal
(ke−)
Dynamic Range
(dB) Notes
40 5 −2 640 20 60
20 5 −2 640 20 64
20 7 −3 1280 40 70
20 7 −3 2560 80 76 1
1. 80,000 electrons achievable in summed interlaced or binning modes.
ESD Protection
Figure 8. ESD Protection
RL H1SL H2SL H1BL H2BL OGL
RR H1SR H2SR H1BR H2BR
ESD
VSUB
D1
D2 D2 D2 D2 D2
D2D2D2D2D2D2
OGR
D2
The ESD protection on the KAI−4021 is implemented
using bipolar transistors. The substrate (VSUB) forms the
common collector of all the ESD protection transistors. The
ESD pin is the common base of all the ESD protection
transistors. Each protected pin is connected to a separate
emitter as shown in Figure 8.
The ESD circuit turns on if the base−emitter junction
voltage exceeds 17 V. Care must be taken while operating
the image sensor, especially during the power on sequence,
to not forward bias the base−emitter or base−collector
junctions. If it is possible for the camera power up sequence
to forward bias these junctions then diodes D1 and D2
should be added to protect the image sensor. Put one diode
D1 between the ESD and VSUB pins. Put one diode D2 on
each pin that may forward bias the base−emitter junction.
The diodes will prevent large currents from flowing through
the image sensor. Note that external diodes D1 and D2 are
optional and are only needed if it is possible to forward bias
any of the junctions.
Note that diodes D1 and D2 are added external to the
KAI−4021.
KAI−4021
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Pin Description and Physical Orientation
Figure 9. Package Pin Designations − Top View
GND
V2E
SUB
V2O
V1E
V1O
SUB
FD
OGR
GND
RDR
VDDR
VOUTR
RR
H2BR
H1BR
H1SR
H2SR
V2E
V2O
V1E
V1O
ESD
GND
OGL
GND
RDL
VDDL
VOUTL
RL
H2BL
H1BL
H1SL
H2SL
1
2
3
4
5
6
Pixel 1,1
7
8
18
9
10
11
12
13
14
15
16
17
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Table 5. PIN DESCRIPTION
Pin Name Description
1 SUB Substrate
2 V2E Vertical Clock, Phase 2, Even
3 V2O Vertical Clock, Phase 2, Odd
4 V1E Vertical Clock, Phase 1, Even
5 V1O Vertical Clock, Phase 1, Odd
6 ESD ESD
7 GND Ground
8 OGL Output Gate, Left
9 GND Ground
10 RDL Reset Drain, Left
11 VDDL VDD, Left
12 VOUTL Video Output, Left
13 RL Reset Gate, Left
14 H2BL H2 Barrier, Left
15 H1BL H1 Barrier, Left
16 H1SL H1 Storage, Left
17 H2SL H2 Storage, Left
Pin Name Description
18 H2SR H2 Storage, Right
19 H1SR H1 Storage, Right
20 H1BR H1 Barrier, Right
21 H2BR H2 Barrier, Right
22 RR Reset Gate, Right
23 VOUTR Video Output, Right
24 VDDR VDD, Right
25 RDR Reset Drain, Right
26 GND Ground
27 OGR Output Gate, Right
28 FD Fast Line Dump Gate
29 SUB Substrate
30 V1O Vertical Clock, Phase 1, Odd
31 V1E Vertical Clock, Phase 1, Even
32 V2O Vertical Clock, Phase 2, Odd
33 V2E Vertical Clock, Phase 2, Even
34 GND Ground
NOTE: The pins are on a 0.070″ spacing.
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IMAGING PERFORMANCE
Table 6. TYPICAL OPERATIONAL CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)
Description Condition Notes
Frame Time 538 ms 1
Horizontal Clock Frequency 10 MHz
Light Source Continuous Red, Green and Blue LED Illumination Centered at 450, 530 and 650 nm 2, 3
Operation Nominal Operating Voltages and Timing
1. Electronic shutter is not used. Integration time equals frame time.
2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP−8115.
3. For monochrome sensor, only green LED used.
Specifications
Table 7. PERFORMANCE SPECIFICATIONS
Description Symbol Min. Nom. Max. Units
Sampling
Plan
Temperature
Tested at
(5C)
ALL CONFIGURATIONS
Dark Center Non-Uniformity N/A N/A 2 mVrms Die 27, 40
Dark Global Non-Uniformity N/A N/A 5.0 mVpp Die 27, 40
Global Non-Uniformity (Note 1) N/A 2.5 5.0 % rms Die 27, 40
Global Peak to Peak Non-Uniformity
(Note 1)
PRNU N/A 10 20 % pp Die 27, 40
Center Non-Uniformity (Note 1) N/A 1.0 2.0 % rms Die 27, 40
Maximum Photoresponse
Non-Linearity (Notes 2, 3)
NL N/A 2 % Design
Maximum Gain Difference between
Outputs (Notes 2, 3)
DGN/A 10 % Design
Maximum Signal Error due to
Non-Linearity Dif. (Notes 2, 3)
DNL N/A 1 % Design
Horizontal CCD Charge Capacity HNe 100 ke−Design
Vertical CCD Charge Capacity VNe 50 60 ke−Die
Photodiode Charge Capacity PNe 38 40 ke−Die
Horizontal CCD Charge Transfer
Efficiency
HCTE 0.99999 N/A Design
Vertical CCD Charge Transfer
Efficiency
VCTE 0.99999 N/A Design
Photodiode Dark Current IPD N/A
N/A
40
0.01
350
0.1
e/p/s
nA/cm2Die
Vertical CCD Dark Current IVD N/A
N/A
400
0.12
1711
0.5
e/p/s
nA/cm2Die
Image Lag Lag N/A < 10 50 e−Design
Anti-Blooming Factor XAB 100 300 N/A
Vertical Smear Smr N/A −80 −75 dB
Total Noise (Note 4) ne−T12 e− rms Design
Total Noise (Note 5) ne−T25 e− rms Design
Dynamic Range (Notes 5, 6) DR 60 dB Design
Output Amplifier DC Offset VODC 4 8.5 14 V Die
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Table 7. PERFORMANCE SPECIFICATIONS (continued)
Description
Temperature
Tested at
(5C)
Sampling
Plan
UnitsMax.Nom.Min.Symbol
ALL CONFIGURATIONS
Output Amplifier Bandwidth f−3DB 140 MHz Design
Output Amplifier Impedance ROUT 100 130 200 WDie
Output Amplifier Sensitivity DV/DN31 mV/e−Design
KAI−4021−ABA CONFIGURATION
Peak Quantum Efficiency QEMAX 45 55 N/A % Design
Peak Quantum Efficiency Wavelength lQE N/A 500 N/A nm Design
KAI−4021−CBA CONFIGURATION*
Peak Quantum Efficiency
Red
Green
Blue
QEMAX
−
−
−
35
42
45
N/A
N/A
N/A
% Design
Peak Quantum Efficiency Wavelength
Red
Green
Blue
lQE
−
−
−
620
540
470
N/A
N/A
N/A
nm Design
NOTE: N/A = Not Applicable.
*Not recommended for new designs.
1. Per color.
2. Value is over the range of 10% to 90% of photodiode saturation.
3. Value is for the sensor operated without binning.
4. Includes system electronics noise, dark pattern noise and dark current shot noise at 20 MHz.
5. Includes system electronics noise, dark pattern noise and dark current shot noise at 40 MHz.
6. Uses 20LOG (PNe /n
e−T).
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TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome with Microlens
Figure 10. Monochrome with Microlens Quantum Efficiency
0.00
0.10
0.20
0.30
0.40
0.50
0.60
300 400 500 600 700 800 900 1000
Wavelength (nm)
Absolute Quantum Efficiency
Measured with glass
Monochrome without Microlens
Figure 11. Monochrome without Microlens Quantum Efficiency
0.00
0.02
0.04
0.06
0.08
0.10
0.12
240 340 440 540 640 740 840 940
Wavelength (nm)
Absolute Quantum Efficiency
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Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Monochrome with Microlens
Figure 13. Monochrome with Microlens Angular Quantum Efficiency
Relative Quantum Efficiency (%)
Angle (degress)
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30
Horizontal
Vertical
Dark Current vs. Temperature
Figure 14. Dark Current vs. Temperature
Electrons/Second
1
10
100
1,000
10,000
100,000
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4
1000/T(K)
T (C) 97 84 72 60 50 40 30 21
VCCD
Photodiodes
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Power-Estimated
Figure 15. Power
Horizontal Clock Frequency (MHz)
Power (mW)
Right Output Disabled
0
50
100
150
200
250
300
350
400
0 5 10 15 20 25 30
Output Power One Output (mW)
Horizonatl Power (mW)
Vertical Power (mW)
Total Power One Output (mW)
Frame Rates
Figure 16. Frame Rates
0
5
10
15
20
25
30
10 15 20 25 30 35 40
Pixel Clock (MHz)
Frame Rate (fps)
Single output
Dual output or
Single 2x2 binning
Dual 2x2 binning
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DEFECT DEFINITIONS
Table 8. DEFECT DEFINITIONS
Description Definition Maximum
Temperature(s)
Tested at (5C) Notes
Major Dark Field Defective Pixel Defect ≥ 148 mV 40 27, 40 1
Major Bright Field Defective Pixel Defect ≥ 10% 40 27, 40 1
Minor Dark Field Defective Pixel Defect ≥ 76 mV 400 27, 40
Dead Pixel Defect ≥ 80% 527, 40 1
Starurated Pixel Defect ≥ 340 mV 10 27, 40 1
Cluster Defect A group of 2 to 10 contiguous major
defective pixels, but no more than 2 adjacent
defects horizontally.
827, 40 1
Column Defect A group of more than 10 contiguous major
defective pixels along a single column.
027, 40 1
1. There will be at least two non-defective pixels separating any two major defective pixels.
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are reference to pixel (1, 1) in the defect maps.
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TEST DEFINITIONS
Test Regions of Interest
Active Area ROI: Pixel (1, 1) to Pixel (2048, 2048)
Center 100 by 100 ROI: Pixel (974, 974) to
Pixel (1073, 1073)
Only the active pixels are used for performance and defect
tests.
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 17 for a pictorial representation of the regions.
Figure 17. Overclock Regions of Interest
Pixel 1,1
Vertical Overclock
Horizontal Overclock
H
V
Tests
Dark Field Center Non-Uniformity
This test is performed under dark field conditions. Only
the center 100 by 100 pixels of the sensor are used for this
test − pixel (974, 974) to pixel (1073, 1073).
Dark Field Center Uniformity +Standard Deviation of Center 100 by 100 Pixels in mW
Units: mV rms
Dark Field Global Non-Uniformity
This test is performed under dark field conditions.
The sensor is partitioned into 256 sub regions of interest,
each of which is 128 by 128 pixels in size. The average signal
level of each of the 256 sub regions of interest is calculated.
The signal level of each of the sub regions of interest is
calculated using the following formula:
Signal of ROI[i] +(ROI Average in ADU *
Units : mVpp (millivolts Peak to Peak)
*Horizontal Overclock Average in ADU) @
@mV per Count
Where i = 1 to 256. During this calculation on the 256 sub
regions of interest, the maximum and minimum signal levels
are found. The dark field global non−uniformity is then
calculated as the maximum signal found minus the
minimum signal level found.
Global Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 868 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 1240 mV. Global non−uniformity is
defined as:
Global Non−Uniformity +100 @ǒActive Area Standard Deviation
Active Area Signal Ǔ
Active Area Signal = Active Area Average −
Units : % rms
− Horizontal Overclock Average
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Global Peak to Peak Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 868 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 1240 mV. The sensor is partitioned
into 256 sub regions of interest, each of which is 128 by 128
pixels in size. The average signal level of each of the 256 sub
regions of interest (ROI) is calculated. The signal level of
each of the sub regions of interest is calculated using the
following formula:
A[i] +(ROI Average *Horizontal Overclock Average)
Where i = 1 to 256. During this calculation on the 256 sub
regions of interest, the maximum and minimum average
signal levels are found. The global peak to peak
non−uniformity is then calculated as:
Global NonUniformity +100 @A[i] Max. Signal *A[i] Min. Signal
Active Area Signal
Units : % pp
Active Area Signal = Active Area Average −
− Horizontal Overclock Average
Center Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 868 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 1240 mV. Defects are excluded for
the calculation of this test. This test is performed on the
center 100 by 100 pixels (see Test Regions of Interest) of the
sensor. Center non−uniformity is defined as:
+100 @ǒCenter ROI Standard Deviation
Center ROI Signal Ǔ
Center ROI Signal = Center ROI Average −
Units : % rms
Center ROI Non−Uniformity +
− Horizontal Overclock Average
Dark Field Defect Test
This test is performed under dark field conditions.
The sensor is partitioned into 256 sub regions of interest,
each of which is 128 by 128 pixels in size. In each region of
interest, the median value of all pixels is found. For each
region of interest, a pixel is marked defective if it is greater
than or equal to the median value of that region of interest
plus the defect threshold specified in “Defect Definitions”
section.
Bright Field Defect Test
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 28,000 electrons). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons.
The average signal level of all active pixels is found.
The bright and dark thresholds are set as:
Dark Defect Threshold = Active Area Signal @Threshold
Bright Defect Threshold = Active Area Signal @Threshold
The sensor is then partitioned into 256 sub regions of
interest, each of which is 128 by 128 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
Example for major bright field defective pixels:
•Average value of all active pixels is found to be
868 mV (28,000 electrons).
•Dark defect threshold: 868 mV ⋅ 15% = 130.2 mV.
•Bright defect threshold: 868 mV ⋅ 15% = 130.2 mV.
•Region of interest #1 selected. This region of interest is
pixels 1, 1 to pixels 128, 128.
♦Median of this region of interest is found to be
868 mV.
♦Any pixel in this region of interest that is
≥(868 + 130.2 mV) 998.2 mV in intensity will be
marked defective.
♦Any pixel in this region of interest that is
≤(868 −130.2 mV) 737.8 mV in intensity will be
marked defective.
•All remaining 255 sub regions of interest are analyzed
for defective pixels in the same manner.
KAI−4021
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OPERATION
Absolute Maximum Ratings
Absolute maximum rating is defined as a level or
condition that should not be exceeded at any time per the
description. If the level or the condition is exceeded,
the device will be degraded and may be damaged.
Table 9. ABSOLUTE MAXIMUM RATINGS
Description Symbol Minimum Maximum Units Notes
Operating Temperature T−50 70 °C 1
Humidity RH 5 90 % 2
Output Bias Current IOUT 0.0 10 mA 3
Off-Chip Load CL10 pF 4
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Each output. See Figure 18: Output Amplifier. Note that the current bias affects the amplifier bandwidth.
4. With total output load capacitance of CL = 10 pF between the outputs and AC ground.
Table 10. MAXIMUM VOLTAGE RATINGS BETWEEN PINS
Description Minimum Maximum Units Notes
RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGR,
OGL to ESD
0 17 V
Pin to Pin with ESD Protection −17 17 V 1
VDDL, VDDR to GND 0 25 V
1. Pins with ESD protection are: RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGL, and OGR.
Table 11. DC BIAS OPERATING CONDITIONS
Description Symbol Min. Nom. Max. Units
Maximum
DC Current Notes
Output Gate OG −3.0 −2.0 −1.5 V1 mA4, 5
Reset Drain RD 11.5 12.0 12.5 V 1 mA4
Output Amplifier Supply VDD 14.5 15.0 15.5 V 1 mA 3
Ground GND 0.0 0.0 0.0 V
Substrate SUB 8.0 VAB 17.0 V 1, 7
ESD Protection ESD −9.5 −9.0 −8.0 V 2
Output Bias Current IOUT 0.0 5.0 10.0 mA 6
1. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value VAB is set such that
the photodiode charge capacity is 40,000 electrons.
2. VESD must be equal to FDL and more negative than H1L, H2L and RL during sensors operation AND during camera power turn on.
3. One output, unloaded. The maximum DC current is for one output unloaded and is shown as Iss in Figure 18. This is the maximum current
that the first two stages of one output amplifier will draw. This value is with Vout disconnected.
4. May be changed in future versions.
5. Output gate voltage level must be set to −3 V for 40,000 − 80,000 electrons output in summed interlaced or binning modes.
6. One output.
7. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
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AC Operating Conditions
Table 12. CLOCK LEVELS
Description Symbol Min. Nom. Max. Unit Notes
Vertical CCD Clock High V2H 8.5 9.0 9.5 V
Vertical CCD Clocks Midlevel V1M, V2M −0.2 0.0 0.2 V
Vertical CCD Clocks Low V1L, V2L −9.5 −9.0 −8.5 V
Horizontal CCD Clocks High H1H, H2H 0.0 0.5 1.0 V
Horizontal CCD Clocks Low H1L, H2L −5.0 −4.5 −4.0 V
Reset Clock Amplitude RH 5.0 V 1
Reset Clock Low RL −3.5 −3.0 −2.5 V
Electronic Shutter Voltage VSHUTTER 44 48 52 V 2
Fast Dump High FDH 4 5 5 V
Fast Dump Low FDL −9.5 −9−8 V
1. Reset amplitude must be set to 7.0 V for 40,000 − 80,000 electrons output in summed interlaced or binning modes.
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Clock Line Capacitances
Figure 19. Clock Line Capacitances
V1E
V1O
V2O
V2E
GND
20nF
20nF
20nF
20nF
5nF
5nF
5nF
5nF
H1SL+H1BL
50pF
H2SL+H2BL
50pF
H1SR+H1BR
50pF
H2SR+H2BR
50pF
25pF
25pF
GND
GND
Reset
10pF
GND
SUB
4nF
GND
FD
40pF
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TIMING
Table 13. TIMING REQUIREMENTS
Description Symbol Min. Nom. Max. Units
HCCD Delay tHD 1.3 1.5 10.0 ms
VCCD Transfer Time tVCCD 1.3 1.5 20.0 ms
Photodiode Transfer Time tV3rd 3.0 5.0 15.0 ms
VCCD Pedestal Time t3P 50.0 60.0 80.0 ms
VCCD Delay t3D 10.0 20.0 80.0 ms
Reset Pulse Time tR2.5 5.0 ns
Shutter Pulse Time tS3.0 4.0 10.0 ms
Shutter Pulse Delay tSD 1.0 1.5 10.0 ms
HCCD Clock Period (Note 1) tH25.0 50.0 200.0 ns
VCCD Rise/Fall Time tVR 0.0 0.1 1.0 ms
Fast Dump Gate Delay tFD 0.5 ms
Vertical Clock Edge Alignment tVE 0.0 100.0 ns
1. For operation at the minimum HCCD clock period (40 MHz), the substrate voltage will need to be raised to limit the signal at the output to
20,000 electrons.
Timing Modes
Progressive Scan
Figure 20. Progressive Scan Operation
Photodiode CCD Shift Register
0
1
2
3
5
4
7
6
Output
HCCD
In progressive scan read out every pixel in the image
sensor is read out simultaneously. Each charge packet is
transferred from the photodiode to the neighboring vertical
CCD shift register simultaneously. The maximum useful
signal output is limited by the photodiode charge capacity to
40,000 electrons.
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Figure 21. Progressive Scan Flow Chart
Vertical Frame
Timing
Line Timing
Repeat for
2072 Lines
Summed Interlaced Scan
Figure 22. Summed Interlaced Scan Operation
0
1
2
3
5
4
7
6
0
1
2
3
5
4
7
6
even field odd field
In the summed interlaced scan read out mode, charge from
two photodiodes is summed together inside the vertical
CCD. The clocking of the VCCD is such that one pixel
occupies the space equivalent to two pixels in the
progressive scan mode. This allows the VCCD to hold twice
as many electrons as in progressive scan mode. Now the
maximum useful signal is limited by the charge capacity of
two photodiodes at 80,000 electrons. If only one field is read
out of the image sensor the apparent vertical resolution will
be 1024 rows instead of the 2048 rows in progressive scan
(equivalent to binning). To recover the full resolution of the
image sensor two fields, even and odd, are read out. In the
even field rows 0+1, 2+3, 4+5, … are summed together. In
the odd field rows 1+2, 3+4, 5+6, … are summed together.
The modulation transfer function (MTF) of the summed
interlaced scan mode is less in the vertical direction than the
progressive scan. But the dynamic range is twice that of
progressive scan. The vertical MTF is better than a simple
binning operation. In this mode the VCCD needs to be
clocked for only 1037 rows to read out each field.
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Figure 23. Summed Interlaced Scan Flow Chart
Summed
Interlaced Even
Frame
Timing
Interlaced Line
Timing
Repeat for
1037 Lines
Summed
Interlaced Odd
Frame
Timing
Interlaced Line
Timing
Repeat for
1037 Lines
Non−Summed Interlaced Scan
Figure 24. Non−Summed Interlaced Scan Operation
0
1
2
3
5
4
7
6
0
1
2
3
5
4
7
6
odd fieldeven field
In the non−summed interlaced scan mode only half the
photodiode are read out in each field. In the even field rows
0, 2, 4, … are transferred to the VCCD. In the odd field rows
1, 3, 5, … are transferred to the VCCD. When the charge
packet is transferred from a photodiode is occupies the
equivalent of two rows in progressive scan mode. This
allows the VCCD to hold twice as much charge a
progressive scan mode. However, since only one
photodiode for each row is transferred to the VCCD the
maximum usable signal is still only 40,000 electrons. The
large extra capacity of the VCCD causes the anti−blooming
protection to be increased dramatically compared to the
progressive scan. The vertical MTF is the same between the
non−summed interlaced scan and progressive scan. There
will be motion related artifacts in the images read out in the
interlaced modes because the two fields are acquired at
different times.
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Frame Timing
Frame Timing without Binning − Progressive Scan
Figure 26. Frame Timing without Binning
V1
V2
H1
H2
Line 2072 Line 1
tL
t3D
t3P
tV3rd
tL
Line 2071
Frame Timing for Vertical Binning by 2 − Progressive Scan
tL
Figure 27. Frame Timing for Vertical Binning by 2
t3D
t3P
tV3rd
tL
V1
V2
H1
H2
Line 1036 Line 1
Line 1035
3 × tVCCD
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Frame Timing Non−Summed Interlaced Scan (Even)
Figure 28. Non−Summed Interlaced Scan Even Frame Timing
V1E
V2E
V1O
V2O
H2
V1L
V2M
V2L
V1M
V1L
V2H
tV3rd tV3rd tVCCD
V2L
V1M
V2M
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
last odd line
readout
even frame timing
vertical retrace
horizontal retrace first even line
readout
tV3rd
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Frame Timing Non−Summed Interlaced Scan (Odd)
Figure 29. Non−Summed Interlaced Scan Odd Frame Timing
V1E
V2E
V1O
V2O
H2
V1L
V2M
V2L
V1M
V1L
V2H
tV3rd tV3rd tVCCD
V2L
V1M
V2M
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
last even line
readout
odd frame timing
vertical retrace
horizontal retrace first odd line
readout
tV3rd
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Frame Timing Summed Interlaced Scan (Even)
Figure 30. Summed Interlaced Scan Even Frame Timing
V1E
V2E
V1O
V2O
H2
V1L
V2M
V2L
V1M
V1L
V2H
t3D tVCCD
V2L
V1M
V2M
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
last odd line
readout
even frame timing
vertical retrace
horizontal retrace first even line
readout
tV3rd tVCCD tVCCD tVCCD
tVCCD
tVCCD
tVCCD
V2H
t3P
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Frame Timing Summed Interlaced Scan (Odd)
Figure 31. Summed Interlaced Scan Odd Frame Timing
V1E
V2E
V1O
V2O
H2
V1L
V2M
V2L
V1M
V1L
V2H
t3D tVCCD
V2L
V1M
V2M
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
last even line
readout
odd frame timing
vertical retrace
horizontal retrace first odd line
readout
tV3rd tVCCD tVCCD tVCCD
tVCCD
tVCCD
tVCCD
V2H
t3P
Frame Timing Edge Alignment
Figure 32. Frame Timing Edge Alignment
V1
V2
V1M
V1L
V2H
V2M
V2L
tVE
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Line Timing
Line Timing Single Output − Progressive Scan
Figure 33. Line Timing Single Output
V1
V2
H1
H2
R
Pixel Count
tL
tVCCD
tHD
2
1
39
11
12
13
14
40
41
42
43
2093
2094
2095
2097
2098
2123
2124
44
2096
2122
Line Timing Dual Output − Progressive Scan
Figure 34. Line Timing Dual Output
V1
V2
H1
H2
R
Pixel Count
tL
tVCCD
tHD
2
1
39
11
12
13
14
40
41
42
43
1058
1059
1060
1062
1063
1067
1068
44
1061
1065
1064
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Line Timing Vertical Binning by 2 − Progressive Scan
Figure 35. Line Timing Vertical Binning by 2
V1
V2
H1
H2
R
Pixel Count
tL
3 × tVCCD
tHD
2
1
39
11
12
13
14
40
41
42
43
2093
2094
2095
2097
2098
2123
2124
44
2096
2122
Line Timing Detail − Progressive Scan
Figure 36. Line Timing Detail
V1
V2
H2
H1
R
tVCCD
tHD
1/2 tH
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Electronic Shutter
Electronic Shutter Line Timing
Figure 43. Electronic Shutter Line Timing
tHD
tVCCD
VSUB
fV1
fV2
fH2
fH1
tSD
tS
fR
VSHUTTER
Electronic Shutter − Integration Time Definition
Figure 44. Integration Time Definition
VSUB
fV2
VSHUTTER
Integration Time
Electronic Shutter − DC and AC Bias Definition
The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock
are referenced to ground.
Figure 45. DC Bias and AC Clock Applied to the SUB Pin
SUB
GND GND
VSHUTTER
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Electronic Shutter Description
The voltage on the substrate (SUB) determines the charge
capacity of the photodiodes. When SUB is 8 V the
photodiodes will be at their maximum charge capacity.
Increasing VSUB above 8 V decreases the charge capacity
of the photodiodes until 48 V when the photodiodes have
a charge capacity of zero electrons. Therefore, a short pulse
on SUB, with a peak amplitude greater than 48 V, empties
all photodiodes and provides the electronic shuttering
action.
It may appear the optimal substrate voltage setting is 8 V
to obtain the maximum charge capacity and dynamic range.
While setting VSUB to 8 V will provide the maximum
dynamic range, it will also provide the minimum
anti-blooming protection.
The KAI−4021 VCCD has a charge capacity of
60,000 electrons (60 ke−). If the SUB voltage is set such that
the photodiode holds more than 60 ke−, then when the
charge is transferred from a full photodiode to VCCD,
the VCCD will overflow. This overflow condition manifests
itself in the image by making bright spots appear elongated
in the vertical direction. The size increase of a bright spot is
called blooming when the spot doubles in size.
The blooming can be eliminated by increasing the voltage
on SUB to lower the charge capacity of the photodiode. This
ensures the VCCD charge capacity is greater than the
photodiode capacity. There are cases where an extremely
bright spot will still cause blooming in the VCCD. Normally,
when the photodiode is full, any additional electrons
generated by photons will spill out of the photodiode.
The excess electrons are drained harmlessly out to the
substrate. There is a maximum rate at which the electrons
can be drained to the substrate. If that maximum rate is
exceeded, (for example, by a very bright light source) then
it is possible for the total amount of charge in the photodiode
to exceed the VCCD capacity. This results in blooming.
The amount of anti-blooming protection also decreases
when the integration time is decreased. There is
a compromise between photodiode dynamic range
(controlled by VSUB) and the amount of anti-blooming
protection. A low VSUB voltage provides the maximum
dynamic range and minimum (or no) anti-blooming
protection. A high VSUB voltage provides lower dynamic
range and maximum anti-blooming protection. The optimal
setting of VSUB is written on the container in which each
KAI−4021 is shipped. The given VSUB voltage for each
sensor is selected to provide anti-blooming protection for
bright spots at least 100 times saturation, while maintaining
at least 40 ke− of dynamic range.
The electronic shutter provides a method of precisely
controlling the image exposure time without any
mechanical components. If an integration time of tINT is
desired, then the substrate voltage of the sensor is pulsed to
at least 40 V tINT seconds before the photodiode to VCCD
transfer pulse on V2. Use of the electronic shutter does not
have to wait until the previously acquired image has been
completely read out of the VCCD.
Large Signal Output
When the image sensor is operated in the binned or
summed interlaced modes there will be more than
20,000 electrons in the output signal. The image sensor is
designed with a 31 mV/e charge to voltage conversion on the
output. This means a full signal of 20,000 electrons will
produce a 640 mV change on the output amplifier.
The output amplifier was designed to handle an output
swing of 640 mV at a pixel rate of 40 MHz. If 40,000
electron charge packets are generated in the binned or
summed interlaced modes then the output amplifier output
will have to swing 1,280 mV. The output amplifier does not
have enough bandwidth (slew rate) to handle 1,280 mV at
40 MHz. Hence, the pixel rate will have to be reduced to
20 MHz if the full dynamic range of 40,000 electrons is
desired.
The charge handling capacity of the output amplifier is
also set by the reset clock voltage levels. The reset clock
driver circuit is very simple if an amplitude of 5 V is used.
But the 5 V amplitude restricts the output amplifier charge
capacity to 20,000 electrons. If the full dynamic range of
40,000 electrons is desired then the reset clock amplitude
will have to be increased to 7 V.
If you only want a maximum signal of 20,000 electrons in
binned or summed interlaced modes, then a 40 MHz pixel
rate with a 5 V reset clock may be used. The output of the
amplifier will be unpredictable above 20,000 electrons so be
sure to set the maximum input signal level of your analog to
digital converter to the equivalent of 20,000 electrons
(640 mV).
KAI−4021
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STORAGE AND HANDLING
Table 14. STORAGE CONDITIONS
Description Symbol Minimum Maximum Unit Notes
Storage Temperature TST −55 80 °C 1
Humidity RH 5 90 % 2
1. Long-term exposure toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference Manual (SOLDERRM/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
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43
Glass
Figure 48. Glass Drawing
Notes:
Units: IN [MM]
Tolerance: Unless otherwise specified
±1% no less than 0.004″
1. Materials: Substrate − Schott D236T eco or equivalent
2. Epoxy − NCO−150HB
Thickness: 0.002” − 0.005”
3. Dust, Scratch Specification − 10 microns max.
4. Multi−Layer Anti−Reflective Coating on 2 Sides:
a.) Double Sided Reflectance:
b.) Range (nm)
420−435 nm < 2.0%
435−630 nm < 0.8%
630−680 nm < 2.0%
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Glass Transmission
Figure 49. Glass Transmission
0
10
20
30
40
50
60
70
80
90
100
200 300 400 500 600 700 800 900
Wavelength (nm)
Transmission (%)
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