Dual 500kHz, 12-Bit, 2 + 2 Channel
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
●4 INPUT CHANNELS
●FULLY DIFFERENTIAL INPUTS
●2µs TOTAL THROUGHPUT PER CHANNEL
●GUARANTEED NO MISSING CODES
●PARALLEL INTERFACE
●1MHz EFFECTIVE SAMPLING RATE
●LOW POWER: 40mW
APPLICATIONS
● MOTOR CONTROL
● MULTI-AXIS POSITIONING SYSTEMS
● 3-PHASE POWER CONTROL
DESCRIPTION
The ADS7862 is a dual 12-bit, 500kHz analog-to-digital
converter (A/D) with 4 fully differential input channels grouped
into two pairs for high speed simultaneous signal acquisition.
Inputs to the sample-and-hold amplifiers are fully differential
and are maintained differential to the input of the A/D con-
verter. This provides excellent common-mode rejection of
80dB at 50kHz, which is important in high noise environ-
ments.
The ADS7862 offers parallel interface and control inputs to
minimize software overhead. The output data for each channel
is available as a 12-bit word. The ADS7862 is offered in an
TQFP-32 package and is fully specified over the –40°C to
+85°C operating range.
ADS7862
SAR
Interface
Conversion
and
Control
Output
Registers
COMP
CONVST
BUSY
RD
CS
Data Output
12
CLOCK
A0
CDAC
Internal
2.5V
Reference
S/H
Amp
S/H
Amp
CH A0–
CH A0+
REF
IN
CH A1–
CH A1+
SAR
COMP
CDAC
MUX
MUX
CH B0–
CH B0+
CH B1–
CH B1+
REF
OUT
ADS7862
®
SBAS101B – JANUARY 1998 – REVISED AUGUST 2005
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998-2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ADS7862
2SBAS101B
www.ti.com
PIN NAME DESCRIPTION
1REF
IN Reference Input
2 REFOUT +2.5V Reference Output. Connect directly to REFIN
(pin 1) when using internal reference.
3 AGND Analog Ground
4+V
AAnalog Power Supply, +5VDC. Connect directly to
digital power supply (pin 24). Decouple to analog
ground with a 0.1µF ceramic capacitor and a 10µF
tantalum capacitor.
5 DB11 Data Bit 11, MSB
6 DB10 Data Bit 10
7 DB9 Data Bit 9
8 DB8 Data Bit 8
9 DB7 Data Bit 7
10 DB6 Data Bit 6
11 DB5 Data Bit 5
12 DB4 Data Bit 4
13 DB3 Data Bit 3
14 DB2 Data Bit 2
15 DB1 Data Bit 1
16 DB0 Data Bit 0, LSB
17 BUSY HIGH when a conversion is in progress.
18 CONVST Convert Start
19 CLOCK An external CMOS-compatible clock can be applied to
the CLOCK input to synchronize the conversion pro-
cess to an external source. The CLOCK pin controls
the sampling rate by the equation: CLOCK 16 • fSAMPLE.
20 CS Chip Select
21 RD Synchronization pulse for the parallel output. During a
Read operation, the first falling edge selects the A
register and the second edge selects the B register,
A0, then controls whether input 0 or input 1 is read.
22 A0 On the falling edge of Convert Start, when A0 is LOW
Channel A0 and Channel B0 are converted and when
it is HIGH, Channel A1 and Channel B1 are converted.
During a Read operation, the first falling edge selects
the A register and the second edge selects the B of RD
register, A0, then controls whether input 0 or input 1 is
read.
23 DGND Digital Ground. Connect directly to analog ground (pin 3).
24 +VDDigital Power Supply, +5VDC
25 CH B1+ Non-Inverting Input Channel B1
26 CH B1–Inverting Input Channel B1
27 CH B0+ Non-Inverting Input Channel B0
28 CH B0–Inverting Input Channel B0
29 CH A1–Inverting Input Channel A1
30 CH A1+ Non-Inverting Input Channel A1
31 CH A0–Inverting Input Channel A0
32 CH A0+ Non-Inverting Input Channel A0
PIN CONFIGURATION
Top View
PIN DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS
Analog Inputs to AGND: Any Channel Input ........ –0.3V to (+VD + 0.3V)
REFIN ............................. –0.3V to (+VD + 0.3V)
Digital Inputs to DGND.......................................... –0.3V to (+VD + 0.3V)
Ground Voltage Differences: AGND, DGND ................................... ±0.3V
+VD to AGND......................... –0.3V to +6V
Power Dissipation .......................................................................... 325mW
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
REFIN
REFOUT
AGND
+VA
DB11
DB10
DB9
DB8
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
+VD
DGND
A0
RD
CS
CLOCK
CONVST
BUSY
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
9 10111213141516
CH A0+
CH A0–
CH A1+
CH A1–
CH B0–
CH B0+
CH B1–
CH B1+
32 31 30 29 28
ADS7862
27 26 25
ORDERING INFORMATION(1)
MAXIMUM MAXIMUM
RELATIVE GAIN SPECIFICATION
ACCURACY ERROR PACKAGE TEMPERATURE ORDERING TRANSPORT
PRODUCT (LSB) (%) PACKAGE DESIGNATOR RANGE NUMBER MEDIA, QUANTITY
ADS7862Y ±2±0.75 TQFP-32 PBS –40°C to +85°C ADS7862Y/250 Tape and Reel, 250
ADS7862Y "" " " "ADS7862Y/2K5 Tape and Reel, 2500
ADS7862YB ±1±0.5 TQFP-32 PBS –40°C to +85°C ADS7862YB/250 Tape and Reel, 250
ADS7862YB "" " " "ADS7862YB/2K5 Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com.
ADS7862 3
SBAS101B www.ti.com
ELECTRICAL CHARACTERISTICS
All specifications TMIN to TMAX, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
ADS7862Y ADS7862YB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 ✻Bits
ANALOG INPUT
Input Voltage Range-Bipolar VCENTER = Internal VREF at 2.5V –VREF +VREF ✻✻V
Absolute Input Range +IN –0.3 VCC + 0.3 V
–IN –0.3 VCC + 0.3 V
Input Capacitance 15 ✻pF
Input Leakage Current CLK = GND ±1✻µA
SYSTEM PERFORMANCE
No Missing Codes 12 ✻Bits
Integral Linearity ±0.75 ±2±0.5 ±1 LSB
Integral Linearity Match 0.5 1 ✻✻ LSB
Differential Linearity ±0.75 ±0.5 ±1 LSB
Bipolar Offset Error Referenced to REFIN ±0.75 ±3±0.5 ±2 LSB
Bipolar Offset Error Match 3 2 LSB
Positive Gain Error Referenced to REFIN ±0.15 ±0.75 ±0.1 ±0.5 % of FSR
Positive Gain Error Match 2 1 LSB
Negative Gain Error Referenced to REFIN ±0.15 ±0.75 ±0.1 ±0.5 % of FSR
Negative Gain Error Match 2 1 LSB
Common-Mode Rejection Ratio At DC 80 ✻dB
VIN = ±1.25VPP at 50kHz 80 ✻dB
Noise 120 ✻µVRMS
Power Supply Rejection Ratio ±0.5 ±2✻✻ LSB
SAMPLING DYNAMICS
Conversion Time per A/D 1.75 ✻µs
Acquisition Time 0.25 ✻µs
Throughput Rate 500 ✻kHz
Aperture Delay 3.5 ✻ns
Aperture Delay Matching 100 ✻ps
Aperture Jitter 50 ✻ps
Small-Signal Bandwidth 40 ✻MHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion VIN = ±2.5VPP at 100kHz 75 ✻dB
SINAD VIN = ±2.5VPP at 100kHz 71 ✻dB
Spurious Free Dynamic Range VIN = ±2.5VPP at 100kHz –78 ✻dB
Channel-to-Channel Isolation VIN = ±2.5VPP at 100kHz –80 ✻dB
VOLTAGE REFERENCE
Internal 2.475 2.5 2.525 ✻✻✻ V
Internal Drift ±25 ✻ppm/°C
Internal Noise 50 ✻µVPP
Internal Source Current 2 ✻mA
Internal Load Rejection 0.005 ✻mV/µA
Internal PSRR 65 ✻dB
External Voltage Range 1.2 2.5 2.6 ✻✻✻ V
Input Current 0.05 1 ✻✻ µA
Input Capacitance 5✻pF
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻
Logic Levels: VIH IIH = +5µA 3.0
+VDD + 0.3
✻✻V
VIL IIL = +5µA–0.3 0.8 ✻✻V
VOH IOH = –500µA 3.5 ✻V
VOL IOL = 500µA 0.4 ✻V
External Clock 0.2 8 ✻✻MHz
Data Format Binary Two’s Complement ✻
POWER SUPPLY REQUIREMENTS
Power Supply Voltage, +V 4.75 5 5.25 ✻✻✻ V
Quiescent Current, +VA58 ✻✻ mA
Power Dissipation 25 40 ✻✻ mW
✻ Specifications same as ADS7862Y.
ADS7862
4SBAS101B
www.ti.com
BASIC OPERATION
REF
IN
REF
OUT
AGND
+V
A
DB11
DB10
DB9
DB8
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
+V
D
DGND
A0
RD
CS
CLOCK
CONVST
BUSY
Address Select
Read Input
Chip Select
Clock Input
Conversion Start
Busy Output
ADS7862Y
10µF
+0.1µF
+5V
Analog Supply
+
32
31
30
29
28
27
26
25
CH A0+
CH A0–
CH A1+
CH A1–
CH B0–
CH B0+
CH B1–
CH B1+
9
10
11
12
13
14
15
16
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADS7862 5
SBAS101B www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS
At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
CHANGE IN SIGNAL-TO-NOISE RATIO
AND SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
Temperature (°C)
0.25
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
Delta from +25°C (dB)
–40 25 85
SNR
SINAD
CHANGE IN SPURIOUS FREE DYNAMIC RANGE
AND TOTAL HARMONIC DISTORTION
vs TEMPERATURE
Temperature (°C)
0.65
0.45
0.25
0.05
–0.15
–0.35
–0.55
–0.75
0.65
0.45
0.25
0.05
–0.15
–0.35
–0.55
–0.75
SFDR Delta from +25°C (dB)
THD Delta from +25°C (dB)
–40 25 85
SFDR
THD
CHANGE IN POSITIVE GAIN MATCH
vs TEMPERATURE
(Maximum Deviation for All Four Channels)
Temperature (°C)
0.6
0.5
0.4
0.3
0.2
0.1
0
Change in Positive Gain Match (LSB)
–40 25 85 150
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
10k 100k1k 1M
Input Frequency (Hz)
SNR and SINAD (dB)
74
72
70
68
66
64
76
SINAD
SNR
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 99.9kHz, –0.5dB)
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
Amplitude (dB)
0 62.5 125 250187.5
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 199.9kHz, –0.5dB)
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
Amplitude (dB)
0 62.5 125 250187.5
ADS7862
6SBAS101B
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (Cont.)
At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
CHANGE IN NEGATIVE GAIN MATCH
vs TEMPERATURE
(Maximum Deviation for All Four Channels)
Temperature (°C)
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
Change in Negative Gain Match (LSB)
–40 25 85 150
CHANGE IN REFERENCE VOLTAGE
vs TEMPERATURE
Temperature (°C)
2.51
2.505
2.5
2.495
2.49
2.485
Change in Reference (V)
–40 25 85 150
CHANGE IN BIPOLAR ZERO
vs TEMPERATURE
Temperature (°C)
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
Change in Bipolar Zero (LSB)
–40 25
A Channel
B Channel
85 150
CHANGE IN BPZ MATCH vs TEMPERATURE
Temperature (°C)
1
0.75
0.5
0.25
0
Change in Bipolar Zero Match (LSB)
–40 25 85 150
CHANGE IN CMRR vs TEMPERATURE
Temperature (°C)
86
85
84
83
82
81
80
79
78
Change in CMRR (dB)
–40 –5255585
INTEGRAL LINEARITY ERROR vs CODE
Hex BTC Code
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
ILE (LSB)
800 000 7FF
Typical of All Four Channels
ADS7862 7
SBAS101B www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (Cont.)
At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
INTEGRAL LINEARITY ERROR vs TEMPERATURE
Positive ILE
Negative ILE
Temperature (°C)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
Change in ILE (LSB)
–40 25 85 150
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
Temperature (°C)
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
DLE Error (LSB)
–40 25
Positive DLE
Negative DLE
85 150
INTEGRAL LINEARITY ERROR MATCH
vs TEMPERATURE
CHANNEL A0/CHANNEL B0
(Different Converter, Different Channels)
Temperature (°C)
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
Change in ILE Match (LSB)
–40 25 85 150
INTEGRAL LINEARITY ERROR MATCH
vs CODE CHANNEL A0/CHANNEL A1
(Same Converter, Different Channels)
Hex BTC Code
0.25
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
ILE (LSB)
800 000 7FF
INTEGRAL LINEARITY ERROR MATCH
vs CODE CHANNEL A0/CHANNEL B1
(Different Converter, Different Channels)
Hex BTC Code
0.25
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
ILE (LSB)
800 000 7FF
DIFFERENTIAL LINEARITY ERROR vs CODE
Hex BTC Code
Typical of All Four Channels
1
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
–1
DLE (LSB)
800 000 7FF
ADS7862
8SBAS101B
www.ti.com
REFERENCE
Under normal operation, the REFOUT pin (pin 2) should be
directly connected to the REFIN pin (pin 1) to provide an
internal +2.5V reference to the ADS7862. The ADS7862
can operate, however, with an external reference in the range
of 1.2V to 2.6V for a corresponding full-scale range of 2.4V
to 5.2V.
The internal reference of the ADS7862 is double-buffered.
If the internal reference is used to drive an external load, a
buffer is provided between the reference and the load ap-
plied to pin 2 (the internal reference can typically source
2mA of current—load capacitance should not exceed 100pF).
If an external reference is used, the second buffer provides
isolation between the external reference and the CDAC.
This buffer is also used to recharge all of the capacitors of
both CDACs during conversion.
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS7862: single-ended or differential (see Figures 1 and 2).
When the input is single-ended, the –IN input is held at the
common-mode voltage. The +IN input swings around the
same common voltage and the peak-to-peak amplitude is the
(common-mode +VREF) and the (common-mode –VREF).
The value of VREF determines the range over which the
common-mode voltage may vary (see Figure 3).
When the input is differential, the amplitude of the input is the
difference between the +IN and –IN input, or: (+IN) – (–IN).
The peak-to-peak amplitude of each input is ±1/2VREF around
this common voltage. However, since the inputs are 180° out
of phase, the peak-to-peak amplitude of the differential voltage
is +VREF to –VREF. The value of VREF also determines the
range of the voltage that may be common to both inputs (see
Figure 4).
INTRODUCTION
The ADS7862 is a high speed, low power, dual 12-bit A/D
converter that operates from a single +5V supply. The input
channels are fully differential with a typical common-mode
rejection of 80dB. The part contains dual 2µs successive
approximation A/Ds, two differential sample-and-hold am-
plifiers, an internal +2.5V reference with REFIN and REFOUT
pins and a high speed parallel interface. There are four
analog inputs that are grouped into two channels (A and B)
selected by the A0 input (A0 LOW selects Channels A0 and
B0, while A0 HIGH selects Channels A1 and B1). Each
A/D converter has two inputs (A0 and A1 and B0 and B1)
that can be sampled and converted simultaneously, thus
preserving the relative phase information of the signals on
both analog inputs. The part accepts an analog input voltage
in the range of –VREF to +VREF, centered around the internal
+2.5V reference. The part will also accept bipolar input
ranges when a level shift circuit is used at the front end (see
Figure 7).
A conversion is initiated on the ADS7862 by bringing the
CONVST pin LOW for a minimum of 15ns. CONVST
LOW places both sample-and-hold amplifiers in the hold
state simultaneously and the conversion process is started on
both channels. The BUSY output will then go HIGH and
remain HIGH for the duration of the conversion cycle.
Depending on the status of the A0 pin, the data will either
reflect a conversion of Channel 0 (A0 LOW) or Channel 1
(A0 HIGH). The data can be read from the parallel output
bus following the conversion by bringing both RD and CS
LOW.
Conversion time for the ADS7862 is 1.75µs when an 8MHz
external clock is used. The corresponding acquisition time is
0.25µs. To achieve maximum output rate (500kHz), the read
function can be performed immediately at the start of the
next conversion.
NOTE: This mode of operation is described in more detail
in the Timing and Control section of this data sheet.
SAMPLE-AND-HOLD SECTION
The sample-and-hold amplifiers on the ADS7862 allow the
A/Ds to accurately convert an input sine wave of full-scale
amplitude to 12-bit accuracy. The input bandwidth of the
sample-and-hold is greater than the Nyquist rate (Nyquist
equals one-half of the sampling rate) of the A/D even when
the A/D is operated at its maximum throughput rate of
500kHz. The typical small-signal bandwidth of the sample-
and-hold amplifiers is 40MHz.
Typical aperture delay time or the time it takes for the
ADS7862 to switch from the sample to the hold mode
following the CONVST pulse is 3.5ns. The average delta of
repeated aperture delay values is typically 50ps (also known
as aperture jitter). These specifications reflect the ability of
the ADS7862 to capture AC input signals accurately at the
exact same moment in time.
ADS7862
ADS7862
Single-Ended Input
Common
Voltage
–VREF to +VREF
peak-to-peak
Differential Input
Common
Voltage
VREF
peak-to-peak
VREF
peak-to-peak
FIGURE 1. Methods of Driving the ADS7862 Single-Ended
or Differential.
ADS7862 9
SBAS101B www.ti.com
FIGURE 3. Single-Ended Input: Common-Mode Voltage
Range vs VREF.
1.0 1.5
1.2
2.0 2.5
2.6
3.0
V
REF
(V)
Common Voltage Range (V)
–1
0
1
2
3
4
5
2.7
2.3
4.1
0.9
V
CC
= 5V
Single-Ended Input
Differential Input
1.0 1.5
1.2
2.0 2.5
2.6
3.0
VREF (V)
Common Voltage Range (V)
–1
0
1
2
3
4
54.7
0.3
VCC = 5V
4.05
0.90
FIGURE 2. Using the ADS7862 in the Single-Ended and Differential Input Modes.
FIGURE 4. Differential Input: Common-Mode Voltage
Range vs V
REF
.
In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and –IN inputs are
matched. Otherwise, this may result in offset error, which
will change with both temperature and input voltage.
The input current on the analog inputs depend on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS7862 charges the inter-
nal capacitor array during the sampling period. After this
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (15pF) to a 12-bit settling
level within 2 clock cycles. When the converter goes into the
hold mode, the input impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input
voltage. The +IN input should always remain within the
range of GND – 300mV to VDD + 0.3V.
CM +VREF +VREF
–VREF
Single-Ended Inputs t
+IN
CM Voltage
CM –VREF
CM +1/2VREF
Differential Inputs
NOTES: Common-Mode Voltage (Differential Mode) = Common-Mode Voltage (Single-Ended Mode) = IN–.
(IN+) + (IN–)
2
The maximum differential voltage between +IN and –IN of the ADS7862 is VREF. See Figures 3 and 4 for a further
explanation of the common voltage range for single-ended and differential inputs.
t
+IN
–IN
CM Voltage
CM –1/2VREF
–IN = CM Voltage
+VREF
–VREF
ADS7862
10 SBAS101B
www.ti.com
Three timing diagrams are used to explain the operation of
the ADS7862. Figure 8 shows the timing relationship be-
tween the CLOCK, CONVST (pin 18) and the conversion
Code (decimal)
8000
7000
6000
5000
4000
3000
2000
1000
0
Number of Conversions
2044 2045 2046 2047 2048
FIGURE 5. Histogram of 8,000 Conversions of a DC Input.
FIGURE 6. Test Circuits for Timing Specifications.
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
FIGURE 8. Conversion Mode.
TRANSITION NOISE
Figure 5 shows a histogram plot for the ADS7862 following
8,000 conversions of a DC input. The DC input was set at
output code 2046. All but one of the conversions had an
output code result of 2046 (one of the conversions resulted
in an output of 2047). The histogram reveals the excellent
noise performance of the ADS7862.
BIPOLAR INPUTS
The differential inputs of the ADS7862 were designed to
accept bipolar inputs (–VREF and +VREF) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resis-
tors, the ADS7862 can be configured to except bipolar
inputs. The conventional ±2.5V, ±5V, and ±10V input
ranges can be interfaced to the ADS7862 using the resistor
values shown in Figure 7.
TIMING AND CONTROL
The ADS7862 uses an external clock (CLOCK, pin 19)
which controls the conversion rate of the CDAC. With an
8MHz external clock, the A/D sampling rate is 500kHz
which corresponds to a 2µs maximum throughput time.
DATA
1.4V
Test Point
3kΩ
100pF
C
LOAD
t
R
DATA
Voltage Waveforms for DATA Rise and Fall Times t
R
, and t
F
.
V
OH
V
OL
t
F
R
1
R
2
+IN
–IN
REF
OUT
(pin 2)
2.5V
4kΩ
20kΩ
Bipolar Input
BIPOLAR INPUT R
1
R
2
±10V 1kΩ5kΩ
±5V 2kΩ10kΩ
±2.5V 4kΩ20kΩ
OPA132
ADS7862
CONVST
CONVERSION
MODE SAMPLE HOLD CONVERT
CLOCK
t
CKH
t
CKP
t
3
t
CKL
NOTE: The ADS7862 will switch from the sample to the hold mode the instant CONVST goes LOW regardless of
the state of the external clock. The conversion process is initiated with the first rising edge of the external clock
following CONVST going LOW.
ADS7862 11
SBAS101B www.ti.com
FIGURE 9. Reading and Writing to the ADS7862 During the Same Cycle.
DESCRIPTION ANALOG INPUT
Full-Scale Input Span –VREF to +VREF(1)
Least Significant (–VREF to +VREF)/4096(2)
Bit (LSB)
+Full Scale 4.99878V 0111 1111 1111 7FF
Midscale 2.5V 0000 0000 0000 000
Midscale – 1 LSB 2.49878V 1111 1111 1111 FFF
–Full Scale 0V 1000 0000 0000 800
NOTES: (1) –VREF to +VREF around VREF. With a 2.5V reference, this corre-
sponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference.
TABLE I. Ideal Input Voltages and Output Codes.
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
BINARY CODE HEX CODE
mode. Figure 9, in conjunction with Table I, shows the basic
read/write functions of the ADS7862 and highlights all of
the timing specifications. Figure 10 shows a more detailed
description of initiating a conversion using CONVST. Fig-
ure 11 illustrates three consecutive conversions and, with the
accompanying text, describes all of the read and write
capabilities of the ADS7862.
The Figure 11 timing diagram can be divided into three
sections: (a) initiating a conversion (n – 2), (b) starting a
second conversion (n – 1) while reading the data output from
the previous conversion (n – 2), and (c) starting a third
conversion (n) while reading both previous conversions
(n – 2 and n – 1). In this sequence, Channel 0 is converted
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tCONV
Conversion Time 1.75 µs
tACQ
Acquisition Time 0.25 µs
tCKP
Clock Period 125 5000 ns
tCKL
Clock LOW 40 ns
tCKH
Clock HIGH 40 ns
t1
CS to RD Setup Time 0 ns
t2
CS to RD Hold Time 0 ns
t3
CONVST LOW 15 ns
t4
RD Pulse Width 30 ns
t5
RD to Valid Data (Bus Access) 16 25 ns
t6
RD to HI-Z Delay (Bus Relinquish) 10 20 ns
t7
Time Between Conversion Reads 40 ns
t8
Address Setup Time 250 ns
t9
CONVST HIGH 20 ns
t10
Address Hold Time 20 ns
t11
CONVST to BUSY Propagation Delay 30 ns
t12
CONVST LOW Prior to CLOCK Rising Edge
10 ns
t13
CONVST LOW After CLOCK Rising Edge
5ns
tF
Data Fall Time 13 25 ns
tR
Data Rise Time 20 30 ns
TIMING SPECIFICATIONS
first followed by Channel 1. Channel 1 can be converted
prior to Channel 0 if the user wishes by simply starting the
conversion process with the A0 pin at logic HIGH (Channel
1) followed by logic LOW (Channel 0).
t
12
t
13
t
3
t
9
t
11
Conversion n
Conversion n – 1 Results Conversion n Results
BUSY
A0
CS
RD
DATA
Conversion n + 1
1CLOCK
CONVST
2 3 4 5 14 15 16 1 2 3 4 5 14 15 16
t
CONV
t
ACQ
t
8
t
4
t
10
t
1
t
5
CHA1 CHB1 CHA0 CHB0
t
6
t
2
t
7
ADS7862
12 SBAS101B
www.ti.com
NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after
the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the
rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will
initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from
HIGH to LOW in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If
CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.
CLOCK
CONVST
Cycle 1 Cycle 2
tCKP
125ns
10ns
5ns
10ns
5ns
A B C
FIGURE 10. Timing Between CLOCK and CONVST to Start a Conversion.
FIGURE 11. ADS7862 Timing Diagram Showing Complete Functionality.
1 11
SECTION A
CLOCK
CONVST
A0
RD
CS
DATA
BUSY
TIME 0 1µ2µ3µ4µ5µ
min 250ns
SECTION B SECTION C
ChA0 ChB0
Time (seconds)
ChA1 ChA0
4 Output-Register
Data of Ch0 Still Stored
A0 Selects Between
Ch0 and Ch1 at Output
Conversion of Ch0
Low Data Level Tri-state of Output
Conversion of Ch0
High Data Level Output Active
1616
A0 = 1 Conversion of Ch1 min 250ns
CS Needed Only During Reading
Conversion of Ch1
ChB0ChB1
A0 = 0 Conversion of Ch0 A0 = 0 Conversion of Ch0
1st RD After CONVST ChA at Output 2nd RD After CONVST ChB at Output
ADS7862 13
SBAS101B www.ti.com
SECTION A
Conversions are initiated by bringing the CONVST pin (pin
18) LOW for a minimum of 5ns (after the 5ns minimum
requirement has been met, the CONVST pin can be brought
HIGH). The ADS7862 will switch from the sample to the
hold mode on the falling edge of the CONVST command.
Following the first rising edge of the external clock after a
CONVST LOW, the ADS7862 will begin conversion (this
first rising edge of the external clock represents the start of
clock cycle one; the ADS7862 requires sixteen cycles to
complete a conversion). The input channel is also latched in
at this point in time. The A0 input (pin 22) must be selected
250ns prior to the CONVST pin going LOW so that the
correct address will be selected prior to conversion. The
BUSY output will go HIGH immediately following CONVST
going LOW. BUSY will stay HIGH through the conversion
process and return LOW when the conversion has ended.
After CONVST has remained LOW for the minimum time,
the ADS7862 will switch from the hold mode to the conver-
sion mode synchronous to the next rising edge of the
external clock and conversion ‘n – 2’ will begin. Both RD
(pin 21) and CS (pin 20) can be HIGH during and before a
conversion. However, they must both be LOW to enable the
output bus and read data out.
SECTION B
The CONVST pin is switched from HIGH to LOW a second
time to initiate conversion ‘n – 1’. Again, the address must be
selected 250ns prior to CONVST going LOW to ensure that
the new address is selected for conversion. Both the RD and
CS pins are brought LOW in order to enable the parallel output
bus with the ‘n – 2’ conversion results of Channel A0. While
continuing to hold CS LOW, RD is held LOW for a minimum
of 30ns which enables the output bus with the Channel A0
results of conversion ‘n – 2’. The RD pin is toggled from
HIGH to LOW a second time in order to enable the output bus
with the Channel B0 results of conversion ‘n – 2’.
SECTION C
CONVST is brought LOW for a third time to initiate
conversion ‘n’ (Channel 0). While the conversion is in
process, the results for both conversions ‘n – 2’ and ‘n – 1’
can be read. The address pin is brought HIGH while CS and
RD are brought LOW which enables the output bus with the
Channel A1 results of conversion ‘n – 1’. The RD pin is
toggled from HIGH to LOW for a second time in Section C
and the ‘n – 1’ conversion results for Channel B1 appear at
the output bus. The address pin (A0) is then brought LOW
and the read process repeats itself with the most recent
conversion results for Channel 0 (n – 2) appearing at the
output bus.
READING DATA
The ADS7862 outputs full parallel data in Binary Two’s
Complement data output format. The parallel output will be
active when CS (pin 20) and RD (pin 21) are both LOW. The
output data should not be read 125ns prior to the falling edge
of CONVST and 10ns after the falling edge. Any other
combination of CS and RD will tri-state the parallel output.
Valid conversion data can be read on pins 5 through 16
(MSB–LSB). Refer to Table I for ideal output codes.
In applications where multiple devices are present on the
data bus, care should be taken to ensure that the signal
applied to RD (pin 21) is toggled only when the target device
is properly chip-selected. Toggling the RD pin will advance
the internal read pointer regardless of the state of the chip
select, causing the output data to appear channel-swapped.
If multiple devices share a single read enable from the host
processor, the signal may be ORed with an address-decoded
chip select to ensure channel data integrity. For more infor-
mation, refer to Application Report SBAA138, Reading
Data from the ADS7862, available for download from the TI
website at www.ti.com.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7862 circuitry. This is particu-
larly true if the CLOCK input is approaching the maximum
throughput rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, driving any single conver-
sion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conver-
sion result. Such glitches might originate from switching
power supplies, nearby digital logic or high power devices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the exter-
nal event. This error can change if the external event changes
in time with respect to the CLOCK input.
With this in mind, power to the ADS7862 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor may be used
to low-pass filter a noisy supply. On average, the ADS7862
draws very little current from an external reference as the
reference voltage is internally buffered. If the reference
voltage is external and originates from an op amp, make sure
that it can drive the bypass capacitor or capacitors without
oscillation. A bypass capacitor is not necessary when using
the internal reference (tie pin 1 directly to pin 2).
The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the ‘analog’
ground. Avoid connections which are too close to the ground-
ing point of a microcontroller or digital signal processor. If
required, run a ground trace directly from the converter to
the power supply entry point. The ideal layout will include
an analog ground plane dedicated to the converter and
associated analog circuitry.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7862Y/250 ACTIVE TQFP PBS 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS7862Y/250G4 ACTIVE TQFP PBS 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS7862Y/2K ACTIVE TQFP PBS 32 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS7862Y/2KG4 ACTIVE TQFP PBS 32 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS7862YB/250 ACTIVE TQFP PBS 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS7862YB/250G4 ACTIVE TQFP PBS 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS7862YB/2K ACTIVE TQFP PBS 32 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS7862YB/2KG4 ACTIVE TQFP PBS 32 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7862Y/250 TQFP PBS 32 250 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2
ADS7862Y/2K TQFP PBS 32 2000 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2
ADS7862YB/250 TQFP PBS 32 250 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2
ADS7862YB/2K TQFP PBS 32 2000 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7862Y/250 TQFP PBS 32 250 367.0 367.0 38.0
ADS7862Y/2K TQFP PBS 32 2000 367.0 367.0 38.0
ADS7862YB/250 TQFP PBS 32 250 367.0 367.0 38.0
ADS7862YB/2K TQFP PBS 32 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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