CS48DV2A-DQZ - Cirrus Logic

CONFIDENTIAL DS875F2

http://www.cirrus.com

CS48DV2B Data Sheet

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FEATURES

World’s most cost-effective 32-bit DSP featuring Dolby®

Vo lum e and Audistry® by Dolb y

— Supports native processing at input Fs up to 48kHz

— Singl e download im age enables support for 32 KHz,

44.1 kHz, and 48 kHz audio input

CS48DV2B supports up to 2.0 channels of audio input

and up to 2.1 channels of output

Enables concurrent processing features beyond Dolby

V olume i ncluding Tone Co ntrol, Multiband Pa rametric EQ,

Bass Management, Delays.

Configurable Serial Audio Inputs/Outputs

— Configurable for all input/output digital audio types

(I2S/LJ/RJ)

— 32-bit data path delivers uncompromised dynamic

range

— 192 kHz capable int egra ted S/PDIF transm itte r

— DAO can op erat e in m as ter o r sla ve mod e (SCLK &

LRCLK)

Integrated Clock Manager/PLL

— Cap ab le of o perating f r om a wide va riety of e xte rna l

crystals or external oscillators

Slave Host Boot Capability via Serial Interface

— SPI™ interface capable of running up to 25 MHz

during r un time

1.8V Core and 3.3V I/O that is tolerant to 5V input

Low-power Mode enabled

—Energy Star

® Desig n Compliance Capability via low-

power mode, 268 µW in Standby mode

32-bit

DSP

PXY

Serial

Control 1

Up to 2.1 Ch

Audio Out

GPIO Debug

Watchdog

TMR1

TMR2

PLL

S/PDIF

2.0 Ch.

Audio In

The new CS48DV2B supports a host of signal processing

applicati ons co ncurre ntly, including the mas s produ ction -ready

Dolby Volume solution. See Section 3. for details about

firmware concurrency on the CS48DV2B. The target

applications for the CS48DV2B DSP are:

— Digital Televisions

— Soundbars / DTVs with Integrated Soundbars

—PMD/iPod

® Docking Stations

— Automotive Head Units

— Automotive Outboard Amplifiers

— Blu- ray Disc® & DVD Receivers / HTiB s

— PC Speakers

All of these applications and many more that use volume

control and are subject to playback from sources that do not

have consi stent vo lume le vels will benefit from the CS48D V2B

Dolby Volume solution.

Ordering Information:

See page 21 for ordering information.

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to

www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject t

change without noti ce and is provided “A S IS” witho ut warranty of any kind (express or imp lie d). Custome rs are advi sed to obtain the l atest versi on of relevant inf o

mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplie

at the ti m e of order acknowledg ment , i ncl udi ng t ho se pertaini n g t o warranty, indemnif ica ti on, and limit ati on of li ability. No responsibility is assumed by Cirrus for th

use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties

This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights

trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copie

to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not exten

to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCT OR PRODUCT S MAY INVOLVE POT ENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPER

TY OR ENVIRONM ENTAL DAMAGE (“CRITICAL APPLICAT IO NS” ). CIRRUS PRO DUCTS ARE NOT DESIGNED, AUTH O RIZED OR WARRANTED FOR USE IN

PRODUCTS S URGICALLY IMPLANTED INTO T HE BODY, AUTOMO TIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICA

APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRU

DISCLAIMS AND MAKES NO W ARRANTY, EX PRESS, ST ATUTORY OR IMPL IED, INCLUDING THE IMPLIED WARRAN TIES OF ME RCHAN TABILITY AND FIT

NESS FOR PARTICULAR PURPOSE, WITH REGA RD TO ANY CIRRUS PRODUCT THAT IS USED IN SUC H A M ANNER. IF THE C USTOMER OR CUST OMER'

CUSTOMER USES OR PERMIT S TH E USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGR EES, BY SUCH USE, TO FULLY INDE M

NIFY CIRRUS, ITS OFFICERS, DIRECTO RS, EMPLOYE ES, DISTRIBUTORS AND OTHER AG ENTS FROM A NY AND ALL LIABIL ITY, INCLUDING ATTORNEY S

FEES AND CO ST S, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logi c, Cirr us, the Cir rus Logi c l ogo desi gn s , DSP Composer is a tradem arks of Cirrus Logic, Inc. A ll ot he r brand and product names in this document may b

trademarks or service marks of their respective owners.

Dolby, Audistry, and the sound shell logo are registered trademarks of Dolby Laboratories. Supply of an implementation of Dolby Technology does not convey a licens

nor imply a rig ht under an y patent, or any other indu stri al or Int el l ectua l P roperty Righ t of Dolby Laborator i es, to use the Imple ment at i on in any f i ni she d end-user o

ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.

SPI is a trademark of Motorola, Inc.

C is a registered trademark of Philips Semiconductor.

iPod is a registered trademark of Apple Computer, Inc.

Blu-ray Disc is a registered trademark of SONY KABUSHIKI KAISHA CORPORATION.

Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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Table of Contents

1. Documentation Str ategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Overv iew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1 Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3. Code Ove rlay s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4. Hardware Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.1 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1.1 DSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1.2 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.2 On-chip DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.1 Digital Audio Input Port (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.2 Digital Audio Output Port (DAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.3 Serial Control Port (I2C® or SPI™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.5 PLL-based Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2.6 Hardware Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3 DSP I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.1 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.2 Termination Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3.3 Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.4 Application Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5. Character istic s a nd Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Digital DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.4 Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.5 Thermal Data (48-Pin LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.6 Switching Characteristics— RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.7 Switching Characteristics — XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.8 Switching Characteristics — Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.10 Switching Characteristics — Serial Control Port - SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.12 Switching Characteristics — Serial Control Port - I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.13 Switching Characteristics — Digital Audio Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.14 Switching Characteristics — DSD Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.15 Switching Characteristics — Digital Audio Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6. Ordering Informa ti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

7. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . .22

8. Device Pi nout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

8.1 CS48DV2B, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2 48-pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9. Revisi on History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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List of Figures

Figure 1. RESET Timing.........................................................................................................................................12

Figure 2. XTI Timing ............................................................................................................................................... 12

Figure 3. Serial Control Port - SPI Slave Mode Timing...........................................................................................14

Figure 4. Serial Control Port - SPI Master Mode Timing......................................................................................... 15

Figure 5. Serial Control Port - I2C Slave Mode Timing ........................................................................................... 16

Figure 6. Serial Control Port - I2C Master Mode Timing ......................................................................................... 17

Figure 7. Digital Audio Input (DAI) Port Timing Diagram ........................................................................................ 18

Figure 8. Direct Stream Digital - Serial Audio Input Timing.....................................................................................18

Figure 9. Digital Audio Output Port Timing, Master Mode.......................................................................................20

Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)............................................ 20

Figure 11. CS48DV2B 48-Pin LQFP Pinout Diagram............................................................................................. 23

Figure 12. 48-Pin LQFP Package Drawing.............................................................................................................24

List of Tables

Table 1. CS48DV2B DSP Related Documentation................................................................................................5

Table 2. Device and Firmware Selection Guide.....................................................................................................7

Table 3. Ordering Information..............................................................................................................................21

Table 4. Environmental, Manufacturing, & Handling Information.........................................................................22

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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1. Documentation Strategy

The CS48DV2B Data Sheet describes CS48DV2B multichannel audio processors. This document

should be used in conjunction with the following documents when evaluating or designing a system

around the CS48DV2B processors.

The scope of the CS48DV2B Data Sheet is primarily the hardware specifications of the CS48DV2B

devices. This includes hardware fu nctionality, characteristi c data, pinout, and packaging information.

The intended audience for the CS48DV2B Data Sheet is the system PCB designer, MCU

programmer, and the quality cont rol engineer.

2. Overvi ew

The CS48DV2B DSP is designed to provide high-performance post-processing and mixing of digital

audio. The dual clock domai n provided on the PCM input s allows f or the mixing of audio str eams with

different sampling frequencies. The low-power standby preserves battery life for applications which

are always on, but not necessarily processing audio, such as automotive audio systems.

The CS48DV2B supports dual input clock domains and dual audio processing paths. The

CS48DV2B is available in a 48-pin QFP package. Please refer to Table 2 on page 7 for the input,

output, firmware features of each device.

2.1 Licensing

Licenses are required for all of the 3rd party audio processing algorithms listed in Section 3. Please

contact your local Cirrus Logic Sales representative for more inf o rmation.

Table 1. CS48DV2B DSP Related Documentation

Document Name Description

CS48DV2B Da t a Shee t This document

CS485xx Family Hardware User’s Manual Include s detailed system des ign information including

Typical Connection Diagrams, Boot-Procedures, Pin

Descriptions, etc.

AN298 - CS485xx Family Firmware User’s Manual Includes detailed firmware design information

includi ng signal processing flow diagram s and cont rol

API informatio n

DSP Composer User’s Manual Includes detailed configuration and usage

information for the GUI development tool.

AN298VPMA,Audistry® by Dolb y®” Describes API used to control the Audistry firmware

module.

AN298PPMN, Dolby® Volume Firmware User’s

Manual for the CS48DV2x Family Describes API used to control the Dolby Volume

firmware module.

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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3. Code Overlays

The suite of software available for the CS48DV2B DSP consists of an operating system (OS) and a

library of overlays. The overlays have been divided into three main groups called Matrix-processors,

Virtualizer-processors, and Post- processors. All software components are defined below:

1. OS/Kernel - Encompasses all non-audio processing t asks, including loading data from exter nal

memory, processing host messages, calling audio-processing subroutines, error concealment,

etc.

2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more

output channels than input channels (2Ön channels). Examples are Dolby® Pro Logic® IIx and

DTS Neo:6™. Generally speaking, these modules increase the number of valid channels in the

audio I/O buffer.

3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than

input channe ls (nÖ2 channels) with the effect of providing “phantom” speakers to represent the

physical audio channels that were eliminated. Examples are Dolby Headphone® and Dolby®

Vir tual S peaker®. Generally speak ing, these modules reduce the number of vali d channels in the

audio I/O buffer.

4. Post-processors - Any module that processes audio I/O buff e r PCM data in-place after the

matrix- or virtualiz er-processor s. Examples are the Dolby Volume and Audistr y by Dolby

firmware, bass management, audio manager, tone control, EQ, delay, and customer-specif ic

effects

The bulk of each overlay is stored in ROM within the CS48DV2B, but a small image is required to

configure the overlays and boot the DSP. This small image can either be stored in an external serial

FLASH/EEPROM, or downloaded via a host control ler through the SPI™/I2C® serial port.

The overlay st ructure r educes the time requi red to reconf igure the DSP when a pr ocessing change i s

requested. Each overlay can be reloaded independently without disturbing the other overlays. For

example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not

need to be reloaded — only the new matrix-processor. This fac t is also true for the other overlays.

Table 2 lists the firmware available based on device selection. Please refer to AN298, CS485xx

Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules

available.

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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4. Hardware Functional Description

4.1 DSP Core

The CS48DV2B DSPs are single-core DSP with sep arat e X and Y data and P code memory sp aces.

The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of

performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight

72-bit accumul a tors, four X- and four Y-data registers, and 12 in dex regi sters.

The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between

peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output

(DAO), or any DSP core memory, all without the intervention of the DSP. The DMA engine off loads

data move instructions from the DSP core, leaving more MIPS available for signal processing

instructions.

CS48DV2B functionality is controlled by application codes that are stored in on-board ROM or

downloaded to the CS48DV2B from a host controller or external serial FLASH/EEPROM.

Users can develop their applications using DSP Composer to create the processing chain and then

compile the image into a series of commands that are sent to the CS48DV2B through the SCP. The

processing application can either load modules (matrix-processors, virtualizers, post-processors)

from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP.

The CS48DV2B is suitable for a variety of audio post-processing applications such as automotive

head-ends, automotive amplifiers, and boom boxes.

4.1.1 DSP Memory

The DSP core has its own on-chip data and program RAM and ROM and does not require external

memory for post-processing applications.

The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P

equal in size, or more memory can be alloca ted for Y-RAM in 2kword blocks.

4.1.2 DMA Controller

The powerful 8-channel DMA con tr oller can move data between 8 on-chip resources. Each resource

has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing

Table 2. Device and Firmware Selection Guide

Devices Availability Suggested Applications Specific Features

CS48DV2B-CQZ

CS48DV2B-DQZ In Production Now

• Digital TV

Portable Audio

Docking Station

• Portable DVD

Players

• Multimedia PC

Speakers

• Soundbars

• Automotive

Entertainment

Systems

• 2.1 channels of audio

input and 2.1

channel s of PCM

audio output.

• 512 FFT Window, 20-

Bands/Channel

• Dolby Volume Native

Processing of the

following Fs:

— 32 kHz

— 44.1 kHz

— 48 kHz

CS48DV2B Data Sheet

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modes are supported, with flexible start address and increment controls. The service intervals for

each DMA channel, as well as up to 6 interrupt events, are programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz.

The port is capable of accept ing PCM or DSD formats. Up to 32- bi t word l engths are supported. DSD

is supported and internally converted to PCM before processing. The DAI also supports a time

divisio n multiplexed (TDM) one-line data mo de that packs multiple channels of PCM audio input on a

single data line. The total number of channels that are possible depends on the ratio of SCLK to

LRCLK.

The port has two independent slave-only clock domains. Each data input can be independently

assigned to a clock domain. The sample rate of the input clock domains can be determined

automatically by the DSP, off-loading the task of monitoring the S/PDIF receiver from the host. A

time-stamping featur e all ows the input data to be sample- rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as

192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a

clock slave if an external MCLK or SCLK/LRCLK source is available. One of the ser ial audio pins can

be re-configured as a S/PDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with

embedded clock on a single line) .

The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple

channels of PCM audio on a single data line.

4.2.3 Serial Contr ol Port (I2C® or SPI™)

The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C®

modes. Master/Slave operation is chosen by mode select pins when the CS48DV2B comes out of

Reset. The seri al clock pin can s upport frequenc ies as high as 25 MHz i n SPI mode (SPI clock speed

must always be ≤ (Fdclk/2)). The CS48DV2B serial control port also includes a pin for flow control of

the communicat ions interf ace (SCP_BSY) and a pin to indic ate when the DSP has a message for the

host (SCP_IRQ).

4.2.4 GPIO

Many of the CS48DV2B peripheral pins are multi plexed with GPI O. Each GPIO can be configured as

an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising

edge, falling edge, active-low, or active-high.

4.2.5 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used

to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock

domain can be output on the DAO port for driving audio converters. The CS48DV2B defaults to

running from the external reference frequency and is switched to use the PLL output after overlays

have been loaded and configured, either through master boot from an external FLASH or through

host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output

frequency ratio is selectable between 1:1 (default) or 2:1.

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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4.2.6 Hardware Watchdog Timer

The CS48DV2B has an integrated watchdog timer that acts as a “health” monitor for the DSP. The

watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This

peripheral ensures that the CS48DV2B will reset itself in the event of a temporary system failure. In

stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode

(that is, host MCU present) a GPIO will be used to signal the host th at the watc hdog has expired and

the DSP should be rebooted and re-configured.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS48DV2B pins are multi-functional. For details on pin functionality please refer to the

CS485xx Hardware User’s Manual.

4.3.2 Termination Requirements

Open-drain pins on the CS48DV2B must be pulled high for proper operation. Please refer to the

CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up

resistor is required for proper operation.

Mode select pins in the CS48DV2B are used to select the boot mode upon the rising edge from

reset. A detailed explanation of termination requirements for each communication mode select pin

can be found in the CS485xx Hardware User’s Manual.

4.3.3 Pads

The CS48DV2B I/Os operate from the 3.3 V supply and are 5 V tolerant.

4.4 Application Code Security

The external program code may be encry pted by the programmer to protect any i ntellectual property

it may contain. A secret, customer-specific key is used to encrypt the program code that is to be

stored external to the devic e. Please cont act your local Cirrus representative for details.

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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5. Characteristics and Specifications

Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and

temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C,

CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.

5.1 Absolute Maximum Ratings

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V)

Caution: O peration at or beyond the se limit s may result in permanen t damage to the device. N ormal ope ration is

not guaranteed at these extremes.

5.2 Recommended Operating Conditions

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V)

Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.)

Parameter Symbol Min Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

|VDDA – VDDIO|

VDD

VDDA

VDDIO

-0.3

2.0

3.6

0.3

Input pin current, any pin except supplies Iin -+/-10mA

Input voltage on PLL_REF_RES Vfilt -0.3 3.6 V

Input voltage on I/O pins Vinio -0.3 5.0 V

Storage temperature Tstg -65 150 °C

Parameter Symbol Min Typ Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

|VDDA – VDDIO|

VDD

VDDA

VDDIO

1.71

3.13

1.8

3.3

1.89

3.46

Ambient operating temperature CS48DV2B-CQZ

CS48DV2B-DQZ

TA0

-40

-+70

+85

°C

Parameter Symbol Min Typ Max Unit

High-level input voltage VIH 2.0 - - V

Low-level input voltage, except XTI VIL --0.8V

Low-level input voltage, XTI VILXTI --0.6V

Input Hysteresis Vhys 0.4 V

High-level output voltage (IO = -2mA), except XTI VOH VDDIO * 0.9 - - V

Low-level output volt age (IO = 2mA) , except XTI VOL - - VDDIO * 0.1 V

Input leakage XTI ILXTI --5μA

Input leakage current (all digital pins with internal

pul l-up re si st or s enab led) ILEAK --70μA

CS48DV2B Data Sheet

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5.4 Power Supply Characteristics

(Measurements performed under operating conditions)

5.5 Thermal Data (48-Pin LQFP)

1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top &

bottom layers.

2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm t hick FR-4 material with 1-oz. copper covering 20 % of the top &

bottom layers and 0.5-oz. copper covering 90 % of the internal power plane & ground plane layers.

3. To calculate the die temperature for a given power dissipation

Tj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ]

4. To calculate the case temperature for a given power dissipation

Tc = Tj - [ (Power Dissipation in Watts) * ψjt ]

Parameter Min Typ Max Unit

Operational Power Supply Current:

VDD: Core and I/O operating1

VDDA: PLL operating

VDDIO: With most ports operating

Total Operational Power Dissipation:

Standby Power Supply Current:

VDD: Core and I/O not clocked

VDDA: PLL halted

VDDIO: All connected I/O pins 3-stated by other ICs in system

Total Standby Power Dissipation:

1. Dependent on application firmware and DSP clock speed.

203

480

100

348

μA

μW

Parameter Symbol Min Typ Max Unit

Junction Temperature Tj- - 125 °C

Thermal Resistance (Junction to Ambient)Two-layer Board1

Four-layer Board2θja -

-63.5

54 -

-°C / Watt

Thermal Resistance (Junction to Top of Package)

Two-layer Board3

Four-layer Board4ψjt -

-0.70

0.64 -

-°C / Watt

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

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5.6 Switching Characteristic s— RESET

Figure 1. RESET Timing

5.7 Switching Characteristi cs — XTI

Figure 2. XTI Timing

Parameter Symbol Min Max Unit

RESET minimum pulse width low Trstl 1-ms

All bidi rectional pins high- Z after RESET low Trst2z -100ns

Configuration pins setup before RESET high Trstsu 50 - ns

Configuration pins hold after RESET high Trsthld 20 - ns

Parameter Symbol Min Max Unit

External Crystal operating frequency1

1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z

Fxtal 11.2896 27 MHz

XTI period Tclki 33.3 100 ns

XTI high time Tclkih 13.3 - ns

XTI low time Tclkil 13.3 - ns

External Crystal Load Capacitance (parallel resonant)2

2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a CL outside this range should

be avoided. The crystal oscillator circuit design should follow the crystal manufacturer ’s recommendation for load capacitor

selection.

CL10 18 pF

External Crystal Equivalent Series Resistance ESR 50 Ω

RESET

Trst2z

Trstl

Trstsu Trsthld

HS[3:0]

ll Bidirectional

Pins

tclkih tclkil

Tclki

CS48DV2B Data Sheet

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5.8 Switching Characteristics — Internal Clock

Parameter Symbol Min Max Unit

Internal DCLK frequency1

CS48DV2B-CQZ

CS48DV2B-DQZ

1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart comma nds, the PLL is locked to max Fdclk and remains locked until

the next power-on reset.

Fdclk -

Fxtal

150

MHz

Internal DCLK period1

CS48DV2B-CQZ

CS48DV2B-DQZ

DCLKP -

6.7

6.7 1/Fxtal

1/Fxtal

CS48DV2B Data Sheet

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5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode.

Figure 3. Serial Control Port - SPI Slave Mode Timing

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin

should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3.

fspisck -25MHz

SCP_CS falling to SCP_CLK rising tspicss 24 - ns

SCP_CLK low time tspickl 20 - ns

SCP_C LK high time tspickh 20 - ns

Setup time SCP_MOSI input tspidsu 5-ns

Hold time SCP_MOSI input tspidh 5-ns

SCP_CLK low to SCP_MISO output valid tspidov -11ns

SCP_CLK falling to SCP_IRQ rising tspiirqh -20ns

SCP_CS rising to SCP_IRQ falling tspiirql 0ns

SCP_CLK low to SCP_CS rising tspicsh 24 - ns

SCP_CS rising to SCP_MISO output high-Z tspicsdz -20 ns

SCP_CLK rising to SCP_BSY falling tspicbsyl -3

*DCLKP+20 ns

SCP_BSY

SCP_CS

SCP_CLK

CP_MOSI

CP_MISO

SCP_IRQ

012670567

tspicss

tspickl

tspickh

tspidsu tspidh tspidov

A6 A5 A0 R/W MSB LSB

MSB LSB

tspicsh

tspibsyl

tspiirql

tspiirqh

fspisck

tspicsdz

CS48DV2B Data Sheet

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5.10 Swi tching Characteristics — Serial Control Port - SPI Master Mode

Figure 4. Serial Control Port - SPI Master Mode Timing

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application.

fspisck -F

xtal/22

2. See Section 5.7.

MHz

SCP_CS falling to SCP_CLK rising 3

3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter

tspicss - 11*DCLKP +

(SCP_CLK PERIOD)/2 -ns

SCP_CLK low time tspickl 20 - ns

SCP_C LK high time tspickh 20 - ns

Setup time SCP_MISO input tspidsu 9-ns

Hold time SCP_MISO input tspidh 5-ns

SCP_CLK low to SCP_MOSI output valid tspidov -8ns

SCP_CLK low to SCP_CS falling tspicsl 7-ns

SCP_CLK low to SCP_CS rising tspicsh - 11*DCLKP +

(SCP_CLK PERIOD)/2 -ns

Bus free time between active SCP_CS tspicsx 3*DCLKP - ns

SCP_CLK falling to SCP_M OSI output hig h-Z tspidz -20ns

EE_CS#

SCP_CLK

CP_MISO

CP_MOSI

012670567

tspicss

tspickl

tspickh

tspidsu tspidh tspidov

A6 A5 A0 R/W MSB LSB

MSB LSB

tspicsh

tspicsx

fspisck

tspidz

tspicsl

CS48DV2B Data Sheet

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5.11 Sw itching Char acteristics — Serial Contro l Port - I2C Slave Mode

Figure 5. Serial Control Port - I2C Slave Mode Timing

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin

should be implemented to prevent overflow of the input data buffer.

fiicck - 400 kHz

SCP_CLK low time tiicckl 1.25 - µs

SCP_C LK high time tiicckh 1.25 - µs

SCP_CLK rising to SCP_SDA rising or fal ling for

START or STOP condition tiicckcmd 1.25 µs

START condition to SCP_CLK falling tiicstscl 1.25 - µs

SCP_CLK falling to STOP condition tiicstp 2.5 - µs

Bus free time between STOP and START conditions tiicbft 3-µs

Setup time SCP_SDA input va lid to SCP_CLK rising tiicsu 100 ns

Hold time SCP_SDA input after SCP_CLK falling tiich 20 - ns

SCP_CLK low to SCP_SDA out valid tiicdov -18ns

SCP_CLK falling to SCP_IRQ ris ing tiicirqh -3

*DCLKP + 40 ns

NAK condition to SCP_IRQ low tiicirql 3*DCLKP + 20 ns

SCP_CLK rising to SCB_BSY low tiicbsyl -3

*DCLKP + 20 ns

CP_BSY

CP_CLK

SCP_SDA

SCP_IRQ

01 67801 7

tiicckl

tiicckh

tiicsu tiich

A6 A0 R/W ACK LSB

tiicirqh tiicirql

ACK

MSB

tiicstp

tiiccbsyl

tiicdov tiicb

tiicstscl

tiicckcmd

fiicck

tiicckcmd

tiicf

tiicr

CS48DV2B Data Sheet

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5.12 Swi tching Characteristics — Serial Control Port - I2C Master Mode

Figure 6. Serial Control Port - I2C Master Mode Timing

Parameter Symbol Min Max Units

SCP_CLK frequency1

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application.

fiicck -400kHz

SCP_CLK low time tiicckl 1.25 - µs

SCP_C LK high time tiicckh 1.25 - µs

SCP_SCK rising to SCP _SDA rising or falling for START o r

STOP condition tiicckcmd 1.25 µs

START condition to SCP_CLK falling tiicstscl 1.25 - µs

SCP_CLK falling to STOP condition tiicstp 2.5 - µs

Bus free time between STOP and START conditions tiicbft 3-µs

Setup time SCP_SDA input va lid to SCP_CLK rising tiicsu 100 ns

Hold time SCP_SDA input after SCP_CLK falling tiich 20 - ns

SCP_CLK low to SCP_SDA out valid tiicdov -18ns

CP_CLK

CP_SDA

01 67801 7

tiicckl

tiicckh

tiicsu tiich

A6 A0 R/W ACK LSB

ACK

MSB

tiicstp

tiicdov tiic

tiicstscl

tiicckcmd

fiicck

tiicckcmd

tiicf

tiicr

CS48DV2B Data Sheet

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5.13 Swi tching Characteristics — Digital Audio Slave Input Port

Figure 7. Digital Audio Input (DAI) Port Timing Diagram

5.14 Switching Characteristics — DSD Slave Input Port

Figure 8. Direct Stream Digital - Serial Audio Input Timing

Parameter Symbol Min Max Unit

DAI_SCLK period Tdaiclkp 40 - ns

DAI_SCLK duty cycle - 45 55 %

Setup time DAI_DATAn tdaidsu 10 - ns

Hold time DAI_DATAn tdaidh 5-ns

Parameter Symbol Min Typ Max Unit

DSD_SCLK Pulse Width Low tsclkl 78 - - ns

DSD_SCLK Pulse Width High tsclkh 78 - - ns

DSD_SCLK Frequency (64x Oversampled) - 1.024 - 3.2 MHz

DSD_ A / _B vali d to DSD_SCL K risi ng se tup tim e tsdlrs 20 - - ns

DSD_SCLK rising to DSD_A or DSD_B hold time tsdh 20 - - ns

DAI_SCLK

AI_DATAn

tdaidh

tdaidsu

CS48DV2B Data Sheet

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5.15 Swi tching Characteristics — Digital Audio Output Port

Parameter Symbol Min Max Unit

DAO_MCLK period Tdaomclk 40 - ns

DAO_MCLK duty cycle - 45 55 %

DAO_SCLK period for Master or Slave mode1

1. Master mode timing specifications are char acterized, not production tested.

Tdaosclk 40 - ns

DAO_SCLK duty cycle for Master or Slave mode1-4060%

Master Mode (Output A1 Mode)1,2

2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce

DAO_SCLK, DAO_LRCLK.

DAO_SCLK delay from DAO_MCLK rising edge,

DAO_MCLK as an input tdaomsck -19ns

DAO_LRCLK delay from DAO_SCLK transition, respectively3

3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the

data is valid.

tdaomstlr -8ns

DAO_SCLK delay from DAO_LRCLK transition, respectively3tdaomlrts -8ns

DAO1_DATA[3..0], DAO2_DATA[1..0]

delay from DAO_SCLK transition3tdaomdv -10ns

Slave Mode (Output A0 Mode)4

4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

DAO1_DATA[3..0], DAO2_DATA[1..0]

delay from DAO_SCLK transition3tdaosdv -15ns

DAO_LRCLK delay from DAO_SCLK transition, respectively3tdaosstlr -30ns

DAO_SCLK delay from DAO_LRCLK transition, respectively3tdaoslrts -15ns

DAO_MCLK

DAO_SCLK

DAO_LRCLK

AOn_DATAn

tdaomlclk

tdaomsck

tdaomdv

tdaomlrts

DAO_MCLK

DAO_SCLK

DAO_LRCLK

AOn_DATAn

tdaomclk

tdaomsck

tdaomstlr

Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

CS48DV2B Data Sheet

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Figure 9. Digital Audio Output Port Timing, Master Mode

Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)

DAO_SCLK

DAO_LRCLK

AOn_DATAn

tdaosstlr

tdaosclk

AO_SCLK

AO_LRCLK

tdaoslrts

tdaosd

tdaosclk

Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

CS48DV2B Data Sheet

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6. Ordering Info rmation

The CS48DV2B part number is described as follows:

CS48DVNI-XYZR

where

N - Product Number Variant

I - ROM ID Number

X - Product Grade

Y - Package Type

Z - Lead (Pb) Free

R - Tape and Reel Packaging

NOTE: Please contact the factory for availability of the -D (automotive grade) package.

Table 3. Ordering Information

Part No. Grade Temp. Range Package

CS48DV2B-CQZ Commercial 0 to +70 °C 48-pin LQFP

CS48DV2B-DQZ Automotive -40 to +85 °C 48-pin LQFP

CS48DV2B Data Sheet

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7. Environmental, Manufacturing, & Handling Information

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Table 4. Environmental, Manufacturing, & Handling Information

Model Number Peak Reflow Temp MSL Rating* Max Floor Life

CS48DV2B-CQZ

CS48DV2B-CQZR 260 °C 3 7 Days

CS48DV2B-DQZ

CS48DV2B-DQZR

CS48DV2B Data Sheet

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8. Device Pinout Dia grams

8.1 CS48DV2B, 48-pin LQFP Pinout Diagram

Figure 11. CS48DV2B 48-Pin LQFP Pinout Diagram

XTO

XTI

GNDA

PLL_REF_RES

VDDA (3.3V) GPIO1, DAI1_DATA2, TM2, DSD2

GPIO2, DAI1_DATA3, TM3, DSD3

GPIO16, DAI1_DATA0, TM0, DSD0

GPIO0, DAI1_DATA1, TM1, DSD1

GPIO13, SCP_BSY , EE_CS

GPOI12, SCP_IRQ

GPIO10, SCP__MISO / SDA

GPIO9, SCP_MOSI

GPIO11, SCP_CLK

GND4

GNDIO4

VDD3

GND3

VDDIO3

GNDIO3

GPIO5, DAO1_DATA3, X MTA

GPIO3, DAO1_ DATA1, HS1

DAO1_DATA0, HS0

DAO_LRCLK

DAI1_LRCLK, DAI1_DATA4, DSD5

GPIO18, DAO_MCLK

DAI1_SCLK, DSD-CLK

VDD1

GND1

DAO_SCLK

GPIO4, DAO1_ DATA2, HS2

RESET#

VDDIO1

GNDIO1

GPIO6, DAO2 _DATA0, HS3

GPIO7, DAO2_D ATA1, HS4

VDD2GND2

VDDIO2

GNDIO2

GPIO8, SCP_CS

TEST

DBDA

DBCK

XTAL_OUT GPIO15, DAI2_SCLK

GPIO14, DAI2_LRCLK

GPIO17, DAI2_DATA0, DSD4

CS48DV2B

48-Pin LQFP

CS48DV2B Data Sheet

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8.2 48-pin LQFP Package Drawing

Figure 12. 48-Pin LQFP Package Drawing

48LDLQFP(7x7x1.4mmbody)

Number of Leads

MIN NOM MAX

A1.60

A1 0.05 0.15

A2 1.35 1.40 1.45

b 0.17 0.22 0.27

D9.00BSC

D1 7.00 BSC

e0.50BSC

E9.00BSC

E1 7.00 BSC

theta 0 7

L 0.45 0.60 0.75

L1 1.00 REF

NOTES:

1) Reference document: JEDEC MS-026

2) All dimensions are in millimeters and controlling dimension is in millimeters.

3) D1 and E1 do not include mold flash which is 0.25 mm max. per side.A1

4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.

CS48DV2B Data Sheet

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9. Revision History

Revision Date Changes

F1 December 3, 2008 Initial Release of CS48DV2B Data Sheet

F2 February 16, 2009 Updated Section 5.5, adding Junction Temperature specification.

CS48DV2B Data Sheet

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