FN8582 Rev 1.00 Page 1 of 20
February 13, 2015
FN8582
Rev 1.00
February 13, 2015
ISL6731A, ISL6731B
Power Factor Correction Controllers
DATASHEET
The ISL6731A and ISL6731B are active power factor
correction (PFC) controller ICs that use a boost topology. The
controllers are suitable for AC/DC power systems up to 2kW
and over the universal line input.
The ISL6731A and ISL6731B operate in Continuous Current
Mode (CCM). Accurate input current shaping is achieved with a
current error amplifier. A patent pending breakthrough
negative capacitance technology minimizes zero crossing
distortion and reduces the magnetic components size. The
small external components result in lower design cost without
sacrificing performance.
The internally clamped 12.5V gate driver delivers 1.5A peak
current to the external power MOSFET. The ISL6731A and
ISL6731B provide a highly reliable system that is fully
protected. Protection features include cycle-by-cycle
overcurrent, over power limit, over-temperature, input
brownout, output overvoltage and undervoltage protection.
The ISL6731A and ISL6731B provide excellent power
efficiency and transitions into a power saving skip mode
during light load conditions, thus improving efficiency
automatically. The ISL6731A and ISL6731B can be shut down
by pulling the FB pin below 0.5V or grounding the BO pin.
Two switching frequency options are provided. The ISL6731B
switches at 62kHz, and the ISL6731A switches at 124kHz.
Related Literature
•AN1884, "ISL6731AEVAL1Z and ISL6731BEVAL1Z: Boost
CCM PFC for 300W Universal Input Adaptors"
•AN1885, “ISL6731AEVAL2Z and ISL6731BEVAL2Z: High
Performance Boost CCM PFC Front End for Server Power
Applications”
Features
• Reduced component size requirements
- Enables smaller, thinner AC/DC adapters
- Choke and cap size can be reduced
- Lower cost of materials
• Excellent power factor and THD over line and load
- CCM mode with negative capacitance generator for
smaller EMI filter and improved performance
- Built-in current amplifier with flexibility of gain change
•Better light-load efficiency
- Automatic pulse skipping with programmable threshold
- Programmable or automatic shutdown
• Highly reliable design
- Cycle-by-cycle current limit
- Input average power limit
- OVP and OTP protection
- Input brownout protection
•Small 14 Ld SOIC package
Applications
• Desktop computer AC/DC adaptor
• Laptop computer AC/DC adaptor
•TV AC/DC power supply
•AC/DC brick converters
FIGURE 1. TYPICAL APPLICATION FIGURE 2. PFC EFFICIENCY
+
ISL6731A
VCC
ISEN
ICOMP
VIN
GATE
GND
FB
BO VREG
COMP
VLINE VOUT
V
I
SKIP
OVP
OUTPUT POWER (%)
EFFICIENCY (%)
ISL6731A, NON-SKIP
ISL6731A, SKIP
100
95
60
65
70
90
85
80
75
0 20 40 60 80 100
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 2 of 20
February 13, 2015
Pin Configuration
ISL6731A, ISL6731B
(14 LD SOIC)
TOP VIEW
11
12
14
13
4
3
2
1
NC
GND
ISEN
ICOMP
GATE
VCC
VREG
NC
10
5
VIN SKIP
9
8
6
7
BO
OVP COMP
FB
Pin Descriptions
PIN # I/O SYMBOL DESCRIPTION
1, 13 - NC Not Connected. Must be floating.
2 - GND Ground pin. All voltage levels refer to this pin.
3 I ISEN Current sense pin. The current through this pin is proportional to the inductor current.
4 I/O ICOMP Current error amplifier output pin.
5 I VIN Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider
from the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the
input current. The phase lag is required to compensate the phase lead generated by the EMI filter.
6 I/O BO This pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor. The BO pin is a voltage follower, which will
follow the DC voltage of the VIN pin. The BO pin is internally tied to GND through a resistor RIS. The decoupling capacitor
provides ripple filtering. When the voltage at the BO pin (VBO) drops below brownout voltage threshold, the controller
enters shutdown mode and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling
threshold.
7 I OVP Overvoltage protection pin. Connect this pin to a resistor divider from the output. The resistor divider sets the OVP set point.
When the OVP pin voltage exceeds 104.5% of the reference voltage VREF, OVP is triggered and the gate drive is disabled.
8 I/O COMP Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will
slowly ramp up the voltage of the COMP pin.
9 I FB Voltage feedback pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage.
When the FB pin voltage exceeds 104% of VREF, OVP is triggered and gate drive is disabled. When the FB pin drops below
10% of VREF, the device is put into shutdown mode. There is an internal pull-down current source for open loop protection.
10 I/O SKIP This pin has dual functions. Connecting this pin to ground disables the light load skip function. An internal 20μA current
sources out of this pin. Connect a resistor from this pin to the ground to set the average power trip point. The converter
exits the skip mode when either the VFB drops below 88% of VREF, or the ISEN current goes above 29μA.
11 - VREG Output of internal regulator. The voltage having a ±2% tolerance over line, load and operating temperature. Bypass to GND
with a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass.
12 I VCC Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor.
14 O GATE Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and
1.5A source capability.
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 3 of 20
February 13, 2015
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6731AFBZ ISL 6731AFBZ -40 to +125 14 Ld SOIC M14.15
ISL6731BFBZ ISL 6731BFBZ -40 to +125 14 Ld SOIC M14.15
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6731A, ISL6731B. For more information on MSL please see techbrief
TB363.
TABLE 1. KEY DIFFERENCES IN FAMILY OF ISL6731
VERSION ISL6731A ISL6731B
Switching Frequency 124kHz 62kHz
FN8582 Rev 1.00 Page 4 of 20
February 13, 2015
ISL6731A, ISL6731B
Block Diagram
FB
COMP
GATE
PWM
VCC
CONTROL
LOGIC
VIN
ISEN
OSCILLATOR
COMP
GND
OTP
VCC
BO
IFB
RSEN
RIS
ICOMP
IREF
CEQ GEN.
CURRENT
MIRROR
OVERPOWER
LIMIT
SOFT-START
ENABLE
Vref
SKIP
20µA
SKIP
CLAMP
SKIP
2:1
0.25 VIN¥
BO2
---------------------------- C O M P B
Q1COUT
VOUT
L
COMP-1V
RCS
VCS
RIS IISEN
¥
2
----------------------------------=
CF1
CF2
VLINE CF3
EMI CHOKE
UVLO
RFB1
RFB2
Lm
RIN2
CBO
RIN1
D
ICS
IOC
2
-------------->
ICS
COMPB
DF1
DF2
CREG
LINEAR
REGULATOR
VREG
VI
Gmi
Gmv
OVP
ROV2
ROV1
LF
Vro1
Vro2
FN8582 Rev 1.00 Page 5 of 20
February 13, 2015
ISL6731A, ISL6731B
Application Schematics
Typical 300W Application Schematic
0.22R28
TP7
DNP
0.22R27
R3
2M
R1
2M
D2
C3D04060A
2 1
TP12
GATE1
1u
C9
-+
DB1
GBU806
L1
0u
R19
42.2k
C35
2.2n
C36
2.2n
C20
47n
C19
0.1
VCC
C17
1n
DNP
P4
P1
8AF1
Q2
2N7002
DNP
1
32
10k
R20
DNP
C21
0.1
25k
R21
DNP
VCC
DC+
P7
P6
GND
VCC
C12
DNP
C26
2.2n
C15
150n
3.3M
R6
S1M
D7
3.3M
R10
S1M
D8
3.3V
DZ1
Q1
SPP20N60C3
1
3 2
C5
2.2n
470k
R11
C14
470n
R17
0
5.76k
R13
C3
680 n
UVLO LOGIC
PWM
gm
gm
2.5V
C
SKIP OPL
2:1
+
-
OTP
I MIRROR CEQ
Gen
ICOMP
GATE
GND
FB
COMP
BO
VIN
ISEN
VCC
I*
4*BO*BO
I*= Vin*C
Lin.Reg.
VREG
SKIP
OVP
U1
ISL6731A/B
9
14
2
12
3
4
5
6
8
11
7
10
1
13
C6
2.2n
C16
100n
51k
R4
R2
2.2
L3
2.2m
4 3
1 2
270u
C1
450V
12
62k
R18
C18
1u
0.22R5
3k
R9
C8
220n
C13
47p
470k
R8
VREG
3.3M
R24
C23
1n
3.3M
R23
R25
42.2k
VOUT
GND
FB
BO COMP
GATE
ICOMP
ISEN
VIN
C22
470n
TP11
DNP
OVP
69.8K
R22
PE
AC2
AC1
L2
1.5m
D1
IN5406
TP2
TP1
TP3
TP4
TP5
390V
UNIVERSAL INPUT
90~265Vac
TP9
TP10
P5
1u
C7
P2
P3
P8DNP
P9
DNP
C10
6.8n
C11
1n
TP6
R14
30k
TP8
DNP
RV1
MOV /DNP
L4
2.2m
4 3
1 2
C2
470n
R26
49.9
FN8582 Rev 1.00 Page 6 of 20
February 13, 2015
ISL6731A, ISL6731B
Typical 85W Application Schematic
Application Schematics (Continued)
1u
C9
R19
42.2k
C20
47n
VCC
P6
P7
GND
VCC
C15
100n
R6
3.3M
R10
3.3M
3.3V
DZ1
R11
470k
C14
470n
R13
5.76k
C16
1n
R18
68k
C18
2.2u
R9
2.1k
C8
220n
C13
220p
R8
470k
R22
69.8K
R1
2M
R3
2M
L4
CMT1
4 3
1 2
P4
P1
S1M
D7
S1M
D8
AC2
AC1
F1 3.15A
UNIVERSAL INP UT
90~265Vac
C2
100n
UVLO LOGIC
PWM
gm
gm
2.5V
C
SKIP OPL
2:1
+
-
OTP
I MIRROR CEQ
Gen
ICOMP
GATE
GND
FB
COMP
BO
VIN
ISEN
VCC
I*
4*BO*BO
I*= Vin*C
Lin.Reg.
VREG
SKIP
OVP
U1
ISL6731A
9
14
2
12
3
4
5
6
8
11
7
10
1
13
1u
C7
C11
470p C10
6.8n
R14
5.36k
R28
0.22
S3KB-TP
D4
S3KB-TP
D5
S3KB-TP
D6
S3KB-TP
D3 D2
C3D04060E
3 1
S3KB-TP
D1
L2
2.2m
DC+
Q1
IPP60R600C6
1
3 2
C3
330n
R4
51k
R2
2.2
56u
C1
450V
12
VOUT
TP9
390V
P2
TP10
P3
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 7 of 20
February 13, 2015
Absolute Maximum Ratings Thermal Information
VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
GATE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18V
VIN, BO, ISEN, FB, OVP, ICOMP, SKIP, VREG and
COMP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.3V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD-C101E) . . . . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V to + 20V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
SOIC Package (Notes 4, 5) . . . . . . . . . . . . . 77 38
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications Operating Conditions: VCC = 15V, TA = +25°C. Boldface limits apply across the operating temperature range,
-40°C to +125°C.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8)TYP
MAX
(Note 8)UNITS
VCC SUPPLY CURRENT
Start-Up Current ISTART VFB = 1V, VCC < VCC(ON) 73 106 139 µA
Standby Current ISTDN VFB = GND, VCC > VCC(ON) 179 237 295 µA
Skip Mode Current ICCSKIP VFB = 2.5V, COMP = SKIP*0.25 +1V 580 690 850 µA
Operating Current (Note 6)I
CC GATE is floating 3.0 3.7 4.5 mA
VCC UVLO
UVLO Rising Threshold VCC(ON) 91011V
UVLO Falling Threshold VCC(OFF) 6.7 7.5 8.3 V
UVLO Threshold Hysteresis VCC(HYS) 2.5 V
REGULATOR VOLTAGE VREG
Overall Accuracy VREG IREG = 0 to -10mA, VCC = 15V, load capacitor = 47nF 5.1 5.4 5.6 V
Current Limit 30 50 70 mA
PWM CONVERTERS
Maximum Duty Cycle fSW = 124kHz for ISL6731A and
fSW = 62kHz for ISL6731B
94.8 96.5 %
OSCILLATOR
Free Running Frequency, ISL6731A TA = -40°C to +125°C, VIN = 0.6V 95.5 107 117 kHz
Free Running Frequency, ISL6731A TA = -40°C to +125°C, VIN = 2.5V 111 125 138 kHz
Free Running Frequency, ISL6731B TA = -40°C to +125°C, VIN = 0.6V 43.5 54 63.7 kHz
Free Running Frequency, ISL6731B TA = -40°C to +125°C, VIN = 2.5V 56.5 64 70.7 kHz
PWM Ramp Amplitude Vm1.33 1.46 1.59 V
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 8 of 20
February 13, 2015
GATE DRIVER
Gate Drive Pull-Down Resistance VCC = 15V, IGATE = 15mA 2.33 4.46 Ω
Gate Drive Pull-Up Voltage Drop VCC = 9V, IGATE = 15mA 0.15 0.3 0.45 V
Gate Drive Max. Sourcing/Sinking
Current
1.5 A
Rise Time CO = 2.2nF, VCC = 15V, gate voltage rise time from 10% to
90% of VGC
34 62 ns
Fall Time CO = 2.2nF, VCC = 15V, gate voltage fall time from 10% to
90% of VGC
34 57 ns
Gate Clamp Voltage VGC 10.5 12 13.5 V
VOLTAGE REFERENCE
Reference Voltage VREF 2.48 2.5 2.52 V
Feedback Pin Pull-Down Current IFB 65 nA
Rising Threshold to Enable Converter FB_EN 280 300 320 mV
Falling Threshold to Disable Converter FB_DIS 190 202 214 mV
Enable Hysteresis FB_Hys 100 mV
VOLTAGE ERROR AMPLIFIER
Error Amp Transconductance Gmv 50 77 104 µA/V
ISource/Sink 13 µA
COMP Offset Voltage VCOMP_OFF 0.95 1.01 1.07 V
COMP Soft-Start Enable Voltage VCOMP_EN 0.58 0.64 0.75 V
INPUT VOLTAGE SENSING
VIN Leakage Current 9nA
MULTIPLIER GAIN
GMUL COMP = 2.5V, VIN = 1.0V, BO = 1.0V, ISEN = 50µA 0.196 0.25 0.296 V/V
CURRENT ERROR AMPLIFIER
Current DC Gain AIDC IICOMP/IISEN 1.6 1.9 2.2 A/A
Error Amp Transconductance Gmi IICOMP = ±20µA 205 268 331 µA/V
ICOMP Source/Sink Current (Note 7) 60 µA
Current Sensing Input Offset -3 2 7 mV
LIGHT LOAD EFFICIENCY ENHANCEMENT AND OVERPOWER PROTECTION
Skip Current Reference (Note 7)I
SKIP VSKIP = 2V -23 -20 -17 µA
Skip Falling Threshold VSKIP_THf 450 498 550 mV
Skip Rasing Threshold VSKIP_THr 570 616 690 mV
COMP Upper Limit VCUL 3.53 3.85 4.17 V
COMP Valid Range VCUL-1V 2.5 2.83 3.16 V
FB Exit Threshold Voltage VFB_EXIT Fraction of VREF, IISEN = 0µA 87 88 89 %
ISEN Exit Threshold Current ISEN_EXIT VFB = 2.5V -38 -29 -20 µA
Electrical Specifications Operating Conditions: VCC = 15V, TA = +25°C. Boldface limits apply across the operating temperature range,
-40°C to +125°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8)TYP
MAX
(Note 8)UNITS
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 9 of 20
February 13, 2015
BROWNOUT DETECTION
Brownout Rising Threshold VBO_R 478 494 510 mV
Brownout Falling Threshold VBO_F 387 401 415 mV
OVERVOLTAGE PROTECTION
Overvoltage Protection, FB pin VRO1 Fraction of VREF; ~1µs noise filter 103 104.1 106 %
Overvoltage Protection, OVP pin VRO2 Fraction of VREF; ~1µs noise filter 103 104.2 106 %
OVERCURRENT PROTECTION
Overcurrent Threshold IOC -197 -177 -159 µA
THERMAL SHUTDOWN
Shutdown Temperature (Note 7)160 °C
Thermal Shutdown Hysteresis (Note 7) 25 °C
NOTES:
6. This is the VCC current consumed when the device is active but not switching. Does not include gate drive current.
7. Limits should be considered typical and are not production tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Electrical Specifications Operating Conditions: VCC = 15V, TA = +25°C. Boldface limits apply across the operating temperature range,
-40°C to +125°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8)TYP
MAX
(Note 8)UNITS
Typical Performance Curves
FIGURE 3. FEEDBACK ACCURACY FIGURE 4. FSW vs TEMPERATURE, VCC = 15V
FSW NORMALIZED (%)
99.0
99.5
100.0
101.0
VIN = 0.6V
VIN = 2.5V
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120 140
100.5
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 10 of 20
February 13, 2015
FIGURE 5. AIDC vs TEMPERATURE FIGURE 6. FSW vs VIN, TA = +25°C
FIGURE 7. UVLO THRESHOLDS vs TEMPERATURE FIGURE 8. VCC SUPPLY CURRENT vs TEMPERATURE
FIGURE 9. GATE DRIVE TIMING vs TEMPERATURE (LOAD = 2.2nF)
Typical Performance Curves (Continued)
TEMPERATURE (°C)
97
98
99
100
101
-40 -20 0 20 40 60 80 100 120 140
AIDC NORMALIZED (%)
75
80
85
90
95
100
105
FSW NORMALIZED (%)
VIN (V)
0 0.51.01.52.02.53.0
98
99
100
101
102
-40 -20 0 20 40 60 80 100 120 140
UP
DOWN
HYSTERESIS
TEMPERATURE (°C)
UVLO THRESHOLD NORMALIZED (%)
THRESHOLD
THRESHOLD
98
99
100
101
102
-40 -20 0 20 40 60 80 100 120 140
ICC
TEMPERATURE (°C)
VCC CURRENT NORMALIZED (%)
(GATE FLOATING)
ISTART
TEMPERATURE (°C)
GATE DRIVE TIMING NORMALIZED (%)
96
98
100
102
104
106
108
110
112
-40 -20 0 20 40 60 80 100 120 140
RISE TIME
FALL TIME
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 11 of 20
February 13, 2015
Functional Description
VCC Undervoltage Lockout (UVLO)
The ISL6731A and ISL6731B start automatically once the
voltage at VCC exceeds the UVLO threshold.
Shutdown
When the VFB pin is below 0.2V, the controller is disabled and
the PWM output driver is tri-stated. When disabled, the IC power
will be reduced. During shutdown, the COMP pin is discharged to
GND and the controller is disabled. The Over-Temperature
Protection (OTP) is still alive to prevent the controller from
starting up in a high temperature ambient condition.
In the event that the FB pin is disconnected from the feedback
resistors, the FB pin is pulled to ground by an internal current
source IFB. When the FB pin voltage drops below 0.2V, the gate
driver is disabled. The ISL6731A or ISL6731B enters shutdown
mode.
Soft-Start
The COMP pin is released once the soft-start operation begins. A
13µA current sources out to the RC network connected from the
COMP pin until the FB pin voltage reaches 90% of the reference
voltage.
Switching is inhibited when the COMP pin voltage is below 1V.
When the COMP pin reaches 1V, the current error amplifier and
the gate driver are activated and the converter starts switching.
During UVLO, brownout and shutdown, the COMP is pulled to the
ground.
Input Voltage Sensing
The VIN pin is needed to sense the rectified input voltage. The
sensed semi-sinusoidal waveform is needed to shape the
inductor current, which helps achieves unity power factor. At the
same time, the voltage on the VIN pin is used to generate the
negative capacitive element at the input. This will cancel the
input filter capacitor, CF. Canceling the effect of CF will increase
the displacement power factor and alleviate the zero crossing
distortion, which is related to the distortion power factor.
The BO pin also utilizes the VIN resistor divider for voltage
sensing. Set the resistor divider ratio to satisfy the brownout
requirement.
First, calculate the resistor divider ratio, KBO.
Where VF is the forward voltage drop of the bridge rectifier and
the voltage drop of DF1; DF2.
Then, select the RIN2 based on the highest reasonable resistance
value. Then select the RIN1 based upon the desirable minimum
RMS value of the line voltage for the PFC operation.
Inductor Current Sensing
The current sensing of the converter has two purposes. One is to
force the inductor current to track the input semi-sinusoidal
waveform. The other purpose is for overcurrent protection. Refer to
Figure 11 for the current sensing scheme. The sensed current ICS
is in proportion to the inductor current, IL as described in
Equation 3:
where:
RCS is the current sensing resistor with low value in the return
path to the bridge rectifier.
RSEN is the current scaling resistor connected between ISEN to
the RCS.
A high value RCS renders more accurate current sensing. It is
recommended to use the RCS to render 120mV peak voltage at
the maximum line voltage during full load condition.
Where is the efficiency of the converter at the maximum line
input with full load.
FIGURE 10. INPUT VOLTAGE SENSING SCHEMATIC
BO
RIN1 CBO
VIN
CF2
VLINE CF3
EMI CHOKE
Lm
DF1
DF2
RIN2
KBO
VBORMAX
VRMSmin 2VF
–
-------------------------------------------
=(EQ. 1)
RIN1
KBO
1K–BO
--------------------- RIN2
=(EQ. 2)
ICS
1
2
---RCS
RSEN
----------------IL
=(EQ. 3)
FIGURE 11. INDUCTOR CURRENT SENSING SCHEME
Q1 COUT
VOUT
L
CF1
VI
RCS
ISEN
RSEN
CURRENT
MIRROR
2:1
ICS 0.5 IOC
>
ICS
RCS
120mV VRMSMAX 
2P
Omax
-------------------------------------------------------------
(EQ. 4)
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 12 of 20
February 13, 2015
Since the RCS sees the average input current, high value RCS
generates high power dissipation on the RCS. Use a reasonable
RCS according to the resistor power rating. The worst-case power
dissipation occurs at the input low line when input current is at
its maximum. Power dissipation by the resistor is:
where:
IRMSMAX is the maximum input RMS current at the minimum
input line voltage, VRMSmin.
Select the RSEN according to the peak current limit requirement.
The resistor is sized for an overload current 25% more than the
peak inductor peak current.
Negative Input Capacitor Generation
(Patent Pending)
The patent pending negative capacitor generation capability of
ISL6731A and ISL6731B allow the capacitor CF2 to be moved
from before the bridge rectifier (Figure 12) to after the bridge
rectifier (Figure 13). Thus, a smaller, lower cost CF2 can be used.
The change in topology reduces the size of the EMI filter.
Furthermore, CF1 can be increased thus decreasing the size of LF
(Figure 13).
For applications where the output power is above 500W, the
negative capacitance helps to improve the power factor
dramatically. Refer to Table 2 for the recommended filtering
capacitor to be placed after the bridge rectifier, CF1.
Additional CF1 may be used to accommodate the use of small
boost inductor or to eliminate the differential mode filter inductor
as long as the equipment meets the power factor or goal.
The equivalent negative capacitor is a function of the input
voltage divider ratio, KBO, the current sensing gain and current
compensation error integration gain.
Adjusting the negative CEQ can be achieved by adjusting the
current compensation network.
Frequency Modulation
The ISL6731A and ISL6731B can further reduce EMI filter size by
lowering the differential noise power density. The reduction is
achieved by switching frequency modulation.
The frequency varies with the VIN pin. The switching frequency
reaches the peak value when the VIN pin voltage is 2V as shown
in Figure 6. The peak value of ISL6731A is 124kHz, and the
ISL6731B is 62kHz.
Output Voltage Regulation
The output voltage is sensed through a resistor divider. The
middle point of the resistor divider is fed to the FB pin. The
resistor divider ratio sets the output voltage. The
transconductance error amplifier generates a current in
proportion to the difference between the FB pin and the 2.5V
internal reference. The PFC is stabilized by the compensation
network that is connected from the COMP pin to the ground.
The voltage of the COMP sets the input average power by
determining the amplitude of the current reference. To keep the
harmonic distortion to a minimum, it is desirable to set the
control bandwidth much lower than twice of the line frequency.
The recommended voltage loop bandwidth is 10Hz.
During start-up, the compensation capacitors and the charging
current from the error amplifier sets the input power increase
rate. Thus, soft-start is achieved.
The COMP is discharged during shutdown and fault conditions.
Light Load Efficiency Enhancement
For PC, adaptor and TV applications, it is desirable to achieve
high efficiency at light load conditions and low standby current.
The ISL6731A and ISL6731B can enter light load skip mode
automatically. The skip mode trigger threshold is adjustable by
the SKIP pin. A 20µA current source out of the SKIP pin sets the
voltage on the pin via a resistor connected between the pin and
ground. Connecting this pin to ground disables the light load skip
function.
The voltage error amplifier output, COMP, is an indicator of the
average input power level. The controller compares the V(COMP)
and V(SKIP). If V(COMP)-1V is less than V(SKIP)*0.25, the PFC
controller stops gate switching and the COMP pin voltage is
clamped to V(SKIP)+0.6V.
The controller exits skip mode when VFB drops to 88% (typical) of
the reference voltage or when the sensed returned current
exceeds 29µA.
FIGURE 12. TYPICAL PFC INPUT FILTER CIRCUIT
FIGURE 13. LOW COST PFC INPUT FILTER CIRCUIT
TABLE 2. RECOMMENDED FILTERING CAPACITOR
CF1 PO < 100W 100W < PO < 500W PO > 500W
Typical
C(µF)/100W
0.68 0.33 0.22
PRCS IRMSMAX

2RCS
=(EQ. 5)
CF1
CF2
VLINE CF3
EMI CHOKE
Lm
BRIDGE RECFIFIER
LF
CF1
CF2
VLINE CF3
EMI CHOKE
Lm
BRIDGE RECFIFIER
LF
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 13 of 20
February 13, 2015
Protection Circuits
Input Brownout, BO Protection
Brownout occurs when there is a drop in the line voltage. The BO
pin is a dual function pin. The BO pin detects the brownout
condition and shuts down the gate driver and controller. During
normal operation, the BO pin is used to compensate the effect of
the input line voltage change on the voltage loop. To keep the
harmonic distortion low, the corner frequency formed by the RBO
and CBO should be lower than 6Hz.
The BO pin is the output of the average voltage of the rectified
voltage. The PFC controller is turned off when the BO pin drops
below 0.4V. This protects the PFC power stage to enable
operation at or below brownout condition for long periods of
time. The controller resumes operation when the BO pin returns
to 0.5V.
The BO pin is usually connected to GND through a capacitor, CBO.
To avoid distortion on the VIN pin, select CBO so that:
Overcurrent Protection
The peak current limit function prevents the inductor from
saturation. The gate driver turns off when the current goes above
the current limit set point.
Overpower Protection
The overpower protection is implemented by limiting the COMP
pin voltage higher than 3.85V (typical).
Overvoltage Protection
If the voltage on the FB pin exceeds the reference voltage VREF by
about 4%, the gate driver is turned off.
If the voltage on the OVP pin exceeds the VREF by about 4.5%, the
gate driver is turned off.
The controller resumes normal operation after both OVP and FB
pin drops below VREF.
Over-Temperature Protection
The ISL6731A and ISL6731B are protected against
over-temperature conditions. When the junction temperature
exceeds +160°C, the PWM shuts down. Normal operation is
resumed when the junction temperature decreases below +135°C.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using wide,
short printed circuit traces. The critical components should be
located as close together as possible using ground plane
construction or single point grounding.
Figure 14 shows the critical power components; Q1, D and COUT.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of the ground or the
power plane in a printed circuit board. The components shown in
Figure 14 should be located as close together as possible. Please
note that the capacitors CVCC and CO each represent numerous
physical capacitors. Locate the ISL6731A or ISL6731B within 2
inches of the MOSFET, Q1. The circuit traces for the MOSFETs’
gate and source connections from the ISL6731A and ISL6731B
must be sized to handle up to 1.5A peak current.
Component Selection Guidelines
A 300W, universal input, PFC converter design is provided for
demonstration. The design method is for a continuous current
mode power factor correction boost converter with the
ISL6731B. The switching frequency is 62kHz.
Tables 3 shows the design parameters.
BOOST INDUCTOR SELECTION
First, calculate the maximum input RMS current, IINMAX.
Where is the converter efficiency at VRMSmin. PF is the power
factor at VRMSmin.
Assuming the current is sinusoidal and the peak-to-peak ripple at
line is 40%.
CBO 0.22F»(EQ. 6)
TABLE 3. CONVERTER DESIGN PARAMETERS
PARAMETER CONDITIONS MIN TYP MAX UNIT
VLINE 90 115/230 265 VAC
FLINE 47 63 Hz
POMAX Maximum Output Power 300 W
THOLD Hold Up Time 20 ms
Efficiency VLINE = 115VAC 92 %
FIGURE 14. CRITICAL CURRENT POWER COMPONENTS
Q1COUT
L
D
GATE
VCC
CVCC
IINMAX
POMAX
VRMSmin
-----------------------------------
=(EQ. 7)
IINMAX
300W
0.92 90V
---------------------------- 3.62A== (EQ. 8)
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 14 of 20
February 13, 2015
The boost inductor, LBST, is given in Equations 9 and 10:
Choose inductance of 1.5mH, consider the µr will decrease at high
current for a powder core inductor. The peak current of the
inductor is the sum of the average peak inductor current and half
of the peak-to-peak ripple current. Select and design the boost
inductor as given by Equation 11. The ISL6731A and ISL6731B
provides peak current limit function that can prevent the boost
inductor saturation. Assuming 25% margin is given to the OCP
threshold, select and design the boost inductor with saturation
current given by Equation 11 with 25% margin.
INPUT RECTIFIER
The maximum average input current is calculated:
Select the bridge diode using Equation 15 and sufficient reverse
breakdown voltage. Assuming the forward voltage, VF,BR, is 1V
across each rectifier diode. The power loss of the rectifier bridge
can be calculated:
INPUT CAPACITOR SELECTION
Refer to Table 2 for the recommended input filter capacitor value.
This is the recommended capacitor used after the diode bridge.
For better power factor, less capacitance can be used. To lower
the input filter inductor size, more capacitance can be used.
One 0.68µF capacitors is used for CF1.
BOOST DIODE SELECTION
The boost diode loss is determined by the diode forward voltage
drop, VF and the output average current. The maximum output
current is:
The forward power loss on the diode is:
The CREE C3D10060A SiC Schottky diode is selected.
The reverse recovery loss on the diode can be calculated. The
QRR is found from the diode datasheet. QRR = 25nC.
The reverse recover loss on the diode can be estimated:
The total power loss on the diode is:
MOSFET POWER DISSIPATION
The power dissipation on the MOSFET is from two different types
of losses; the conduction loss and the switching loss.
For the MOSFET, the worst case is at minimum line input voltage.
First, the drain-to-source RMS current is calculated:
The MOSFET, SPP20N60C3 is selected.
The switching loss of the MOSFET consists of three parts: the
turn-on loss, the turn-off loss and the diode reverse recovery loss.
From the MOSFET datasheet, the typical switching losses curves
are provided.
When RG = 3.6Ω, ID = 6A, EON = 0.013mJ, EOFF = 0.020mJ.
The switching loss due to transition is calculated:
The loss caused by COSS can be estimated as:
From the MOSFET datasheet, the COSS =197pF when
VOUT = 390V.
LBST
2VRMSmin
0.4 Fsw 2 IINMAX
----------------------------------------------------------------1
2V
RMSmin
VOUT
---------------------------------------
–



(EQ. 9)
LBST
90V
0.4 64kHz 3.62A
------------------------------------------------------1290V
390V
------------------------
–


654H=(EQ. 10)
ILPeak 2IINMAX 1I
2
-----
+


=(EQ. 11)
ILPeak 23.88A11.786A
2
-------------------
+


6.017A==
(EQ. 12)
IINAVE max
22IINMAX
------------------------------------------
=(EQ. 13)
IINAVE max
223.62A
-------------------------------------- 3.3A== (EQ. 14)
PBR 2V
FBR
IINAVE MAX
=(EQ. 15)
PBR 21V3.3A6.524W== (EQ. 16)
CF1 300W 0.33
100
-----------
0.99F== (EQ. 17)
IOUT max
POMAX
VOUT
--------------------
=(EQ. 18)
IOUT max
300W
390V
----------------0.77A== (EQ. 19)
PFD IOUT max
VF
=(EQ. 20)
PFD 0.77A 0.9V0.692W== (EQ. 21)
PRRD
1
4
---QRR VOUT
Fsw
=(EQ. 22)
PRRD
1
4
---25nC390V62kHz0.156W==
(EQ. 23)
PDPFD PRRD
+0.692 0.156+W 0.848W== = (EQ. 24)
IDS max
IINMAX 182
3
-----------VRMSmin
VOUT
--------------------------
–= (EQ. 25)
IDS max
3.623A 1 82
3
-----------90V
390V
--------------
–3.081A==
(EQ. 26)
PCOND IDS max
2rDS on
=(EQ. 27)
PCOND 3.3A20.285 2.71W== (EQ. 28)
PSW EON EOFF
+Fsw
=(EQ. 29)
PSW 0.013mJ 0.020mJ+64kHz2.09W==
(EQ. 30)
POSS
2
3
---Coss VOUT
2
Fsw
=(EQ. 31)
POSS
2
3
---197pF 390V2
64kHz1.28W==
(EQ. 32)
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 15 of 20
February 13, 2015
THE TOTAL LOSS ON THE MOSFET
OUTPUT CAPACITOR SELECTION
The output capacitor, CO, is required to hold the output above
300V during one line cycle. For capacitors with 20% tolerance,
the tolerance should be taken into consideration. Thus, the
output capacitance should be greater than:
Calculate the ripple RMS current through the capacitor:
Select the proper capacitor according to the hold time and ripple
RMS current requirement. The actual capacitance is 270µF.
It is important to make sure the output peak-to-peak ripple is
less than the minimum OVP threshold as specified in the table
on “Electrical Specifications” on page 7. The ESR of the capacitor
at 2 times of line frequency is found in the capacitor datasheet.
The ESR is 737mΩ at 100Hz.
The minimum OVP threshold is 103% of the nominal output
value. The maximum output peak-to-peak ripple should be less
than 6% of the nominal value, which is 23.4VP-P.
CURRENT SENSING RESISTORS
Please refer to Equation 4 for calculation of the current sensing
resistor RCS.
While a large RCS renders better current sensing accuracy, larger
RCS also incurs higher power dissipation. Select three 0.22Ω
resistors in parallel as RCS.
The maximum power dissipation on the RCS occurs at low line and
full load condition. The maximum power dissipation is calculated:
The resistor, RSEN sets the overcurrent protection limit. From
Equation 3, RSEN should be greater than:
Where |x| stands for the ABS(x) function, IOC is the overcurrent
threshold.
Select RSEN from available standard value resistors, the selected
RSEN is 3kΩ
CURRENT LOOP COMPENSATION
The input current shaping is achieved by comparing the sensed
current signal to the sensed input voltage signal. The current error
amplifier (Gmi), together with the current compensation network,
adjusts the duty cycle so that the inductor current traces the
sensed rectified voltage. Thus, unity power factor is achieved.
The compensation network consists of the Trans-Conductance
error amplifier (Gmi) and the impedance network (ZICOMP). The
goal of the compensation network is to provide a closed loop
transfer function with the sufficient 0dB crossing frequency
(f0dB) and adequate phase margin. Phase margin is the
difference between the open loop phase at f0dB and 180°. The
following equations relate the compensation network’s poles,
zeros and gain to the components (Ric, Cic and Cip) in Figure 15.
PCOND PSW P+OSS
+2.71W 2.09W 1.28W++ 6.08W==
(EQ. 33)
CO
2T
HOLD P
OMAX
VOUT
2VHOLD
2
–
---------------------------------------------------- 1
10.2–
-----------------
(EQ. 34)
CO
2 20ms 300W
390
2300V
2
–
---------------------------------------------- 1.25 242F= (EQ. 35)
ICORMS max
IOUT max
82
3
-----------VOUT
VRMSmin
--------------------------
1–= (EQ. 36)
ICORMS max
0.77A 82
3
-----------390V
90V
--------------
1–1.577A==
(EQ. 37)
VOpp IOUT max
4fline COESR
21+
2fline
CO0.8
-----------------------------------------------------------------------
=(EQ. 38)
VOpp 0.77A 450Hz 270F0.77 
21+
250Hz270F0.8
--------------------------------------------------------------------------------------------
9.6V==
(EQ. 39)
RCS
120mV 265V 0.92
2300W
-------------------------------------------------------
0.069=(EQ. 40)
RCS 0.073=(EQ. 41)
PRCSMAX IINMAX
2RCS
=(EQ. 42)
PRCSMAX 3.623A20.073 0.963W== (EQ. 43)
RSEN
RCS ILPeak 10.2+
20.5I
OC
-----------------------------------------------------------------
(EQ. 44)
RSEN
0.0736.017A 1.2
290A
-----------------------------------------------------------
2.9k=(EQ. 45)
FIGURE 15. INDUCTOR CURRENT SENSING SCHEME
Q1COUT
VOUT
L
CF1
RCS
ISEN
RSEN
CURRENT
MIRROR
2:1 ICS
ICOMP
IREF
Gmi
Ric
Cic
RIS
Cip
VI
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 16 of 20
February 13, 2015
Use the following guidelines for locating the poles and zeros of
the compensation network.
Near the crossover frequency, the transfer function from duty
cycle to inductor current is well approximated by Equation 48:
The compensation gain uses external impedance networks as
shown in Figure 15, Gci(s) is given by:
The current gain and modulation gain Gsm is:
where Vm is the amplitude of the PWM carrier. The open loop
gain of the current loop is:
It is recommended to set the crossover frequency, FC from 1/10
to 1/6 of the switching frequency with a phase margin of 60°. A
high frequency pole, FP, is set at 1/2 of the switching frequency
for ripple filtering. In this example, we set the FC at 14kHz.
Where M is the phase margin, which is 20°. FP = 6kHz. This is
an aggressive example to fulfill a tight THD for light load.
Thus, the current loop compensation zero is:
The total compensation capacitance is calculated:
The value of the noise filtering capacitor is:
The value of Cic is:
The value of Ric is:
Select the RC value from the standard value, we have:
Ric = 30kΩ, Cic = 6.8nF, Cip = 1nF. Figure 17 shows the actual
bode plot of current loop gain.
FIGURE 16. ASYMPTOTIC BODE PLOT FOR CURRENT LOOP GAIN
10 100
-40
-20
0
20
40
60
80
100
120
FREQUENCY (Hz)
GAIN (dB)
FP
FZ
1k 10k 100k
GILOOP (s)
FC
Gsm
Gid (s)
Gci (s)
FZ
1
2Ric Cic
------------------------------------
=(EQ. 46)
FP
1
2Ric
Cip Cic
Cip Cic
+
------------------------
---------------------------------------------------
=
(EQ. 47)
Gid s VOUT
LBST s
----------------------
=(EQ. 48)
Gci s Gmi 1
Cic Cip
+s
------------------------------------
s
2FZ

---------------------- 1+
s
2FP

-----------------------1+
---------------------------------
=(EQ. 49)
Gsm Rcs
Rsen
---------------Ris
2
--------- 1
Vm
---------
=(EQ. 50)
GILOOP s Gid s Gsm Gci
s=(EQ. 51)
FZ
FC
FC
FP
-------



atan M
+



tan
--------------------------------------------------------
=(EQ. 52)
FZ
14kHz
14kHz
6kHz
------------------


atan 20deg+


tan
----------------------------------------------------------------------------
=0.78kHz=(EQ. 53)
Cip Cic
VOUT
LBST 2fc

2
---------------------------------------AIDC
Vm
--------------RCS
RSEN
----------------




1f
cfz

2
+
1f
cfp

2
+
-------------------------------




=+ (EQ. 54)
Cip Cic 7.345nF=+ (EQ. 55)
Cip Cip CiC
+
fz
fp
----
=(EQ. 56)
Cip 7.345nF 0.78kHz
6Hz
-----------------------
0.958nF== (EQ. 57)
Cic 7.345nF 0.958nF–6.378nF== (EQ. 58)
Ric
1
20.78kHz 6.378nF
--------------------------------------------------------------31.85k== (EQ. 59)
0
50
GAIN (dB)
10 100
0
30
60
90
FREQUENCY (Hz)
PHASE (°)
45
60
1k 10k 100k
FIGURE 17. BODE PLOT OF THE ACTUAL CURRENT LOOP GAIN
100 FP
FZ
FP
FZ
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 17 of 20
February 13, 2015
INPUT VOLTAGE SETTING
First, set the BO resistor divider gain, KBO according to
Equations 1 and 2.
Assuming the converter starts at VLINE = 80VRMS, then the BO
resistor divider gain, KBO, should be:
In this design, two 470kΩ resistors in series are used for RIN2.
Therefore, RIN1 is calculated:
We choose RIN1 = 5.76kΩ, the actual KBO is calculated:
NEGATIVE INPUT CAPACITOR GENERATION
The ISL6731A and ISL6731B generate an equivalent negative
capacitance at the input to cancel the input filter capacitance.
Thus, more input capacitors can be used without reducing the
power factor.
The input equivalent negative capacitance is a function of the
current sensing gain, BO resistor divider gain and the
compensation components.
This equivalent negative capacitor cancels the input filter
capacitor required for EMI filtering. Therefore, the displacement
power factor significantly improves.
For example, CF1 = 0.68µF, CF2 = CF3 = 0.47µF, using the low
cost EMI filter shown in Figure 13. When VLINE = 230VAC,
fLINE = 50Hz, PO= 300W.
Assuming 95% efficiency under the above test condition, the
resistive component of the line current, which is in phase to voltage:
The reactive current through the input capacitors:
Thus, the displacement power factor is:
The reactive current generated by the equivalent negative
capacitor is:
With the equivalent negative capacitor, the total reactive current
reduces to:
The displacement power factor increases to:
VOLTAGE LOOP COMPENSATION
The average boost diode forward current can be approximated by:
Assuming the input current traces the input voltage perfectly. The
input power is in proportion to (VCOMP - 1V).
Where COMP is the VCOMP - 1V. 1V is the offset voltage.
RIS is the internal current scaling resistor. RIS = 14.2kΩ.
Thus, the transfer function from VCOMP to VOUT is:
As shown in Figure 18, the voltage loop gain is:
KBO
0.5V
80V 2V–
------------------------ 0.00641== (EQ. 60)
RIN1
0.00641
1 0.00641–
-------------------------------0.94M6.065k== (EQ. 61)
KBO
RIN1
RIN1 RIN2
+
---------------------------------0.00609== (EQ. 62)
CNEG KBO 0.8
Vm
VOUT
----------------
–



RSEN
RCSAiDC
--------------------------Cic Cip
+=(EQ. 63)
CNEG 0.00609 0.8 1.5
390
----------
–


3k
0.073 1.9
--------------------------- 6.8nF 1nF+=0.17F=
(EQ. 64)
Ia
Po
VLINE 0.95
---------------------------------
=1.373A=(EQ. 65)
IcVLINE 2fLINE
CF1 CF2 CF3
++=0.14A=(EQ. 66)
PFDIS
Ia
Ia

2Ic

2
+
-----------------------------------
=0.9948=(EQ. 67)
Icneg VLINE 2fLINE
CNEG
=0.015A=(EQ. 68)
IcIcneg
–0.126A=(EQ. 69)
PFDIS
Ia
Ia

2IcIcneg
–
2
+
--------------------------------------------------------
=0.9958=(EQ. 70)
IDave
Pin
VOUT
----------------
=(EQ. 71)
IDave
RSEN
RCS 0.5 RIS
--------------------------------------- 1
VOUT
----------------
0.25
22
2KBO
------------------------------------------------




COMP
=
(EQ. 72)
IDave
0.749A
V
----COMP
=(EQ. 73)
FB
COMP
Gmv
IFB
2.5V
RFB1
RFB2
VOUT
FIGURE 18. OUTPUT VOLTAGE SENSING AND COMPENSATION
Rvc
Cvc
Cvp
GPS s VOUT s
COMP
------------------------
=1
COs
----------------IDave
COMP
--------------------
=(EQ. 74)
GPS s IDave
COs
------------------- 1
COMP
--------------------



=0.749
COs
----------------
=(EQ. 75)
GVLOOP s GPS s GDIV Gmv ZCOMP
s=(EQ. 76)
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 18 of 20
February 13, 2015
The output feedback resistor divider gain, GDIV is:
The compensation gain uses external impedance networks as
shown in Figure 18, ZCOMP(s) is given by:
The targeted crossover frequency, FCV is 7.5Hz. The high
frequency pole, FPV, is required in order to reject the 2 time line
frequency component. FPV = 20Hz. The targeted phase margin
is 50°.
The zero, FZv is calculated:
Then the total capacitance used for compensation is calculated:
Thus, the total compensation capacitance is:
Choose components from the standard values. We have
CVP = 150nF, CVC = 1µF, RVC = 62kΩ. The actual bode plot is
shown in Figure 20.
GDIV
VREF
VOUT
----------------
=(EQ. 77)
ZCOMP s 1
Cvc Cvp
+s
---------------------------------------Rvc Cvc s1+
Rvc Cvc
Cvp
Cvc Cvp
+
------------------------------------------s1+
-------------------------------------------------------------
=(EQ. 78)
FIGURE 19. ASYMPTOTIC BODE PLOT OF VOLTAGE LOOP GAIN
1100
-60
-40
-20
0
20
40
60
FREQUENCY (Hz)
GAIN (dB)
FPV
FZV
1k
GmV*ZCOMP (s)
FCV Gps (s)
GVLOOP (s)
10
GDIV
FZv
FCV
mFCV FPV
atan+tan
-------------------------------------------------------------------------------
=(EQ. 79)
FZv
7.5Hz
50deg 7.5Hz20Hzatan+tan
----------------------------------------------------------------------------------------------------- 2.648Hz==
(EQ. 80)
Cvc Cvp
+
GPS i2FCV
GDIV Gmv
2FCV

-------------------------------------------------------------------------------------------FCV FZV

21+
FCV FPV

21+
--------------------------------------------=
(EQ. 81)
Cvc Cvp
+1127nF=(EQ. 82)
Cvp 1127nF
FZV
FPV
-----------
149nF== (EQ. 83)
Cvc 1127nF 149.1nF–977nF== (EQ. 84)
Rvc
1
2FZV CVC

-------------------------------------------61.5k== (EQ. 85)
FIGURE 20. BODE PLOT OF THE ACTUAL VOLTAGE LOOP GAIN
GAIN (dB)
FREQUENCY (Hz)
PHASE (°)
-20
0
20
40 FCV 120Hz
110 100
0
30
60
90 FCV
1k
120Hz
0
45
60
FN8582 Rev 1.00 Page 19 of 20
February 13, 2015
ISL6731A, ISL6731B
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
February 13, 2015 FN8582.1 Recommended operating conditions on page 7: changed VCC to GND value from “15V to +20V ‘to “12V to
+20V’.
Updated Equations 38 and 39 on page 15.
March 25, 2014 FN8582.0 Initial Release
ISL6731A, ISL6731B
FN8582 Rev 1.00 Page 20 of 20
February 13, 2015
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
A
D
4
0.25 A-BMC
C
0.10 C
5B
D
3
0.10 A-BC
4
0.20 C 2X
2X
0.10 DC 2X
H
0.10 C
6
36
ID MARK
PIN NO.1 (0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
1.27
0.31-0.51
4° ± 4°
DETAIL"A" 0.22±0.03
0.10-0.25
1.25 MIN
1.75 MAX
(1.27) (0.6)
6.0
8.65
3.9
7
14 8
Dimensioning and tolerancing conform to AMSEY14.5m-1994.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Datums A and B to be determined at Datum H.
4.
5.
3.
2.
Dimensions are in millimeters.
NOTES:
1.
The pin #1 indentifier may be either a mold or mark feature.
6. Does not include dambar protrusion. Allowable dambar protrusion
7. Reference to JEDEC MS-012-AB.
shall be 0.10mm total in excess of lead width at maximum condition.
DETAIL "A"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW