DATA SH EET
Product specification
Supersedes data of 1999 Sep 21 2002 Oct 23
INTEGRATED CIRCUITS
TDA8784
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
2002 Oct 23 2
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
FEATURES
•Correlated Double Sampling (CDS), AGC, 10-bit ADC
and reference regulator included, adjustable bandwidth
(CDS and AGC)
•Fully programmable via a 3-wire serial interface
•Sampling frequency up to 18 MHz
•AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps)
•CDS programmable bandwidth from 4 to 120 MHz
•AGC programmable bandwidth from 4 to 54 MHz
•Standby mode available for each block for power saving
applications 20 mW (typ)
•6 dB fixed gain analog output for analog iris control
•8-bit and 10-bit DAC included for analog settings
•Low power consumption of only 483 mW (typ)
•5 V operation and 2.5 to 5.25 V operation for the digital
outputs
•TTL compatible inputs, TTL and CMOS compatible
outputs.
APPLICATIONS
•CCD camera systems.
GENERAL DESCRIPTION
The TDA8784 is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, AGC and a low-power 10-bit
Analog-to-Digital Converter (ADC) together with its
reference voltage regulator.
The AGC and CDS have a bandwidth circuit controlled by
on-chip DACs via a serial interface.
A 10-bit DAC controls the ADC input clamp level.
An additional 8-bit DAC is provided for additional system
controls; its output voltage range is 1.4 V (p-p) which is
available at pin OFDOUT.
ORDERING INFORMATION
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA8784HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 ×7×1.4 mm SOT313-2
2002 Oct 23 3
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCCA analog supply voltage 4.75 5 5.25 V
VCCD digital supply voltage 4.75 5 5.25 V
VCCO digital outputs supply voltage 2.5 3 5.25 V
ICCA analog supply current −78 95 mA
ICCD digital supply current −18 20 mA
ICCO digital outputs supply current fCLK = 18 MHz;
CL= 20 pF; ramp input −1−mA
ADCres ADC resolution −10 −bits
Vi(CDS)(p-p) CDS input voltage (peak-to-peak value) −400 1200 mV
GCDS CDS output amplifier gain −6−dB
fCLK(max) maximum clock frequency fcut(CDS) = 120 MHz;
fcut(AGC) = 54 MHz 18 −−MHz
AGCdyn AGC dynamic range −30 −dB
Ntot(rms) total output noise from CDS input to
ADC output (RMS value) gain = 4.5 dB;
fcut(CDS) = 120 MHz;
fcut(AGC) = 40 MHz
−0.125 −LSB
Ein(rms) equivalent input noise (RMS value) gain = 34.5 dB −125 −µV
P
tot total power consumption −483 −mW
2002 Oct 23 4
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
BLOCK DIAGRAM
handbook, full pagewidth
MGM505
TRACK-
AND-HOLD TRACK-
AND-HOLD
TRACK-
AND-HOLD
CLAMP
ref1
CLAMP
8-BIT DAC
10-BIT DAC
9-BIT DAC
6 dB
AGC
1
1
CLOCK
GENERATOR
10-BIT ADC
REGULATOR SERIAL
INTERFACE
4-BIT DAC
CUT-OFF
OUTPUTS
BUFFER
5
4
2
7
6
9
10
14
11
12
13 15 16 17 18 20
21
22
2319 24
36
3
25
26
27
28
29
30
31
32
33
34
35
3738394041424344
454846
47
IND INP AGND3 SHD SHP CLPDM CLK DGND2 VCCO
VCCD2
VCCA3 OE
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DGND1
OFDOUT
OGND
VCCD1
STDBY SENAGND6 SCLK
SDATA
DEC1
VRT
VRB
VCCA2
DACOUT
Vref
CLPADC
AGND2
ADCIN
AGND5
VCCA1
AGCOUT
AGND4
AGND1
8
CPCDS
AMPOUT
TDA8784
4-BIT DAC
CUT-OFF
1
CLPOB
Fig.1 Block diagram.
2002 Oct 23 5
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
PINNING
SYMBOL PIN DESCRIPTION
CLPOB 1 clamp pulse input at optical black
AGND4 2 analog ground 4
OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface)
AMPOUT 4 CDS amplifier output (fixed gain = 6 dB)
AGND1 5 analog ground 1
VCCA1 6 analog supply voltage 1
AGCOUT 7 AGC amplifier signal output
CPCDS 8 clamp storage capacitor pin
AGND5 9 analog ground 5
ADCIN 10 ADC analog signal input from AGCOUT via a short circuit
CLPADC 11 clamp control input for ADC analog input signal clamp (used with a capacitor from Vref to ground)
Vref 12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or connected to
ground via a capacitor)
DACOUT 13 DAC output for ADC clamp level
AGND2 14 analog ground 2
VCCA2 15 analog supply voltage 2
VRB 16 ADC reference voltage (BOTTOM) code 0
VRT 17 ADC reference voltage (TOP) code 1023
DEC1 18 decoupling 1 (decoupled to ground via a capacitor)
AGND6 19 analog ground 6
SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off;
additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby mode
per block and edge pulse control); see Fig.3, Fig.4 and Table 1
SCLK 21 serial clock input for the control DACs and their serial interface; see Fig.3, Fig.4 and Table 1
SEN 22 enable input for the serial interface shift register (active when SEN = logic 0); see Fig.3, Fig.4 and
Table 1
STDBY 23 standby control (active HIGH); all the output bits are logic 0 when standby is enabled
VCCD1 24 digital supply voltage 1
DGND1 25 digital ground 1
D0 26 ADC digital output 0 (LSB)
D1 27 ADC digital output 1
D2 28 ADC digital output 2
D3 29 ADC digital output 3
D4 30 ADC digital output 4
D5 31 ADC digital output 5
D6 32 ADC digital output 6
D7 33 ADC digital output 7
D8 34 ADC digital output 8
D9 35 ADC digital output 9 (MSB)
OGND 36 digital output ground
2002 Oct 23 6
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
VCCO 37 digital output supply voltage
OE 38 output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance)
VCCD2 39 digital supply voltage 2
DGND2 40 digital ground 2
CLK 41 ADC clock input
CLPDM 42 clamp pulse input at dummy pixel
SHP 43 pre-set sample-and-hold pulse input
SHD 44 data sample-and-hold pulse input
VCCA3 45 analog supply voltage 3
INP 46 pre-set input signal from CCD
IND 47 data input signal from CCD
AGND3 48 analog ground 3
SYMBOL PIN DESCRIPTION
Fig.2 Pin configuration.
1
2
3
4
5
6
7
8
9
10
11
36
35
34
33
32
31
30
29
28
27
26
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
12
24 37
25
TDA8784HL
MGM506
OGND
D9
D8
D7
D5
D4
D3
D2
D1
D0
DGND1
CLPOB
AGND4
OFDOUT
AMPOUT
AGND1
VCCA1
CPCDS
AGND5
CLPADC
Vref
D6
IND
INP
VCCA3
SHD
SHP
CLPDM
DGND2
VCCD2
OE
VCCO
AGND3
CLK
AGCOUT
ADCIN
AGND2
VCCA2
VRB
VRT
DEC1
AGND6
SDATA
SEN
STDBY
VCCD1
DACOUT
SCLK
2002 Oct 23 7
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply
voltage difference ∆VCC remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCCA analog supply voltage note 1 −0.3 +7.0 V
VCCD digital supply voltage note 1 −0.3 +7.0 V
VCCO output stages supply voltage note 1 −0.3 +7.0 V
∆VCC supply voltage difference
between VCCA and VCCD −1.0 +1.0 V
between VCCA and VCCO −1.0 +4.0 V
between VCCD and VCCO −1.0 +4.0 V
Viinput voltage referenced to AGND −0.3 +7.0 V
VCLK(p-p) AC input voltage for switching
(peak-to-peak value) referenced to DGND −VCCD V
Iooutput current −10 mA
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −20 +75 °C
Tjjunction temperature −150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air 76 K/W
2002 Oct 23 8
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
CHARACTERISTICS
VCCA =V
CCD =5V; V
CCO =3V; f
CLK = 18 MHz; Tamb =25°C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VCCA analog supply voltage 4.75 5 5.25 V
VCCD digital supply voltage 4.75 5 5.25 V
VCCO digital outputs supply voltage 2.5 3 5.25 V
ICCA analog supply current −78 95 mA
ICCD digital supply current −18 20 mA
ICCO digital outputs supply current CL= 20 pF on all data outputs;
ramp input −1−mA
Digital inputs
CLOCK INPUT: CLK (REFERENCED TO DGND)
VIL LOW-level input voltage 0 −0.8 V
VIH HIGH-level input voltage 2.0 −VCCD V
IIL LOW-level input current VCLK = 0.8 V −1−+1 µA
IIH HIGH-level input current VCLK = 2.0 V −−20 µA
Ziinput impedance fCLK = 18 MHz −46 −kΩ
Ciinput capacitance fCLK = 18 MHz −1−pF
INPUTS: SHP AND SHD
VIL LOW-level input voltage 0 −0.8 V
VIH HIGH-level input voltage 2.0 −VCCD V
IIL LOW-level input current VIL = 0.8 V −−6−µA
I
IH HIGH-level input current VIH = 2.0 V −0−µA
INPUTS: SEN, SCLK, SDATA, OE, STDBY, CLPDM, CLPOB AND CLPADC
VIL LOW-level input voltage 0 −0.8 V
VIH HIGH-level input voltage 2.0 −VCCD V
Iiinput current −2−+2 µA
Correlated Double Sampling (CDS); note 1
Vi(CDS)(p-p) CDS input amplitude pin 47
(peak-to-peak value) −400 1200 mV
ICPCDS, IINP,
IIND
input current pins 8, 46 and 47 −2−+2 µA
tCDS(min) CDS control pulses minimum
active time fi(CDS1,2) =f
CLK(pix);
Vi(CDS) = 1200 mV (p-p)
black-to-white transition in
1 pixel (±1 LSB typ.);
fcut(CDS) = 40 MHz;
fcut(AGC) = 40 MHz
12 −−ns
thd1 hold time INP compared to
control pulse SHP see Fig.5 −1−ns
2002 Oct 23 9
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
thd2 hold time of IND compared to
control pulse SHD see Fig.5 −1−ns
tset(CDS) CDS settling time see Fig.12; control DAC 4 bits
input code; AGC gain=0dB;
f
cut(AGC) = 54 MHz;
Vi(CDS) = 1200 mV (p-p)
black-to-white transition in
1 pixel (1 LSB typ.)
0000 −12 −ns
0001 −25 −ns
0010 −45 −ns
0011 −55 −ns
0100 −105 −ns
0111 −140 −ns
1000 −270 −ns
1011 −300 −ns
1111 −365 −ns
Amplifier outputs
GAMPOUT output amplifier gain −6−dB
ZAMPOUT output amplifier impedance −300 −Ω
V
AMPOUT(p-p) output amplifier dynamic
voltage (peak-to-peak value) −2.4 −V
VAMPOUT(bl) output amplifier black level
voltage −1.5 −V
VAGCOUT(p-p) AGC output amplifier dynamic
voltage level (peak-to-peak
value)
−2000 −mV
VAGCOUT(bl) AGC output amplifier
black level voltage Vref connected to DACOUT −Vref −V
ZAGCOUT AGC output amplifier output
impedance at 10 kHz −5−Ω
I
AGCOUT AGC output static drive current static −−1mA
G
AGC(min) minimum gain of AGC circuit AGC DAC input code = 00
(9-bit control); see Fig.7 −4.5 −dB
GAGC(max) maximum gain of AGC circuit AGC DAC input code ≥319
(9-bit control); see Fig.7 −34.5 −dB
fcut(AGC) cut-off frequency AGC 4-bit control DAC
input code = 00 −54 −MHz
input code = 01 −40 −MHz
input code = 15 −4−MHz
other codes see Fig.13
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 Oct 23 10
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
Clamps
gm(ADC) ADC clamp transconductance at clamp level −7−mS
gm(CDS) CDS clamp transconductance at clamp level −1.5 −mS
Analog-to-Digital Converter (ADC)
fCLK(max) maximum clock frequency 18 −−MHz
tCPH clock pulse width HIGH 15 −−ns
tCPL clock pulse width LOW 15 −−ns
SRCLK clock input slew rate (rising
and falling edge) 10% to 90% 0.5 −−V/ns
Vi(ADC)(p-p) ADC input voltage level
(peak-to-peak value) −2−V
VRB ADC reference voltage output
code 0 −1.5 −V
VRT ADC reference voltage output
code 1023 −3.5 −V
IADCIN input current pin 10 −2−+120 µA
INL integral non-linearity ramp input −±0.6 ±1.5 LSB
DNL differential non-linearity ramp input −±0.2 ±0.75 LSB
td(s) sampling delay time −−5ns
Total chain characteristics (CDS + AGC + ADC)
tddelay between SHD and CLK see Fig.5; 50% at rising
edges CLK and SHP:
transition full scale
code 0 to 1023;
fcut(CDS) = 40 MHz;
fcut(AGC) = 40 MHz;
Vi(CDS) = 1200 mV
−40 −ns
Ntot(rms) total output noise (RMS value) fcut(CDS) = 120 MHz;
fcut(AGC) = 40 MHz; note 2
GAGC = 4.5 dB −0.125 −LSB
GAGC = 34.5 dB −1.6 −LSB
Voffset(fl-d) maximum offset between CCD
floating level and CCD dark
pixel level
−200 −+200 mV
Vn(i)(eq)(rms) equivalent input noise voltage
(RMS value) AGC gain = 34.5 dB −125 −µV
AGC gain = 4.5 dB −150 −µV
Digital-to-analog converter (OFDOUT)
VOFDOUT(p-p) additional 8-bit control DAC
(OFD) output voltage
(peak-to-peak value)
−1.4 −V
VOFDOUT(0) DC output voltage for code 0 −2.3 −V
VOFDOUT(255) DC output voltage for
code 255 −3.7 −V
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 Oct 23 11
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
Notes
1. More information about CDS related signals is available in the following figures: The clamp current for pin CPCDS is
given in Fig. 9, clamp current for pins IND and INP in Fig 10 and for clamp current for pin Vref in Fig 11. The CDS
output amplitude is shown in Fig. 14
2. NoisemeasurementatADCoutputs: the couplingcapacitor at theinput is connectedto ground, sothat only thenoise
contributionofthe front-endis evaluated.Thefront-end operatesat 18 Mpixwitha lineof 1024 pixels.Thefirst 40 are
used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels.
The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise
is taken into account as no signal is input. Figure 15 gives noise figure graphs with signal input.
ZOFDOUT additional 8-bit control DAC
(OFD) output impedance −2000 −Ω
I
OFDOUT OFD output current drive static −−50 µA
ADC clamp control DAC (see Fig.8)
VDACOUT(p-p) ADC clamp 10-bit control DAC
output voltage (peak-to-peak
value)
−1−V
VDACOUT DC output voltage code 0 −1.5 −V
code 1023 −2.5 −V
ZDACOUT ADC clamp control DAC output
impedance −−250 Ω
IDACOUT DAC output current drive static −−50 µA
OFELOOP maximum offset error of
DAC + ADC clamp loop code 0 −±5−LSB
code 1023 −±5−LSB
Digital outputs (fCLK = 18 MHz; CL=20pF)
V
OH HIGH-level output voltage IOH =−1mA V
CCO −0.5 −VCCO V
VOL LOW-level output voltage IOL =1mA 0 −0.5 V
IOZ output current in 3-state mode 0 V < Vo<V
CCO −20 −+20 µA
to(h) output hold time see Fig.5 8 −−ns
to(d) output delay time CL= 20 pF; VCCO =5V −17 23 ns
CL= 10 pF; VCCO =5V −15 21 ns
CL= 20 pF; VCCO =3V −20 29 ns
CL= 10 pF; VCCO =3V −17 25 ns
CL= 20 pF; VCCO = 2.5 V −22 33 ns
CL= 10 pF; VCCO = 2.5 V −18 28 ns
Serial interface
fSCLK(max) maximum frequency of serial
interface 5−−MHz
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 Oct 23 12
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
Fig.3 Serial interface block diagram.
handbook, full pagewidth
OFD
LATCHES AGC GAIN
LATCHES FREQUENCY
LATCHES
PARTIAL
STANDBY
AND EDGE
CLAMP
REFERENCE
LATCHES
LATCH
SELECTION
D0
LSB MSB
SDATA
SCLK
SEN
8-bit DAC 10-bit DAC
MGM515
AGC control frequency
control
CDS and AGC
standby
control
or edge clocks
D1 D2 D3 D4 D5
10
D6
SHIFT REGISTER
D7 D8 D9 A0 A1 A2
8
(D7 to D0) 9
(D8 to D0) 8
(D7 to D0) 7
(D6 to D0) 10
(D9 to D0)
Fig.4 Loading sequence of control DACs input data via the serial interface.
handbook, full pagewidth
MGE373
A2SDATA
SCLK
SEN
A1 A0 D9 D7 D6 D5 D4 D3
MSB LSB
D2 D1 D0
thd3
tsu3
tsu1
thd4
tsu2
D8
tsu1 =t
su2 =t
su3 = 4 ns (min.); thd3 =t
hd4 = 4 ns (min.).
2002 Oct 23 13
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
Table 1 Serial interface programming
Note
1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level Vref.
Vref is connected to ground via a capacitance.
Table 2 Standby selection
ADDRESS BITS DATA BITS D9 to D0
A2 A1 A0
0 0 0 OFD output control (D7 to D0).
0 0 1 Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for
CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0.
0 1 0 AGC gain control (D8 to D0).
0 1 1 Partial standby controls for power consumption optimization. Only the 4 LSBs
(D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and
clock ADC:
D0 = 1: CDS + AGC in standby; ICCA +I
CCD =35mA
D1 = 1: OFD DAC in standby; ICCA +I
CCD =95mA
D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby;
ICCA +I
CCD = 95.5 mA
D3 = 1: SHP and SHD activated with falling edge (for positive pulse)
D4 = 1: CLPDM, CLPOB and CLPADC activated on HIGH level; note 1
D5 = 0: CLKADC activated with falling edge
D6 must be set to logic 0.
1 0 0 Clamp reference DAC (D9 to D0).
STDBY DATA BITS D9 to D0 ICCA +I
CCD (TYP.)
1LOW4mA
0 active 96 mA
2002 Oct 23 14
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
handbook, full pagewidth
MGR395
N
IND
SHP 1.4 V
SHD
CLK
ADCIN
DATA
N + 3N + 2N + 1
N − 1
N
N
tCDS
tCPH
td(s)
td
to(d)
to(h)
tn(IN; SHP)
tn(IN; SHD)
90%
10%
1.4 V
1.4 V
N − 3N − 2
Fig.5 Pixel frequency timing diagram.
2002 Oct 23 15
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
Fig.6 Line frequency timing diagram.
(1) When dummy pixels are not available.
handbook, full pagewidth
MGR396
CLPADC
(active HIGH)
CLPDM
(active HIGH)
CLPOB
(active HIGH)
OPTICAL BLACK HORIZONTAL FLYBLACK DUMMY VIDEOVIDEOAGCOUT
CLPDM
CLPADC
WINDOW
CLPOB
WINDOW
(1)
(1)
1 pixel
CLPDM
CLPADC
WINDOW
1 pixel
2002 Oct 23 16
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
handbook, halfpage
MGM507
GAGC
(dB)
34.5
4.50 319 511
AGC control DAC input code
Fig.7 AGC gain as a function of DAC input code.
handbook, full pagewidth
0
ADC CLAMP DAC
voltage
output
(V)
2.5
1.5 1023
ADC CLAMP control DAC input code
MGM508
0
OFD DAC
voltage
output
(V)
3.7
2.3 255
OFD control DAC input code
Fig.8 DAC voltage output as a function of DAC input code.
2002 Oct 23 17
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
Fig.9 Typical clamp current for pin CPCDS.
handbook, halfpage
MGR397
+100
0
−100
I
(µA)
V (V)
200 mV
2.00
Fig.10 Typical clamp current for pins IND and INP.
handbook, halfpage
MGR398
+300
0
−300
I
(µA)
V (V)
400 mV
2.85
handbook, halfpage
MGR399
+200
0
−200
I
(µA)
V (V)
400 mV
Vref
Fig.11 Typical clamp current for pin Vref.
2002 Oct 23 18
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
Fig.12 CDS settling time and bandwidth.
handbook, full pagewidth
160
120
40
0
80
MGR400
F05A16B27C38D49E
4-bit control DAC input code
fcut
(MHz)
400
300
100
0
200
tset
(ns)
(2) (3)
(4)
(1)
(1) fcut.
(2) tset (10 bits accuracy).
(3) tset (9 bits accuracy).
(4) tset (8 bits accuracy)).
2002 Oct 23 19
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
handbook, full pagewidth
F
60
40
20
005A16B27C38D49E
MGR401
4-bit control DAC input code
fcut
(MHz)
Fig.13 AGC bandwidth.
Fig.14 CDS output.
handbook, full pagewidth
1.6
1.6
1.2
0.4
00 0.4 1.2
0.8
0.80.2 0.6 1.41.0
MGR402
Vi(CDS)(p-p) (V)
Vo(CDS)(p-p)
(V)
tset(CDS) =12ns.
Fig.14 CDS output.
tset(CDS) =12ns.
2002 Oct 23 20
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
handbook, full pagewidth
13F
code
3
2
1
000 40 80 C0 100 (34.5)(4.5) (10.5) (16.5) (22.5) (28.5)
MGR403
GAGC (dB)
Ntot(rms)
(LSB)
(2)
(3)
(4)
(5)
(1)
(1) fpix = 18 MHz; control DAC = 10H; fcut(CDS) = 120 MHz; fcut(AGC) = 40 MHz.
(2) fpix = 10 MHz; control DAC = 31H; fcut(CDS) = 80 MHz; fcut(AGC) = 30 MHz.
(3) fpix = 5 MHz; control DAC = 43H; fcut(CDS) = 35 MHz; fcut(AGC) = 12 MHz.
(4) fpix = 1 MHz; control DAC = F8H; fcut(CDS) = 6 MHz; fcut(AGC) = 4 MHz.
(5) fpix = 375 kHz; control DAC = FFH; fcut(CDS) = 4 MHz; fcut(AGC) = 4 MHz.
Fig.15 Output noise (RMS value).
2002 Oct 23 21
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
APPLICATION INFORMATION
handbook, full pagewidth
MGM516
1
2
3
4
5
6
7
8
9
10
11
36
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
35
34
33
32
31
30
29
28
27
26
12 25
TDA8784
OGND
D9
D8
D7
D5
D4
D3
D2
D1
D0
DGND1
CLPOB
AGND4
OFDOUT
AMPOUT
AGND1
VCCA1
CPCDS
AGND5
CLPADC
Vref
D6
IND
INP
VCCA3
SHD
SHP
CLPDM
DGND2
VCCD2
OE
VCCO
AGND3
CLK
AGCOUT
ADCIN
AGND2
VCCA2
VRB
VRT
DEC1
AGND6
SDATA
SEN
STDBY
VCCD1
DACOUT
SCLK
from timing
generator
serial
interface
5.0 V 5.0 V
5.0 V
5.0 V
CCD 2.5 to 5.25 V
(3)
1 µF
1 µF
(3)
(3)
(2)
(1)
(3)
5.0 V
(3)
100
nF
1
nF
2.2
nF
1
nF
(3)
1 µF
Fig.16 Application diagram.
Depending on the application, the following connections must be made:
(1) The clamp level of the signal input at ADCIN can be tuned from code 00 to code 511 in 0.5 LSB steps of ADC via the serial interface
(clamp ADC activated).
(2) Clamp ADC not activated, direct connection from DACOUT to Vref.
(3) All supply pins must be decoupled with 100 nF capacitors as close as possible to the device.
2002 Oct 23 22
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
Power and grounding recommendations
Care must be taken to minimize noise when designing a
printed-circuit board for applications such as PC cameras,
surveillance cameras, camcorders and digital still
cameras.
For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of analog
components (such as classical operational amplifiers)
must be taken into account, particularly with respect to
power and ground connections.
The connections between CCD interface and CDS input
should be as short as possible and a ground ring
protection around these connections can be beneficial.
Decoupling capacitors are necessary on all supply pins as
shown in Fig.16.
Separate analog and digital supplies provide the best
performance. If it is not possible to do this on the board,
then decouple the analog supply pins effectively from the
digital supply pins. The decoupling capacitors must be
placed as close as possible to the IC package.
In a two-ground system, in order to minimize the noise
from package and die parasitics, the following
recommendations must be implemented:
•The ground pin associated with the digital outputs must
be connected to the digital ground plane and special
care should be taken to avoid feedthrough in the analog
ground plane. The analog and digital ground planes
mustbe connectedwith an inductor asclose as possible
to the IC package, in order to have the same DC voltage
on the ground planes.
•The digital output pins and their associated lines should
be shielded by the digital ground plane, which can be
used as return path for the digital signals.
2002 Oct 23 23
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
PACKAGE OUTLINE
UNIT A
max. A1A2A3bpcE
(1) eH
E
LL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 1.60 0.20
0.05 1.45
1.35 0.25 0.27
0.17 0.18
0.12 7.1
6.9 0.5 9.15
8.85 0.95
0.55 7
0
o
o
0.12 0.10.21.0
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT313-2 MS-026136E05 99-12-27
00-01-19
D(1) (1)(1)
7.1
6.9
HD
9.15
8.85
E
Z
0.95
0.55
D
bp
e
E
B
12
D
H
bp
E
H
vMB
D
ZD
A
ZE
e
vMA
1
48
37
36 25
24
13
θ
A1
A
Lp
detail X
L
(A )
3
A2
X
y
c
wM
wM
0 2.5 5 mm
scale
pin 1 index
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
2002 Oct 23 24
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
SOLDERING
Introduction to soldering surface mount packages
Thistextgives averybrief insighttoa complextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs, butitisnot suitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuitboard byscreen printing, stencillingor
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices (SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleads onfoursides,the footprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2002 Oct 23 25
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formore detailedinformation onthe BGApackages referto the
“(LF)BGAApplication Note
”(AN01026); ordera copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
2002 Oct 23 26
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor atany otherconditionsabove thosegiven inthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplications willbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2002 Oct 23 27
Philips Semiconductors Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras TDA8784
NOTES
© Koninklijke Philips Electronics N.V. 2002 SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a world wide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands 753504/03/pp28 Date of release: 2002 Oct 23 Document order number: 9397 750 10177
