April 2007

LatticeEC™ Standard Evaluation Board – Revision B

User’s Guide

Introduction

• SPI3 Flash device included for low cost, non-volatile configuration storage

• PCI edge connector (120-pin) for 32-bit PCI interface

• Large Prototyping Area with access to over 290 I/O pins

• Optional SMA/SMB connectors (up to six) for high-speed clock and data interfacing

Figure 1. LatticeEC Standard Evaluation Board

Electrical, Mechanical and Environmental Specifications

The nominal board dimensions are 7 inches by 3.9 inches. The environmental specifications are as follows:

• Operating temperature: 0ºC to 55ºC

• Storage temperature: -40ºC to 75ºC

Table 1. Embedded Functions

The 3.3V oscillator socket accepts both full-size and half-size oscillators and can route to different clock inputs,

depending on its position within the socket. The 16-pin socket will allow connection to PLL clock pin V1 when the

bottom of the oscillator is aligned to socket pins 8 and 9. When the top of the oscillator is aligned to socket pins 1

and 16, the clock is provided to primary clock pin AB10.

LatticeEC Device

This board features a LatticeEC FPGA with a 1.2V DC core. It can accommodate all pin-compatible LatticeEC

devices in plastic 484-ball fpBGA (1mm pitch) packages. A complete description of this device can be found in the

LatticeECP/EC Family Data Sheet on the Lattice web site at www.latticesemi.com.

Programming Headers

Table 2. JTAG Programming Headers

Table 3. Flash Programming Headers

Description Source LatticeEC Pin Notes

(3.3V) 1 6

(3.3V) 1 6

SFLASH_S_N 4 10

GND 7, 9 2, 4

Power Setup

power rail. When plugged into the PCI slot, the on-board 3.3V regulator (U4) will be disabled automatically, allowing

3.3V to be supplied directly from the PCI host system.

Power can also be supplied directly for each individual supply rail using banana jack connectors. To enable this

cations in Table 5. No special power sequencing is required for the evaluation board.

3.3V power can then be supplied directly to banana jack J22, providing power to the remaining regulators.

Table 5. Individual Control of Supplies

Current Capacity Up to 4A

1.2V J23 J27 1.2V +/- 5%

Table 7. sysIO Bank Considerations

The following tables detail the various standards supported by the LatticeEC FPGA Input/Output (sysIO) struc-

tures. More information can be found in Lattice technical note number TN1056,

LatticeECP/EC sysIO Usage

, available on the Lattice web site at www.latticesemi.com.

Table 8. Mixed Voltage Support

For example, if V

is 3.3V then signals from devices powered by 1.2V, 2.5V or 3.3V can be input and the thresh-

Any

Any

Any

3.3V if SPI configuration mode selected, otherwise any

Any

Input sysIO Standards Output sysIO Standards

Table 9. sysIO Standards Supported per Bank

PCI Support PCI33 with clamp PCI33 no clamp PCI33 with clamp PCI no clamp

LVDS Output Buffers LVDS (3.5mA) Buffers LVDS (3.5mA) Buffers

Table 10. PCI Connections – Solder Side (Continued)

Table 12. LatticeEC Pins Accessible at Test Points

(1) C13 (1) E6 (0) F21 (2) J20 (2) N20 (3) U15 (4) Y16 (4)

(7) N21 (3) U16 (4) Y17 (4)

(7) K2

(7) N22 (3) U17 (4) Y18 (4)

Table 11. PCI Connections - Component Side (Continued)

Switches

Switch 1 (SW1) on the left side of the board is an eight-switch block that is part of the prototyping area. The pull-up

resistors associated with SW1 are wired to 3.3V but any I/O voltage up to 3.3V may be used. A switch in the down

position produces a low (0), while the up position produces a high (1).

Table 13. SW1 Connections

SW2 is a momentary switch that the user can define for any purpose, such as a global reset. SW2 is wired to I/O

ball A19 (bank 1) and applies a low logic level when depressed.

able the adjustable voltage, J29 for 3.3V, and J30 for 1.2V. Installing the jumper disables the regulator.

jumpers must be installed horizontally. See Table 5 for more information.

The jumpers at J20 determine which type of device the FPGA expects to receive programming information from

and whether the FPGA will be master or slave during the transfer. Table 14 lists the possible configuration modes.

Installing the jumper produces a low (0), removing the jumper produces a high (1).

Table 12. LatticeEC Pins Accessible at Test Points (Continued)

Figure 9. 32-Bit PCI Interface

TDI 4

+3.3V_27 27

+3.3V_39 39

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Figure 10. Prototyping Support

Figure 11. Prototyping Support

PCLKC2_0 / PR22B J22

Figure 12. JTAG and FPGA Programming

Hardware Setup

Figure 13. Prototyping Support

(33.33 MHz OSC Installed)

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