User's Guide SCAU039 - October 2009 Low Additive Phase Noise Clock Buffer Evaluation Board Figure 1. CDCLVP2104EVM Evaluation Board Features: * Easy-to-use evaluation board to fan out low phase noise clocks * Easy device setup * Fast configuration * Control pins configurable through jumpers * Board powered at +2.5-V/+3.3-V * Single-ended or differential input clocks * CDCLVP2104 supports eight LVPECL outputs; CDCLVP2104EVM supports four LVPECL outputs 1 2 3 4 5 6 Contents General Description ......................................................................................................... Signal Path and Control Circuitry ......................................................................................... Getting Started .............................................................................................................. Input Clock Selection ....................................................................................................... Output Clock ................................................................................................................. Schematics and Layout .................................................................................................... 2 2 2 2 3 3 List of Figures 1 CDCLVP2104EVM Evaluation Board .................................................................................... 1 2 CDCLVP2104EVM--Schematic 3 CDCLVP2104EVM--Schematic .......................................................................................... .......................................................................................... 3 4 All trademarks are the property of their respective owners. SCAU039 - October 2009 Submit Documentation Feedback Low Additive Phase Noise Clock Buffer Evaluation Board Copyright (c) 2009, Texas Instruments Incorporated 1 General Description 1 www.ti.com General Description The CDCLVP2104 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs. Each input feeds a bank of four LVPECL outputs. The device also features on-chip bias generators that can provide the LVPECL common-mode voltage to the device inputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP2104. This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP2104 device functionalities. Throughout this document, the acronym EVM and the phrases evaluation module and evaluation board are synonymous with the CDCLVP2104EVM. See Figure 1 for an illustration of the CDCLVP2104EVM. For optimum performance, the board is equipped with 50- SMA connectors and well-controlled, 50- impedance microstrip transmission lines. 2 Signal Path and Control Circuitry The CDCLVP2104 supports single-ended inputs up to 200 MHz and differential inputs up to 2 GHz. The device provides up to eight LVPECL outputs operating at the input frequency. For more information about the CDCLVP2104, see the CDCLVP2104 product data sheet available for download from the TI web site (www.ti.com). 3 Getting Started The CDCLVP2104EVM has self-explanatory labeling and uses similar naming conventions as the CDCLVP2104 product data sheet. In this user's guide, all words in boldface and italic print reflect the actual labeling on the EVM. The CDCLVP2104EVM can be used with either single-ended or differential inputs. 3.1 Power-Supply Connections Connect the power-supply source to the banana plug labeled VDD (P4), and connect the ground of the power-supply source to GND (P5). There are decoupling capacitors and a ferrite bead to isolate the EVM power from the CDCLVP2104 device power pins. The CDCLVP2104EVM can use a supply voltage of 2.375 V to 3.6 V. 4 Input Clock Selection The CDCLVP2104EVM offers users the option of receiving either a differential or single-ended clock as the clock input. The default option is for the differential signal at both device inputs. The inputs can be applied through the SMAs (J103, J104 or J105, J106). These inputs are ac-coupled to the device inputs. The common-mode voltage for these inputs after the ac-coupling capacitors is provided by 50 (R152, R153 and R154, R155) to the device on-chip bias generator (VAC_REF) pins. 4.1 Configuring Single-Ended Input For a single-ended clock applied to IN0, remove capacitors C68 and C69 and replace them with 0- resistors of the same footprint. The single-ended signal should be applied to INP0 (J103) and the dc bias voltage should be applied to INN0 (J104). For a single-ended clock applied to IN1, remove capacitors C72 and C73 and replace them with 0- resistors of the same footprint. The single-ended signal should be applied to INP1 (J105) and the dc bias voltage should be applied to INN1 (J106). 2 Low Additive Phase Noise Clock Buffer Evaluation Board Copyright (c) 2009, Texas Instruments Incorporated SCAU039 - October 2009 Submit Documentation Feedback Output Clock www.ti.com 5 Output Clock The CDCLVP2104 generates up to eight LVPECL outputs. Four outputs are available on the CDCLVP2104EVM (outputs 0, 3, 4, and 7) through the following SMAs: * J13, J23 for OUT0 * J17, J27 for OUT3 * J33, J32 for OUT4 * J39, J38 for OUT7 The LVPECL outputs are terminated with 150 to ground and ac-coupled to the respective SMAs. 6 Schematics and Layout Figure 2 and Figure 3 show the printed circuit board (PCB) schematics. NOTE: Board layouts are not to scale. These figures are intended to show how the board is laid out; they are not intended to be used for manufacturing CDCLVP2104EVM PCBs. Figure 2. CDCLVP2104EVM--Schematic SCAU039 - October 2009 Submit Documentation Feedback Low Additive Phase Noise Clock Buffer Evaluation Board Copyright (c) 2009, Texas Instruments Incorporated 3 Schematics and Layout www.ti.com Figure 3. CDCLVP2104EVM--Schematic space 4 Low Additive Phase Noise Clock Buffer Evaluation Board Copyright (c) 2009, Texas Instruments Incorporated SCAU039 - October 2009 Submit Documentation Feedback Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives. Should this evaluation board/kit not meet the specifications indicated in the User's Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. 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TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. EVM Warnings and Restrictions It is important to operate this EVM within the input voltage range of -0.5 V to 4.0 V and the output voltage range of 0 V to 3.6 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than +120 C. The EVM is designed to operate properly with certain components above +85 C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. 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