0.079
2.00
0.047
1.20
0.063
1.60
0.165
4.20
0.276
7.00
0.118
3.00
0.276
7.00
0.354
9.00
Pin # 1 Identifier
1 2 3
456
0.088
2.24
0.047
1.20
0.067
1.70
0.110
2.80
TYP.
0.102
2.60
TYP.
0.055
1.40
0.055
1.40
0.122
3.10
OUTOUT
VDD
PROG
FSEL0FSEL1
GND
VC
OE
321
456
Recommended land Pattern
"This 3x7mm area should be "masked"
on the end-customer PCB and
preferably not connected to Ground.
Also, please do not route
electrical signals under
the oscillator package area".
PIN #
SYMBOL
DESCRIPTION
COMMENT
1
OE
Output Enable
Active High, leave floating if not used
2
Vc
Control Voltage
0 ~ Vdd can be applied to pull frequency
3
GND
Ground
Connect to Analog Ground
4
OUT
Primary Output
LVDS/LVPECL Primary output
5
OUT
Complimentary
Output
LVDS/LVPECL Complimentary output
6
VDD
Bias Voltage
Apply +3.30V ±0.3V
PROG, FSEL0 & FSEL1
Factory
Configuration Pins
DONOT Connect, this area needs to be masked on customer PCB
-
-
ASGTX
XXXXXX
SAAZVAT
WEIGHT:
A3
SHEET 1 OF 1
SCALE:8:1
DWG NO.
TITLE:
REVISION
DO NOT SCALE DRAWING
MATERIAL:
DATE
SIGNATURE
NAME
DEBUR AND
BREAK SHARP
EDGES
FINISH:
UNLESS OTHERWISE SPECIFIED:
DIMENSIONS ARE IN MM
SURFACE FINISH:
TOLERANCES:
LINEAR:
ANGULAR:
Q.A
MFG
APPV'D
CHK'D
DRAWN
30332 Esperanza, Rancho Santa margarita, California 92688
TOP PACKAGE MARKING IS
FOR ILLUSTRATION PURPOSES ONLY
