4 0.276 7.00 2 0.122 3.10 COMMENT 1 OE Output Enable Active High, leave floating if not used 2 Vc Control Voltage 0 ~ Vdd can be applied to pull frequency 3 GND Ground Connect to Analog Ground 4 OUT Primary Output LVDS/LVPECL Primary output 5 OUT Complimentary Output LVDS/LVPECL Complimentary output 6 VDD Bias Voltage Apply +3.30V 0.3V Factory PROG, FSEL0 & FSEL1 Configuration Pins DONOT Connect, this area needs to be masked on customer PCB Recommended land Pattern Pin # 1 Identifier 0.063 1.60 0.047 1.20 1 2 OE VC GND FSEL0 PROG VDD OUT 6 5 0.165 4.20 0.079 2.00 0.047 1.20 FSEL1 0.067 1.70 DESCRIPTION 3 0.102 2.60 TYP. 55 0 . 0 0 1.4 SYMBOL 3 "This 3x7mm area should be "masked" on the end-customer PCB and preferably not connected to Ground. Also, please do not route electrical signals under the oscillator package area". 0.055 1.40 0.088 2.24 1 PIN # OUT 0.118 3.00 6 0.354 9.00 5 0.276 7.00 UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN MM SURFACE FINISH: TOLERANCES: LINEAR: ANGULAR: NAME 4 0.110 TYP. 2.80 DRAWN SAAZVAT CHK'D XXXXXX DEBUR AND BREAK SHARP EDGES FINISH: SIGNATURE DO NOT SCALE DRAWING - DATE 30332 Esperanza, Rancho Santa margarita, California 92688 APPV'D TITLE: MFG Q.A REVISION MATERIAL: TOP PACKAGE MARKING IS FOR ILLUSTRATION PURPOSES ONLY WEIGHT: DWG NO. SCALE:8:1 - ASGTX SHEET 1 OF 1 A3