CY62128E MoBL®
1-Mbit (128 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05485 Rev. *J Revised July 4, 2011
1-Mbit (128 K × 8) Static RAM
Features
■Very high speed: 45 ns
■Temperature ranges
❐Industrial: –40 °C to +85 °C
❐Automotive-A: –40 °C to +85 °C
❐Automotive-E: –40 °C to +125 °C
■Voltage range: 4.5 V to 5.5 V
■Pin compatible with CY62128B
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 4 A (Industrial)
■Ultra low active power
❐Typical active current: 1.3 mA at f = 1 MHz
■Easy memory expansion with CE1, CE2, and OE features
■Automatic power down when deselected
■complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and
32-pin thin small outline package (TSOP) Type I packages
Functional Description
The CY62128E is a high performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99 percent when deselected (CE1 HIGH or CE2 LOW). The
eight input and output pins (I/O0 through I/O7) are placed in a
high impedance state when the device is deselected (CE1 HIGH
or CE2 LOW), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE1 LOW and CE2 HIGH and WE LOW)
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A16).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
A0
I/O0
I/O7
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
A1
A2
A3
A4
A5
A6
A7
A8
A9
A12
SENSE AMPS
POWER
DOWN
WE
OE
A13
A14
A15
A16
ROW DECODER
COLUMN DECODER
128K x 8
ARRAY
INPUT BUFFER
A10
A11
CE1
CE2
Logic Block Diagram
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
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CY62128E MoBL®
Document #: 38-05485 Rev. *J Page 2 of 18
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics .................................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Characteristics ................................................8
Switching Waveforms ......................................................9
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC Solutions ......................................................... 18
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Pin Configuration
Figure 1. 32-pin STSOP [1]
Figure 2. 32-pin TSOP I [1]
Figure 3. 32-pin SOIC [1]
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9
OE
STSOP
Top View
(not to scale)
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A59
10
32
1
2
3
4
5
6
7
8
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
26
25
26
27
8
9
10
11
14
12
13
16
15
21
22
19
20
25
17
18
23
24
A
11
A
10
4
A
3
A
2
A
1
A
0
/O
0
/O
1
O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
VSS
OE
CE1
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
1
2
3
4
5
6
7
31
32
29
30
27
28
26
32-Pin SOIC
Top View
C
16
A
15
14
A
13
12
A
A
9
A
8
A
7
A
6
A
5
A
VCC
CE
2
WE
A16
A14
WE
VCC
A13
A8
A9
STSOP
Top View
(not to scale)
30
28
29
31
A11
32
1
2
3
CE2
A15
NC
26
25
26
27
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
TSOP I
Top View
(not to scale)
6
3
4
5
7
A5
8
9
10
11
12
13
14
15
16
CE2
A15
NC
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
Top View
Top View
NC
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
VSS
VCC
CE
2
WE
OE
CE1
Note
1. NC pins are not connected on the die.
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CY62128E MoBL®
Document #: 38-05485 Rev. *J Page 4 of 18
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA)
Standby ISB2 (µA)
f = 1MHz f = fmax
Min Typ [2] Max Typ [2] Max Typ [2] Max Typ [2] Max
CY62128ELL Industrial /
Automotive-A
4.5 5.0 5.5 45 [3] 1.3 2 11 16 1 4
CY62128ELL Automotive-E 4.5 5.0 5.5 55 1.3 4 11 35 1 30
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
3. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (tAA, tACE) and 25 ns (tDOE) are guaranteed.
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CY62128E MoBL®
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Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage to ground
potential ........................... –0.5 V to 6.0 V (VCC(max) + 0.5 V)
DC voltage applied to outputs
in High Z State [4, 5] .......... –0.5 V to 6.0 V (VCC(max) + 0.5 V)
DC input voltage[4, 5] ........ –0.5 V to 6.0 V (VCC(max) + 0.5 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage ........................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up current ..................................................... > 200 mA
Operating Range
Device Range Ambient
Temperature VCC[6]
CY62128ELL Industrial /
Automotive-A
–40 °C to +85 °C 4.5 V to 5.5 V
Automotive-E –40 °C to +125 °C
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
45 ns (Industrial/
Automotive-A) 55 ns (Automotive-E) Unit
Min Typ [7] Max Min Typ [7] Max
VOH Output HIGH voltage IOH = –1 mA 2.4 – – 2.4 – – V
VOL Output LOW voltage IOL = 2.1 mA – – 0.4 – – 0.4 V
VIH Input HIGH voltage VCC = 4.5 V to 5.5 V 2.2 – VCC + 0.5 2.2 – VCC + 0.5 V
VIL Input LOW voltage VCC = 4.5 V to 5.5 V –0.5 – 0.8 –0.5 – 0.8 V
IIX Input leakage current GND < VI < VCC –1 – +1 –4 – +4 A
IOZ Output leakage current GND < VO < VCC, Output Disabled –1 – +1 –4 – +4 A
ICC VCC Operating supply
current
f = fmax = 1/tRC VCC = VCC(max)
IOUT = 0 mA
CMOS levels
–11 16 –11 35 mA
f = 1 MHz – 1.3 2 – 1.3 4
ISB2 [8] Automatic CE
power-down
Current—CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–1 4 –1 30 A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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Capacitance
Parameter [9] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter [9] Description Test Conditions 32-pin SOIC
Package
32-pin STSOP
Package
32-pin TSOP
Package Unit
JA Thermal resistance
(Junction to ambient)
Still Air, soldered on a 3 × 4.5
inch, two-layer printed circuit
board
48.67 32.56 33.01 C/W
JC Thermal resistance
(Junction to case)
25.86 3.59 3.42 C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.0 V
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Parameters Value Unit
R1 1800
R2 990
RTH 639
VTH 1.77 V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
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Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [10] Max Unit
VDR VCC for data retention 2 – – V
ICCDR [11] Data retention current VCC = VDR,
CE1 > VCC 0.2 V or
CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Industrial /
Automotive-A ––4
A
Automotive-E – – 30 A
tCDR [12] Chip deselect to data
retention time
0––ns
tR [13] Operation recovery time CY62128ELL-45 45 – – ns
CY62128ELL-55 55 – –
Data Retention Waveform
Figure 5. Data Retention Waveform [14]
V
CC(min)
V
CC(min)
t
CDR
V
DR
>2.0 V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
14. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
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CY62128E MoBL®
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Switching Characteristics
Over the Operating Range
Parameter [15] Description
45 ns (Industrial /
Automotive-A) 55 ns (Automotive-E) Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 45–55–ns
tAA Address to data valid – 45 – 55 ns
tOHA Data hold from address change 10 – 10 – ns
tACE CE1 LOW and CE2 HIGH to data valid – 45 – 55 ns
tDOE OE LOW to data valid – 22 – 25 ns
tLZOE OE LOW to Low Z[16] 5–5–ns
tHZOE OE HIGH to High Z[16, 17] –18–20 ns
tLZCE CE1 LOW and CE2 HIGH to Low Z[16] 10 – 10 –ns
tHZCE CE1 HIGH or CE2 LOW to High Z[16, 17] –18–20 ns
tPU CE1 LOW and CE2 HIGH to power-up 0 – 0–ns
tPD CE1 HIGH or CE2 LOW to power-down – 45 – 55 ns
Write Cycle[18]
tWC Write cycle time 45 – 55 – ns
tSCE CE1 LOW and CE2 HIGH to write end 35 – 40 –ns
tAW Address setup to write end 35 – 40 –ns
tHA Address hold from write end 0 – 0–ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 35 – 40 –ns
tSD Data setup to write end 25 – 25 – ns
tHD Data hold from write end 0 – 0 – ns
tHZWE WE LOW to High Z[16, 17] –18–20 ns
tLZWE WE HIGH to Low Z[16] 10 – 10 –ns
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of 1.5 V, input pulse
levels of 0 to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 4 on page 6.
16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
17. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
18. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 6. Read Cycle 1 (Address Transition Controlled) [19, 20]
Figure 7. Read Cycle No. 2 (OE Controlled) [20, 21, 22]
Figure 8. Write Cycle No. 1 (WE Controlled) [22, 23, 24, 25]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA I/O
OE
NOTE
26
Notes
19. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
22. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
23. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
24. Data I/O is high impedance if OE = VIH.
25. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
26. During this period, the I/Os are in output state and input signals must not be applied.
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CY62128E MoBL®
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Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [27, 28, 29, 30]
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 30]
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA I/O
WE
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA I/O
NOTE
31
Notes
27. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
28. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
29. Data I/O is high impedance if OE = VIH.
30. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
31. During this period, the I/Os are in output state and input signals must not be applied.
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CY62128E MoBL®
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Truth Table
CE1CE2WE OE Inputs/Outputs Mode Power
HX
[32] X X High Z Deselect/Power down Standby (ISB)
X [32] L X X High Z Deselect/Power down Standby (ISB)
L H H L Data Out Read Active (ICC)
L H L X Data In Write Active (ICC)
L H H H High Z Selected, outputs disabled Active (ICC)
Note
32. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
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CY62128E MoBL®
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Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62128ELL-45SXI 51-85081 32-pin 450-Mil SOIC (Pb-free) Industrial
CY62128ELL-45ZAXI 51-85094 32-pin STSOP (Pb-free)
CY62128ELL-45ZXI 51-85056 32-pin TSOP Type I (Pb-free)
CY62128ELL-45SXA 51-85081 32-pin 450-Mil SOIC (Pb-free) Automotive-A
CY62128ELL-45ZXA 51-85056 32-pin TSOP Type I (Pb-free)
55 CY62128ELL-55SXE 51-85081 32-pin 450-Mil SOIC (Pb-free) Automotive-E
CY62128ELL-55ZAXE 51-85094 32-pin STSOP (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Temperature Grade: X = I or A or E
I = Industrial; A = Automotive-A; E = Automotive-E
Pb-free
Package Type: XX = S or ZA or Z
S = 32-pin SOIC
ZA = 32-pin STSOP
Z = 32-pin TSOP Type I
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
E = Process Technology 90 nm
Bus width = × 8
Density = 1-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY XX XX
621 28X
LL X
-
E
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Acronyms Document Conventions
Units of Measure
Figure 13. 32-pin TSOP I (8 × 20 × 1.0 mm) Z32, 51-85056
Package Diagrams (continued)
51-85056 *F
Acronym Description
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
SOIC small outline integrated circuit
STSOP small thin small outline package
TSOP thin small outline package
WE write enable
Symbol Unit of Measure
°C degree Celsius
MHz Mega Hertz
Amicro Amperes
smicro seconds
mA milli Amperes
mm milli meter
ns nano seconds
ohms
%percent
pF pico Farad
VVolts
WWatts
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Document History Page
Document Title: CY62128E MoBL®, 1-Mbit (128 K × 8) Static RAM
Document Number: 38-05485
Rev. ECN No. Submission
Date
Orig. of
Change Description of Change
** 203120 See ECN AJU New data sheet
*A 299472 See ECN SYT Converted from Advance Information to Preliminary
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns, respectively
Changed tDOE from 15 ns to 18 ns for 35 ns speed bin
Changed tHZOE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns
speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed
bins, respectively
Changed tSCE from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed bins,
respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins,
respectively
Added Pb-free package information
Added footnote #9
Changed operating range for SOIC package from Commercial to Industrial
Modified signal transition time from 5 ns to 3 ns in footnote #11
Changed max of ISB1, ISB2 and ICCDR from 1.0 A to 1.5 A
*B 461631 See ECN NXR Converted from Preliminary to Final
Included Automotive Range and 55 ns speed bin
Removed 35 ns speed bin
Removed “L” version of CY62128E
Removed Reverse TSOP I package from Product offering
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f =
fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz
Removed ISB1 DC Specs from Electrical characteristics table
Changed ISB2 (max) from 1.5 A to 4 A
Changed ISB2 (Typ) from 0.5 A to 1 A
Changed ICCDR (max) from 1.5 A to 4 A
Changed the AC Test load Capacitance value from 100 pF to 30 pF
Changed tLZOE from 3 to 5 ns
Changed tLZCE from 6 to 10 ns
Changed tHZCE from 22 to 18 ns
Changed tPWE from 30 to 35 ns
Changed tSD from 22 to 25 ns
Changed tLZWE from 6 to 10 ns
Updated the Ordering Information Table
*C 464721 See ECN NXR Updated the Block Diagram on page # 1
*D 563144 See ECN AJU Added footnote 4 on page 2
*E 1024520 See ECN VKN Added Automotive-A information
Converted Automotive-E specs to final
Added footnote #9 related to ISB2 and ICCDR
Updated Ordering Information table
*F 2548575 08/05/08 NXR Corrected typo error in Ordering Information table
*G 2934396 06/03/10 VKN Added footnote #22 related to chip enable
Updated package diagrams
Updated template
*H 3113780 12/17/2010 PRAS Updated Logic Block Diagram.
Added Ordering Code Definitions.
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CY62128E MoBL®
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*I 3223635 04/12/2011 RAME Updated as per new template
Removed V30 value from Ordering Code Definition.
Added Acronyms and Units of Measure table
Updated Package diagram 51-85056 from *E to *F and 51-85094 *E to *F
*J 3292276 06/24/2011 RAME Updated Data Retention Characteristics (Changed the conditions and minimum
value of tR parameter).
Updated in new template.
Document History Page (continued)
Document Title: CY62128E MoBL®, 1-Mbit (128 K × 8) Static RAM
Document Number: 38-05485
Rev. ECN No. Submission
Date
Orig. of
Change Description of Change
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Document #: 38-05485 Rev. *J Revised July 4, 2011 Page 18 of 18
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CY62128E MoBL®
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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