DS1225Y-200IND - Maxim Integrated Products, Inc.

DS1225Y

64k Nonvolatile SRAM

www.maxim-ic.com

FEATURES

 10 years minimum data retention in the

absence of external power

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 Data is automatically protected during power

loss

 Directly replaces 2k x 8 volatile static RAM

or EEPROM

 Unlimited write cycles

 Low-power CMOS

 JEDEC standard 28-pin DIP package

 Read and write access times as fast as 150 ns

 Full ±10% operating range

 Optional industrial temperature range of

-40°C to +85°C, designated IND

PIN ASSIGNMENT

24-Pin ENCAPSULATED PACKAGE

720-mil EXTENDED

PIN DESCRIPTION

A0-A12 - Address Inputs

DQ0-DQ7 - Data In/Data Out

CE - Chip Enable

WE - Write Enable

OE - Output Enable

VCC - Power (+5V)

GND - Ground

DESCRIPTION

The DS1225Y 64k Nonvolatile SRAM is a 65,536-bit, fully static, nonvolatile RAM organized as 8192

words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which

constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium

energy source is automatically switched on and write protection is unconditionally enabled to prevent

data corruption. The NV SRAM can be used in place of existing 8k x 8 SRAMs directly conforming to

the popular bytewide 28-pin DIP standard. The DS1225Y also matches the pinout of the 2764 EPROM or

the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the

number of write cycles that can be executed and no additional support circuitry is required for micro-

processor interfacing.

27 VCC

128

A12

DQ0

DQ1

GND

DQ2

A11

A10

DQ7

DQ6

DQ5

DQ3

DQ4

DS1225Y

READ MODE

The DS1225Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip

Enable) and OE (Output Enable) are active (low). The unique address specified by the 13 address inputs

(A0-A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the

eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing

that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data

access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE

or tOE for OE rather than address access.

WRITE MODE

The DS1225Y executes a write cycle whenever the WE and CE signals are active (low) after address

inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write

cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be

kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time

(tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during

write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then

WE will disable the outputs in tODW from its falling edge.

DATA RETENTION MODE

The DS1225Y provides full functional capability for VCC greater than 4.5 volts and write protects at 4.25

nominal. Data is maintained in the absence of VCC without any additional support circuitry. The

DS1225Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write

protects itself, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls

below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to

retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit

connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can

resume after VCC exceeds 4.5 volts.

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DS1225Y

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground -0.3V to +7.0V

Operating Temperature 0C to 70C; -40C to +85C for IND parts

Storage Temperature -40C to +70C; -40C to +85C for IND parts

Soldering Temperature +260°C for 10 seconds

Caution: Do Not Reflow (Wave or Hand Solder Only)

 This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (TA : See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Power Supply Voltage VCC 4.5 5.0 5.5 V

Input Logic 1 VIH 2.2 VCC V

Input Logic 0 VIL 0.0 +0.8 V

DC ELECTRICAL CHARACTERISTICS (TA : See Note 10; VCC = 5V ± 10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current IIL -1.0 +1.0

A

I/O Leakage Current

CE  VIH  VCC IIO -1.0 +1.0

A

Output Current @ 2.4V IOH -1.0 mA

Output Current @ 0.4V IOL 2.0 mA

Standby Current CE = 2.2V 1CCS1 5 10 mA

Standby Current CE =VCC -0.5V 1CCS2 3 5 mA

Operating Current tCYC =200ns

(Commercial) 1CCO1 75 mA

Operating Current tCYC= 200ns

(Industrial) ICCO1 85 mA

Write Protection Voltage VTP 4.25 V 10

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DS1225Y

AC ELECTRICAL CHARACTERISTICS (t A : See Note 10; VCC =5.0V ± 10%)

DS1225Y-150 DS1225Y-170 DS1225Y-200

PARAMETER SYMBOL

MIN MAX MIN MAX MIN MAX UNITS NOTES

Read Cycle Time tRC 150 170 200 ns

Access Time tACC 150 170 200 ns

OE to Output Valid tOE 70 80 100 ns

CEto Output Valid tCO 150 170 200 ns

OE or CE to

Output Active tCOE 5 5 5 ns 5

Output High Z from

Deselection tOD 35 35 35 ns 5

Output Hold from

AddressChange tOH 5 5 5 ns

Write Cycle Time tWC 150 170 200 ns

Write Pulse Width tWP 100 120 150 ns 3

Address Setup Time tAW 0 0 0 ns

Write Recovery Time tWR1

tWR2 0

10 0

10 ns

ns 12

Output High Z from WE tODW 35 35 35 ns 5

Output Active from WE tOEW 5 5 5 ns 5

Data Setup Time tDS 60 70 80 ns 4

Data Hold Time tDH1

tDH2 0

10 0

10 ns

ns 12

CAPACITANCE (T

A = 25C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance CIN 10 pF

Input/Output Capacitance CI/O 10 pF

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DS1225Y

READ CYCLE

SEE NOTE 1

WRITE CYCLE 1

SEE NOTE 2, 3, 4, 6, 7, 8 AND 12

WRITE CYCLE 2

SEE NOTE 2, 3, 4, 6, 7, 8 AND 13

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DS1225Y

POWER-DOWN/POWER-UP CONDITION

SEE NOTE 11

POWER-DOWN/POWER-UP TIMING

PARAMETER SYMBOL MIN MAX UNITS NOTES

CE at VIH before Power-Down tPD 0 s 11

VCC Slew from VTP to 0V tF 100 s

VCC Slew from 0V to VTP t

R 0 s

CE at VIH after Power-Up tREC 2 ms

(TA = 25C)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Expected Data Retention Time tDR 10 years 9

WARNING:

Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery

backup mode.

NOTES:

1. WE is high for a read cycle.

2. OE = VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance

state.

3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE

going low to the earlier of CE or WE going high.

4. tDS is measured from the earlier of CE or WE going high.

5. These parameters are sampled with a 5 pF load and are not 100% tested.

6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write

Cycle 1, the output buffers remain in a high-impedance state during this period.

7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output

buffers remain in a high-impedance state during this period.

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DS1225Y

8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,

the output buffers remain in a high-impedance state during this period.

9. Each DS1225Y is marked with a 4-digit date code AABB. AA designates the year of manufacture.

BB designates the week of manufacture. The expected tDR is defined as starting at the date of

manufacture.

10. All AC and DC electrical characteristics are valid over the full operating temperature range. For

commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to

+85°C.

11. In a power down condition the voltage on any pin may not exceed the voltage on VCC.

12. tWR1 , tDH1 are measured from WE going high.

13. tWR2 , tDH2 are measured from CE going high.

14. DS1225Y modules are recognized by Underwriters Laboratory (U.L.) under file E99151 (R).

DC TEST CONDITIONS AC TEST CONDITIONS

Outputs open. Output Load: 100pF + 1TTL Gate

All voltages are referenced to ground. Input Pulse Levels: 0-3.0V

Timing Measurement Reference Levels

Input:1.5V Output: 1.5V

Input Pulse Rise and Fall Times: 5ns

ORDERING INFORMATION

PART NUMBER TEMPERATURE

RANGE SUPPLY

TOLERANCE PIN/PACKAGE SPEED

GRADE

DS1225Y-150 0°C to +70°C

5V  10% 28 / 720 EMOD 150ns

DS1225Y-150+ 0°C to +70°C

5V  10% 28 / 720 EMOD 150ns

DS1225Y-150IND -40°C to +85°C

5V  10% 28 / 720 EMOD 150ns

DS1225Y-150IND+ -40°C to +85°C

5V  10% 28 / 720 EMOD 150ns

DS1225Y-170 0°C to +70°C

5V  10% 28 / 720 EMOD 170ns

DS1225Y-170+ 0°C to +70°C

5V  10% 28 / 720 EMOD 170ns

DS1225Y-200 0°C to +70°C

5V  10% 28 / 720 EMOD 200ns

DS1225Y-200+ 0°C to +70°C

5V  10% 28 / 720 EMOD 200ns

DS1225Y-200IND -40°C to +85°C

5V  10% 28 / 720 EMOD 200ns

DS1225Y-200IND+ -40°C to +85°C

5V  10% 28 / 720 EMOD 200ns

+ Denotes lead(Pb)-free/RoHS-compliant product.

PACKAGE INFORMATION

For the latest package outline info rmation and land patterns, go to http://www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

28 EDIP MDT28+2 21-0245

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DS1225Y

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REVISION HISTORY

REVISION

DATE DESCRIPTION PAGES CHANGED

121907

Added package information table.

Removed the DIP module package drawing and

dimension table.