TMS320DM355 Evaluation Module Technical Reference 2008 DSP Development Systems TMS320DM355 Evaluation Module Technical Reference 509905-0001 Rev. E April 2008 SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digital's standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference. Copyright (c) 2008 Spectrum Digital, Inc. Contents 1 Introduction to the DM355 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides you with a description of the DM355 Evaluation Module, key features, and block diagram. 1.1 Key Features .......................................................... 1.2 Functional Overview of the DM355 EVM ................................. 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Power Supply ......................................................... 2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the operation of the major board components on the DM355 Evaluation Module. 2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Flash, NAND Flash, Ethernet Interface .................................... 2.1.2 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 Memory Card Interface .............................................. 2.1.4 UART Interface ................................................... 2.1.5 USB Interface ..................................................... 2.2 Input Video Port Interfaces ............................................... 2.2.1 On Chip Video Output DAC ............................................. 2.2.2 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Ethernet Interface ....................................................... 2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Daughter Card Interface ................................................ 2.6 DM355 CPU Video Clocks .............................................. 2.7 Battery .............................................................. 1-1 1-2 1-4 1-4 1-5 1-6 1-6 2-1 2-2 2-2 2-2 2-2 2-2 2-3 2-3 2-3 2-4 2-5 2-5 2-6 2-6 2-6 2-7 3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the physical layout of the DM355 Evaluation Module and its connectors. 3.1 Board Layout ........................................................ 3.2 Connectors ........................................................ 3.2.1 J1, NTSC/PAL Select ................................................. 3.2.2 J2, Video In .......................................................... 3.2.3 J3, MSP430 JTAG Header ............................................. 3.2.4 J4, Composite Video Out ............................................... 3.2.5 J5, USB Connector .................................................... 3.2.6 J6, 14 Pin External JTAG Connector ..................................... 3.2.7 J8, ARM JTAG Emulation Header ....................................... 3.2.8 J9, USB Capacitance Select ........................................... 3.2.9 J10, USB ID Select ................................................... 3.2.10 J11, S-Video In ..................................................... 3.2.11 J12, ATA/CE Interface .............................................. 3.2.12 J16, +5 Volt Input ................................................... 3.2.13 J27, MMC/SD Connector ............................................ 3.2.14 J28, MMC/SD Connector ............................................ 3.2.15 J30, Imager Interface Connector 1 ..................................... 3.2.16 J31, Imager Interface Connector 2 .................................... 3.2.17 P1, Microphone In .................................................. 3.2.18 P2, Headphone Out ................................................. 3.2.19 P3, Line Out ....................................................... 3.2.20 P4, RS-232 UART .................................................. 3.2.21 P5, Ethernet Interface ............................................... 3.2.22 P6, Line In ......................................................... 3.2.23 DC3, I/O Daughter Card Expansion .................................... 3.2.24 DC5, TH8200 Daughter Card Interface ................................. 3.2.25 DC6, Expansion Connector ........................................... 3.2.26 DC7, Expansion Connector ........................................... 3.2.27 U10, Infrared Interface ............................................... 3.3 LEDs ................................................................ 3.4 Switches ............................................................. 3.4.1 SW1, EMU0/1 Select Switch ........................................... 3.4.2 SW5, Reset Switch .................................................. 3.4.3 SW6, User Readable 4 Position DIP Switch .............................. 3.4.4 SW7, ARM Boot Mode Select .......................................... 3.4.5 SW10 - SW14 ...................................................... 3.5 Test Points ........................................................ A Schematics .............................................................. Contains the schematics for the DM355 Evaluation Module B Mechanical Information .................................................. Contains the mechanical information about the DM355 Evaluation Module 3-1 3-3 3-5 3-6 3-7 3-7 3-8 3-8 3-9 3-10 3-10 3-11 3-11 3-12 3-13 3-13 3-14 3-15 3-16 3-16 3-17 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-23 3-24 3-24 3-25 3-25 3-26 3-26 3-27 3-27 3-28 A-1 B-1 About This Manual This document describes the board level operations of the DM355 Evaluation Module (EVM). The EVM is based on the Texas Instruments TMS320DM355 Processor. The DM355 Evaluation Module is a table top card that allows engineers and software developers to evaluate certain characteristics of the DM355 processor to determine if the processor meets the designers application requirements. Evaluators can create software to execute on board or expand the system in a variety of ways. Notational Conventions This document uses the following conventions. The DM355 Evaluation Module will sometimes be referred to as the DM355 EVM or EVM. Program listings, program examples, and interactive displays are shown in a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw; Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents, Application Notes and User Guides Information regarding the TMS320DM355 can be found at the following Texas Instruments website: http://www.ti.com Table 1: Manual History Revision History A Production Release B Updated Figures C Edited text D Updated schematics E Updated schematics, Silkscreens, Figures Table 2: Board History PWB Revision History A Production Release B Updated Silk-screen C2 0.55 mm. Production Release D2 0.65 mm. Production Release Chapter 1 Introduction to the DM355 EVM Chapter One provides a description of the DM355 EVM along with the key features and a block diagram of the circuit board. Topic 1.1 1.2 1.3 1.4 1.5 1.6 Page Key Features Functional Overview of the DM355 EVM Basic Operation Memory Map Configuration Switch Settings Power Supply 1-2 1-4 1-4 1-5 1-6 1-6 1-1 Spectrum Digital, Inc 1.1 Key Features MSP430 JTAG IR HP OUT LINE OUT LINE IN LEDs EMIF I2C Bus SPI ROM MIC OUT DC6 NAND DC3 SW6 1 1 2 3 4 Switches SW7 2 DC7 McBSPs SD/MMC USB SD/MMC Connectors SD0 on Bottom Reset MSP430 DM9000A MAC/PHY AIC33 Codec J1 ENET RJ45 Battery J7 The DM355 EVM is a standalone development platform that enables users to evaluate and develop applications for the TMS320DM355 processor. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market. DM355 16 3.3V I/O Supply DDR2 1.8V Supply Video In DC5 1.2V Core Supply USB 2.0 Mux UART0 14 Pin TI JTAG J30 Imager PWR J31 Imager Comp In RS-232 Video Decoder TVP5146 S-Video In 20 Pin ARM JTAG Video Out Comp Out JTAG Figure 1-1, Block Diagram DM355 EVM The EVM comes with a full complement of on board devices that suit a wide variety of application environments. Key features include: * A Texas Instruments DM355 processor with an ARM processor operating up to 216 Mhz. * 1 video input port, supports composite or S video * 1 composite video DAC output * 128 Mbytes of DDR2 DRAM * UART, 2 SD/MMC card interfaces or 1 SD/MMC and 1 CE-ATA Disk Drive Interface * 2 Gigabytes NAND Flash * AIC33 stereo codec * USB2 Interface 1-2 DM355 EVM Technical Reference Spectrum Digital, Inc * 10/100 MBS Memory Mapped Ethernet Controller * SPI EEPROM * IR Remote Interface, real time clock, via MSP430 * Configurable boot load options * 8 user LEDs/4 position user DIP switch/5 user push button switches * Single voltage power supply (+5V) * Expansion connectors for daughter card use * 14 Pin TI JTAG/20 Pin ARM JTAG Interfaces Figure 1-2, DM355 EVM 1-3 Spectrum Digital, Inc 1.2 Functional Overview of the DM355 EVM The DM355 on the EVM interfaces to on-board peripherals through the 8/16-bit wide EMIF peripheral interface pins. The DDR2 memory is connected to its own dedicated 16 bit wide bus. The EMIF bus is also connected to the NAND Flash and ethernet controller. On board video decoder and on chip encoder interface video streams to the DM355 processor. One decoder and 1 on chip DAC channel are standard on the EVM. On screen display functions are implemented in software on the DM355 processor. An on-board AIC33 codec allows the DSP to transmit and receive analog audio signals. The I2C bus is used for the codec control interface, while the McBSP controls the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond to microphone input, headphone output, line input, and line output. The EVM includes 8 user LEDs, a 4 position user DIP switch, an IR interface, a Real time clock along with 5 user push button switches to provide the user with application interaction. These interfaces are implemented via software on a MSP430 and are accessed by reading and writing to the I2C registers. An included +5V external power supply is used to power the board. On-board switching voltage regulators provide the +1.3V CPU core voltage, +3.3V for peripherals and +1.8V for DDR2 memory. The board is held in reset by the on board MSP430 microcontroller until these supplies are within operating specifications. Code Composer Studio communicates with the EVM through an external emulator via the 14 pin external JTAG connector. 1.3 Basic Operation The EVM is designed to work with TI's Code Composer Studio development, or standard GDB tool environments. Code Composer communicates with the board through an external JTAG emulator. To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers. 1-4 DM355 EVM Technical Reference Spectrum Digital, Inc 1.4 Memory Map The DM355 processor has a byte addressable address space. There are some limitations to byte addressing which are determined by peripheral interconnection to the DM355 device. Program code and data can be placed anywhere in the unified address space. Addresses are multiple sizes depending on hardware implementation. Refer to the appropriate device data sheets for more details. The memory map shows the address space of a generic DM355 processor on the left with specific details of how each region is used on the right. By default, the internal memory sits at the beginning of the address space. Portions of memory can be remapped in software as L2 cache rather than fixed RAM. The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces to the DDR2 memory. The other EMIF has 2 separate addressable regions called chip enable spaces (CE0 & CE1). The NAND Flash and ethernet controller are mapped into these chip enable spaces. DM355 EVM Address 0x00000000 Memory Map Address Space ARM Instruction RAM 0x00008000 ARM Instruction ROM 0x00010000 ARM RAM (Data) 0x00020000 Reserved 0x02000000 CE0 0x04000000 CE1 0x06000000 Reserved 0x80000000 DDR 0x8FFFFFFF Figure 1-3, Memory Map, DM355 EVM 1-5 Spectrum Digital, Inc Shown below is a break out of the memory spaces. Address 0x02000000 Memory Space NAND Chip Select 0 0x02004000 NAND Chip Select 1 0x04014000 DM9000A ENET Controller Figure 1-4, DM355 EVM Chip Enable Memory Space 1.5 Configuration Switch Settings The EVM has a configuration switch that allow users to control the operational state of the processor when it is released from reset and determine the source for processor booting. Switch SW7 configures the boot mode that will be used when the DSP starts executing. By default the switches are configured to NAND Flash boot. The EMIF configuration switch must be set accordingly. Table 1: SW7, Boot Mode Select Pos 2 Pos 1 Boot Pin BTSEL1/BTSEL0 Function ON ON 0 0 NAND boot CE0 * ON OFF 0 1 Not Supported OFF ON 1 0 Boot from SD/MMC OFF OFF 1 1 Boot from UART * Default Setting 1.6 Power Supply The EVM operates from a single +5V external power supply connected to the main power input (J14), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted into +1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The +1.3V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers and other chips on the board. The +1.8 volt supply is used for DM355 DDR2 memory. 1-6 DM355 EVM Technical Reference Chapter 2 Board Components This chapter describes the operation of the major board components on the DM355 EVM. Topic 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.2 2.2.1 2.2.2 2.3 2.4 2.4.1 2.5 2.6 2.7 Page EMIF Interfaces Flash, NAND Flash, Ethernet Interface DDR2 Memory Interface Memory Card Interface UART Interface USB Interface Input Video Port Interfaces On Chip Video Output DAC AIC33 Interface Ethernet Interface I2C Interface MSP430 Daughter Card Interface DM355 CPU/Video Clocks Battery 2-2 2-2 2-2 2-2 2-3 2-3 2-3 2-3 2-4 2-5 2-5 2-6 2-6 2-6 2-7 2-1 Spectrum Digital, Inc 2.1 EMIF Interfaces A separate 16 bit EMIF with two chip enables divide up the address space and allow for asynchronous accesses on the EVM. 2.1.1 Flash, NAND Flash, Ethernet Interface The DM355 has 2 gigabytes of NAND Flash memory, and an ethernet interface memory mapped into the CE0 and CE1 spaces. The NAND Flash memory is used primarily for boot loading and file system on the DM355 EVM. The CE0 and CE1 space are configured as 8 and 16 bits wide respectively on the DM355 EVM. 2.1.2 DDR2 Memory Interface The DM355 device incorporates a dedicated 16 bit wide DDR2 memory bus. The EVM uses one gigabit 16 bit wide memories on this bus, for a total of 128 megabytes of memory for program, data, and video storage. The internal DDR controller uses a PLL to control the DDR memory timing. Memory refresh for DDR2 is handled automatically by the DM355 internal DDR controller. 2.1.3 Memory Card Interface The EVM supports two (2) SD/MMC media card interfaces. The second SD connector is connected in parallel to the CE-ATA disk drive connector. 2-2 DM355 EVM Technical Reference Spectrum Digital, Inc 2.1.4 UART Interface The internal UART0 on the DM355 device is driven to connector P4. The UART's interface is routed to the RS-232 line drivers prior to being brought out to a DB-9 connector, P4. 2.1.5 USB Interface The DM355 incorporates an on chip USB II controller. This interface is brought out to a mini A/B connector with its own power regulator. Two jumpers are provided to make a flexible host peripheral, and USB on the go interface. 2.2 Input Video Port Interfaces/Imager Input Ports The DM355 EVM supports video capture via the devices internal video ports. A Texas Instruments TVP5146 is used to decode composite video or S-video inputs into the device. J11 is used for the S-video inputs and J2 for the composite inputs on the EVM. The input port can also be driven by LCD imagers connected to connectors J30 and J31. The imager or encoder is selectable via software control on I2C bus by accessing MSP430 registers. 2.2.1 On Chip Video Output DAC The DM355 incorporates 1 composite video output DAC to interface to various video output standards. The DAC is filtered and driven to RCA jack, J4. 2-3 Spectrum Digital, Inc 2.2.2 AIC33 Interface The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output of audio signals. The codec samples analog signals on the microphone or line inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples back into analog signals on the line output so the user can hear the output. The codec communicates using two serial channels, one to control the codec's internal configuration registers and one to send and receive digital audio samples. The I2C bus is used as the AIC33's control channel. The control channel is generally only used when configuring the codec, it is typically idle when audio data is being transmitted, McBSP1 is used as the bi-directional data channel. All audio data flows through the data channel. Many data formats are supported based on the three variables of sample width, clock signal source and serial data format. The EVM examples generally use a 16-bit sample width with the codec in master mode so it generates the frame sync and bit clocks at the correct sample rate without effort on the DSP side. The codec is clocked via a 27 Mhz oscillator. The internal sample rate generator subdivides the default system clock to generate common audio frequencies. The sample rate is set by a codec register. The figure below shows the codec interface on the DM355 EVM. AIC33 Codec MIC IN 2 IC SCL SDA Control I2C Format SCL SDA LINE IN Control Registers Analog Digital LINE OUT DR DX CLKR CLKX FSR FSX McBSP I2S Format DOUT DIN BCLK WCLK MIC IN ADC LINE IN DAC LINE OUT HP OUT HP OUT Figure 2-2, DM355 EVM CODEC INTERFACE 2-4 DM355 EVM Technical Reference Spectrum Digital, Inc 2.3 Ethernet Interface The DM355 EVM incorporates an ethernet controller chip. This interface is connected to the DM355's EMIF. The EVM uses an Intel DAVICOM DM9000A. The 10/100 Mbit interface is isolated and brought out to a RJ-45 standard ethernet connector, P5. The ethernet address is stored in the ethernet controller's SPI ROM during manufacturing. The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellow and indicate the status of the ethernet link. The green LED, when on, indicates link and when blinking indicates link activity. The yellow LED, when illuminated, indicates full duplex mode. 2.4 I2C Interface The I2C bus on the DM355 is ideal for interfacing to the control registers of many devices. On the DM355 EVM the I2C bus is used to configure the video decoder, stereo Codec, I/O expanders, and communicate with the MSP430. An I2C ROM is also interfaced via the serial bus. The format of the bus is shown in the figure below. Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop Write Sequence Start Slave Address R Data STOP Read Sequence Figure 2-4, I2C Bus Format The addresses of the on board peripherals are shown in the table below. Table 1: I2C Memory Map Device Address R/W Function TVP5146 0x5D R/W Capture 1 Decoder TLV320AIC33 0x1B R/W CODEC MSP430 0x25 R/W LEDs, IR, RTC, User I/O 2-5 Spectrum Digital, Inc 2.4.1 MSP430 The DM355 EVM incorporates infrared remote, real time clock, and user and system bit I/O in a MSP430 microcontroller. The I2C interface is used on the DM355 processor to communicate to the MSP430. The MSP430 acts as a slave device on the I2C bus. 2.5 Daughter Card Interfaces The EVM provides expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their EVM platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are interfaces which include McBSP, and serial I/O expansion. The unused EMIF signals are brought out as user GPIO signals. The video output port is brought out to the daughter card interface along with I/O and imager interface. 2.6 DM355 CPU/Video Clocks The DM355 EVM uses a 24 Megahertz crystal to generate the main input clock. The DM355 has an internal PLL which can multiply the input clock to generate the internal clock. The PLL multiplier is set via software on the DM355 device. The secondary clock is generated from a 27 Megahertz crystal. the clock domain is generally used for internal video clock generation. 2-6 DM355 EVM Technical Reference Spectrum Digital, Inc 2.7 Battery The DM355 EVM incorporates a battery holder to provide backup power to the MSP430's real time clock when the power is not applied to the board. The optional battery should be +3 volt 20 millimeter coin type Lithium single cell. Some common part numbers for batteries which should operate in the EVM are shown in the table below. Table 2: Battery Part Numbers Part Numbers CR2032 DL2032 BR2032 CR2025 BR2025 CR2016 BR2016 DL2016 These batteries are available from Duracell, Eveready, Panasonic, Ray-O-Vac, Sanyo, Sony, Sieko, Toshiba, Varta, and other battery manufacturers. 2-7 Spectrum Digital, Inc 2-8 DM355 EVM Technical Reference Chapter 3 Physical Description This chapter describes the physical layout of the DM355 EVM and its interfaces. Topic 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.12 3.2.13 3.2.14 3.2.15 3.2.16 3.2.17 3.2.18 3.2.19 3.2.20 3.2.21 3.2.22 3.2.23 3.2.24 3.2.25 3.2.26 3.2.27 Page Board Layout Connectors J1, NTSC/PAL Select J2, Video In J3, MSP430 JTAG Header J4, Composite Video Out J5, USB Connector and Jumpers J6, 14 Pin External JTAG Connector J8, ARM JTAG Emulation Header J9, USB Capacitance Select J10, USB ID Select J11, S-Video In J12, ATA/CE Interface J16, +5V Input J27, MMC/SD Connector J28, MMC/SD Connector J30, Imager Interface Connector 1 J31, Imager Interface Connector 2 P1, Microphone In P2, Headphone Out P3, Line Out P4, RS-232 UART P5, Ethernet Interface P6, Line In DC3, I/O Daughter Card Expansion DC5, TH8200 Daughter Card Interface DC6, Expansion Connector DC7, Expansion Connector U10, Infrared Interface 3-3 3-5 3-6 3-7 3-7 3-8 3-8 3-9 3-10 3-10 3-11 3-11 3-12 3-13 3-13 3-14 3-15 3-16 3-17 3-18 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-24 3-25 3-1 Spectrum Digital, Inc Topic 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 3-2 LEDs Switches SW1, EMU0/1 Select Switch SW5, Reset Switch SW6, User Readable 4 Position DIP Switch SW7, ARM Boot Mode Select SW10 - SW14 Test Points Page 3-25 3-26 3-26 3-27 3-27 3-28 3-28 3-29 DM355 EVM Technical Reference Spectrum Digital, Inc 3.1 Board Layout The DM355 EVM is a 5.0 x 6.5 inch (127 x 165 mm.) ten (10) layer printed circuit board which is powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the top side of the DM355 EVM. BHT1 P5 U10 J3 DS14-DS21 J1 SW5 J13 SW10 P2 SW12 SW11 SW13 P3 SW14 P6 SW6 SW7 P1 DC7 DC6 DC3 DS5 J28 J16 DC5 J31 J5 J30 J10 S1 J9 J4 J8 J11 J6 J2 P4 Figure 3-1, DM355 EVM, Interfaces Top Side 3-3 Spectrum Digital, Inc Figure 3-2 shows the layout of the bottom side of the DM355 EVM. J27 J12 Figure 3-2, DM355 EVM, Interfaces Bottom Side 3-4 DM355 EVM Technical Reference Spectrum Digital, Inc 3.2 Connectors The EVM has numerous connectors and option jumpers to control and provide connections to various peripherals. These connectors and jumpers are described in the following sections. Table 1: Connectors Connector Size Function J1 1x3 NTSC/PAL Video Select J2 Video In J3 2x7 MSP430 JTAG J4 8 Composite Video Out J5 1x4 Mini A/B USB Connector J6 2x7 TI 14 Pin JTAG J8 2x8 ARM JTAG Emulation Header J9 2x1 USB Capacitor J10 2x1 USB ID Jumper J11 4 Video In J12 12 x 1 ATA/CE Interface J13 4x2 Spare Jumper Storage J16 2 +5V In J27 18 SD/MMC Connector J28 18 SD/MMC Connector J30 13 x 2 Imager Interface J31 13 x 1 Imager Interface P1 4 Microphone In P2 2x5 Headphone Out P3 4 Line Out P4 9 RS-232 UART P5 12 Ethernet P6 4 Line In DC3 15 x 2 I/O Daughter Card Expansion DC5 25 x 2 THS8200 Daughter Card Interface DC6 5x2 Expansion Connector DC7 10 x 2 U10 GP I/O Signals Infrared Receiver 3-5 Spectrum Digital, Inc 3.2.1 J1, NTSC/PAL Select The J1 connector is a 3 position jumper located on the top side of the board and is used to select the type of video data the DM355 will be working with. NTSC format is expected if the jumper is in the 1-2 position. The selection of 2-3 indicates PAL format data will be used. Either the NTSC (1-2 position) or PAL (2-3 position) must be selected. To reconfigure this selection, power down the EVM, change the jumper, and then power the board back up. Do NOT change this jumper with the power on. The image of this jumper is shown in the figure below. Board Edge NTSC NTSC 1 1 J1 J1 PAL NTSC Format PAL PAL Format Figure 3-3, J1, NTSC/PAL Select Table 2: J15, NTSC/PAL Select 3-6 Video Format Position NTSC 1-2 PAL 2-3 DM355 EVM Technical Reference Spectrum Digital, Inc 3.2.2 J2, Video In J2 is an RCA jack used as a composite video input to the TVP5146 encoder. This connector brings in a video signal to pin 8 on the TVP5146. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge. Pin 2, Shield (ground) Pin 1, Signal Input Figure 3-4, J2, Video In RCA Jack Table 3: J2, Video In, RCA Jack Pin # Signal Name 1 Pin 8, TVP5146 2 GND 3.2.3 J3, MSP430 JTAG Header The J3 MSP430 JTAG Header is located on the top side of the board and is used to provide a programming interface to the MSP430 microcontroller. The pinout for the J3 connector is shown in the table below. This connector is typically used for factory use only. Board Edge J3 1 2 MSP430 EMU Figure 3-5, J3, MSP430 JTAG Header Table 4: J3, MSP430 JTAG Header Pin # Signal Pin # Signal 1 430_TDO 2 NC 3 430_TDI 4 MSP430_3V3 5 430_TMS 6 NC 7 430_TCK 8 NC 9 GND 10 NC 11 430_RESET 12 NC 13 NC 14 NC 3-7 Spectrum Digital, Inc 3.2.4 J4, Composite Video Out Connector J4 is an RCA jack used as a composite video output from the "TVOUT" signal of the TMS320DM355. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge. Pin 2, Shield (ground) Pin 1, Composite Signal Figure 3-6, J4, TV Out, RCA Jack Table 5: J4, TV Out, RCA Jack Pin # Signal Name 1 Composite video output 2 GND 3.2.5 J5, USB Connector and Jumpers Connector J5 is a mini A/B USB connector. The pinout for the J5 connector is shown in the figure below. Table 6: J5, USB Connector Pins Signal 1 USB_VBUS 2 USB_DM 3 USB_DP 4 USB_ID 5-9 USB_SHIELD * Use internal register to swap DM/DP pair. This feature was used to improve printed circuit board routing. The EVM incorporates the ability to toggle the ID pin on the USB connector via software control. The GIO2 pin on the DM355 controls this function. For "USB ON The Go" mode remove jumper J10. This will allow the cable to configure the ID pin on the DM355 processor. 3-8 The EVM supplies up to 500 ma of current to the USB_VBUS via a TPS61092 DC/DC converter. This is enabled via the DM355's DRV_VBUS pin. J9 supplies extra capacitance for host mode operations. Remove J9 for "USB On The Go" operations. Spare jumpers can be stored on connector J13. DM355 EVM Technical Reference Spectrum Digital, Inc 3.2.6 J6, 14 Pin External JTAG Connector Connector J6 is a 2 x7 double row male header with pin 6 clipped to serve as a key. This is the standard interface used by JTAG emulators to interface to Texas Instruments DSPs. The pinout for the connector is shown in the figure below. TMS TDI PD (+3.3V) TDO TCK-RET TCK EMU0 1 3 5 7 9 11 13 2 4 6 8 10 12 14 TRSTGND no pin (key) GND GND GND EMU1 Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal Figure 3-7, JTAG INTERFACE The signal names for each pin are shown in the table below. Table 7: J6, JTAG Interface Pin # Signal Name Pin # Signal Name 1 TMS 2 TRST- 3 TDI 4 GND 5 PD 6 no pin - key 7 TDO 8 GND 9 TCKRET 10 GND 11 TCK 12 GND 13 EMU0 14 EMU1 * Note: EMU0/EMU1 mode must be selected to ICEPICK mode 3-9 Spectrum Digital, Inc 3.2.7 J8, ARM JTAG Emulation Header The J8 Emulation Header is located on the top side of the board and is used to provide an interface to ARM compatible JTAG emulators. The pinout for this connector is shown in the table below. Table 8: J8, ARM JTAG Emulation Header Pin # Signal Pin # Signal 1 VCC_3V3 2 VCC_3V3 3 ARM_TRSTn 4 Ground 5 ARM_TDI 6 Ground 7 ARM_TMS 8 Ground 9 ARM_TCK 10 Ground 11 ARM_TCKRET 12 Ground 13 ARM_TDO 14 Ground 15 ARM_RSTn 16 Ground 17 NC 18 Ground 19 NC 20 Ground * Note: EMU0/EMU1 switch must be set to ARM mode 3.2.8 J9, USB Capacitance Select The J9 jumper is used to provide more capacitance when the USB connector is used in the host mode. When the jumper is shorted the extra capacitance is provided. These open and shorted position are shown below. Open Shorted USB VBUS USB VBUS J9 J9 Figure 3-8, J9, USB Capacitance Select Table 9: J9, USB Capacitance Select 3-10 Position Function Open 6.9 uF Capacitance Shorted 106.8 uF Capacitance DM355 EVM Technical Reference Spectrum Digital, Inc 3.2.9 J10, USB ID Select The J10 jumper is used to allow the cable to configure the ID pin on the DM355. This is used for the "USB On The Go" mode. When the jumper is shorted, access to the ID is provided. The open and shorted position are shown below. Shorted Open USB ID USB ID J10 J10 Figure 3-9, J10, USB ID Select Table 10: J10, USB ID Select Position Function Open ID from USB connector Shorted ID controlled from GIO2 3.2.10 J11, S-Video In Connector J11 is a four pin mini din connector which interfaces to the TVP5146 encoder. This connector brings in a video signal (LUMA) to pin 9 on the TVP5146. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge. Pin 3 Pin 1 Pin 4 Pin 2 Figure 3-10, J11, Front View, Mini Din Connector Table 11: J11, Video In, Mini Din Connector Pin # Signal Name 1 GND 2 GND 3 LUMA 4 Chroma 3-11 Spectrum Digital, Inc 3.2.11 J12, ATA/CE Interface Connector J12 is a 12 x 1 flex cable connector mounted on the bottom side of the board. The signals on this connector parallel the signals present on the connector J28 which is located on the top side of the board. The signals present on connector J12 are shown in the table below. when this connector is used the corresponding SD connector can not be used. Table 12: J12, ATA/CE Interface 3-12 Pin # Signal Name 1 Ground 2 SD1_DAT2 3 SD1_DAT3 4 VCC_3V3 5 SD1_CMD 6 VCC_3V3 7 SD1_CLK 8 Ground 9 SD1_DATA0 10 SD1_DATA1 11 Ground 12 NC DM355 EVM Technical Reference Spectrum Digital, Inc 3.2.12 J16, +5V Input Connector J16 is the input power connector. This connector bring in +5 volts to the EVM. This is a 2.5mm. jack. Inside of the jack is tied to through a fuse to VCC_5V. The other side is tied to ground and LED DS5. The figure below shows this connector as viewed from the card edge. +5V J16 Ground PC Board Front View Figure 3-11, J16, +5 Volt Input Connector 3.2.13 J27, MMC/SD Connector The J27 MMC/SD connector is located on the bottom side of the board and is used to provide an interface to a MMC/SD card. The pinout for the J27 connector is shown in the table below. Table 13: J27, MMC/SD Connector Pin # Signal Pin # Signal 1 SD0_DATA3 2 SD0_CMD 3 GND 4 VCC_3V3 5 SD0_CLK 6 GND 7 SD0_DATA0 8 SD0_DATA1 9 SD0_DATA2 10 Write Protect 0 11 GND 12 Insert 0 3-13 Spectrum Digital, Inc 3.2.14 J28, MMC/SD Connector The J28 MMC/SD connector is located on the top side of the board and is used to provide an interface to a MMC/SD card. The signals present on J28 are also present on J12. Therefore, when J28 is used the operator can not use J12 for a CE-ATA disk drive. The pinout for the J28 connector is shown in the table below. Table 14: J28, MMC/SD Connector 3-14 Pin # Signal Pin # Signal 1 SD1_DATA3 2 SD1_CMD 3 GND 4 VCC_3V3 5 SD1_CLK 6 GND 7 SD1_DATA0 8 SD1_DATA1 9 SD1_DATA2 10 Write Protect 1 11 GND 12 Insert 1 DM355 EVM Technical Reference Spectrum Digital, Inc 3.2.15 J30, Imager Interface Connector 1 The connector J30 is a 13 x 2 double row header which is part of the imager interface. It is used with connector J31. The pinout for the J30 connector is shown in the table below. Table 15: J30, Imager Interface Connector 1 Pin # Signal Pin # Signal 1 IMAGER_D4 2 IMAGER_D5 3 IMAGER_D6 4 IMAGER_D7 5 IMAGER_D8 6 IMAGER_D9 7 IMAGER_D10 8 IMAGER_D11 9 IMAGER_D2 10 IMAGER_D3 11 Ground 12 Ground 13 IMAGER_LINE_VALID 14 NC 15 NC 16 IMAGER_RESET 17 IMAGER_FRAME_VALID 18 I2C_DATA_IMG 19 I2C_SCLK_IMG 20 NC 21 IMAGER_VBUS 22 IMAGER_VBUS 23 IMAGER_PXCLK 24 Ground 25 Ground 26 Ground Note: When using the imager the user needs to select the video input multiplier to imager mode via I2C control registers in the MSP430. 3-15 Spectrum Digital, Inc 3.2.16 J31, Imager Interface Connector 2 The connector J31 is a 13 x 1 single row header which is part of the imager interface. It is used with connector J30. The pinout for the J31 connector is shown in the table below. Table 16: J30, Imager Interface Connector 1 Pin # Signal 1 IMAGER_D0 2 IMAGER_D1 3 NC 4 NC 5 NC 6 NC 7 NC 8 NC 9 NC 10 IMAGER_GBL_SHUTTER 11 IMAGER_TRG 12 NC 13 Ground Note: When using the imager the user needs to select the video input multiplier to imager mode via I2C control registers in the MSP430. 3.2.17 P1, Microphone In The microphone input, P1 is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural. The signal is connected to signals "MIC3R" and "MIC3L" of the AIC33. The signals on the plug are shown in the figure below. Ground Microphone In Figure 3-13, Microphone Input Jack 3-16 DM355 EVM Technical Reference Spectrum Digital, Inc 3.2.18 P2, Headphone Out The P2 connector is a 3.5 mm. stereo headphone output from the TVL320AIC33 on the EVM. This connector is located on the top side of the board. A view of the connector from the card edge is shown in the figure below. The signals present on this connector are defined in the following table. Stereo Line Out Figure 3-14, P2, Headphone Out Interface Table 17: P2, Headphone Out Interface Pin # AIC33 Signal 1 Ground 2 HPLOUT 3 HPROUT 4 NC 3.2.19 P3, Line Out The audio line out connector P3, is a stereo output. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below. Ground Right Line Out Left Line Out Figure 3-15, Audio Line Out Stereo Jack Table 18: P3, Audio Line Out Stereo Jack Pin # AIC33 Signal 1 Ground 2 LEFT_LO+ 3 RIGHT_LO+ 4 NC 3-17 Spectrum Digital, Inc 3.2.20 P4, RS-232 UART The P4 connector is a 9 pin make D-connector which provides a UART interface to the EVM. This connector interfaces to the MAX 3221 RS-232 line driver (U34) and is located on the top side of the board. A view of the connector from the card edge is shown in the figure below. The signals present on this connector are defined in the following table. 4 5 9 3 8 2 7 1 6 Figure 3-16, P4, DB9 Male Connector The pin numbers and their corresponding signals are shown in the table below. This corresponds to a standard dual row to DB-9 connector interface used on personal computers. Table 19: P4, RS-232 Pinout 3-18 Pin # Signal Name 1 NC 2 DM355 UART0 Rx Data 3 DM355 UART0 Tx Data 4 NC 5 GND 6 NC 7 Pin 8 8 Pin 7 9 NC DM355 EVM Technical Reference Spectrum Digital, Inc 3.3.21 P5, Ethernet Interface The P5 connector is located on the top side of the board and is used to provide an Ethernet interface. P5 integrates the magnetics and standard RJ-45 connector. The two tables below shoe the signals present on the magnetics interface and the connector side. Table 20: P5, Magnetics/LEDs Interface Signals Pin # Signal Pin # Signal 1 ENET_TXO+ 2 ENET_TXO- 3 ENET_RXI+ 4 ENET_2V5(RX Center Tap) 5 ENET_2V5(RX Center Tap) 6 ENET_RXI- 7 NC 8 GND 9 VCC_3V3(LED1+) 10 ENET_LED1(LED1-) 11 VCC_3V3(LED2+) 12 ENET_LED2(LED2-) The ethernet connector incorporates 2 LEDs which give link and transmit status from the ethernet controller. Table 21: P5, RJ-45 Connector Pin # Signal Pin # Signal 1 TX_DATA+ 2 TX_DATA- 3 RX_DATA+ 4 NC 5 NC 6 RX_DATA- 7 NC 8 NC 3-19 Spectrum Digital, Inc 3.2.22 P6, Line In Connector P6 is an stereo audio line input. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below. Ground Left Line In Right Line In Figure 3-17, P6, Audio Line In Stereo Jack Table 22: P6, Headphone Out Interface 3-20 Pin # AIC33 Signal 1 Ground 2 LINE2L+ 3 LINE2R+ 4 NC DM355 EVM Technical Reference Spectrum Digital, Inc 3.2.23 DC3, I/O Daughter Card Expansion The DC3 connector is an I/O expansion interface for a daughter card. This is a 15 x 2 pinned female surface mount connector. The pinout for the DC3 connector is shown in the table below. Table 23: DC3, I/O Daughter Card Expansion Pin # Signal Pin # Signal 1 SPI1_SDENA0 2 NC 3 SPI1_SDI 4 SPI_SDO 5 SPI1_CLK 6 DM355_TIMERIN3 7 Ground 8 Ground 9 McBSP_DR0 10 McBSP_DX0 11 McBSP_CLKR0 12 McBSP_CLKX0 13 McBSP_FSR0 14 McBSP_FSX0 15 Ground 16 Ground 17 SYS_RESETz 18 I2C_SCLK 19 UART1_TXD 20 I2C_DATA 21 UART1_RXD 22 Ground 23 Ground 24 GIO18 25 VCC_3V3 26 VCC_3V3 27 Ground 28 Ground 29 VCC_5V 30 VCC_5V The manufacturer and part number of this connector is: SAMTEC SFM-115-02-S-D-LC A possible mating connector is: SAMTEC TFM-115-32-S-D-LC. This height is .44 inches. Your actual height may vary. 3-21 Spectrum Digital, Inc 3.2.24 DC5, TH8200 Daughter Card Interface The DC5 connector is an expansion interface for the TH8200 daughter card. This is a 25 x 2 pinned female surface mount connector. The pinout for the DC5 connector is shown in the table below. Table 24: DC5, TH8200 Daughter Card Interface Pin # Signal Pin # Signal 1 VDOUT_LCD_OE 2 GIO16 3 VDOUT_FIELD 4 GIO17 5 DM355_GIO6 6 DM355_GIO7 7 Ground 8 Ground 9 VDOUT_C0 10 VDOUT_C1 11 VDOUT_C2 12 VDOUT_C3 13 VDOUT_C4 14 VDOUT_C5 15 VDOUT_C6 16 VDOUT_C7 17 Ground 18 Ground 19 VDOUT_EXTCLK 20 CDOUT_HSYNC 21 Ground 22 Ground 23 VDOUT_VCLK 24 CDOUT_VSYNC 25 Ground 26 Ground 27 VDOUT_Y0 28 VDOUT_Y1 29 VDOUT_Y2 30 VDOUT_Y3 31 VDOUT_Y4 32 VDOUT_Y5 33 VDOUT_Y6 34 VDOUT_Y7 35 Ground 36 Ground 37 I2C_SCLK 38 DC5_RESETn 39 I2C_DATA 40 Ground 41 VCC_1V8 42 VCC_1V8 43 Ground 44 Ground 45 VCC_3V3 46 VCC_3V3 47 Ground 48 Ground 49 VCC_5V 50 VCC_5V The manufacturer and part number of this connector is: SAMTEC SFM-125-02-S-D-LC A possible mating connector is: SAMTEC TFM-125-32-S-D-LC. This height is .44 inches. Your actual height may vary. 3-22 DM355 EVM Technical Reference Spectrum Digital, Inc 3.2.25 DC6, Expansion Connector The DC6 connector is an expansion connector used to provide compatibility with the THS8200 video daughter card. This is a 5 x 2 pinned female surface mount connector. The pinout for the DC6 connector is shown in the table below. Table 25: DC6, Video Output Connector Pin # Signal Pin # Signal 1 NC 2 NC 3 VCC_3V3 4 Ground 5 NC 6 NC 7 NC 8 NC 9 Ground 10 Ground The manufacturer and part number of this connector is: SAMTEC SFM-105-02-S-D-LC A possible mating connector is: SAMTEC TFM-105-32-S-D-LC. This height is .44 inches. Your actual height may vary. 3.2.26 DC7, Expansion Connector Extra EMIF signals are available as general purpose I/O in some configurations. Connector DC7 provides access to these pins. This is a 10 x 2 pinned female surface mount connector. The pinout for the DC7 connector is shown in the table below. Table 26: DC7, Expansion Connector Pin # Signal Pin # Signal 1 GIO54 2 GIO67 3 GIO65 4 GIO31 5 GIO63 6 GIO64 7 Ground 8 Ground 9 GIO62 10 GIO61 11 GIO60 12 GIO59 13 GIO58 14 GIO57 15 GIO56 16 GIO032 17 Ground 18 Ground 19 VCC_3V3 20 VCC_3V3 3-23 Spectrum Digital, Inc 3.2.27 U10, Infrared Interface U10 is an infrared receiver mounted on the edge of the board. This device interfaces to the MSP430 mircrocontroller. The view of U10 is shown from a board edge view in the figure below. U10 PC Card Figure 3-18, U10, IR Interface, Card Edge View The receiver supports interaction with an Infrared remote control included with your EVM 3.3 LEDs The EVM has ten (10) LEDs which are located on the top side of the board. Information regarding the LEDs are shown in the table below. Table 27: LEDs 3-24 LED # Use DS5 +5 Volts present Color Green DS14 2C User control via MSP430 I Green DS15 User control via MSP430 I2C Green DS16 User control via MSP430 I2C Green DS17 User control via MSP430 I2C Green DS18 User control via MSP430 I2C Green DS19 User control via MSP430 I2C Green DS20 User control via MSP430 I2C Green DS21 User control via MSP430 I2C Green DS22 Boot Mode Status Green DM355 EVM Technical Reference Spectrum Digital, Inc 3.4 Switches The EVM has nine (9) switches. The function of these switches are shown in the table below. Table 28: Switches Switch Function Type SW1 EMU0/EMU1 Control 4 Position DIP SW5 Reset Push Button/Momentary SW6 User Readable 4 Position DIP SW7 ARM Boot Mode Select 2 Position DIP SW10 User Readable Push Button/Momentary SW11 User Readable Push Button/Momentary SW12 User Readable Push Button/Momentary SW13 User Readable Push Button/Momentary SW14 User Readable Push Button/Momentary 3.4.1 SW1, EMU0/1 Select Switch SW1 is a 2 position DIP switch providing 4 options in selecting the state of the EMU0 and EMU1 pins on the TMS320DM355 processor. A view of the switch is shown in the figure below. The selection options with this switch are in the table below. EMU1 Raised NIB H S1 L EMU0 Figure 3-19, SW1, EMU0/1 Select Switch Table 29: SW1, EMU0/1 Select State at Reset EMU1 EMU0 Function L(0) L(0) Emulation Debug ARM JTAG Enabled L(0) H(1) Not Defined H(1) L(0) Not Defined H(1) H(1) ICE PICK Mode * Both ARM & DSP JTAG Enabled * is the factory shipped configuration 3-25 Spectrum Digital, Inc 3.4.2 SW5, Reset Switch Switch SW5 is a push button reset switch that will RESET the board. The MSP430 controls all reset and power monitoring logic on the EVM. 3.4.3 SW6, User Readable 4 Position DIP Switch Switch SW6 is a 4 position DIP switch with each position being an input to the MSP430 microcontroller and accessible to the DM355 via the I2C control registers. The table below shows what signal each position appears on. Raised NIB ON 1 3 2 SW6 4 Figure 3-20, SW6, User Readable 4 Position DIP Switch . Table 30: SW6, User Readable 4 Position DIP Switch 3-26 Position Signal 1 SW_DIP0 2 SW_DIP1 3 SW_DIP2 4 SW_DIP3 DM355 EVM Technical Reference Spectrum Digital, Inc 3.4.4 SW7, ARM Boot Mode Select Switch SW7 is a 2 position DIP switch used to select the ARM Boot Mode. The figure and table below show these options. BOOT MODE ON Raised NIB 1 2 SW7 Figure 3-21, SW7, ARM Boot Mode Select Table 31: SW7, ARM Boot Mode Select Pos 2 Pos 1 HW Code Function ON ON 00 NAND boot CE0 * ON OFF 01 NOR direct execute OFF ON 10 Boot from SD/MMC OFF OFF 11 Boot from UART * default setting 3.4.5 SW10 - SW14 Switches S10 through SW14 are push button momentary switches that are inputs in to the MSP430 microcontroller and accessible to the DM355 via I2C control registers on the MSP430. The table below shows what signal each switch appears on. Table 32: SW10 - SW14, Processor Configuration/Boot Load Options Switch Signal SW10 PB_SW10 SW11 PB_SW11 SW12 PB_SW12 SW13 PB_SW13 SW14 PB_SW14 3-27 Spectrum Digital, Inc 3.5 Test Points The EVM has 35 test points. All test points appear on the top of the board. The following figure identifies the position of each test point. the next table list each test point and the signal appearing on that test point. TP27 TP27 TP3,TP4 TP2,TP14 TP21 TP22,TP23 TP10,TP43 TP36 TP11 TP37,TP38 TP5 TP30 TP42 TP32 TP9 TP33,TP34 TP7 TP31 TP41 TP39,TP40 TP1 TP8 TP12 TP13 TP29 TP6 TP25 TP26 Figure 3-22, DM355 EVM, Test Points 3-28 DM355 EVM Technical Reference Spectrum Digital, Inc Table 33: DM355 EVM Test Points Test Point # Signal Test Point # Signal TP2 VCC_1V8 TP29 Ground TP3 AIC33 MFP2 TP30 Ground TP4 AIC33 MFP3 TP31 VCC_5V TP10 EM_ADV/GIO032 TP32 3V3_PWR_OK TP13 VDDA_DAC TP33 VCC_3V3 TP14 EM_CLK/GIO031 TP36 1V8_PWR_OK TP21 CORE_PWR_OK TP37 VCC_1V8 TP23 VCC_1V3 TP39 TMS320DM355 MXI2 TP25 Ground TP40 TMS320DM355 MXO2 TP26 Ground TP41 TMS320DM355 MXI1 TP27 Ground TP42 TMS320DM355 MXO1 TP28 Ground TP43 EM_A7 There are 12 power test points on the EVM. These test points provide a convenient mechanism to check the EVM's multiple power supplies. The table below shows the voltages for each test point and what the supply is used for. Table 34: Power Test Points Access Test Point Voltage Shunt Power Domain VDDAHV3V3 TP1 +1.8V 0.02 ohms TP5 +1.3V 0.02 ohms CVDD TP6 +1.8V 0.02 ohms VDDA1V8 HSSI TP7 +1.3V 0.02 ohms USB1V3 TP8 +3.3V 0.02 ohms USB3V3 TP9 +1.3V 0.02 ohms VDDA.PLL1 & 2 TP11 +3.3V 0.02 ohms VDD TP12 +1.8V 0.02 ohms VDDS TP22 +1.3V 0.02 ohms Main 1.3V TP34 +3.3V 0.025 ohms Main 3.3V TP38 +1.8V 0.025 ohms Main 1.8V TP12 +1.8V 0.025 ohms DDR2 Power 3-29 Spectrum Digital, Inc 3-30 DM355 EVM Technical Reference Appendix A Schematics This appendix contains the schematics for the DM355 EVM. A-1 A-2 A B C D X X D 2 D2 1 3 D 13 A D2 12 A 11 23 22 21 4 D 14 A 24 A 33 A A 34 A C 32 A A 31 5 5 D2 15 A 25 A 6 D 16 A 26 A 7 D 17 A 27 A 8 D 18 A 28 A TVP5146 01011101B 0x5D REVISION STATUS OF SHEETS AIC33 00011011B DEVICE 0x1B A 1 A9 1 F A8 1 A7 1 A6 1 A5 9 A 1 A1 F 1 A0 1 WORD 10 A 20 A 30 A APPLICATION NEXT ASSY 4 USED ON T.W.K. R.R.P. R.R.P. ENGR-MGR R.R.P. QA C.M.D. MFG R.R.P. RLSE R.R.P. ENGR CHK DWN VIDEO DECODER - 101110(I2CA) 19 A 1 A2 FUNCTION F 1 A3 AUDIO CODEC - 00110(MFP1)(MFP0) 29 A 1 A4 DM9000A READ WRITE NAND FLASH CS1 R/W NAND FLASH CS0 R/W FUNCTION 4 RTC,IR CTL, IO CTL, POWER MONITOR I2C Address Table 1 A10 MSP430 1 A11 00100011B BINARY A12 A13 0x25 HEX ADDRESS A14 0x0401 4000 CE1 - PHY/MAC CHIP ARM ADDRESSING 0x0200 4000 CE0 - NAND CS1 HEX 0x0200 0000 ADDRESS BASE Memory Address Table CE0 - NAND CS0 CHIP SELECT 5 DATE 04/01/2007 DATE 04/01/2007 DATE 04/01/2007 DATE 04/01/2007 DATE 04/01/2007 DATE 04/01/2007 DATE 04/01/2007 Production release for 0.50 mm Pre-production release for 0.65 mm D Pre-production release - Beta Release B C Initial schematic ready for layout - Alpha Release - SHEET20 SHEET21 SHEET22 SHEET23 SHEET24 SHEET26 SHEET27 - SHEET10 SHEET11 SHEET12 SHEET13 SHEET14 SHEET15 SHEET16 SHEET17 SHEET18 SHEET19 SHEET01 SHEET02 SHEET03 SHEET04 SHEET05 SHEET06 SHEET07 SHEET08 SHEET09 3 2 DESCRIPTION A REV SERIAL I/O DDR2 INTERFACE EMIF USB VIDEO JTAG,CLKS,RESET POWER/GND-pins DECOUPLING CAPS 2 Date: Size: B DATE 09/28/07 09/01/07 07/01/07 04/01/07 1 DWG NO TITLE SHEET 1 509902-0001 DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED Wednesday, January 30, 2008 Page Contents: Title: DM9000A ENET CONTROLLER ETHERNET CONNECTOR MSP430 LEDS/SWITCHED ETC I/O DAUGHTER CARD IF CORE PWR SUPPLY,MSP430 PWR SUPPLY 3V3 AND 1V8 POWER SUPPLY DDR2 MEMORY JTAG CONNECTORS NAND FLASH, SPI EEPROM, EMIF I/O DC RS232 INTERFACE SD/MMC IF - CE ATA IF VIDEO INPUT MULTIPLEXER IMAGER INTERFACE 5146 DECODER VIDEO DAUGHTER CARD IF AIC33 TITLE DM355 DM355 DM355 DM355 DM355 DM355 DM355 DM355 SCHEMATIC CONTENTS 3 1 of 26 Revision: D2 RRP RRP RRP RRP APPROVED A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C D 5 19 McBSP_DX1 19 McBSP_CLKX1 19 McBSP_FSX1 19 McBSP_DR1 19 McBSP_CLKR1 19 McBSP_FSR1 19 McBSP_CLKS1 McBSP_DX0 McBSP_CLKX0 McBSP_FSX0 McBSP_DR0 McBSP_CLKR0 McBSP_FSR0 SD0_CLK SD0_CMD SD0_DATA3 SD0_DATA2 SD0_DATA1 SD0_DATA0 14 14 14 14 14 14 24 24 24 24 24 24 SD1_CLK SD1_CMD SD1_DATA3 SD1_DATA2 SD1_DATA1 SD1_DATA0 14 14 14 14 14 14 24 UART1_TXD 24 UART1_RXD 13 UART0_RXD 13 UART0_TXD 15,18,19,22,24 I2C_SCLK 15,18,19,22,24 I2C_DATA 5 R14 McBSP_DX1 McBSP_CLKX1 McBSP_FSX1 McBSP_DR1 McBSP_CLKR1 McBSP_FSR1 McBSP_CLKS1 4 RPACK8-33 1 2 3 4 5 6 7 8 RN9 16 15 14 13 12 11 10 9 McBSP_DX0 McBSP_CLKX0 McBSP_FSX0 McBSP_DR0 McBSP_CLKR0 McBSP_FSR0 RPACK8-33 16 CPU_GIO30 15 CPU_GIO29 14 CPU_GIO28 13 CPU_GIO27 12 CPU_GIO26 11 CPU_GIO25 10 9 C18 D19 E16 C19 D18 E17 D17 H15 F18 G17 E18 F17 F16 A15 C14 A14 B13 D14 B14 SD0_CLK SD0_CMD SD0_DATA3 SD0_DATA2 SD0_DATA1 SD0_DATA0 RN21 1 2 3 4 5 6 7 8 C15 A17 B16 A16 B15 A18 SD1_CLK SD1_CMD SD1_DATA3 SD1_DATA2 SD1_DATA1 SD1_DATA0 R17 R15 U18 T18 R13 I2C_SCLK R115 2.2K I2C_DATA R135 2.2K VCC_3V3 4 ASP1_DX ASP1_CLKX ASP1_FSX ASP1_DR ASP1_CLKR ASP1_FSR ASP1_CLKS ASP0_DX/GIO30 ASP0_CLKX/GIO29 ASP0_FSX/GIO28 ASP0_DR/GIO27 ASP0_CLKR/GIO26 ASP0_FSR/GIO25 MS/SD0_CLK MS_BS/SD0_CMD MS/SD0_DAT3 MS/SD0_DAT2 MS/SD0_DAT1 MS/SD0_DAT0 SD1_CLK / GIO24 SD1_CMD / GIO23 SD1_D3 / RTS2 / GIO22 SD1_D2 / CTS2 / GIO21 SD1_D1 / RXD2 / GIO20 SD1_D0 / TXD2 / GIO19 UART1_TXD1/GIO012 UART1_RXD1/GIO013 UART0_RXD0 UART0_TXD0 I2C_SCL / GIO14 I2C_SDA / GIO15 U18-1 3 3 DM355_65MM GIO0 GIO1 GIO2 GIO3 GIO4 GIO5 GIO6 GIO7 SPI0_SDENA0 SPI0_SCLK SPI0_SDI SPI0_SDO SPI1_SDENA / GIO11 SPI1_SCLK / GIO10 SPI1_SDI / GIO9 SPI1_SDO / GIO8 C16 E14 F15 G15 B17 D15 B18 C17 B12 C12 A12 B11 E13 C13 A13 E12 RN23 1 2 3 4 2 RN22 1 2 3 4 2 RPACK4-33 8 7 6 5 RPACK4-33 8 7 6 5 Date: Size: B DWG NO 1 509902-0001 DM355 SERIAL I/O DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED Friday, March 14, 2008 Page Contents: Title: DEEPSLP_EN 22 ENET_INT 20 USB_ID_TOGGLE 5 DM350_TIMERIN3 24 ATA_CE_IO 14 MSP430_INT 22 DM350_GIO6 18 DM350_GIO7 18 SPI0_SDENA0 12 SPI0_SCLK 12 SPI0_SDI 12 SPI0_SDO 12 SPI1_SDENA0 24 SPI1_SCLK 24 SPI1_SDI 24 SPI1_SDO 24 1 2 of 26 Revision: D A B C D Spectrum Digital, Inc A-3 A-4 A B C W12 U12 T11 DDR_DQ5 DDR_DQ4 DDR_DQ3 DDR_GATE0 DDR_GATE1 DDR_DQS1 DDR_DQS0 DDR_DQM1 DDR_DQM0 DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 U18-4 5 4 This net is equal to the DDR_CLKP ( or DDR_CLKN ) plus the length of DDR_DQXX Average Trace length Trace to DDR memory for delay compensation W18 DDR_STRBEN V15 V12 V17 DDR_DQS1 DDR_DQS0 U15 V13 DDR_DQ6 DDR_DQM1 W13 DDR_DQ7 T12 U13 DDR_DQ8 DDR_DQM0 V14 DDR_DQ9 V11 W14 DDR_DQ10 U11 W15 DDR_DQ11 W11 U16 DDR_DQ12 DDR_DQ0 W16 DDR_DQ13 DDR_DQ1 V16 DDR_DQ14 DDR_DQ2 W17 DDR_DQ15 DDR_STRBEN_DEL 10 DDR_DQS1 10 DDR_DQS0 10 DDR_DQM1 10 DDR_DQM0 10 DDR_DQ0 10 DDR_DQ1 10 DDR_DQ2 10 DDR_DQ3 10 DDR_DQ4 10 DDR_DQ5 10 DDR_DQ6 10 DDR_DQ7 10 DDR_DQ8 10 DDR_DQ9 10 DDR_DQ10 10 DDR_DQ11 10 DDR_DQ12 10 DDR_DQ13 10 DDR_DQ14 10 DDR_DQ15 4 DM355_65MM DDR_VREF VSSA_DLL DDR_ZN VDDA33DDR_DLL DDR_CLKN DDR_CLKP DDR_CKE DDR_CS DDR_WE DDR_CAS DDR_RAS DDR_BA2 DDR_BA1 DDR_BA0 DDR_A13 DDR_A12 DDR_A11 DDR_A10 DDR_A9 DDR_A8 DDR_A7 DDR_A6 DDR_A5 DDR_A4 DDR_A3 DDR_A2 DDR_A1 DDR_A0 U10 R11 T9 R10 W8 W9 V10 T8 W10 V9 T6 V8 U7 U8 U6 V7 W7 V6 W6 W5 V5 U5 W4 V4 W3 W2 V3 V2 3 VREF_STL 3 50 OHM 0.5% DDR_CLKN DDR_CLKP DD R_CKE DDR_ CS DDR_WE DD R_CAS DD R_RAS DDR_BA2 DDR_BA1 DDR_BA0 DDR_A13 DDR_A12 DDR_A11 DDR_A10 DDR_A9 DDR_A8 DDR_A7 DDR_A6 DDR_A5 DDR_A4 DDR_A3 DDR_A2 DDR_A1 DDR_A0 10 R3 R2 DDR_CLKN 10 VREF_STL 0 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 DDR_CLKP 10 DDR_CKE DDR_CS DDR_WE DDR_CAS DDR_RAS DDR_BA2 DDR_BA1 DDR_BA0 DDR_A13 DDR_A12 DDR_A11 DDR_A10 DDR_A9 DDR_A8 DDR_A7 DDR_A6 DDR_A5 DDR_A4 DDR_A3 DDR_A2 DDR_A1 DDR_A0 2 C3 0.01uF 0.020 2 2 TP1 1 R1 VCC_3V3 Friday, March 14, 2008 1 509902-0001 DM355 DDR INTERFACE DWG NO DM355 Evaluation Module Size: B Date: 1 Sheet SPECTRUM DIGITAL INCORPORATED C1 2.2uF Page Contents: Title: C2 0.01uF E1 NFM2012P13C105F 1 3 2 D 5 3 of 26 Revision: D A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C D EM_WAIT EM_D[15..0] RN16 8 7 6 5 EM_D7 EM_D6 EM_D5 EM_D4 RN17 8 7 6 5 RN15 8 7 6 5 EM_D11 EM_D10 EM_D9 EM_D8 EM_D3 EM_D2 EM_D1 EM_D0 RN14 8 7 6 5 EM_D15 EM_D14 EM_D13 EM_D12 33 RPACK4-33 RPACK4-33 1 2 3 4 1 2 3 4 RPACK4-33 1 2 3 4 RPACK4-33 1 2 3 4 R96 OFF ON OFF OFF OFF ON ON POS 1 ON 5 1 1 1 0 0 1 0 0 HW CODE BOOT ROM - LOAD FROM UART BOOT ROM - LOAD FROM SD/MMC NOT AVAILABLE BOOT ROM - NAND LOAD FROM CE0 Boot Select Setting for ARM Boot Mode: POS 2 SW7 Note: ICE PICK Mode may have an issue booting from Reset EMU0 = 1, EMU1 = 1 use ARM Mode EMU0 = 0, EMU1 = 0 See page 11 for more information 12,20 EM_D[15..0] 12 R97 10K VCC_3V3 4 H18 J17 H19 J18 L15 J19 K17 K19 L16 K18 L19 L17 L18 M15 M19 M18 G18 4 U18-3 EM_A1 / ALE 3 DM355_65MM EM_CE0 / GIO037 EM_CE1 / GIO036 EM_WE / GIO035 EM_OE / GIO034 EM_CLK / GIO031 EM_ADV / GIO032 EM_BA1 / GIO055 EM_A00 / GIO056 EM_D00 / GIO038 EM_D01 / GIO039 EM_A2 /CLE EM_A03 / GIO057 EM_A04 / GIO058 EM_A05 / GIO059 EM_A06 / GIO060 EM_A07 / GIO061 EM_A08 / GIO62 / CFG0 EM_A09 / GIO63 / CFG1 EM_A10 / GIO64 / CFG2 EM_A11 / GIO65 / CFG3 EM_A12 / GIO66 / BTSEL0 EM_A13 / GIO67 / BTSEL1 EM_BA0 / GIO054 / EM_A14 EM_D02 / GIO040 EM_D03 / GIO041 EM_D04 / GIO042 EM_D05 / GIO043 EM_D06 / GIO044 EM_D07 / GIO045 EM_D08 / GIO046 EM_D09 / GIO047 EM_D10 / GIO048 EM_D11 / GIO049 EM_D12 / GIO050 EM_D13 / GIO051 EM_D14 / GIO052 EM_D15 / GIO053 EM_WAIT / GIO033 3 J16 G19 J15 F19 E19 H16 P19 M16 N17 N15 N18 P15 R19 P18 P16 T19 P17 R18 R16 U19 V19 N19 RN18 1 2 3 4 RN13 4 3 2 1 RN12 4 3 2 1 RN11 4 3 2 1 RN10 4 3 2 1 1 2 3 4 8 7 6 5 12 RPACK4-33 RN19 2 TP43 GIO61 ENET_CE EM_CE0 1 12 12 12,20 12,20 12 12 12 20 12 12 12 12 12 12 12 12 12 12 12 12 2 1 Date: Size:B SN74LVC1G08 4 C249 0.1uF U19 20 12 1 R16 NO-POP 1 0 R17 NO-POP R149 20K ON SW7 2 1 1 2 1 1 509902-0001 Friday, March 14, 2008 DWG NO DM355 EMIF DM355 Evaluation Module R19 NO-POP R151 10K R14 1K Sheet 4 of NAND BOOT STATUS LED 26 Revision: C DS22 R15 1K R152 10K R225 330 VCC_3V3 NAND CFG R18 1K R150 20K DIP_SWITCH_2 4 3 R12 10K VCC_3V3 VCC_3V3 R10 10K VCC_3V3 1 SPECTRUM DIGITAL INCORPORATED VCC_3V3 ENET_CE EM_CE0 GIO62 GIO63 GIO64 GIO65 EM_A12 GIO67 Page Contents: Title: R230 10K VCC_3V3 GIO032 GIO31 EM_OE EM_WE EM_A2 EM_A1 GIO56 EM_BA1 GIO60 GIO59 GIO58 GIO57 GIO64 GIO63 GIO62 GIO61 GIO54 GIO67 EM_A12 GIO65 R229 10K VCC_3V3 RPACK4-33 GIO032 8 GIO31 7 EM_OE 6 EM_WE 5 RPACK4-33 EM_A2 5 EM_A1 6 GIO56 7 EM_BA1 8 RPACK4-33 GIO60 5 GIO59 6 GIO58 7 GIO57 8 RPACK4-33 GIO64 5 GIO63 6 GIO62 7 GIO61 8 RPACK4-33 GIO54 5 GIO67 6 EM_A12 7 GIO65 8 2 5 3 5 A B C D Spectrum Digital, Inc A-5 A B C U18-7 J1 K1 M1 L1 C8 R189 R440 0 R214 10K R93 100 R92 100 DIFFERENTIAL PAIRS 9 10 5 6 7 LBI SYNC PGND1 PGND2 PGND3 VBAT ENABLE SW1 SW2 U24 4 HEADER 13 12 2 14 1 16 15 TPS61092RSA GND1 LBO NC FB OUT1 OUT2 OUT3 3 R213 NO-POP R193 NO-POP + R192 C627 100uF VCC_3V3 R191 10K R212 NO-POP R113 C618 1uF 10K R13 10K R194 0 2 1 2 1 2 2 4 6 8 J13 + DWG NO 1 509902-0001 Friday, March 14, 2008 DM355 USB Size: B DM355 Evaluation Module Page Contents: Date: 1 2 3 4 5 5 VBUS DD+ ID GND J5 Sheet SPECTRUM DIGITAL INCORPORATED SPARE JUMPERS 1 3 5 7 R188 100K L72 miniAB BLM21PG221SN1 USB_VBUS_CONN USB_DM USB_DP USB_ID C241 100uF HEADER 4X2 HEADER 2 J9 USB_VBUS Title: HEADER 2 J10 C240 + 6.8uF Q4 BSS138 R11 1K Q3 BSS138 VCC_3V3 R190 10K 10K C160 1uF Q1 IRLML6401 1 L67 4 2 USB_ID_TOGGLE 1 2 3 4 0 8 11 3 4 DIFFERENTIAL PAIR 90 OHM DIFFERENTIAL IMPEDANCE SHORT AND STRAIGHT AS POSSIBLE, MINIMUM NUMBER OF VIAS J35 NO-POP FOR TEST SPECTRUM DIGITAL TEST ONLY 10K 1% R227 7.3uH R216 10K PLACE THESE RESISTORS CLOSE TO DM355 A6 C7 USB_ID USB_DP D5 USB_DM DRV_VBUS C5 A7 USB_VBUS E5 C159 NO-POP + USB_VBUS_PWR 2 BLM21PG221SN1 5 DM355_65MM RSV01 RSV02 RSV04 RSV03 VSS_USB_REF USB_R1 USB_ID USB_DM USB_DP USB_DRVVBUS USB_VBUS USE INTERNAL CONTROL REGISTER TO FLIP DM/DP POLARITIES C239 10uF L15 3 D VCC_5V PWRPAD 17 S G D 4 S1 S2 S3 S4 A-6 of 26 Revision: D2 6 7 8 9 5 A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C DSP_GND BLM21B050S 5 C198 0.01uF 1 R146 DSP_GND RCA JACK J4 E6 NFM21PC474R1C3D 1 3 C196 2.2uF L20 VCC_1V8 2 D 2 5 1 2 TP13 C195 270pF VDDA_DAC C194 270pF DSP_GND C197 0.01uF DSP_GND R68 4 C193 1070 1% R67 0.1uF 1000 1% 2550 1% VDIN_C0 VDIN_C1 VDIN_C2 VDIN_C3 VDIN_C4 VDIN_C5 VDIN_C6 VDIN_C7 15 15 15 15 15 15 15 15 R147 VDIN_Y0 VDIN_Y1 VDIN_Y2 VDIN_Y3 VDIN_Y4 VDIN_Y5 VDIN_Y6 VDIN_Y7 15 15 15 15 15 15 15 15 0.020 L19 3uH P5 P2 P4 R3 P3 M5 M4 L5 15 VDIN_WEN 15 VDIN_VD 15 VDIN_HD J7 F2 L8 VREF IBIAS VSSA_DAC L7 E1 G1 F1 J3 L3 J5 J4 L4 M3 K5 N3 T3 R5 R4 N5 15 VDIN_PCLK 4 DM355_65MM VSSA_DAC IBIAS VREF VDDA18_DAC IOUT VFB TVOUT CIN0 CIN1 CIN2 CIN3 SPI2_SDI/CIN4 SPI2_SEN/CIN5 SPI2_SDO/CIN6 SPI2_CLK/CIN7 YIN0 YIN1 YIN2 YIN3 YIN4 YIN5 YIN6 YIN7 GIO83/ CAM_WEN CAM_VD CAM_HD PCLK 3 3 YOUT7 YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 YOUT1 YOUT0 GIO81/PWM0/COUT7 GIO80/PWM1/COUT6 RTO0/COUT5 RTO1/COUT4 RTO2/COUT3 RTO3/COUT2 PWM3A / COUT1 PWM3B / COUT0 GIO70 / FIELD GIO71/LCD_OE VSYNC HSYNC GIO69/EXTCLK VCLK U18-6 H3 CPU_COUT7 CPU_COUT6 CPU_COUT5 CPU_COUT4 CPU_COUT3 CPU_COUT2 CPU_COUT1 CPU_COUT0 CPU_YOUT7 CPU_YOUT6 CPU_YOUT5 CPU_YOUT4 CPU_YOUT3 CPU_YOUT2 CPU_YOUT1 CPU_YOUT0 C2 D2 C1 D3 E3 E4 F3 F4 C3 A4 B4 B3 B2 A3 A2 B1 H4 H5 G5 F5 G3 33 0 R91 R90 2 2 1 509902-0001 Friday, March 14, 2008 DWG NO DM355 Evaluation Module DM355 VIDEO Date: Sheet 6 VDOUT_Y0 VDOUT_Y1 VDOUT_Y7 VDOUT_Y2 VDOUT_Y4 VDOUT_Y3 VDOUT_Y5 VDOUT_Y6 VDOUT_C2 VDOUT_C1 VDOUT_C0 VDOUT_C7 VDOUT_C4 VDOUT_C6 VDOUT_C5 VDOUT_C3 of 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 26 Revision: A VDOUT_HSYNC 18 VDOUT_FIELD 18 VDOUT_VSYNC 18 VDOUT_LCD_OE 18 VDOUT_EXTCLK 18 VDOUT_VCLK 18 SPECTRUM DIGITAL INCORPORATED RPACK8-33 RPACK8-33 16 15 14 13 12 11 10 9 Size: B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Page Contents: Title: RN30 RN31 CPU_YOU T0 CPU_YOU T1 CPU_YOU T7 CPU_YOU T2 CPU_YOU T4 CPU_YOU T3 CPU_YOU T5 CPU_YOU T6 1 2 3 4 5 6 7 8 RPACK4-33 8 7 6 5 CPU_COUT2 CPU_COUT1 CPU_COUT0 CPU_COUT7 CPU_COUT4 CPU_COUT6 CPU_COUT5 CPU_COUT3 RN32 1 2 3 4 1 A B C D Spectrum Digital, Inc A-7 A B C 11 ARM_RSTn 22 CPU_RESETz 5 2 1 VCC_3V3 5 A-8 3 D 5 R347 CPU_TDO 11 CPU_EMU1 11 CPU_EMU0 11 CPU_TRSTn 11 CPU_TMS 11 11 CPU_TDI 11 CPU_RTCK 11 CPU_TCK SN74LVC1G08 4 U23 C238 0.1uF 4 360 4 DM350_RESETn E7 E8 C9 D8 E9 D9 E11 E10 D11 EMU1 EMU0 TRST TMS TDO TDI RTCK TCK RESET U18-5 DM350_RESETn 22 3 3 DM355_65MM GIO016 / CLKOUT3 GIO017 /CLKOUT2 GIO018 / CLKOUT1 VSS_MX1 MXO1 MXI1 VSS_MX2 MXO2 MXI2 C11 A11 D12 C10 B9 A9 P1 T1 R1 R205 R204 2 2 NO-POP NO-POP GIO16 GIO17 GIO18 1 1 1 Date: Size: B C234 27 pF 27 pF 27 pF 27 pF 1 509902-0001 Friday, March 14, 2008 DWG NO DM355 JTAG,RESET,CLOCKS DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED C237 TP42 TP41 C236 C235 TP40 TP39 Page Contents: Title: 18 18 24 Y2 24MHz Y3 27MHz 1 1 7 of 26 Revision: A A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C D C171 2.2uF C146 2.2uF C189 4.7uF VCC_1V8 CPU_VDD_DDR CPU_VDD C172 4.7uF VCC_3V3 C147 4.7uF 5 C122 1.0uF 1 1 2 0.020 BLM21B050S C119 0.01uF L18 VCC_1V3 C188 1.0uF 2 CPU_VDD CPU_CVDD E2 NFM21PC474R1C3D 1 3 C120 0.01uF R30 1 4 2 TP9 CPU _VDD_DDR CPU_VDD_DDR CPU_ALT_VDD CPU_VDD 0.020 C127 2.2uF 0.020 CPU_ALT_VDD 1 TP11 2 TP12 R33 R32 R36 NO-POP 0 VCC_1V3 C170 1.0uF C145 1.0uF C187 2.2uF R34 R35 VCC_1V3 VCC_1V3 4 0.020 H8 M9 T14 P9 P10 P11 P12 P13 P14 R9 R12 F6 F7 F8 P6 P7 P8 L13 M10 M11 M12 M13 N11 N12 F10 F11 F12 F13 F14 G8 G14 K15 F9 L6 K8 A1 J11 J12 J13 K6 K11 K12 L11 L12 N6 R7 A10 R8 T17 W19 B19 C4 G6 G11 H10 H13 H17 C121 0.01uF C153 0.1uF DM355_65MM NC VDD_DDR VDD_DDR VDD_DDR VDD_DDR VDD_DDR VDD_DDR VDD_DDR VDD_DDR VDD_DDR VDD_DDR VDD_VOUT VDD_VOUT VDD_VOUT VDD_VIN VDD_VIN VDD_VIN VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD U18-2 VDDA_PLL1 VDDA_PLL2 G12 H9 CPU_CVDD VSSA_PLL2 VSSA_PLL1 J9 H12 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 VSS RSV07 RSV05 RSV07 VSSA1P3USB.1 VSSD1P3USB VDDA13_USB VDDD13_USB VSSA_3P3_USB VDDA33_USB VDDA33_USB_PLL 3 U1 K2 N2 M2 E6 D6 H7 C6 B7 J8 B6 A5 A8 G2 G9 H1 H2 H6 H11 H14 J2 J14 J6 J10 K3 K9 K10 K14 L2 L9 L10 L14 E2 D1 B10 T15 T5 T2 B5 R6 R2 N14 N9 N8 N1 M17 M14 M8 M7 A19 M6 E15 B8 U4 U9 U3 W1 V18 V1 U17 U14 U2 R26 0 2 R114 0 C157 0.001uF C154 0.1uF 2 C156 0.1uF C155 0.001uF C117 0.01uF 3 DWG NO 1 509902-0001 Wednesday, January 30, 2008 DM355 POWER DM355 Evaluation Module Size: B Date: C112 NO-POP Sheet of C111 NO-POP 8 C115 1.0uF 26 Revision: D VCC_1V8 BLM21B050S C116 1.0uF L17 VCC_1V3 1.0uF C123 VCC_3V3 VCC_1V3 C124 0.01uF SPECTRUM DIGITAL INCORPORATED R27 E3 NO-POP 1 E4 NFM21PC474R1C3D 3 1 C125 0.01uF NOT POPULATED R28 1 E5 NFM21PC474R1C3D 3 1 Page Contents: Title: 1 R31 C113 NO-POP 1 2 NO-POP 2 1 TP7 2 TP6 C118 0.01uF 0.020 C126 0.01uF 0.020 TP8 2 2 TP5 2 2 5 A B C D Spectrum Digital, Inc A-9 A-10 A B C D 5 C169 0.01uF 5 C178 0.01uF CPU_ALT_VDD C186 0.01uF CPU_VDD_DDR CPU_VDD C144 0.01uF CPU_CVDD C177 0.01uF C185 0.01uF C168 0.01uF C143 0.01uF C184 0.01uF C167 0.01uF C142 0.01uF C176 0.01uF C183 0.01uF C166 0.01uF C141 0.01uF C175 0.01uF C182 0.01uF C165 0.01uF C140 0.01uF C174 0.01uF C181 0.01uF C164 0.01uF C139 0.01uF 4 4 C173 0.01uF C180 0.01uF C163 0.01uF C138 0.01uF C179 0.01uF C152 0.01uF C137 0.01uF C21 0.01uF C151 0.01uF C136 0.01uF C20 0.01uF C150 0.01uF C135 0.01uF C149 0.01uF C134 0.01uF 3 3 C148 0.01uF C133 0.01uF C132 0.01uF C131 0.01uF C130 0.01uF C129 0.01uF 2 2 C128 0.01uF Date: Size: B DWG NO 1 509902-0001 Sheet DM350 DECOUPLING CAPACITORS DM355 Evaluation Module SPECTRUM DIGITAL INCORPORATED Wednesday, January 30, 2008 Page Contents: Title: 1 9 of 26 Revision: A A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C D 3 VREF_STL 5 C8 0.01uF C15 0.01uF C7 0.01uF VREF_STL C6 0.01uF DDR_VDD 5 R7 1K 1% R6 1K 1% DDR_VDD C10 0.01uF DDR_VDD C9 0.01uF 4 4 C11 0.01uF C12 0.01uF R8 C13 0.01uF C4 4.7uF C14 0.01uF 0 C5 2.2uF E2 G2 J2 L2 D7 E8 G8 H7 J8 L8 U9 M3 H3 D3 T1 M7 H2 D2 A1 A2 A8 A9 AA1 AA2 AA8 AA9 V3 V7 N9 M2 M1 D1 H1 V1 M9 R9 F3 K3 F9 D9 K7 F7 K1 F1 H9 K9 R5 0.020 VCC_1V8 1 U2 TP2 3 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSSDL N.C.1 N.C.2 N.C.3 N.C.4 N.C.5 N.C.6 N.C.7 N.C.8 N.C.9 N.C.10 RFU1 RFU2 ODT VREF VDDL VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 2 3 LDQS UDQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS UDQS LDM UDM CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 NC/A13 BA0 BA1 BA2 CS WE CAS RAS CK CK DDR_DQS0 DDR_DQS1 DDR_DQM0 DDR_DQM1 DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 K8 K2 L7 L3 L1 L9 J1 J9 F8 F2 G7 G3 G1 G9 E1 E9 H8 D8 DDR_CKE J7 E7 J3 E3 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_BA0 DDR_BA1 DDR_BA2 R8 R3 R7 T2 T8 T3 T7 U2 U8 U3 R2 U7 V2 V8 P2 P3 P1 N2 DDR_ CS DDR_WE DDR_CAS DDR_RAS DDR_CLKN DDR_CL KP P8 N3 P7 N7 N8 M8 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 DDR_DQ0 3 DDR_DQ1 3 DDR_DQ2 3 DDR_DQ3 3 DDR_DQ4 3 DDR_DQ5 3 DDR_DQ6 3 DDR_DQ7 3 DDR_DQ8 3 DDR_DQ9 3 DDR_DQ10 3 DDR_DQ11 3 DDR_DQ12 3 DDR_DQ13 3 DDR_DQ14 3 DDR_DQ15 3 DDR_DQS0 DDR_DQS1 DDR_DQM0 DDR_DQM1 DD R_CKE DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_BA0 DDR_BA1 DDR_BA2 DDR_ CS DDR_WE DD R_CAS DD R_RAS DDR_CLKN DDR_CLKP Friday, March 14, 2008 1 509902-0001 DWG NO Date: DDR2 MEMORY Size: B DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED Page Contents: Title: 1 10 o f 26 Revision: A A B C D Spectrum Digital, Inc A-11 MT47H64M16BT-37E A-12 A B C D 5 R39 2.2K 5 TI_EMU1 KEY 1 3 5 7 9 11 13 TSW-107-14-G-D-006 TRST TMS GND TDI nc PD GND TDO GND TCKRET GND TCK EMU1 EMU0 J6 R101 0 VCC_3V3 1 3 5 7 9 11 13 15 17 19 R103 0 4 VCC_3V3 ARM_TRSTn ARM_TDI ARM_TMS ARM_TCK ARM_TCKRET ARM_TDO ARM_RSTn TI_TMS TI_TDI TI_PWR_DECT TI_TDO TI_TCK_RET TI_TCK TI_EMU0 ARM_DEBUG_REQ ARM_DEBUG_ACK 20 PIN ARM JTAG INTERFACE SAMTEC-TSM-110-DV 2 4 6 8 10 12 14 16 18 20 J8 14 PIN TI JTAG INTERFACE 2 4 6 8 10 12 14 TI_TRSTn 4 3 3 4 5 6 CASD20TB SW1 R104 2.2K 1 2 3 R98 10K VCC_3V3 R105 2.2K R102 10K 2 2 33 33 33 R24 R25 R29 33 7 7 CPU_EMU1 7 CPU_EMU0 7 CPU_TDO 7 CPU_RTCK 7 CPU_TCK 7 CPU_TMS CPU_TDI CPU_TRSTn 7 0 1 1 1 R111 10k Date: Size: B * DEFAULT ICE PICK MODE * RESERVED RESERVED ARM MODE DWG NO 1 509902-0001 JTAG INTERFACE DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED Friday, March 14, 2008 Page Contents: Title: 1 0 FUNCTION ARM_RSTn 7 0 0 VCC_3V3 EMU0 EMU1 SWITCH CONTROLS JTAG TAP: R38 33 33 33 R22 R23 R37 33 R20 1 11 o f 26 Revision: A A B C D Spectrum Digital, Inc DM355 EVM Technical Reference B_ARM_TCKRET ARM_TCK ARM_TDO ARM_TDI ARM_TRSTn ARM_TMS A B C EM_CE0 EM_A12 4 4 5 C 6 A U4 C A 6 3 B U5 VCC_3V3 B 1 VCC_3V3 5 3 2 5 1 2 D 5 R224 C247 0.1uF EM_OE EM_WAIT R226 1GAU97TYPE5 4 C248 0.1uF 1GAU97TYPE7 4 4,20 4 0 0 4 4 GIO54 GIO65 GIO63 GIO62 GIO60 GIO58 GIO56 4 4 4 4 4 4 4 VCC_3V3 C18 0.1uF VCC_3V3 10K R21 10K VCC_3V3 NAND_CLE NAND_ALE EM_WE VCC HOLD SCK SI 8 7 6 5 1 2 3 4 5 6 NAND_RB 7 8 9 10 11 12 0 13 14 15 16 17 18 19 20 21 22 23 24 1 3 5 7 9 11 13 15 17 19 DC7 2 4 6 8 10 12 14 16 18 20 AT25640AN-10SU-2.7 CS SO WP GND U65 R9 10 K VCC_3V3 1 2 3 4 0 0 R107 3 3 SMT RECPTACLE 10X2 R159 R158 NAND_RE NANDCE NANDCE2 R162 10 K VCC_3V3 EM_A2 EM_A1 EM_WE R310 VCC_3V3 2 SPI0_SDENA0 2 SPI0_SDI 4 4 4,20 R161 10 K VCC_3V3 10K 1 1 VCC_3V3 R309 TP10 TP14 GIO61 GIO59 GIO57 GIO032 GIO31 GIO64 GIO67 SPI0_SCLK 2 SPI0_SDO 2 0.1uF C366 VCC_3V3 SOCKET48 XU3 MT29F16G08FAAWC:A NC.1 NC.2 NC.3 NC.4 NC.5 R/B2n R/Bn RE CE CE2 NC.11 VCC.1 VSS.1 NC.14 NC.15 CLE ALE WE WP NC.20 NC.21 NC.22 NC.23 NC.24 U3 4 4 4 4 4 4 4 2 DNU.48 NC.47 NC.46 NC.45 I/O7 I/O6 I/O5 I/O4 NC.40 NC.39 DNU/VSS VCC.2 VSS.2 NC.35 NC.34 NC.33 I/O3 I/O2 I/O1 I/O0 NC.28 NC.27 DNU.26 DNU.25 2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 EM_D3 EM_D2 EM_D1 EM_D0 R106 EM_D7 EM_D6 EM_D5 EM_D4 Date: Size: B 1 EM_D[15..0] 4,20 DWG NO 1 509902-0001 Sheet 12 o f NAND FLASH, SPI EEPROM, EMIF I/O DC DM355 Evaluation Module SPECTRUM DIGITAL INCORPORATED C17 2.2uF VCC_3V3 C16 0.1uF Friday, March 14, 2008 Page Contents: Title: 0 EM_D[15..0] 26 Revision: D2 A B C D Spectrum Digital, Inc A-13 A B C D 5 2 UART0_RXD 2 UART0_TXD C205 1uF 15 4 14 4 2 1 9 C200 10uF UART0_RXD + 11 C199 1uF VCC_3V3 UART0_TXD R165 10K 4 U34 3 V- V+ C2- C2+ INVALID R_IN T_OUT FORCEON FORCEOFF MAX3221CPWRG4 GND C1- C1+ EN R_OUT T_IN VCC 3 16 7 3 6 5 10 8 13 12 C207 1uF C206 1uF GND_E_RS232 C203 10pF C208 1 uF L61 1uH L60 1uH R164 10K VCC_3V3 GND_E_RS232 C201 10pF R163 10K VCC_3V3 C202 10pF GND_E_RS232 C204 10pF GND_E_RS232 2 2 L57 DWG NO 1 509902-0001 Friday, March 14, 2008 RS232 DM355 Evaluation Module Size:B Date: 1 Sheet SPECTRUM DIGITAL INCORPORATED GND_E_RS232 Page Contents: Title: BLM21PG221SN1D L58 BLM21PG221SN1D P4 DB9-MALE GND_E_RS232 GND_E_RS232 5 9 4 8 3 7 2 6 1 SILKSCREEN: UART B A-14 A 5 13 o f 26 Revision: A A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C 2 SD1_DATA0 2 SD1_DATA1 2 SD1_CLK 2 SD1_DATA2 2 SD1_DATA3 2 SD1_CMD 2 SD0_DATA0 2 SD0_DATA1 2 SD0_CLK 2 SD0_DATA2 2 SD0_DATA3 2 SD0_CMD 5 R127 51K R123 51K R128 51K R124 51K R129 51K R125 NO-POP R126 51K R121 NO-POP R132 51K R134 NO-POP R131 51K VCC_3V3 R119 NO-POP R120 51K VCC_3V3 R122 51K 4 R130 NO-POP R133 51K R118 NO-POP R117 51K 4 3 2 1 NC.4 IO3 IO2 IO1 IO4 IO5 IO6 NC.9 NOT POPULATED TPDE60001RSE 6 7 8 9 C28 NO-POP 4 3 2 1 NC.4 IO3 IO2 IO1 IO4 IO5 IO6 NC.9 3 9 1 2 3 4 5 6 7 8 6 WP COM INS 2 WP COM INS 10 11 12 0 0 1 2 3 4 5 6 7 8 9 10 11 12 2 J12 0.5MM CONN NO-POP MMC/SD_CARD DAT2 DAT3 CMD VSS1 VDD CLK VSS2 DAT0 DAT1 J28 MMC/SD_CARD R137 CE-ATA DRIVE CONNECTOR J27 DAT2 DAT3 CMD VSS1 VDD CLK VSS2 DAT0 DAT1 7 NOT POPULATED .1uF 10uF 9 1 2 3 4 5 6 7 8 R215 C103 + C102 VCC_3V3 .1uF C101 R136 TPDE60001RSE SD0_DATA0 SD0_DATA1 SD0_CLK SD0_DATA2 SD0_DATA3 SD0_CMD 10uF + C100 VCC_3V3 8 9 C29 NO-POP OPTIONAL ESD CLAMPING U26 VCC_3V3 SD1_DATA0 SD1_DATA1 SD1_CLK SD1_DATA2 SD1_DATA3 SD1_CMD OPTIONAL ESD CLAMPING U25 VCC_3V3 3 MH1 13 4 MH2 14 MH1 13 MH4 16 MH2 14 VCC_3V3 10 VCC GND 5 MH3 15 17 MH3 15 MH5 18 MH4 16 MH6 MH5 17 VCC_3V3 10 VCC GND 5 MH6 10 11 12 Date: Size:B DWG NO 1 509902-0001 SD/MMC CARD INTERFACE DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED SD/MMC1.INS 22 Friday, March 14, 2008 Page Contents: Title: 1 SD/MMC1.WP 22 SD/MMC0.INS 22 SD/MMC0.WP 22 R109 51K VCC_3V3 ATA_CE_IO 2 R100 0 R154 51K R108 51K VCC_3V3 VCC_3V3 R99 0 R153 51K VCC_3V3 VCC_3V3 18 D 5 14 o f 26 Revision: A A B C D Spectrum Digital, Inc A-15 A B C D TVP5146_C7 TVP5146_C6 TVP5146_C5 TVP5146_C4 TVP5146_C3 TVP5146_C2 TVP5146_C1 TVP5146_C0 16 IMAGER_GBL_SHUTTER 16 IMAGER_TRG 16 IMAGER_D11 16 IMAGER_D10 16 IMAGER_D9 16 IMAGER_D8 17 17 17 17 17 17 17 17 5 TVP5146_Y7 TVP5146_Y6 TVP5146_Y5 TVP5146_Y4 TVP5146_Y3 TVP5146_Y2 TVP5146_Y1 TVP5146_Y0 TVP5146_C7 TVP5146_C6 TVP5146_C5 TVP5146_C4 TVP5146_C3 TVP5146_C2 TVP5146_C1 TVP5146_C0 16 IMAGER_PXCLK 16 IMAGER_D7 16 IMAGER_D6 16 IMAGER_D5 16 IMAGER_D4 16 IMAGER_D3 16 IMAGER_D2 16 IMAGER_D1 16 IMAGER_D0 16 IMAGER_FRAME_VALID 16 IMAGER_LINE_VALID 17 TVP5146PCLK 17 TVP5146_Y7 17 TVP5146_Y6 17 TVP5146_Y5 17 TVP5146_Y4 17 TVP5146_Y3 17 TVP5146_Y2 17 TVP5146_Y1 17 TVP5146_Y0 17 TVP5146VSYNC 17 TVP5146HSYNC 0.1uF C110 VCC_3V3 0.1uF C108 VCC_3V3 53 51 48 46 44 42 40 37 35 33 31 29 54 52 50 47 45 43 41 39 36 34 32 30 53 51 48 46 44 42 40 37 35 33 31 29 54 52 50 47 45 43 41 39 36 34 32 30 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 U54 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 U53 4 17 VCC.1 GND.4 GND.3 GND.2 GND.1 49 38 19 8 17 VCC.1 GND.4 GND.3 GND.2 GND.1 A-16 4 49 38 19 8 5 S 1 3 5 7 10 12 14 16 20 22 24 26 28 55 56 2 4 6 9 11 13 15 18 21 23 25 27 S 1 3 5 7 10 12 14 16 20 22 24 26 28 55 56 2 4 6 9 11 13 15 18 21 23 25 27 SN74CBTLV16292DGGR NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A R218 360 DECODER_IMAGER R217 360 DECODER_IMAGER SN74CBTLV16292DGGR NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 3 3 R4 10K 6 6 6 6 6 6 6 6 VDIN_WEN 6 VDIN_C7 VDIN_C6 VDIN_C5 VDIN_C4 VDIN_C3 VDIN_C2 VDIN_C1 VDIN_C0 0.1uF C158 7 2,18,19,22,24 I2C_SCLK 8 16 12 9 4 2,18,19,22,24 I2C_DATA VCC_3V3 VDIN_PCLK 6 6 6 6 6 6 6 6 6 6 6 DECODER_IMAGER 22 VDIN_Y7 VDIN_Y6 VDIN_Y5 VDIN_Y4 VDIN_Y3 VDIN_Y2 VDIN_Y1 VDIN_Y0 VDIN_VD VDIN_HD OE A/B 1B 2B 3B 4B 1A 2A 3A 4A 15 1 3 6 10 13 2 5 11 14 2 SN74CBTLV3257 GND Vcc 4Y 3Y 2Y 1Y U1 2 R373 47K R374 47K Date: Size: B I2C_DATA_IMG 16 I2C_SCLK_IMG 16 I2C_DATA_5416 17 I2C_SCLK_5416 17 DWG NO 1 509902-0001 VIDEO INPUT MULTIPLEXER DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED R375 47K Friday, March 14, 2008 Page Contents: Title: DECODER_IMAGER R372 47K VCC_3V3 1 15 o f 26 Revision: A A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C D 15 IMAGER_D4 15 IMAGER_D6 15 IMAGER_D8 15 IMAGER_D10 15 IMAGER_D2 5 15 IMAGER_GBL_SHUTTER 15 IMAGER_TRG 15 IMAGER_D0 15 IMAGER_D1 15 IMAGER_PXCLK 15 IMAGER_FRAME_VALID 15 I2C_SCLK_IMG 15 IMAGER_LINE_VALID 5 0 0 0 R155 R157 R156 4 4 J30 J31 HEADER 13 1 2 3 4 5 6 7 8 9 10 11 12 13 HEADER 13X2 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 3 3 C190 0.01uF C191 0.1uF 10uF C192 IMAGER_VBUS IMAGER_RESET 22 I2C_DATA_IMG 15 IMAGER_D5 15 IMAGER_D7 15 IMAGER_D9 15 IMAGER_D11 15 IMAGER_D3 15 2 IMAGER_VBUS 2 VCC_5V Friday, March 14, 2008 1 509902-0001 DWG NO Date: IMAGER INTERFACE Size:B DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED Page Contents: Title: BLM41P750SPT L69 1 16 o f 26 Revision: A A B C D Spectrum Digital, Inc A-17 A B C D VCC_1V8 VCC_1V8 DEC_GND 1 1 L12 1 L10 RCA JACK J2 1.8VA_DDEC DEC_GND 2.7uH 5 2 BLM41P750SPT 1.8VD_DDEC 2 BLM41P750SPT DEC_GND C85 330pF L8 VCC_3V3 VCC_3V3 L64 C87 330pF 1 L13 1 L11 0.1uF C73 3.3VA_DDEC DEC_GND 75 R80 DEC_GND 3.3VD_DDEC 2 BLM41P750SPT .1uF C84 C67 C218 4 2K R70 NO POP R69 3.3VD_DDEC C77 DEC_GND ISOLATE GROUNDS AND CONNECT AT SINGLE LOCATION IN THE GROUND PLANE DEC_GND 0.1uF C91 NO POP R86 3.3VD_DDEC DEC_GND DEC_GND C90 0.1uF .1uF C83 DEC_GND 0.1uF DEC_GND C82 0.1uF DEC_GND 0.1uF C78 C81 DEC_GND 0.1uF 15 I2C_SCLK_5416 15 I2C_DATA_5416 22 TVP5146_RESETn 0.1uF C76 DEC_GND 0.1uF C75 0.1uF .1uF R186 75 C222 .1uF R187 75 2 BLM41P750SPT 330pF 0.1uF C74 .1uF C66 DEC_GND DEC_GND C221 330pF C223 DEC_GND 2.7uH C65 0.1uF 2.7uH 0.1uF C72 C220 680pF DEC_GND DEC_GND 2.7uH C86 680pF L9 DEC_GND 680pF L66 330pF 2.7uH C225 L65 DEC_GND 330pF 2.7uH 0.1uF C71 1.8VA_DDEC C219 L63 0.1uF C70 C224 DEC_GND DEC_GND 2 1 6 4 3 5 749181-1 0.1uF 0.1uF LUMA J11 C69 C68 3.3VD_DDEC DEC_GND 0.1uF C64 0.1uF 0.1uF 0.1uF 0.1uF 1.8VD_DDEC C63 C60 C62 C61 3.3VA_DDEC 81 23 18 17 16 9 8 7 2 1 80 28 29 34 33 35 THERMAL VI_4_A VI_3_C VI_3_B VI_3_A VI_2_C VI_2_B VI_2_A VI_1_C VI_1_B VI_1_A SCL SDA RESETB PWRDWN FSS/GPIO U9 TVP5146 XTAL2 XTAL1 INTREQ DATACLK AVID/GPIO GLCO/12CA FID/GPIO VS/VBLK/GPIO HS/CS/GPIO C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 12 3 DEC_GND 75 74 30 40 36 37 71 73 72 57 58 59 60 63 64 65 66 69 70 43 44 45 46 47 50 51 52 53 54 3.3VD_DDEC 76 PLL_A18VDD A18VDD_REF 3.3VA_DDEC 1.8VD_DDEC 11 14 25 78 CH2_A18VDD CH3_A18VDD CH4_A18VDD CH1_A18VDD 1.8VA_DDEC 3 4 5 20 21 CH1_A33VDD CH2_A33VDD CH3_A33VDD CH4_A33VDD CH2_A18GND CH3_A18GND CH4_A18GND CH1_A18GND CH1_A33GND CH2_A33GND CH3_A33GND CH4_A33GND AGND A18GND_REF PLL_A18GND 4 31 41 55 67 DVDD1 DVDD2 DVDD3 DVDD4 10 15 24 79 3 6 19 22 26 13 77 2 38 48 61 IOVDD1 IOVDD2 IOVDD3 DGND1 DGND2 DGND3 DGND4 DGND5 IOGND1 IOGND2 IOGND3 A-18 27 32 42 56 68 39 49 62 5 2 2 100K R81 R79 2.2K R78 0 33pF DWG NO 1 509902-0001 Sheet 17 o f 4.7K R72 26 Revision: A TVP5146PCLK 15 TVP5146VSYNC 15 3.3VD_DDEC TVP5146 VIDEO DECODER DM355 Evaluation Module Date: Friday, March 14, 2008 Size: B Page Contents: NO POP R74 4.7K R71 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 TVP5146HSYNC 15 TVP5146_C7 TVP5146_C6 TVP5146_C5 TVP5146_C4 TVP5146_C3 TVP5146_C2 TVP5146_C1 TVP5146_C0 TVP5146_Y7 TVP5146_Y6 TVP5146_Y5 TVP5146_Y4 TVP5146_Y3 TVP5146_Y2 TVP5146_Y1 TVP5146_Y0 SPECTRUM DIGITAL INCORPORATED C89 33pF Title: 22 3.3VD_DDEC 22 R77 22 R76 C88 14.31818mhz Y1 2K R73 TVP5146_C7 TVP5146_C6 TVP5146_C5 TVP5146_C4 TVP5146_C3 TVP5146_C2 TVP5146_C1 TVP5146_C0 TVP5146_Y7 TVP5146_Y6 TVP5146_Y5 TVP5146_Y4 TVP5146_Y3 TVP5146_Y2 TVP5146_Y1 TVP5146_Y0 R75 RN20 RPACK8-33 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 RN5 RPACK8-33 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1 A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C D 5 5 VDOUT_C0 VDOUT_C2 VDOUT_C4 VDOUT_C6 VDOUT_Y0 VDOUT_Y2 VDOUT_Y4 VDOUT_Y6 2,15,19,22,24 I2C_SCLK 2,15,19,22,24 I2C_DATA 6 6 6 6 6 VDOUT_VCLK 6 VDOUT_EXTCLK 6 6 6 6 6 VDOUT_LCD_OE 6 VDOUT_FIELD 2 DM350_GIO6 4 4 R112 10K R88 10K VCC_3V3 VCC_5V VCC_3V3 DC5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 SMT RECEPTACLE 25X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 R174 R175 3 DC6 2 4 6 8 10 SMT RECEPTACLE 5X2 1 3 5 7 9 VIDEO OUTPUT CONNECTOR 0 R177 VCC_1V8 0 R176 3 0 0 2 VCC_5V VCC_3V3 VCC_1V8 2 6 6 6 6 6 6 6 6 Friday, March 14, 2008 1 509902-0001 Sheet 18 o f DWG NO Date: THS8200 DAUGHTER CARD INTERFACE Size: B DM355 Evaluation Module SPECTRUM DIGITAL INCORPORATED Page Contents: Title: DC5_RESETn 22 VDOUT_Y1 VDOUT_Y3 VDOUT_Y5 VDOUT_Y7 VDOUT_VSYNC 6 VDOUT_HSYNC 6 VDOUT_C1 VDOUT_C3 VDOUT_C5 VDOUT_C7 GIO16 7 GIO17 7 DM350_GIO7 2 1 26 Revision: A A B C D Spectrum Digital, Inc A-19 P1 P6 GND_AIC 2 McBSP_DX1 2 McBSP_FSR1 2 McBSP_FSX1 2 McBSP_CLKR1 2 McBSP_CLKS1 2 McBSP_DR1 GND_AIC C57 .1uF R42 1 2 OUT 27Mhz GND EN C51 .1uF R48 330 VCC 10 R60 U66 10 R59 10 10 R58 10 10 R56 R62 R65 R49 10K R44 330 GND_AIC 3 4 VCC_3V3 R43 5.6K R41 5.6K C34 .1uF GND_AIC VCC_3V3 5.6K 5.6K BLM21PG221SN1D L3 R40 C33 .1uF 22 AIC33_RESETn GND_AIC R47 47K 4 2 1 3 GND_AIC 2 McBSP_CLKX1 C55 220pF Mic In 4 2 1 3 Line In L1 BLM21PG221SN1D .1uF R160 R64 10 10K NO-POP NO-POP 10K C36 .1uF 22 R63 10K TP3 TP4 .1uF GND_AIC .1uF .1uF .1uF C53 C35 .1uF C50 C52 C49 .1uF C48 220pF C47 C367 R66 20K .1uF C44 220pF C43 C32 10uF R52 R53 R54 R55 + 0 0 G8 G9 F9 E9 F8 E8 B8 B9 A8 A9 H8 A2 A1 B3 B2 A4 B5 B4 A3 2,15,18,22,24 I2C_SCLK U8 GND_AIC SCL SDA GPIO1 GPIO2 LEFT_LO+ LEFT_LORIGHT_LO+ RIGHT_LO- MONO_LO+ MONO_LO- HPLOUT HPLCOM DRVSS.1 DRVSS.2 HPRCOM HPROUT DRVDD.1 DRVDD.2 AVDD_ADC AVSS_ADC.1 AVSS_ADC.2 AVDD_DAC AVSS_DAC.1 AVSS_DAC.2 ISOLATE GROUNDS AND CONNECT AT SINGLE LOCATION IN THE GROUND PLANE TVL320AIC33IZQE MCLK BCLK WCLK DIN DOUT SELECT MFP0 MFP1 MPF2 MFP3 RESET MICBIAS MIC3R MIC3L MICDET LINE2L+ LINE2LLINE2R+ LINE2R- LINE1L+ LINE1LLINE1R+ LINE1R- DVDD IOVDD DVSS 1uF .1uF 2,15,18,22,24 I2C_DATA 1 1 R46 R45 A6 A5 B7 B6 H9 C9 D9 C46 C45 VCC_1V8 C8 D8 J9 J8 J4 J5 J6 J7 J2 J3 D1 E1 E2 F2 F1 G1 C1 H1 B1 C2 D2 J1 G2 H2 GND_AIC GND_AIC GND_AIC C56 C54 L7 10uF,6.3V C59 L6 L5 L4 C40 .1uF 10uF,6.3V C58 33uF,6.3V C39 .1uF 33uF,6.3V C38 .1uF + + + A-20 + VCC_3V3 C37 10uF P2 P3 DWG NO 509902-0001 Sheet AIC33 AUDIO INTERFACE DM355 Evaluation Module 19 o f Line Out 3 1 2 4 Headphone Out 3 1 2 4 SPECTRUM DIGITAL INCORPORATED GND_AIC R51 20K R57 20K GND_AIC R61 20K GND_AIC R50 20K GND_AIC .1uF C42 VCC_3V3 BLM21PG221SN1D Date: Friday, March 14, 2008 Size:B Page Contents: Title: GND_AIC BLM21PG221SN1D BLM21PG221SN1D BLM21PG221SN1D GND_AIC C41 .1uF BLM21PG221SN1D GND_AIC + L2 26 Revision: A Spectrum Digital, Inc DM355 EVM Technical Reference A B C D 4,12 EM_D[15..0] EM_BA1 5 2 ENET_INT 4,12 EM_OE 4,12 EM_WE 4 EM_D[15..0] R201 10K C231 .1uF ENET_D15 ENET_D14 ENET_D13 ENET_D12 ENET_D11 ENET_D10 ENET_D9 ENET_D8 ENET_D7 ENET_D6 ENET_D5 ENET_D4 ENET_D3 ENET_D2 ENET_D1 ENET_D0 C24 .1uF EM_BA1 C232 .1uF RPACK8-33 16 15 14 13 12 11 10 9 RPACK8-33 16 15 14 13 12 11 10 9 VCC_3V3 RN25 1 2 3 4 5 6 7 8 RN24 1 2 3 4 5 6 7 8 4 ENET_CE 22 ENET_RESETz EM_D15 EM_D14 EM_D13 EM_D12 EM_D11 EM_D10 EM_D9 EM_D8 EM_D7 EM_D6 EM_D5 EM_D4 EM_D3 EM_D2 EM_D1 EM_D0 4 C25 .1uF 4 VCC_3V3 25 26 27 28 29 30 31 32 33 34 35 36 SD13 SD12 SD11 SD10 SD9 DVDD SD8 CMD DGND INT IOR# IOW# 3 24 23 22 21 20 19 18 17 16 15 14 13 SD14 VDD SD15 EECS EECK EEDI0 SD0 SD1 SD2 DGND SD3 SD4 CSn LED2 LED1 PW_RST# TEST DVDD X2 X1 DGND SD RX_GND BGGND R203 10K 3 37 38 39 40 41 42 43 44 45 46 47 48 5 22 pF 22 pF 6.8K 1% C233 Y4 25MHz C230 R202 SD5 SD6 SD7 TX_VDD_2V5 TXOTXO+ TXGND RXGND RXIRXI+ RXVDD_2V5 BGRES 12 11 10 9 8 7 6 5 4 3 2 1 U22 DM9000A-QFP48 ENET-AGND C227 .1uF 2 U21 VCC DC ORG GND 8 7 6 5 BLM41PG750SN1L L68 ENET-AGND DWG NO Friday, March 14, 2008 1 509902-0001 Ethernet Interface Size:B DM355 Evaluation Module Page Contents: Date: 4.7K VCC_3V3 C226 .1uF Sheet 20 o f 26 Revision: A ENET_2V5 IS DM9000A INTERNALLY GENERATED POWER SUPPLY R197 1 SPECTRUM DIGITAL INCORPORATED ENET_RXI- 21 ENET_RXI+ 21 ENET_2V5 AT93C46-10TI-2.7 CS SK DI DO ENET_TXO- 21 ENET_TXO+ 21 Title: C229 100uF ENET-AGND + 1 2 3 1K 4 DIFFERENTIAL PAIRS R200 NO-POP R198 R196 NO-POP ENET_LED1 21 ENET_LED2 21 C228 .1uF R199 NO-POP R195 NO-POP VCC_3V3 2 A B C D Spectrum Digital, Inc A-21 A B C 5 20 ENET_LED1 20 ENET_LED2 4 4 20 ENET_RXI- 20 ENET_RXI+ 20 ENET_TXO- 20 ENET_TXO+ R184 49.9 R182 49.9 0.1uF 3 R180 R181 R185 49.9 R183 49.9 360 360 0.1uF C216 ENET-AGND 2 2 VCC_3V3 GND_E_ENET EPHY_LED1 EPHY_LED2 1000pF 2kV C215 ENET-AGND 0.1uF C214 ENET_2V5 ENET-AGND ENET-AGND 0.1uF C213 C217 ENET-AGND 3 3 5 6 1 4 2 7 8 12 11 10 9 P5 RJ45 HALO HFJ11-2450E-L21 Date: Size: B 1 1 509902-0001 Friday, March 14, 2008 DWG NO ETHERNET OUTPUT DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED GND_E_ENET Page Contents: Title: RXD+ RXD-CT RXD- TXD+ TXD-CT TXD- NC1 GND LED2LED2+ LED1LED1+ S1 S0 A-22 13 14 D 5 21 o f 26 Revision: A A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C D TSOP34840 C93 + 10uF 6.3V R83 100 U10 5 C99 0.1uF C22 NO-POP 3 1 2 BA2032SM BHT1 R208 R207 R206 DM350_RESETn SD/MMC0.WP SD/MMC0.INS SD/MMC1.WP SD/MMC1.INS 23 23 23 23 23 PB_SW10 PB_SW11 PB_SW12 PB_SW13 PB_SW14 MSP_AGND MSP_AGND 4 R211 1K MSP_AGND R110 NO-POP R210 1K + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MSP430_3V3 MSP_AGND DVCC.1 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT VEREF+ VREF-/VEREFP1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK U15 MSP430_AVCC 0.1uF C96 MSP430_3V3 C94 10uF 6.3V MSP430_RESETz MSP430_3V3 4 MSP_AGND R84 47K R209 1K NO-POP 2,15,18,19,24 I2C_DATA 2,15,18,19,24 I2C_SCLK R85 100K 7 14 14 14 14 VCC_3V3 R82 10K 100 100 1K 23 PB_RESETn C104 10uF 6.3V MSP430_3V3 + VCC_1V3 VCC_1V8 VCC_3V3 R89 BLM41P750SPT L14 C95 .1uF 25 ALT_MSP430_RESETz C92 .1uF C19 NO-POP Y5 32.768KHz 2 1 1 2 D2 BAT17 D1 BAT17 5 3 430_TCK 430_TMS 430_TDI 430_TDO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH.SVSOUT P5.6/ACLK P5.5/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6/ADC12C/DMAE0 P2.7/TA0 P3.0/STE0 P3.1/SIMO0/SDA P3.2/SOMI0 P3.3/UCLK0/SCL P3.4/UTXD0 3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4 P5.4/MCLK P5.3 P5.2 P5.1 P5.0 P4.7/TBCLK P4.6 P4.5 P4.4 P4.3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7 P3.6 P3.5/URXD0 1 ALT_3V3 C26 C23 18pF 18pF MSP430F155IPW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Y6 8MHz 9 10 11 12 13 14 15 16 2 J3 L70 MSP_AGND Date: Friday, March 14, 2008 1 509902-0001 MSP430 & IR INTERFACE DWG NO Size: B DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED TVP5146_RESETn 17 DC5_RESETn 18 AIC33_RESETn 19 CPU_RESETz 7 IMAGER_RESET 16 MSP_AGND MSP430_3V3 22 o f 26 Revision: C MSP430_3V3 BLM41P750SPT L71 14 12 10 8 6 4 2 C98 10uF 6.3V BLM41P750SPT MSP_AGND 0.1uF C97 + HEADER 7X2 NC1 TCLKEN RST/NMI ACLKEN GND ACLK TCK TEST/VPP TMS XOUT TDI/VPP VCC_MSP TDO/TDI NC2 MSP430_AVCC 13 11 9 7 5 3 1 1 Page Contents: Title: RPACK8-10K LED7 23 LED6 23 LED5 23 LED4 23 LED3 23 LED2 23 LED1 23 LED0 23 DECODER_IMAGER 15 MSP430_3V3_ENABLE 26 MSP430_1V8_ENABLE 26 MSP430_1V3_ENABLE 25 SYS_RESETz 24 ENET_RESETz 20 DEEPSLP_EN 2 RN29 8 7 6 5 4 3 2 1 430_TCK 430_TMS 430_TDI 430_TDO MSP430_RESETz NTSC_PAL 23 SW_DIP3 23 SW_DIP2 23 SW_DIP1 23 SW_DIP0 23 R228 10K ALT_3V3 MSP430_INT 2 2 A B C D Spectrum Digital, Inc A-23 A B C SW_DIP0 SW_DIP1 SW_DIP2 SW_DIP3 22 22 22 22 A AA LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 22 22 22 22 22 22 22 22 B BB 5 PUSHBUTTON SW SW5 33 R166 330 R346 LED DS14 ALT_3V3 1uF C368 R345 10K ALT_3V3 LED DS15 R167 330 LED DS16 R168 330 4 8 7 6 5 A-24 1 2 3 4 HEADER 3 J1 1 2 3 4 D 5 1 2 3 4 R314 ALT_3V3 RN27 RPACK4-10K LED LED ON 8 7 6 5 PAL 0 NTSC DIP_SWITCH-4 4 2 3 1 SW6 DS18 R170 330 DS17 R169 330 3 R173 330 LED DS21 ALT_3V3 RPACK4-1K 1 2 3 4 LED DS20 R172 330 NTSC_PAL 22 RN26 8 7 6 5 PB_RESETn 22 LED DS19 R171 330 3 A AA A AA A AA A AA A AA B BB B BB B BB B BB B BB 2 PUSHBUTTON SW SW14 PUSHBUTTON SW SW13 PUSHBUTTON SW SW12 PUSHBUTTON SW SW11 PUSHBUTTON SW SW10 2 Date: Size: B 1 PB_SW14 PB_SW13 PB_SW12 PB_SW11 PB_SW10 DWG NO 1 509902-0001 SWITCHES, LEDS ETC DM355 Evaluation Module Sheet SPECTRUM DIGITAL INCORPORATED Friday, March 14, 2008 Page Contents: Title: 1uF C246 R223 10K ALT_3V3 1uF C245 R222 10K ALT_3V3 1uF C244 R221 10K ALT_3V3 1uF C243 R220 10K ALT_3V3 1uF C242 R219 10K ALT_3V3 23 o f 22 22 22 22 22 26 Revision: A A B C D Spectrum Digital, Inc DM355 EVM Technical Reference 4 3 VCC_1V8 VCC_3V3 McBSP_DX0 McBSP_CLKX0 McBSP_FSX0 GIO18 7 2 I2C_SCLK 2,15,18,19,22 I2C_DATA 2,15,18,19,22 McBSP_DX0 2 McBSP_CLKX0 2 McBSP_FSX0 2 SPI1_SDO 2 DM350_TIMERIN3 2 Title: SPECTRUM DIGITAL INCORPORATED 1 24 o f Revision: A D A Friday, March 14, 2008 1 509902-0001 Sheet DWG NO Size:B Date: I/O DAUGHTER CARD INTERFACE Page Contents: DM355 Evaluation Module 26 A B 5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 SMT RECPTACLE 15X2 DC3 2 B VCC_5V VCC_3V3 McBSP_DR0 McBSP_CLKR0 McBSP_FSR0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 3 C 22 SYS_RESETz 2 UART1_TXD 2 UART1_RXD 2 McBSP_DR0 2 McBSP_CLKR0 2 McBSP_FSR0 2 SPI1_SDENA0 2 SPI1_SDI 2 SPI1_SCLK 4 C D 5 Spectrum Digital, Inc A-25 A B C VCC_5V VCC_5V L49 0.1uF C314 BLM41P750SPT C320 0.1uF 0 R349 + 5 BLM41P750SPT L62 0.1uF C211 + C321 0.039uF C315 10uF LESR C209 10uF EMI SUPPRESION. LOCATE NEAR EACH REGULATOR. 6 VIAS FROM PAD TO PLANE OR DIRECT TIE. R95 10K MSP430_1V3_ENABLE 1 2 D 22 MSP430_1V3_ENABLE 1 2 0.1uF C212 0.1uF C322 71.5K 1% R275 13 12 11 16 15 14 21 20 19 18 17 SENSE RESET OUT OUT 6 7 8 9 10 TPS7301QDRG4 GND EN IN IN U20 PH1 PH2 PH3 PH4 PH5 1 2 3 4 5 7 8 6 5 0.047uF C318 C316 560pF 2.7 uH C313 0.01uF R274 R276 1.65K 1% 22.1K 1% 4 R1503 = 346K Vout = 3.6 volts Vref = 1.182 Volts Vout = Vref * ( 1 + R1503/R1504) 1 2 4 3 TPS54310PWP 101338-0001 PGND3 PGND2 PGND1 VIN3 VIN2 VIN1 AGND VSENSE COMP PWRGD BOOT AGND 3.3 sq in AGND, min thermal pad POWERPAD RT SYNC SS/ENA VBIAS U55 Connect at pin 1 4 L50 3 17.4K 22.1K 28.0K 42.2K 1000pF C324 R179 169K 1% + C210 10uF ALT_3V3 100uF 4V C323 C317 1% 1% 1% 1% 10K 1% R178 348K 1% + -> -> -> -> 3300pF 1.4V 1.3V 1.2V 1.1V 3 1 A-26 2 5 R279 0.025 R277 TP23 TP-60 R280 ALT_MSP430_RESETz 22 TP22 TP-60 107 1% 2 2 + 1 00 uF C325 VCC_1V3 10K Date: Size:B TP27 TP-60 TP28 TP-60 GND Test Points TP26 TP-60 TP21 TP-30 TP29 TP-60 TP30 TP-60 DWG NO 1 509902-0001 Sheet 25 o f 26 Revision: A POWER SUPPLY MSP430_3V3, DSP CORE( 1V3) DM355 Evaluation Module SPECTRUM DIGITAL INCORPORATED TP25 TP-60 CORE_PWR_OK Friday, March 14, 2008 Page Contents: Title: NO-POP C319 R278 VCC_5V 1 A B C D Spectrum Digital, Inc DM355 EVM Technical Reference A B C D CENTER SHUNT SLEEVE NO-POP 1 F1 R316 2 D3 SMCJ6A F_4.0A VCC_5V R94 10K 5 C340 47uF L53 BLM41P750SPT C354 0.1uF 0 R439 + VCC_5V GREEN DS5 R299 220 TP31 TP-30 R87 10K EMI SUPPRESION. LOCATE NEAR EACH REGULATOR. 6 VIAS FROM PAD TO PLANE OR DIRECT TIE. 22 MSP430_1V8_ENABLE 2.5 MM JACK RASM712 J16 SILKSCREEN: 5V IN 22 MSP430_3V3_ENABLE L51 4 71.5K 1% R301 0.1uF C356 0.039uF 0.1uF C355 10uF LESR C349 C348 + 0.1uF C339 71.5K 1% R294 13 12 11 16 15 14 21 20 19 18 17 AGND TPS54310PWP 101338-0001 PGND3 PGND2 PGND1 VIN3 VIN2 VIN1 PH1 PH2 PH3 PH4 PH5 AGND VSENSE COMP PWRGD BOOT 3.3 sq in AGND, min thermal pad POWERPAD RT SYNC SS/ENA VBIAS U59 Connect at pin 1 3 13 12 11 16 15 14 21 20 19 18 17 AGND 3.3 sq in AGND, min thermal pad TPS54310PWP 101338-0001 POWERPAD RT AGND SYNC VSENSE SS/ENA COMP VBIAS PWRGD BOOT VIN3 VIN2 VIN1 PH1 PH2 PGND3 PH3 PGND2 PH4 PGND1 PH5 U60 Connect at pin 1 3 6 7 8 9 10 1 2 3 4 5 EMI SUPPRESION. LOCATE NEAR EACH REGULATOR. 6 VIAS FROM PAD TO PLANE OR DIRECT TIE. 10uF LESR C342 0.039uF 0.1uF + C334 C333 BLM41P750SPT C341 0.1uF 0 R393 4 C352 C350 470pF 2.7 uH L52 L54 + + 100uF 4V R296 R297 2 10K 1% R303 1000pF C344 1000pF C358 3300pF 100uF 4V C343 R305 C357 C351 Sets Voltage 3.3 uH 3300pF 10K 1% C336 Sets Voltage C332 8200pF C347 8200pF R300 10.2K 1% C337 R302 2K 1% 0.047uF 0.047uF 6 7 8 9 10 1 2 3 4 5 C335 470pF R293 2K 1% R291 3.74K 1% 2 + TP37 TP-60 TP34 TP-60 R298 100 uF C359 DWG NO Size: B Friday, March 14, 2008 1 509902-0001 POWER SUPPLY 3V3, 1V8 Page Contents: Date: Sheet 26 o f 1V8_PWR_OK SPECTRUM DIGITAL INCORPORATED + C353 10K R304 VCC_5V NO-POP 100 uF C346 C338 10K R295 VCC_5V NO-POP DM355 Evaluation Module TP38 TP-60 R306 + VCC_3V3 VCC_1V8 3.3V @1.5Amp Max 0.025 3V3_PWR_OK 1 Title: 0.025 107 1% TP33 TP-60 107 1% 100 uF 4V C345 1 5 26 Revision: A TP36 TP-30 TP32 TP-30 A B C D Spectrum Digital, Inc A-27 Spectrum Digital, Inc A-28 DM355 EVM Technical Reference Appendix B Mechanical Information This appendix contains the mechanical information about the DM355 EVM produced by Spectrum Digital. B-1 THIS DRAWING IS NOT TO SCALE Spectrum Digital, Inc B-2 DM355 EVM Technical Reference Spectrum Digital, Inc B-3 Spectrum Digital, Inc B-4 DM355 EVM Technical Reference Printed in U.S.A., April 2008 509905-0001 Rev E Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Spectrum Digital: 702065