IGLOOe(R) Handbook IGLOOe Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I - IGLOOe Datasheet IGLOOe Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I IGLOOe Device Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 IGLOOe DC and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 Package Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Section II - User's Guide Low-Power Flash Technology and Flash*Freeze Mode FPGA Array Architecture in Low-Power Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 Actel's Flash*Freeze Technology and Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 Global Resources and Clock Conditioning Global Resources in Actel Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs . . . . . . . . . . . . . . .4-1 Embedded Memories FlashROM in Actel's Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 I/O Descriptions and Usage I/O Structures in IGLOOe and ProASIC3E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 I/O Software Control in Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 DDR for Actel's Low-Power Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 Packaging and Pin Descriptions Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 Programming and Security Programming Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 Security in Low-Power Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 . . . . . . . . . . . . .14-1 Core Voltage Switching Circuit for IGLOO and ProASIC3L In-System Programming . . . . . . . . . . . . .15-1 Microprocessor Programming of Actel's Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . .16-1 Table of Contents Boundary Scan and UJTAG Boundary Scan in Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 UJTAG Applications in Actel's Low-Power Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1 Board-Level Requirements Power-Up/-Down Behavior of Low-Power Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1 Low-Power Flash Device Handbooks Introduction Device Handbooks contain all the information available to help designers understand and use Actel's devices. Handbook chapters are grouped into sections on the website to simplify navigation. Each chapter of the handbook can be viewed as an individual PDF file. At the top of the handbook web page, you will see a PDF file for each product family. This file contains the complete device handbook. Please register for product updates to be notified when a section of the handbook changes. Table 1 * Differences between Former Datasheets and Device Handbooks Description of Change Comparison between Handbook and Datasheet The silicon datasheet in the handbook The former version of the silicon datasheet contained the following: does not contain the same chapters as * General Description the previous versions of the datasheets. * Device Architecture * DC and Switching Characteristics * Packaging The current datasheet now contains: * Product Brief (same information as the General Description) * DC and Switching Characteristics * Packaging The information previously contained in the Device Architecture chapter has been separated into individual chapters and merged with relevant application note content to provide one location for information on each architectural feature. The Device Architecture section still exists in the Fusion Handbook only. The General Description section no The Product Brief and the General Description consisted of basically longer exists in datasheets. the same information but with different titles. To eliminate the duplicated information, we changed the document name to Product Brief. Change tables were carried forward through this process; they contain information from the old datasheets and the new datasheets. It is important that all earlier technical changes from the datasheets are listed so customers can determine if any of the changes affect their designs. Changes are listed chronologically, with the most current at the top and the earlier changes listed below them. Version numbers were restarted. The version numbers were restarted when the handbooks were created. For example, a datasheet may have been v2.1 and is now v1.0. The category (i.e., advance or production) of the datasheet did not change. The only change occurred to the actual numbering of the datasheet. All version numbers are located in the footer of the page. Publication date The publication date indicates when the document was published and posted to the Actel website. The former datasheets were two We changed the datasheet format to accommodate the large columns and the current datasheets and graphics and to improve readability. handbooks are formatted with one column. v1.2 i Low-Power Flash Device Handbooks Introduction Table 1 * Differences between Former Datasheets and Device Handbooks (continued) Description of Change Comparison between Handbook and Datasheet Each chapter within a handbook can Each chapter in the handbook has its own version number. Since the have a different version number. chapters are independent documents and can be updated at different times, the version numbers for each chapter increment only when a change is made to that chapter. For example, in the ProASIC3L handbook, the DC and Switching section is Advance v0.2, the Packaging Pin Assignments section is v1.0, and the Global Resources section is v1.1. The DC and Switching section is advance because the data has not been fully characterized. The Packaging and Global Resources chapters are both production versions because the data is final. They have different version numbers because they were updated at different times. Chapters can be numbered differently in each of the handbooks, but the version number for a chapter should be consistent throughout all handbooks. Chapters are also published individually without chapter numbers. Chapters with shared content are reused across multiple handbooks. The number of chapters in each handbook varies depending on content, so the Pin Descriptions chapter could be chapter 7 in one handbook and chapter 9 in another. This is shown only in the combined handbook version of the document. The content within the chapters and version numbers is the same across each handbook for that chapter. If the chapter is updated, it will be reposted for all associated handbooks. There are multiple versions of the I/O There are several major differences between the families regarding Structures chapter. I/O structures, so the information has been grouped by similar families. As a result, we have multiple I/O Structures chapters to describe the features for each group of families in detail. The part number of the datasheet has Part numbers are used internally to track documents. Each document changed. has its own unique part number. The number after the second dash indicates the revision of the document. For example, in the part number 51700094-006-1, 51700094-006 is the part number and 1 is the revision of the document. We start with 0 for all new documents. There is a part number for the current version of the datasheet on the back page with the addresses. In addition, all chapters in the datasheet and handbooks have their own unique part numbers. When we implemented the current handbook format, existing documents were assigned new part numbers. The information contained in the Core Architecture section of the silicon handbook includes information previously found in application notes. ii The chapters in the silicon handbook combine application notes that previously had very detailed information about an architectural feature and information from the former datasheets. In addition, because the information was very similar among several of Actel's low-power flash devices, we combined the information into one document. The Supported Families tables describe which devices are supported in the document. The application notes that contained specific architecture information were combined into the handbook and many no longer exist as standalone application notes. Those that do exist in standalone version have been assigned an AC number (top right of first page) to help identify them. The AC number appears in the standalone version and in the handbook chapters where they occur. v1.2 Low-Power Flash Device Handbooks Introduction Table 1 * Differences between Former Datasheets and Device Handbooks (continued) Description of Change Comparison between Handbook and Datasheet The location of the following information has changed in the current handbook format: Former Datasheet Location Current Handbook Location CCC/PLL Specification Table Core Architecture DC and Switching section > Clock Conditioning Circuits Peak-to-Peak Jitter Waveform Core Architecture DC and Switching section > Clock Conditioning Circuits Versions Device handbook chapters may have different version numbers. Actel's goal is to provide customers with the latest information in a timely matter. As a result, the handbook chapters will be updated independently of the handbook. Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. v1.2 iii Low-Power Flash Device Handbooks Introduction Part Number and Revision Date Part Number 51700094-001-2 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.2) Page v1.1 (November 2008) Table 1 * Differences between Former Datasheets and Device Handbooks was revised to indicate that only the Fusion Handbook retains a Device Architecture section. The information on the I/O Structures chapters was revised, as an I/O Structures chapter has been added for nano devices. i v1.0 (January 2008) This document was rewritten to address the differences between the former datasheets and new device handbooks. N/A iv v1.2 Section I - IGLOOe Datasheet v2.0 IGLOOe Low-Power Flash FPGAs (R) with Flash*Freeze Technology Features and Benefits Low Power * * * * 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content * Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-LowPower Flash*Freeze Mode High Capacity * 600 k to 3 Million System Gates * 108 to 504 kbits of True Dual-Port SRAM * Up to 620 User I/Os Reprogrammable Flash Technology * * * * * 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance In-System Programming (ISP) and Security * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents High-Performance Routing Hierarchy * Segmented, Hierarchical Routing and Clock Structure * High-Performance, Low-Skew Global Network * Architecture Supports Ultra-High Utilization Pro (Professional) I/O * 700 Mbps DDR, LVDS-Capable I/Os * 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation * Bank-Selectable I/O Voltages--Up to 8 Banks per Chip * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input * Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS * Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II * Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V * Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V * I/O Registers on Input, Output, and Enable Paths * Hot-Swappable and Cold-Sparing I/Os * Programmable Output Slew Rate and Drive Strength * Programmable Input Delay * Schmitt Trigger Option on Single-Ended Inputs * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Packages across the IGLOO(R)e Family Clock Conditioning Circuit (CCC) and PLL * Six CCC Blocks, Each with an Integrated PLL * Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback * Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory * 1 kbit of FlashROM User Nonvolatile Memory * SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations available) * True Dual-Port SRAM (except x18) ARM Processor Support in IGLOOe FPGAs * M1 IGLOOe Devices--CortexTM-M1 Soft Processor Available with or without Debug IGLOOe Product Family IGLOOe Devices AGLE600 ARM-Enabled IGLOOe Devices AGLE3000 M1AGLE3000 System Gates 600 k 3M VersaTiles (D-flip-flops) 13,824 75,264 Quiescent Current (typical) in Flash*Freeze Mode (W) 49 137 RAM kbits (1,024 bits) 108 504 4,608-Bit Blocks 24 112 FlashROM Bits 1k 1k Secure (AES) ISP Yes Yes 6 6 18 18 8 8 270 620 FG256, FG484 FG484, FG896 CCCs with Integrated PLLs VersaNet Globals 1 I/O Banks Maximum User I/Os Package Pins FBGA Notes: 1. Refer to the Cortex-M1 Handbook for more information. 2. Six chip (main) and twelve quadrant global networks are available. 3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology handbook. November 2009 (c) 2009 Actel Corporation I I/Os Per Package 1 IGLOOe Devices AGLE600 AGLE3000 ARM-Enabled IGLOOe Devices M1AGLE3000 I/O Types Single-Ended I/O1 Differential I/O Pairs Single-Ended I/O1 Differential I/O Pairs FG256 165 79 - - FG484 270 135 341 168 FG896 - - 620 310 Package Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze Technology handbook to ensure compliance with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For AGLE3000 devices, the usage of certain I/O standards is limited as follows: - SSTL3(I) and (II): up to 40 I/Os per north or south bank - LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank - SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 4. FG256 and FG484 are footprint-compatible packages. 5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank (group of I/Os). When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one. 6. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of singleended user I/Os available is reduced by one. 7. "G" indicates RoHS-compliant packages. Refer to "IGLOOe Ordering Information" on page III for the location of the "G" in the part number. IGLOOe FPGAs Package Sizes Dimensions Package Length x Width (mm x mm) Nominal Area (mm Pitch (mm) Height (mm) II 2) FG256 FG484 FG896 17 x 17 23 x 23 31 x 31 289 529 961 1 1 1 1.6 2.23 2.23 v2.0 IGLOOe Low-Power Flash FPGAs IGLOOe Ordering Information AGLE3000 V2 _ FG G 896 I Application (Temperature Range) Blank = Commercial (0C to +70C Ambient Temperature) I = Industrial (-40C to +85C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS-Compliant Packaging Package Type FG = Fine Pitch Ball Grid Array (1.0 mm pitch) 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number IGLOOe Devices AGLE600 = 600,000 System Gates AGLE3000 = 3,000,000 System Gates IGLOOe Devices with Cortex-M1 M1AGLE3000 = 3,000,000 System Gates Note: Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly. v2.0 III Temperature Grade Offerings AGLE600 Package AGLE3000 M1AGLPE3000 FG256 C, I - FG484 C, I C, I FG896 - C, I Note: C = Commercial temperature range: 0C to 70C ambient temperature. I = Industrial temperature range: -40C to 85C ambient temperature. References made to IGLOOe devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. IV v2.0 1 - IGLOOe Device Family Overview General Description The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOOe devices enables entering and exiting an ultra-lowpower mode while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low-power consumption while the IGLOOe device is completely functional in the system. This allows the IGLOOe device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOOe devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). IGLOOe is reprogrammable and offers time-tomarket benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOOe devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on 6 integrated phase-locked loops (PLLs). IGLOOe devices have up to 3 million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620 user I/Os. M1 IGLOOe devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between low-power consumption and speed when implemented in an M1 IGLOOe device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOOe FPGAs. The ARM-enabled devices have Actel ordering numbers that begin with M1AGLE and do not support AES decryption. Flash*Freeze Technology The IGLOOe device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low-power Flash*Freeze mode. IGLOOe devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOOe V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. When the IGLOOe device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low-power modes, combined with reprogrammability, a single-chip and singlevoltage solution, and availability of small-footprint, high pin-count packages, make IGLOOe devices the best fit for portable electronics. v2.0 1-1 IGLOOe Device Family Overview Flash Advantages Low Power Flash-based IGLOOe devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOOe devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOOe devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOOe device the lowest total system power offered by any FPGA. Security The nonvolatile, flash-based IGLOOe devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOOe devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOOe devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOOe devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOOe devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOOe devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOOe device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the IGLOOe family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOOe family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An IGLOOe device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOOe FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based IGLOOe devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOOe devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOOe device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOOe devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. 1 -2 v2.0 IGLOOe Low-Power Flash FPGAs Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, Flash-based IGLOOe devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The IGLOOe family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOOe family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOOe flashbased FPGAs. Once it is programmed, the flash cell configuration element of IGLOOe FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOOe family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOOe family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOOe architecture provides granularity comparable to standard-cell ASICs. The IGLOOe device consists of five distinct and programmable architectural features (Figure 1-1 on page 4): * Flash*Freeze technology * FPGA VersaTiles * Dedicated FlashROM * Dedicated SRAM/FIFO memory * Extensive CCCs and PLLs * Pro I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOOe core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC(R) family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. v2.0 1-3 IGLOOe Device Family Overview In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG interface. CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Figure 1-1 * IGLOOe Device Architecture Overview Flash*Freeze Technology The IGLOOe device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL in this mode. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the 1 -4 v2.0 IGLOOe Low-Power Flash FPGAs inherent low power static and dynamic capabilities of the IGLOOe device. Refer to Figure 1-2 for an illustration of entering/exiting Flash*Freeze mode. Actel IGLOOe FPGA Flash*Freeze Mode Control Flash*Freeze Pin Figure 1-2 * IGLOOe Flash*Freeze Mode VersaTiles The IGLOOe core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The IGLOOe VersaTile supports the following: * All 3-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 D-Flip-Flop with Clear or Set Y Data CLK CLR Y Enable D-Flip-Flop with Clear or Set Data CLK D-FF Y D-FF Enable CLR Figure 1-3 * VersaTile Configurations User Nonvolatile FlashROM Actel IGLOOe devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FlashROM is written using the standard IGLOOe IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks, as in security keys stored in the FlashROM for a user design. v2.0 1-5 IGLOOe Device Family Overview The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel IGLOOe development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO IGLOOe devices have embedded SRAM blocks along their north and south sides. Each variableaspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC IGLOOe devices provide designers with very flexible clock conditioning capabilities. Each member of the IGLOOe family contains six CCCs, each with an integrated PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz * 2 programmable delay types for clock skew minimization * Clock frequency synthesis Additional CCC specifications: * 1 -6 Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration. * Output duty cycle = 50% 1.5% or better * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used * Maximum acquisition time is 300 s * Exceptional tolerance to input period jitter--allowable input jitter is up to 1.5 ns * Four precise phases; maximum misalignment between adjacent phases of 40 ps x 250 MHz / fOUT_CCC v2.0 IGLOOe Low-Power Flash FPGAs Global Clocking IGLOOe devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. Pro I/Os with Advanced I/O Standards The IGLOOe family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOOe FPGAs support 19 different I/O standards, including single-ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltagereferenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: * Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II) * Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II). IGLOOe banks support M-LVDS with 20 multi-drop points. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support Actel IGLOOe devices support JEDEC-defined wide range I/O operation. IGLOOe devices support both the JESD8-B specification, covering 3.0 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Part Number and Revision Date Part Number 51700096-001-6 Revised November 2009 v2.0 1-7 IGLOOe Device Family Overview List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v2.0) Page The version changed to v2.0 for IGLOOe datasheet chapters, indicating the datasheet contains information based on final characterization. N/A The "Pro (Professional) I/O" section was revised to add "Hot-swappable and cold-sparing I/Os." I The "Reprogrammable Flash Technology" section was revised to add "250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance." I Definitions of hot-swap and cold-sparing were added to the "Pro I/Os with Advanced I/O Standards" section. 1-7 v1.3 (February 2009) The -F speed grade is no longer offered for IGLOOe devices. The speed grade column and note regarding -F speed grade were removed from "IGLOOe Ordering Information". The "Speed Grade and Temperature Grade Matrix" section was removed. III, IV v1.2 (October 2008) The "Pro (Professional) I/O" section was revised to add two bullets regarding wide range power supply voltage support. I 3.0 V was added to the list of supported voltages in the "Pro I/Os with Advanced I/O Standards" section. The "Wide Range I/O Support" section is new. 1-7 v1.1 (June 2008) The Quiescent Current values in the "IGLOOe Product Family" table were updated. I v1.0 (April 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. N/A 51700096-001-1 (March 2008) This document was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. N/A 51700096-001-0 (January 2008) The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage" to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 25 W)" was removed from "Low-Power Active FPGA Operation." I v1.4 (April 2009) 1.2_V was added to the list of core and I/O voltages in the "Pro (Professional) I/O" and "Pro I/Os with Advanced I/O Standards" sections. I, 1-7 Advance v0.4 (December 2007) This document was previously in datasheet Advance v0.4. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700096-001-0. N/A Advance v0.3 (September 2007) The "IGLOOe Product Family" table was updated to change the maximum number of user I/Os for AGLE3000. I The "IGLOOe FPGAs Package Sizes Dimensions" table is new. Package dimensions were removed from the "I/Os Per Package1" table. The number of I/Os was updated for FG896. II A note regarding marking information was added to the "IGLOOe Ordering Information" table. III 1 -8 v2.0 IGLOOe Low-Power Flash FPGAs Previous Version Changes in Current Version (v2.0) Page Advance v0.2 (July 2007) Cortex-M1 device information was added to the "IGLOOe Product Family" I, II, III, IV table, the "I/Os Per Package 1" table, "IGLOOe Ordering Information", and "Temperature Grade Offerings". Advance v0.1 The words "ambient temperature" were added to the temperature range in the "IGLOOe Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix" sections. III, IV Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v2.0 1-9 2 - IGLOOe DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 * Symbol Absolute Maximum Ratings Parameter Limits Units VCC DC core supply voltage -0.3 to 1.65 V VJTAG JTAG DC voltage -0.3 to 3.75 V VPUMP Programming voltage -0.3 to 3.75 V VCCPLL Analog power supply (PLL) -0.3 to 1.65 V VCCI and VMV 3 DC I/O buffer supply voltage -0.3 to 3.75 V VI I/O input voltage -0.3 V to 3.6 V (when I/O hot insertion mode is enabled) -0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) V TSTG 2 Storage temperature -65 to +150 C TJ 2 Junction temperature +125 C Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-3, and for recommended operating limits, refer to Table 2-2 on page 2-2. 3. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information. v2.0 2-1 IGLOOe DC and Switching Characteristics Table 2-2 * Recommended Operating Conditions 1 Symbol TA Commercial Industrial Units 0 to +70 -40 to +85 C 0 to + 85 -40 to +100 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.2 V-1.5 V wide range DC core voltage5, 6 1.14 to 1.575 1.14 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.15 to 3.45 3.15 to 3.45 V 0 to 3.45 0 to 3.45 V 1.4 to 1.6 1.4 to 1.6 V 1.14 to 1.26 1.14 to 1.26 V 1.14 to 1.26 1.14 to 1.26 V 1.14 to 1.575 1.14 to 1.575 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 2.7 to 3.6 2.7 to 3.6 3.0 to 3.6 3.0 to 3.6 V 2.375 to 2.625 2.375 to 2.625 V 3.0 to 3.6 3.0 to 3.6 V Ambient Temperature TJ VCC Parameter Junction Temperature 3 VJTAG VPUMP 2 4 JTAG DC voltage 6 Programming voltage Programming Mode Operation VCCPLL8 Analog power supply (PLL) 7 4 1.5 V DC core supply voltage 1.2 V-1.5 V DC core supply voltage5 VCCI and 1.2 V DC supply voltage5 VMV9 1.2 V wide range DC supply voltage5 3.0 V DC supply voltage10 3.3 V DC supply voltage LVDS differential I/O LVPECL differential I/O Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel's timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-20 on page 2-20. VCCI should be at the same voltage within a given I/O bank. 4. For IGLOOe V5 devices 5. For IGLOOe V2 devices only, operating at VCCI VCC 6. All IGLOOe devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using the V2 devices powered by a 1.2 V supply must switch the core supply to 1.5 V for in-system programming. 7. VPUMP can be left floating during operation (not programming mode). 8. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information. 9. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information. 10. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation. 2 -2 v2.0 IGLOOe DC and Switching Characteristics Table 2-3 * Flash Programming Limits - Retention, Storage, and Operating Temperature1 Product Grade Programming Program Retention Cycles (biased/unbiased) Maximum Storage Temperature TSTG (C) 2 Maximum Operating Junction Temperature TJ (C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. Table 2-4 * VCCI Overshoot and Undershoot Limits 1, 3 Average VCCI-GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 2.7 V or less 3V 3.3 V 3.6 V Maximum Overshoot/ Undershoot2 10% 1.4 V 5% 1.49 V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at junction temperature at 85C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every IGLOOe device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5. There are five regions to consider during power-up. IGLOOe I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5). 2. VCCI > VCC - 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: v2.0 2-3 IGLOOe DC and Switching Characteristics * During programming, I/Os become tristated and weakly pulled up to VCCI. * JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2-2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation. VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V Figure 2-1 * V5 - I/O State as a Function of VCCI and VCC Voltage Levels 2 -4 v2.0 VCCI IGLOOe DC and Switching Characteristics VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.2 V Deactivation trip point: Vd = 0.75 V 0.2 V Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.15 V Deactivation trip point: Vd = 0.8 V 0.15 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V VCCI Figure 2-2 * V2 Devices - I/O State as a Function of VCCI and VCC Voltage Levels Thermal Characteristics Introduction The temperature variable in Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 2-1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5. P = Power dissipation v2.0 2-5 IGLOOe DC and Switching Characteristics Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 100C. EQ 2-2 shows a sample calculation of the absolute maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and in still air. 100C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 2.206 W 13.6C/W ja (C/W) EQ 2-2 Table 2-5 * Package Thermal Resistivities ja Pin Count jc Still Air 200 ft./min. 500 ft./min. Units Plastic Quad Flat Package (PQFP) 208 8.0 26.1 22.5 20.8 C/W Plastic Quad Flat Package (PQFP) with embedded heat spreader 208 3.8 16.2 13.3 11.9 C/W Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.9 22.8 21.5 C/W 484 3.2 20.5 17.0 15.9 C/W 676 3.2 16.4 13.0 12.0 C/W 896 2.4 13.6 10.4 9.4 C/W Package Type Temperature and Voltage Derating Factors Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C,VCC = 1.425 V) For IGLOOe V2 or V5 devices, 1.5 V DC Core Supply Voltage Junction Temperature (C) Array Voltage VCC (V) -40C 0C 25C 70C 85C 100C 1.425 0.945 0.965 0.978 1.000 1.008 1.013 1.500 0.876 0.893 0.906 0.927 0.934 0.940 1.575 0.824 0.840 0.852 0.872 0.879 0.884 Table 2-7 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.14 V) For IGLOOe V2, 1.2 V DC Core Supply Voltage Junction Temperature (C) Array Voltage VCC (V) -40C 0C 25C 70C 85C 100C 1.14 0.968 0.978 0.991 1.000 1.006 1.010 1.20 0.864 0.873 0.885 0.893 0.898 0.902 1.26 0.793 0.803 0.813 0.821 0.826 0.829 2 -6 v2.0 IGLOOe DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC , VCCI , and VJTAG), operating temperature, system clock frequency, and power modes usage. Actel recommends using the PowerCalculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 * Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode* Core Voltage AGLE600 AGLE3000 Units 1.2 V 34 95 A 1.5 V 72 310 A Typical (25C) * IDD includes VCC, VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-9 * Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)* Core Voltage AGLE600 AGLE3000 Units VCCI /VJTAG = 1.2 V (per bank) Typical (25C) 1.2 V 1.7 1.7 A VCCI /VJTAG = 1.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.8 1.8 A VCCI /VJTAG = 1.8 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.9 1.9 A VCCI /VJTAG = 2.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.2 2.2 A VCCI /VJTAG= 3.3 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.5 2.5 A * IDD includes VCC , VPUMP , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-10 * Quiescent Supply Current (IDD), IGLOOe Shutdown Mode (VCC, VCCI = 0 V)* Typical (25C) Core Voltage AGLE600 AGLE3000 Units 1.2 V / 1.5 V 0 0 A * IDD includes VCC , VPUMP , VCCI , VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). v2.0 2-7 IGLOOe DC and Switching Characteristics Table 2-11 * Quiescent Supply Current, No IGLOOe Flash*Freeze Mode* Core Voltage AGLE600 AGLE3000 Units 1.2 V 28 89 A 1.5 V 82 320 A VCCI /VJTAG = 1.2 V (per bank) Typical (25C) 1.2 V 1.7 1.7 A VCCI /VJTAG = 1.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.8 1.8 A VCCI /VJTAG = 1.8 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.9 1.9 A VCCI /VJTAG = 2.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.2 2.2 A VCCI /VJTAG= 3.3 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.5 2.5 A 2 ICCA Current Typical (25C) 3, 4 ICCI or IJTAG Current Notes: 1. To calculate total device IDD, multiply the number of banks used in ICCI and add ICCA contribution. 2. Includes VCC , VCCPLL, and VPUMP currents. 3. Per VCCI or VJTAG bank 4. Values do not include I/O static contribution (PDC6 and PDC7). 2 -8 v2.0 IGLOOe DC and Switching Characteristics Power per I/O Pin Table 2-12 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings VCCI (V) Static Power PDC6 (mW)1 Dynamic Power PAC9 (W/MHz)2 Single-Ended 3.3 V LVTTL/LVCMOS 3.3 - 16.34 3.3 V LVTTL/LVCMOS - Schmitt trigger 3.3 - 24.49 3.3 - 16.34 3.3 V LVCMOS Wide Range 3 3.3 V LVCMOS Wide Range - Schmitt trigger 3 3.3 - 24.49 2.5 V LVCMOS 2.5 - 4.71 2.5 V LVCMOS 2.5 - 6.13 1.8 V LVCMOS 1.8 - 1.66 1.8 V LVCMOS - Schmitt trigger 1.8 - 1.78 1.5 V LVCMOS (JESD8-11) 1.5 - 1.01 1.5 V LVCMOS (JESD8-11) - Schmitt trigger 1.5 - 0.97 1.2 V LVCMOS 4 1.2 - 0.60 1.2 V LVCMOS - Schmitt trigger 4 1.2 - 0.53 0.60 1.2 V LVCMOS Wide Range 4 1.2 - 1.2 V LVCMOS Wide Range - Schmitt trigger 4 1.2 - 0.53 3.3 V PCI 3.3 - 17.76 3.3 V PCI - Schmitt trigger 3.3 - 19.10 3.3 V PCI-X 3.3 - 17.76 3.3 V PCI-X - Schmitt trigger 3.3 - 19.10 3.3 V GTL 3.3 2.90 7.14 2.5 V GTL 2.5 2.13 3.54 3.3 V GTL+ 3.3 2.81 2.91 2.5 V GTL+ 2.5 2.57 2.61 HSTL (I) 1.5 0.17 0.79 Voltage-Referenced HSTL (II) 1.5 0.17 .079 SSTL2 (I) 2.5 1.38 3.26 SSTL2 (II) 2.5 1.38 3.26 SSTL3 (I) 3.3 3.21 7.97 SSTL3 (II) 3.3 3.21 7.97 Differential LVDS 2.5 2.26 0.89 LVPECL 3.3 5.71 1.94 Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI . 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 4. Applicable for IGLOOe V2 devices only. v2.0 2-9 IGLOOe DC and Switching Characteristics Table 2-13 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 CLOAD (pF) VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL/LVCMOS 5 3.3 - 148.00 3.3 V LVCMOS Wide Range 4 5 3.3 - 148.00 2.5 V LVCMOS 5 2.5 - 83.23 1.8 V LVCMOS 5 1.8 - 54.58 1.5 V LVCMOS (JESD8-11) 5 1.5 - 37.05 1.2 V LVCMOS (JESD8-11) 5 1.2 - 17.94 Single-Ended 1.2 V LVCMOS (JESD8-11) - Wide Range 17.94 3.3 V PCI 10 3.3 - 204.61 3.3 V PCI-X 10 3.3 - 204.61 3.3 V GTL 10 3.3 - 24.08 2.5 V GTL 10 2.5 - 13.52 3.3 V GTL+ 10 3.3 - 24.10 2.5 V GTL+ 10 2.5 - 13.54 HSTL (I) 20 1.5 7.08 26.22 HSTL (II) 20 1.5 13.88 27.18 SSTL2 (I) 30 2.5 16.69 105.56 SSTL2 (II) 30 2.5 25.91 116.60 SSTL3 (I) 30 3.3 26.02 114.67 SSTL3 (II) 30 3.3 42.21 131.69 LVDS - 2.5 7.70 89.62 LVPECL - 3.3 19.42 167.86 Voltage-Referenced Differential Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 2 -1 0 v2.0 IGLOOe DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-14 * Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage Device-Specific Dynamic Contributions (W/MHz) Parameter Definition AGLE600 AGLE3000 PAC1 Clock contribution of a Global Rib 19.7 12.77 PAC2 Clock contribution of a Global Spine 4.16 1.85 PAC3 Clock contribution of a VersaTile row 0.88 PAC4 Clock contribution of a VersaTile used as a sequential module 0.11 PAC5 First contribution of a VersaTile used as a sequential module 0.057 PAC6 Second contribution of a VersaTile used as a sequential module 0.207 PAC7 Contribution of a VersaTile used as a combinatorial module 0.207 PAC8 Average contribution of a routing net PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-12 on page 2-9. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-13 on page 2-10. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.70 0.7 * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or SmartPower in Actel Libero(R) Integrated Design Environment (IDE) software. Table 2-15 * Different Components Contributing to the Static Power Consumption in IGLOO Devices For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage Device Specific Static Power (mW) Parameter Definition AGLE600 AGLE3000 PDC1 Array static power in Active mode See Table 2-11 on page 2-8. PDC2 Array static power in Static (Idle) mode See Table 2-10 on page 2-7. PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7. PDC4 Static PLL contribution PDC5 Bank quiescent power (VCCI-dependent) See Table 2-11 on page 2-8. PDC6 I/O input pin static power (standard-dependent) See Table 2-12 on page 2-9. PDC7 I/O output pin static power (standard-dependent) See Table 2-13 on page 2-10. 1.84 v2.0 2 - 11 IGLOOe DC and Switching Characteristics Table 2-16 * Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage Device-Specific Dynamic Contributions (W/MHz) Parameter Definition AGLE600 AGLE3000 PAC1 Clock contribution of a Global Rib 12.61 8.17 PAC2 Clock contribution of a Global Spine 2.66 1.18 PAC3 Clock contribution of a VersaTile row 0.56 PAC4 Clock contribution of a VersaTile used as a sequential module 0.071 PAC5 First contribution of a VersaTile used as a sequential module 0.045 PAC6 Second contribution of a VersaTile used as a sequential module 0.186 PAC7 Contribution of a VersaTile used as a combinatorial module 0.109 PAC8 Average contribution of a routing net 0.449 PAC9 Contribution of an I/O input pin (standard-dependent) PAC10 Contribution of an I/O output pin (standard-dependent) PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic PLL contribution 2.10 See Table 2-8 on page 2-7. See Table 2-9 on page 2-7 and Table 2-10 on page 2-7. * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or SmartPower in Actel Libero IDE software. Table 2-17 * Different Components Contributing to the Static Power Consumption in IGLOO Devices For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage Device Specific Static Power (mW) Parameter Definition AGLE600 AGLE3000 PDC1 Array static power in Active mode See Table 2-11 on page 2-8. PDC2 Array static power in Static (Idle) mode See Table 2-10 on page 2-7. PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7. PDC4 Static PLL contribution PDC5 Bank quiescent power (VCCI-dependent) See Table 2-11 on page 2-8. PDC6 I/O input pin static power (standard-dependent) See Table 2-12 on page 2-9. PDC7 I/O output pin static power (standard-dependent) See Table 2-13 on page 2-10. 2 -1 2 0.90 v2.0 IGLOOe DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation methodology described below uses the following variables: * The number of PLLs as well as the number and the frequency of each output clock generated * The number of combinatorial and sequential cells used in the design * The internal clock frequencies * The number and the standard of I/O pins used in the design * The number of RAM blocks used in the design * Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 2-18 on page 2-15. * Enable rates of output buffers--guidelines are provided for typical applications in Table 2-19 on page 2-15. * Read rate and write rate to the memory--guidelines are provided for typical applications in Table 2-19 on page 2-15. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption--PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption--PSTAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption--PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution--PCLOCK PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK NSPINE is the number of global spines used in the user design--guidelines are provided in Table 2-18 on page 2-15. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 2-18 on page 2-15. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution--PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-18 on page 2-15. FCLK is the global clock signal frequency. v2.0 2 - 13 IGLOOe DC and Switching Characteristics Combinatorial Cells Contribution--PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-18 on page 2-15. FCLK is the global clock signal frequency. Routing Net Contribution--PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-18 on page 2-15. FCLK is the global clock signal frequency. I/O Input Buffer Contribution--PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-18 on page 2-15. FCLK is the global clock signal frequency. I/O Output Buffer Contribution--POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-18 on page 2-15. 1 is the I/O buffer enable rate--guidelines are provided in Table 2-19 on page 2-15. FCLK is the global clock signal frequency. RAM Contribution--PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations--guidelines are provided in Table 2-19 on page 2-15. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations--guidelines are provided in Table 2-19 on page 2-15. PLL Contribution--PPLL PPLL = PDC4 + PAC13 * FCLKOUT FCLKOUT is the output clock frequency.1 1. 2 -1 4 If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution. v2.0 IGLOOe DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock frequency. * The average toggle rate of an 8-bit counter is 25%: - Bit 0 (LSB) = 100% - Bit 1 = 50% - Bit 2 = 25% - ... - Bit 7 (MSB) = 0.78125% - Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-18 * Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-19 * Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% v2.0 2 - 15 IGLOOe DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y Y tPD = 1.19 ns LVPECL tPD = 1.04 ns tDP = 1.75 ns I/O Module (Non-Registered) Combinational Cell Y LVTTL/LVCMOS 3.3 V Output drive strength = 12 mA High slew rate tDP = 3.13 ns tPD = 1.77 ns Combinational Cell I/O Module (Non-Registered) Y I/O Module (Registered) tPY = 1.45 ns tDP = 2.76 ns LVTTL/LVCMOS 3.3 V Output drive strength = 24 mA High slew rate tPD = 1.33 ns LVPECL D Q Combinational Cell I/O Module (Non-Registered) Y tICLKQ = 0.43 ns tISUD = 0.47 ns tDP = 3.30 ns tPD = 0.85 ns LVCMOS 1.5V Output drive strength = 12 mA High slew Input LVTTL/LVCMOS 3.3 V Clock Register Cell Combinational Cell tPY = 1.10 ns D Y Q I/O Module (Non-Registered) tPY = 1.62 ns D Q D Q GTL+ 3.3V tDP = 1.85 ns tPD = 0.90 ns tCLKQ = 0.90 ns tSUD = 0.82 ns LVDS, BLVDS, M-LVDS I/O Module (Registered) Register Cell tCLKQ = 0.90 ns tSUD = 0.82 ns tOCLKQ = 1.02 ns tOSUD = 0.52 ns Input LVTTL/LVCMOS 3.3 V Input LVTTL/LVCMOS 3.3 V Clock Clock tPY = 1.10 ns tPY = 1.10 ns Figure 2-3 * Timing Model Operating Conditions: Std. Speed, Commercial Temperature Range (TJ = 70C), Worst-Case VCC = 1.425 V, Applicable to 1.5 V DC Core Voltage, V2 and V5 devices 2 -1 6 v2.0 IGLOOe DC and Switching Characteristics tPY tDIN D PAD Q DIN Y CLK To Array I/O Interface tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) VIH Vtrip Vtrip PAD VIL VCC 50% 50% Y GND tPY tPY (R) (F) tPYS tPYS (R) (F) VCC 50% DIN GND 50% tDOUT tDOUT (R) (F) Figure 2-4 * Input Buffer Timing Model and Delays (example) v2.0 2 - 17 IGLOOe DC and Switching Characteristics tDOUT tDP D Q D PAD DOUT Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT tDOUT (R) D 50% VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) Figure 2-5 * Output Buffer Model and Delays (example) 2 -1 8 v2.0 tDP (F) IGLOOe DC and Switching Characteristics tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% E 50% tEOUT (F) tEOUT (R) VCC 50% 50% EOUT tZL 50% tZH tHZ Vtrip VCCI 90% VCCI PAD 50% tLZ Vtrip VOL 10% VCCI VCC D VCC E 50% 50% tEOUT (R) tEOUT (F) VCC EOUT 50% 50% tZLS VOH PAD Vtrip 50% tZHS Vtrip VOL Figure 2-6 * Tristate Output Buffer Timing Model and Delays (example) v2.0 2 - 19 IGLOOe DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels - Default I/O Software Settings Table 2-20 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions I/O Standard VIL Equivalent Software Default Slew Min., Drive Drive V Max., V Strength Strength2 Rate VIH VOL VOH IOL1 IOH1 mA mA Min., V Max., V Max., V Min., V 3.3 V LVTTL / 3.3 V LVCMOS 12 mA 12 mA High -0.3 0.8 2 3.6 0.4 2.4 3.3 V LVCMOS Wide Range3, 4 100 A 12 mA High -0.3 0.8 2 3.6 0.2 VCCI - 0.2 2.5 V LVCMOS 12 mA 12 mA High -0.3 0.7 1.7 3.6 0.7 1.7 1.8 V LVCMOS 12 mA 12 mA High -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 1.5 V LVCMOS 12 mA 12 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.2 V LVCMOS2,5 2 mA 2 mA High -0.3 0.35 * VCCI 0.65 * VCCI 2 mA High -0.3 1.2 V 100 A LVCMOS Wide Range 2,4,5 3.3 V PCI 0.7 * VCCI 12 0.1 0.1 12 12 VCCI - 0.45 12 12 3.6 0.25 * VCCI 0.75 * VCCI 12 12 3.6 0.25 * VCCI 0.75 * VCCI 2 3.6 0.1 VCCI - 0.1 2 0.1 0.1 Per PCI Specification 3.3 V PCI-X 3.3 V GTL 0.3 * VCCI 12 Per PCI-X Specification 25 mA6 6 25 mA6 High -0.3 VREF - 0.05 VREF + 0.05 3.6 0.4 - 25 25 mA6 High -0.3 VREF - 0.05 VREF + 0.05 3.6 0.4 - 25 25 High -0.3 3.6 0.6 - 51 51 2.5 V GTL 25 mA 25 3.3 V GTL+ 35 mA 35 mA VREF - 0.1 VREF + 0.1 Notes: 1. Currents are measured at 85C junction temperature. 2. Applicable to IGLOO V2 devices operating at VCCI VCC. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-12 specification. 4. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 6. Output drive strength is below JEDEC specification. 7. Output Slew Rates can be extracted from IBIS Models, http://www.actel.com/download/ibis/default.aspx. 2 -2 0 v2.0 IGLOOe DC and Switching Characteristics Table 2-20 * Summary of Maximum and Minimum DC Input and Output Levels (continued) Applicable to Commercial and Industrial Conditions I/O Standard Equivalent VIL Software Default Drive Drive Slew Min., Strength Strength2 Rate V Max., V VIH VOL VOH IOL1 IOH1 mA mA Min., V Max., V Max., V Min., V 2.5 V GTL+ 33 mA 33 mA High -0.3 VREF - 0.1 VREF + 0.1 3.6 0.6 - 40 40 HSTL (I) 8 mA 8 mA High -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCI - 0.4 8 8 HSTL (II) 15 mA6 15 mA6 High -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCI - 0.4 15 15 SSTL2 (I) 15 mA 15 mA High -0.3 VREF - 0.2 VREF + 0.2 3.6 0.54 VCCI - 0.62 15 15 SSTL2 (II) 18 mA 18 mA High -0.3 VREF - 0.2 VREF + 0.2 3.6 0.35 VCCI - 0.43 18 18 SSTL3 (I) 14 mA 14 mA High -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCI - 1.1 14 14 SSTL3 (II) 21 mA 21 mA High -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCI - 0.9 21 21 Notes: 1. Currents are measured at 85C junction temperature. 2. Applicable to IGLOO V2 devices operating at VCCI VCC. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-12 specification. 4. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 6. Output drive strength is below JEDEC specification. 7. Output Slew Rates can be extracted from IBIS Models, http://www.actel.com/download/ibis/default.aspx. v2.0 2 - 21 IGLOOe DC and Switching Characteristics Table 2-21 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 Industrial2 IIL3 IIH4 IIL3 IIH4 DC I/O Standards A A A A 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 3.3 V LVCMOS Wide Range 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 10 10 15 15 10 10 15 15 1.2 V LVCOMS Wide Range 10 10 15 15 3.3 V PCI 10 10 15 15 3.3 V PCI-X 10 10 15 15 3.3 V GTL 10 10 15 15 2.5 V GTL 10 10 15 15 3.3 V GTL+ 10 10 15 15 2.5 V GTL+ 10 10 15 15 HSTL (I) 10 10 15 15 HSTL (II) 10 10 15 15 SSTL2 (I) 10 10 15 15 SSTL2 (II) 10 10 15 15 SSTL3 (I) 10 10 15 15 SSTL3 (II) 10 10 15 15 1.5 V LVCMOS 1.2 V LVCMOS 5 5 Notes: 1. Commercial range (0C < TA < 70C) 2. Industrial range (-40C < TA < 85C) 3. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Applicable to V2 devices operating at VCCI VCC. 2 -2 2 v2.0 IGLOOe DC and Switching Characteristics Summary of I/O Timing Characteristics - Default I/O Software Settings Table 2-22 * Summary of AC Measuring Points Input Reference Voltage (VREF_TYP) Standard Board Termination Voltage (VTT_REF) Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS - - 1.4 V 3.3 V LVCMOS Wide Range - - 1.4 V 2.5 V LVCMOS - - 1.2 V 1.8 V LVCMOS - - 0.90 V 1.5 V LVCMOS - - 0.75 V 1.2 V LVCMOS* - - 0.6 V 1.2 V LVCMOS - Wide Range* - - 0.6 V 3.3 V PCI - - 0.285 * VCCI (RR) - - 0.615 * VCCI (FF)) 3.3 V PCI-X - - 0.285 * VCCI (RR) - - 0.615 * VCCI (FF) 3.3 V GTL 0.8 V 1.2 V VREF 2.5 V GTL 0.8 V 1.2 V VREF 3.3 V GTL+ 1.0 V 1.5 V VREF 2.5 V GTL+ 1.0 V 1.5 V VREF HSTL (I) 0.75 V 0.75 V VREF HSTL (II) 0.75 V 0.75 V VREF SSTL2 (I) 1.25 V 1.25 V VREF SSTL2 (II) 1.25 V 1.25 V VREF SSTL3 (I) 1.5 V 1.485 V VREF SSTL3 (II) 1.5 V 1.485 V VREF LVDS - - Cross point LVPECL - - Cross point Note: *Applicable to V2 devices ONLY operating in the 1.2 V core range. Table 2-23 * I/O AC Parameter Definitions Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer with Schmitt trigger disabled tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tPYS Pad to Data delay through the Input Buffer with Schmitt trigger enabled tHZ Enable to Pad delay through the Output Buffer--HIGH to Z tZH Enable to Pad delay through the Output Buffer--Z to HIGH tLZ Enable to Pad delay through the Output Buffer--LOW to Z tZL Enable to Pad delay through the Output Buffer--Z to LOW tZHS Enable to Pad delay through the Output Buffer with delayed enable--Z to HIGH tZLS Enable to Pad delay through the Output Buffer with delayed enable--Z to LOW v2.0 2 - 23 IGLOOe DC and Switching Characteristics 2.5 V LVCMOS 12 12 High 5 - .097 2.15 0.18 1.31 1.41 0.66 2.20 1.85 2.78 2.98 5.80 5.45 ns 1.8 V LVCMOS 12 12 High 5 - 0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns 1.5 V LVCMOS 12 12 High 5 - Units 0.97 2.96 0.18 1.42 1.84 0.66 2.98 2.28 3.86 4.36 6.58 5.87 ns tZHS (ns) - tZLS (ns) 5 tHZ (ns) High tLZ (ns) 12 tZ H (ns) 3.3 V LVCMOS 100 A Wide Range1, 2 tZL (ns) 0.97 2.12 0.18 1.08 1.34 0.66 2.17 1.69 2.71 3.08 5.76 5.28 ns tE OUT (ns) - tPYS (ns) External Resistor () 5 tPY (ns) Capacitive Load (pF) High tDIN (ns) Slew Rate 12 3.3 V LVTTL / 3.3 V LVCMOS tDP (ns) Equivalent Software Default Drive Strength Option4 (mA) 12 I/O Standard tDOUT (ns) Drive Strength (mA) Table 2-24 * Summary of I/O Timing Characteristics--Software Default Settings Std. Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard) 0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns 3 3.3 V PCI Per PCI spec - High 10 25 3.3 V PCI-X Per PCI-X spec - High 10 25 3 0.97 2.38 0.19 0.92 1.34 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns 3.3 V GTL 25 - High 10 25 0.97 1.78 0.19 2.35 - 0.66 1.80 1.78 - - 5.39 5.38 ns 2.5 V GTL 25 - High 10 25 0.97 1.85 0.19 1.98 - 0.66 1.89 1.82 - - 5.49 5.42 ns 3.3 V GTL+ 35 - High 10 25 0.97 1.80 0.19 1.32 - 0.66 1.84 1.77 - - 5.44 5.36 ns 2.5 V GTL+ 33 - High 10 25 0.97 1.92 0.19 1.26 - 0.66 1.96 1.80 - - 5.56 5.40 ns HSTL (I) 8 - High 20 50 0.97 2.67 0.18 1.72 - 0.66 2.72 2.67 - - 6.32 6.26 ns HSTL (II) 15 - High 20 25 0.97 2.55 0.18 1.72 - 0.66 2.60 2.34 - - 6.20 5.93 ns SSTL2 (I) 15 - High 30 50 0.97 1.86 0.19 1.12 - 0.66 1.90 1.68 - - 5.50 5.28 ns SSTL2 (II) 18 - High 30 25 0.97 1.89 0.19 1.12 - 0.66 1.93 1.62 - - 5.53 5.22 ns SSTL3 (I) 14 - High 30 50 0.97 2.00 0.19 1.06 - 0.66 2.04 1.67 - - 5.64 5.27 ns SSTL3 (II) 21 - High 30 25 0.97 1.81 0.19 1.06 - 0.66 1.85 1.55 - - 5.45 5.14 ns LVDS 24 - High - - 0.97 1.73 0.19 1.62 - - - - - - - - ns LVPECL 24 - High - - 0.97 1.65 0.18 1.42 - - - - - - - - ns 0.97 2.38 0.18 0.96 1.42 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns Notes: 1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-48 for connectivity. This resistor is not required during normal operation. 2. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges 3. Resistance is used to measure I/O propagation delays as defined in PCI Specifications. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -2 4 v2.0 IGLOOe DC and Switching Characteristics 1.8 V LVCMOS 12 12 High 5 - 1.55 2.75 0.26 1.53 1.96 1.10 2.78 2.40 3.68 4.56 8.57 8.19 ns 1.5 V LVCMOS 12 12 High 5 - 1.55 3.10 0.26 1.72 2.16 1.10 3.15 2.70 3.86 4.68 8.93 8.49 ns 1.2 V LVCMOS 2 2 High 5 - 1.55 4.06 0.26 2.09 2.95 1.10 3.92 3.46 4.01 3.79 9.71 9.24 ns 1.2 V LVCMOS 100 A Wide Range2,3 2 High 5 - 1.55 4.06 0.26 2.09 2.95 1.10 3.92 3.46 4.01 3.79 9.71 9.24 ns 3.3 V PCI Per PCI spec - High 10 254 1.55 2.76 0.26 1.19 1.63 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns Per PCI-X spec - High 10 254 1.55 2.76 0.25 1.22 1.58 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns 3.3 V GTL 25 - High 10 25 1.55 2.08 0.25 2.76 - 1.10 2.09 2.08 - - 7.88 7.87 ns 2.5 V GTL 25 - High 10 25 1.55 2.17 0.25 2.35 - 1.10 2.20 2.13 - - 7.99 7.91 ns 3.3 V GTL+ 35 - High 10 25 1.55 2.12 0.25 1.62 - 1.10 2.14 2.07 - - 7.93 7.85 ns 2.5 V GTL+ 33 - High 10 25 1.55 2.25 0.25 1.55 - 1.10 2.27 2.10 - - 8.06 7.89 ns HSTL (I) 8 - High 20 50 1.55 3.09 0.25 1.95 - 1.10 3.11 3.09 - - 8.90 8.88 ns HSTL (II) 15 - High 20 25 1.55 2.94 0.25 1.95 - 1.10 2.98 2.74 - - 8.77 8.53 ns SSTL2 (I) 15 - High 30 50 1.55 2.18 0.25 1.40 - 1.10 2.21 2.03 - - 7.99 7.82 ns 3.3 V PCI-X Units ns tZHS (ns) 1.55 2.51 0.26 1.55 1.77 1.10 2.54 2.22 3.36 3.85 8.33 8.00 tZLS (ns) - tHZ (ns) 12 High 5 tLZ (ns) 12 tZ H (ns) 2.5 V LVCMOS tZL (ns) 1.55 3.40 0.26 1.66 2.14 1.10 3.40 2.68 4.55 5.49 9.19 8.46 ns tE OU T (ns) - tPYS (ns) 3.3 V LVCMOS 100 A 12 High 35 Wide Range1,2 tPY (ns) 1.55 2.47 0.26 1.31 1.58 1.10 2.51 2.04 3.28 3.97 8.29 7.82 tDIN (ns) External Resistor () - tDP (ns) Capacitive Load (pF) 12 High 5 3.3 V LVTTL / 3.3 V LVCMOS tDOUT (ns) Equivalent Software Default Drive Strength Option5 (mA) 12 I/O Standard Slew Rate Drive Strength (mA) Table 2-25 * Summary of I/O Timing Characteristics--Software Default Settings Std. Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard) ns Notes: 1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 10 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges only. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-48 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 25 IGLOOe DC and Switching Characteristics - High 30 50 1.55 2.33 0.25 1.33 - 1.10 2.36 2.02 - - 8.15 7.81 ns SSTL3 (II) 21 - High 30 25 1.55 2.13 0.25 1.33 - 1.10 2.16 1.89 - - 7.94 7.67 ns LVDS 24 - High - - 1.55 2.26 0.25 1.95 - - - - - - - - ns LVPECL 24 - High - - 1.55 2.17 0.25 1.70 - - - - - - - - ns Units 14 tZHS (ns) tHZ (ns) SSTL3 (I) tZLS (ns) tLZ (ns) ns tZ H (ns) 8.03 7.76 tZL (ns) - tE OU T (ns) - tPYS (ns) 1.10 2.24 1.97 tPY (ns) - tDIN (ns) 25 1.55 2.21 0.25 1.40 tDP (ns) High 30 tDOUT (ns) - External Resistor () 18 Capacitive Load (pF) Equivalent Software Default Drive Strength Option5 (mA) SSTL2 (II) Slew Rate I/O Standard Drive Strength (mA) Table 2-25 * Summary of I/O Timing Characteristics--Software Default Settings (continued) Std. Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard) Notes: 1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 10 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges only. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-48 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2 -2 6 v2.0 IGLOOe DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-26 * Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF Drive Strength RPULL-DOWN ()2 RPULL-UP ()3 4 mA 100 300 Table 2-27 * I/O Output Buffer Maximum Resistances1 Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range4 3.3 V PCI/PCI-X 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 100 A TBD TBD 4 mA 100 200 8 mA 50 100 12 mA 25 50 16 mA 20 40 24 mA 11 22 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 12 mA 20 22 16 mA 20 22 2 mA 200 224 4 mA 100 112 6 mA 67 75 8 mA 33 37 12 mA 33 37 2 mA TBD TBD 100 A TBD TBD Per PCI/PCI-X specification 25 75 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHs pe c 4. Applicable to IGLOOe V2 devices operating in the 1.2 V core range ONLY. v2.0 2 - 27 IGLOOe DC and Switching Characteristics Table 2-27 * I/O Output Buffer Maximum Resistances1 (continued) Standard Drive Strength RPULL-DOWN ()2 RPULL-UP ()3 3.3 V GTL 25 mA 11 - 2.5 V GTL 25 mA 14 - 3.3 V GTL+ 35 mA 12 - 2.5 V GTL+ 33 mA 15 - HSTL (I) 8 mA 50 50 HSTL (II) 15 mA 25 25 SSTL2 (I) 15 mA 27 31 SSTL2 (II) 18 mA 13 15 SSTL3 (I) 14 mA 44 69 SSTL3 (II) 21 mA 18 32 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHs pe c 4. Applicable to IGLOOe V2 devices operating in the 1.2 V core range ONLY. Table 2-28 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R((WEAK PULL-UP)1 () R(WEAK PULL-DOWN)2 () VCCI Minimum Maximum Minimum Maximum 3.3 V 10 k 45 k 10 k 45 k 3.3 V (wide range I/Os) 10 k 45 k 10 k 45 k 2.5 V 11 k 55 k 12 k 74 k 1.8 V 18 k 70 k 17 k 110 k 1.5 V 19 k 90 k 19 k 140 k 1.2 V 25 k 110 k 25 k 150 k 1.2 V (wide range I/Os) 19 k 110 k 19 k 150 k Notes: 1. R(WEAK PULL-DOWN-MAX) = (VOLspec) / IWEAK PULL-DOWN-MIN 2. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / IWEAK PULL-UP-MIN 2 -2 8 v2.0 IGLOOe DC and Switching Characteristics Table 2-29 * I/O Short Currents IOSH/IOSL 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCIX Drive Strength IOSH (mA)* IOSL (mA)* 4 mA 25 27 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181 100 A TBD TBD 4 mA 16 18 8 mA 32 37 12 mA 65 74 16 mA 83 87 24 mA 169 124 2 mA 9 11 4 mA 17 22 6 mA 35 44 8 mA 45 51 12 mA 91 74 16 mA 91 74 2 mA 13 16 4 mA 25 33 6 mA 32 39 8 mA 66 55 12 mA 66 55 2 mA TBD TBD 100 A TBD TBD Per PCI/PCI-X Specification Per PCI Curves 3.3 V GTL 25 mA 268 181 2.5 V GTL 25 mA 169 124 3.3 V GTL+ 35 mA 268 181 2.5 V GTL+ 33 mA 169 124 HSTL (I) 8 mA 32 39 HSTL (II) 15 mA 66 55 SSTL2 (I) 15 mA 83 87 SSTL2 (II) 18 mA 169 124 SSTL3 (I) 14 mA 51 54 SSTL3 (II) 21 mA 103 109 * TJ = 100C v2.0 2 - 29 IGLOOe DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of analysis. For example, at 110C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-30 * Duration of Short Circuit Event before Failure Temperature Time before Failure -40C > 20 years 0C > 20 years 25C > 20 years 70C 5 years 85C 2 years 100C 6 months Table 2-31 * Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.) 3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV 1.2 V LVCMOS (Schmitt trigger mode) 40 mV Table 2-32 * I/O Input Rise Time, Fall Time, and Related I/O Reliability* Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS (Schmitt trigger disabled) No requirement 10 ns* 20 years (100C) LVTTL/LVCMOS (Schmitt trigger enabled) No requirement HSTL/SSTL/GTL No requirement 10 ns* 10 years (100C) LVDS/B-LVDS/M-LVDS/LVPECL No requirement 10 ns* 10 years (100C) No requirement, but input noise 20 years (100C) voltage cannot exceed Schmitt hysteresis. * The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2 -3 0 v2.0 IGLOOe DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported as part of the 3.3 V LVTTL support. Table 2-33 * Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS VIH VIL VOL VOH IOL IOH IOSH IIL1 IIH2 IOSL Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10 24 mA -0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-7 * AC Loading Table 2-34 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF) 3.3 1.4 - 5 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. v2.0 2 - 31 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-35 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tHZ tZLS tZHS Units 4 mA Std. 0.97 4.90 0.18 1.08 1.34 tDIN tPY tPYS tEOUT 0.66 5.00 3.99 2.27 2.16 tZL tZH tLZ 8.60 7.59 ns 8 mA Std. 0.97 4.05 0.18 1.08 1.34 0.66 4.13 3.45 2.53 2.65 7.73 7.05 ns 12 mA Std. 0.97 3.44 0.18 1.08 1.34 0.66 3.51 3.05 2.71 2.95 7.11 6.64 ns 16 mA Std. 0.97 3.27 0.18 1.08 1.34 0.66 3.34 2.96 2.74 3.04 6.93 6.55 ns 24 mA Std. 0.97 3.18 0.18 1.08 1.34 0.66 3.24 2.97 2.79 3.36 6.84 6.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-36 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP 4 mA Std. 0.97 2.85 0.18 1.08 1.34 8 mA Std. 0.97 12 mA Std. 16 mA 24 mA tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 0.66 2.92 2.27 2.27 2.27 6.51 5.87 ns 2.39 0.18 1.08 1.34 0.66 2.44 1.88 2.53 2.76 6.03 5.47 ns 0.97 2.12 0.18 1.08 1.34 0.66 2.17 1.69 2.71 3.08 5.76 5.28 ns Std. 0.97 2.08 0.18 1.08 1.34 0.66 2.12 1.65 2.75 3.17 5.72 5.25 ns Std. 0.97 2.10 0.18 1.08 1.34 0.66 2.14 1.60 2.80 3.49 5.74 5.20 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 2 v2.0 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-37 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 4 mA Std. 1.55 5.54 0.26 1.31 1.58 1.10 5.63 4.53 2.79 2.87 11.42 10.32 ns 8 mA Std. 1.55 4.60 0.26 1.31 1.58 1.10 4.67 3.94 3.09 3.45 10.45 9.73 ns 12 mA Std. 1.55 3.93 0.26 1.31 1.58 1.10 3.99 3.51 3.28 3.82 9.77 9.29 ns 16 mA Std. 1.55 3.74 0.26 1.31 1.58 1.10 3.79 3.41 3.32 3.92 9.58 9.20 ns 24 mA Std. 1.55 3.64 0.26 1.31 1.58 1.10 3.69 3.42 3.38 4.30 9.48 9.21 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-38 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP 4 mA Std. 1.55 3.26 0.26 1.31 1.58 8 mA Std. 1.55 12 mA Std. 16 mA 24 mA tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 1.10 3.33 2.67 2.79 3.01 9.12 8.46 ns 2.77 0.26 1.31 1.58 1.10 2.80 2.24 3.09 3.59 8.59 8.03 ns 1.55 2.47 0.26 1.31 1.58 1.10 2.51 2.04 3.28 3.97 8.29 7.82 ns Std. 1.55 2.42 0.26 1.31 1.58 1.10 2.46 2.00 3.33 4.08 8.24 7.79 ns Std. 1.55 2.45 0.26 1.31 1.58 1.10 2.48 1.95 3.38 4.46 8.26 7.73 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 33 IGLOOe DC and Switching Characteristics 3.3 V LVCMOS Wide Range Table 2-39 * Minimum and Maximum DC Input and Output Levels 3.3 V LVCMOS Wide Range VIL VIH VOL VOH IOL IOH IOSH Max (V) Max. (V) Min. (V) A A Max. (mA)4 IOSL IIL1 IIH2 Equivalent Software Default Drive Drive Strength Strength Option3 Min. (V) 100 A 2 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 TBD TBD 10 10 100 A 4 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 TBD TBD 10 10 100 A 6 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 TBD TBD 10 10 100 A 8 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 TBD TBD 10 10 100 A 12 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 TBD TBD 10 10 100 A 16 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 TBD TBD 10 10 100 A 24 mA -0.3 0.8 2 3.6 0.2 VDD - 0.2 100 100 TBD TBD 10 10 Max. Min. (V) (V) Max. (mA)4 A5 A5 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is larger when operating outside recommended ranges. 3. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 4. Currents are measured at 85C junction temperature. 5. All LVCMOS 3.3 V software macros supports LVCMOS 3.3 V wide range as specified in the JDEC8a specification. 6. Software default selection highlighted in gray. Table 2-40 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF) 3.3 1.4 - 5 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -3 4 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-41 * 3.3 V LVCMOS Wide Range Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Speed Strength Option1 Grade tDOUT tDP 100 A tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 4 mA Std. 0.97 7.26 0.18 1.42 1.84 0.66 7.28 5.78 3.18 2.93 10.88 9.38 ns 100 A 8 mA Std. 0.97 5.94 0.18 1.42 1.84 0.66 5.96 4.96 3.59 3.69 9.56 8.56 ns 100 A 12 mA Std. 0.97 5.00 0.18 1.42 1.84 0.66 5.02 4.34 3.86 4.16 8.62 7.94 ns 100 A 16 mA Std. 0.97 4.73 0.18 1.42 1.84 0.66 4.75 4.21 3.92 4.29 8.35 7.81 ns 100 A 24 mA Std. 0.97 4.59 0.18 1.42 1.84 0.66 4.61 4.23 3.99 4.78 8.21 7.82 ns Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-42 * 3.3 V LVCMOS Wide Range High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Speed Strength Option1 Grade tDOUT tDP tHZ tZLS tZHS Units 100 A 4 mA Std. 0.97 4.10 0.18 1.42 1.84 0.66 4.12 3.17 3.18 3.11 7.71 6.77 ns 100 A 8 mA Std. 0.97 3.37 0.18 1.42 1.84 0.66 3.39 2.57 3.59 3.87 6.99 6.16 ns 100 A 12 mA Std. 0.97 2.96 0.18 1.42 1.84 0.66 2.98 2.28 3.86 4.36 6.58 5.87 ns 100 A 16 mA Std. 0.97 2.90 0.18 1.42 1.84 0.66 2.92 2.22 3.93 4.49 6.51 5.82 ns 100 A 24 mA Std. 0.97 2.92 0.18 1.42 1.84 0.66 2.94 2.15 4.00 4.99 6.54 5.75 ns tDIN tPY tPYS tEOUT tZL tZH tLZ Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray. v2.0 2 - 35 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-43 * 3.3 V LVCMOS Wide Range Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Speed Strength Strength Option1 Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 100 A 4 mA Std. 1.55 8.14 0.26 1.66 2.14 1.10 8.14 6.46 3.80 3.79 13.93 12.25 ns 100 A 8 mA Std. 1.55 6.68 0.26 1.66 2.14 1.10 6.68 5.57 4.25 4.69 12.47 11.36 ns 100 A 12 mA Std. 1.55 5.65 0.26 1.66 2.14 1.10 5.65 4.91 4.55 5.25 11.44 10.69 ns 100 A 16 mA Std. 1.55 5.36 0.26 1.66 2.14 1.10 5.36 4.76 4.61 5.41 11.14 10.55 ns 100 A 24 mA Std. 1.55 5.20 0.26 1.66 2.14 1.10 5.20 4.78 4.69 6.00 10.99 10.56 ns Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-44 * 3.3 V LVCMOS Wide Range High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Speed Drive Strength Grade tDOUT Strength Option1 tDP 100 A 4 mA Std. 1.55 4.65 0.26 1.66 2.14 110 100 A 8 mA Std. 1.55 3.85 0.26 1.66 2.14 tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 4.65 3.64 3.80 4.00 10.44 9.43 ns 1.10 3.85 2.99 4.25 4.91 8.77 ns 9.64 100 A 12 mA Std. 1.55 3.40 0.26 1.66 2.14 1.10 3.40 2.68 4.55 5.49 9.19 8.46 ns 100 A 16 mA Std. 1.55 3.33 0.26 1.66 2.14 1.10 3.33 2.62 4.62 5.65 9.11 8.41 ns 100 A 24 mA Std. 1.55 3.36 0.26 1.66 2.14 1.10 3.36 2.54 4.71 6.24 9.15 8.32 ns Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 3. Software default selection highlighted in gray. 2 -3 6 v2.0 IGLOOe DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. It uses a 5 V-tolerant input buffer and push-pull output buffer. Table 2-45 * Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSH IIL1 IIH2 IOSL Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 4 mA -0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 8 mA -0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 12 mA -0.3 0.7 1.7 3.6 0.7 1.7 12 12 65 74 10 10 16 mA -0.3 0.7 1.7 3.6 0.7 1.7 16 16 83 87 10 10 24 mA -0.3 0.7 1.7 3.6 0.7 1.7 24 24 169 124 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-8 * AC Loading Table 2-46 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF) 2.5 1.2 - 5 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. v2.0 2 - 37 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-47 * 2.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tHZ tZLS tZHS Units 4 mA Std. 0.97 5.55 0.18 1.31 1.41 tDIN tPY tPYS tEOUT 0.66 5.66 4.75 2.28 1.96 tZL tZH tLZ 9.26 8.34 ns 8 mA Std. 0.97 4.58 0.18 1.31 1.41 0.66 4.67 4.07 2.58 2.53 8.27 7.66 ns 12 mA Std. 0.97 3.89 0.18 1.31 1.41 0.66 3.97 3.58 2.78 2.91 7.56 7.17 ns 16 mA Std. 0.97 3.68 0.18 1.31 1.41 0.66 3.75 3.47 2.82 3.01 7.35 7.06 ns 24 mA Std. 0.97 3.59 0.18 1.31 1.41 0.66 3.66 3.48 2.88 3.37 7.26 7.08 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-48 * 2.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP 4 mA Std. 0.97 2.94 0.18 1.31 1.41 8 mA Std. 0.97 12 mA Std. 16 mA 24 mA tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 0.66 3.00 2.68 2.28 2.03 6.60 6.27 ns 2.45 0.18 1.31 1.41 0.66 2.50 2.12 2.58 2.62 6.10 5.72 ns 0.97 2.15 0.18 1.31 1.41 0.66 2.20 1.85 2.78 2.98 5.80 5.45 ns Std. 0.97 2.10 0.18 1.31 1.41 0.66 2.15 1.80 2.82 3.08 5.75 5.40 ns Std. 0.97 2.11 0.18 1.31 1.41 0.66 2.16 1.74 2.88 3.47 5.75 5.33 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 8 v2.0 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-49 * 2.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 4 mA Std. 1.55 6.25 0.26 1.55 1.77 1.10 6.36 5.34 2.81 2.63 12.14 11.13 ns 8 mA Std. 1.55 5.18 0.26 1.55 1.77 1.10 5.26 4.61 3.13 3.32 11.05 10.39 ns 12 mA Std. 1.55 4.42 0.26 1.55 1.77 1.10 4.49 4.08 3.36 3.76 10.28 9.86 ns 16 mA Std. 1.55 4.19 0.26 1.55 1.77 1.10 4.25 3.96 3.40 3.89 10.04 9.75 ns 24 mA Std. 1.55 4.09 0.26 1.55 1.76 1.10 4.15 3.97 3.47 4.32 9.76 ns 9.94 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-50 * 2.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 4 mA Std. 1.55 3.38 0.26 1.55 1.77 1.10 3.42 3.11 2.81 2.72 9.21 8.89 ns 8 mA Std. 1.55 2.83 0.26 1.55 1.77 1.10 2.87 2.51 3.13 3.42 8.66 8.30 ns 12 mA Std. 1.55 2.51 0.26 1.55 1.77 1.10 2.54 2.22 3.36 3.85 8.33 8.00 ns 16 mA Std. 1.55 2.45 0.26 1.55 1.77 1.10 2.48 2.16 3.40 3.97 8.27 7.95 ns 24 mA Std. 1.55 2.46 0.26 1.55 1.77 1.10 2.49 2.09 3.47 4.44 8.28 7.88 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 39 IGLOOe DC and Switching Characteristics 1.8 V LVCMOS Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-51 * Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS VIL Drive Strength Min., V 2 mA -0.3 VIH Max., V Min., V VOL VOH Max., V Max., V Min., V IOL IOH IOSH IIL1 IIH2 IOSL mA mA Max., mA3 Max., mA3 A4 A4 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 2 2 9 11 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 4 4 17 22 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 6 6 35 44 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 8 8 45 51 10 10 12 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 12 12 91 74 10 10 16 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 16 16 91 74 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-9 * AC Loading Table 2-52 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF) 1.8 0.9 - 5 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -4 0 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-53 * 1.8 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 2 mA Std. 0.97 7.33 0.18 1.27 1.59 0.66 7.47 6.18 2.34 1.18 11.07 9.77 ns 4 mA Std. 0.97 6.07 0.18 1.27 1.59 0.66 6.20 5.25 2.69 2.42 8.84 ns 9.79 6 mA Std. 0.97 5.18 0.18 1.27 1.59 0.66 5.29 4.61 2.93 2.88 8.88 8.21 ns 8 mA Std. 0.97 4.88 0.18 1.27 1.59 0.66 4.98 4.48 2.99 3.01 8.58 8.08 ns 12 mA Std. 0.97 4.80 0.18 1.27 1.59 0.66 4.89 4.49 3.07 3.47 8.49 8.09 ns 16 mA Std. 0.97 4.80 0.18 1.27 1.59 0.66 4.89 4.49 3.07 3.47 8.49 8.09 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-54 * 1.8 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 2 mA Std. 0.97 3.43 0.18 1.27 1.59 0.66 3.51 3.39 2.33 1.19 7.10 6.98 ns 4 mA Std. 0.97 2.83 0.18 1.27 1.59 0.66 2.89 2.59 2.69 2.49 6.48 6.18 ns 6 mA Std. 0.97 2.45 0.18 1.27 1.59 0.66 2.51 2.19 2.93 2.95 6.10 5.79 ns 8 mA Std. 0.97 2.38 0.18 1.27 1.59 0.66 2.43 2.12 2.98 3.08 6.03 5.71 ns 12 mA Std. 0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns 16 mA Std. 0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v2.0 2 - 41 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-55 * 1.8 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 2 mA Std. 1.55 8.21 0.26 1.53 1.96 1.10 8.35 6.88 2.87 1.70 14.14 12.67 ns 4 mA Std. 1.55 6.83 0.26 1.53 1.96 1.10 6.94 5.88 3.27 3.18 12.73 11.67 ns 6 mA Std. 1.55 5.85 0.26 1.53 1.96 1.10 5.94 5.19 3.53 3.37 11.73 10.98 ns 8 mA Std. 1.55 5.52 0.26 1.53 1.96 1.10 5.61 5.06 3.59 3.88 11.39 10.84 ns 12 mA Std. 1.55 5.42 0.26 1.53 1.96 1.10 5.51 5.06 3.68 4.44 11.30 10.85 ns 16 mA Std. 1.55 5.42 0.26 1.53 1.96 1.10 5.51 5.06 3.68 4.44 11.30 10.85 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-56 * 1.8 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 2 mA Std. 1.55 3.82 0.26 1.53 1.96 1.10 3.98 3.87 2.86 1.72 9.76 9.66 ns 4 mA Std. 1.55 3.25 0.26 1.53 1.96 1.10 3.30 3.01 3.26 3.26 9.08 8.79 ns 6 mA Std. 1.55 2.84 0.26 1.53 1.96 1.10 2.88 2.58 3.53 3.81 8.66 8.37 ns 8 mA Std. 1.55 2.76 0.26 1.53 1.96 1.10 2.80 2.50 3.58 3.97 8.58 8.29 ns 12 mA Std. 1.55 2.75 0.26 1.53 1.96 1.10 2.78 2.40 3.68 4.56 8.57 8.19 ns 16 mA Std. 1.55 2.75 0.26 1.53 1.96 1.10 2.78 2.40 3.68 4.56 8.57 8.19 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2 -4 2 v2.0 IGLOOe DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-57 * Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS VIL Drive Strength Min., V VIH Max., V Min., V Max., V VOL VOH Max., V Min., V IOL IOH IOSH IIL1 IIH2 IOSL mA mA Max., mA3 Max., mA3 A4 A4 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 6 6 32 39 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 8 8 66 55 10 10 12 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 66 55 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-10 * AC Loading Table 2-58 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF) 1.5 0.75 - 5 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. v2.0 2 - 43 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-59 * 1.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 2 mA Std. 0.97 7.61 0.18 1.47 1.77 0.66 7.76 6.33 2.81 2.34 11.36 9.92 ns 4 mA Std. 0.97 6.54 0.18 1.47 1.77 0.66 6.67 5.56 3.09 2.88 10.26 9.16 ns 6 mA Std. 0.97 6.15 0.18 1.47 1.77 0.66 6.27 5.42 3.15 3.02 9.87 9.02 ns 8 mA Std. 0.97 6.07 0.18 1.47 1.77 0.66 6.20 5.42 2.64 3.56 9.79 9.02 ns 12 mA Std. 0.97 6.07 0.18 1.47 1.77 0.66 6.20 5.42 2.64 3.56 9.79 9.02 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-60 * 1.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 2 mA Std. 0.97 3.25 0.18 1.47 1.77 0.66 3.32 3.00 2.80 2.43 6.92 6.59 ns 4 mA Std. 0.97 2.81 0.18 1.47 1.77 0.66 2.87 2.51 3.08 2.97 6.46 6.10 ns 6 mA Std. 0.97 2.72 0.18 1.47 1.77 0.66 2.78 2.41 3.14 3.12 6.37 6.01 ns 8 mA Std. 0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns 12 mA Std. 0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -4 4 v2.0 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-61 * 1.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 2 mA Std. 1.55 8.53 0.26 1.72 2.16 1.10 8.67 7.05 3.39 3.09 14.46 12.83 ns 4 mA Std. 1.55 7.34 0.26 1.72 2.16 1.10 7.46 6.22 3.70 3.73 13.25 12.01 ns 6 mA Std. 1.55 6.91 0.26 1.72 2.16 1.10 7.03 6.07 3.77 3.90 12.82 11.85 ns 8 mA Std. 1.55 6.83 0.26 1.72 2.16 1.10 6.94 6.07 2.91 4.54 12.73 11.86 ns 12 mA Std. 1.55 6.83 0.26 1.72 2.16 1.10 6.94 6.07 2.91 4.54 12.73 11.86 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-62 * 1.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 2 mA Std. 1.55 3.72 0.26 1.72 2.16 1.10 3.78 3.45 3.38 3.19 9.56 9.24 ns 4 mA Std. 1.55 3.23 0.26 1.72 2.16 1.10 3.27 2.92 3.69 3.83 9.06 8.71 ns 6 mA Std. 1.55 3.13 0.26 1.72 2.16 1.10 3.18 2.82 3.76 4.01 8.96 8.61 ns 8 mA Std. 1.55 3.10 0.26 1.72 2.16 1.10 3.15 2.70 3.86 4.68 8.93 8.49 ns 12 mA Std. 1.55 3.10 0.26 1.72 2.16 1.10 3.15 2.70 3.86 4.68 8.93 8.49 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 45 IGLOOe DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-63 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.2 V LVCMOS1 VIL Drive Min., Strength V 2 mA -0.3 VIH Max., V Min., V 0.35 * VCCI 0.65 * VCCI Max., V 3.6 VOL VOH Max., V Min., V IOL IOH IOSH IIL2 IIH3 IOSL mA mA Max., mA4 Max., mA4 A5 A5 0.25 * VCCI 0.75 * VCCI 2 2 TBD TBD 10 10 Notes: 1. Applicable to V2 devices ONLY. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is larger when operating outside recommended ranges. 4. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 5. Currents are measured at 85C junction temperature. 6. Software default selection highlighted in gray. Test Point Datapath 5 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-11 * AC Loading Table 2-64 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF) 1.2 0.6 - 5 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -4 6 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.2 V DC Core Voltage Table 2-65 * 1.2 LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 2 mA Speed Grade tDOUT Std. 1.55 tDP tDIN tPY tPYS tEOUT 9.92 0.26 2.09 2.95 1.10 tZL tZH tLZ 9.53 7.48 4.02 tHZ tZLS 3.67 tZHS Units 15.31 13.26 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-66 * 1.2 LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 2 mA Speed Grade tDOUT Std. 1.55 tDP tDIN tPY tPYS tEOUT 4.06 0.26 2.09 2.95 1.10 tZL tZH tLZ 3.92 3.46 4.01 tHZ tZLS tZHS Units 3.79 9.71 9.24 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 1.2 V LVCMOS Wide Range Table 2-67 * Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS Wide Range1 VIL Equivalent Software Default Drive Drive Strength Min. Strength Option4 (V) 100 A 2 mA Max. (V) VIH Min. (V) Max (V) VOL VOH IOL IOH Max. (V) Min. (V) A A -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 100 100 IOSH IOSL IIL2 IIH3 Max. Max. (mA)5 (mA)5 A6 A6 TBD TBD 10 10 Notes: 1. Applicable to V2 devices ONLY. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is larger when operating outside recommended ranges. 4. Note that 1.2 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 5. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 6. Currents are measured at 85C junction temperature. 7. Software default selection highlighted in gray. Timing Characteristics Refer to LVCMOS 1.2 V (normal range) "Timing Characteristics" on page 2-47 for worst-case timing. v2.0 2 - 47 IGLOOe DC and Switching Characteristics 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-68 * Minimum and Maximum DC Input and Output Levels IO 3.3 V PCI/PCI-X Drive Strength VIH VIL Min., V Max., V Min., V Max., V Per PCI specification IOSH IIL1 IOSL IIH2 VOL VOH IOL H Max., V Min., V m A m A Max., mA3 Max., mA3 A4 A4 Per PCI curves 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described in Figure 2-12. R = 25 Test Point Datapath R to VCCI for tDP (F) R to GND for tDP (R) R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 10 pF for tZH /tZHS /tZL /t ZLS 5 pF for tHZ /tLZ Figure 2-12 * AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 2-69. Table 2-69 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF) 3.3 0.285 * VCCI for tDP(R) - 10 0.615 * VCCI for tDP(F) * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -4 8 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-70 * 3.3 V PCI/PCI-X - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade Std. tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 0.97 2.38 0.18 0.96 1.42 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-71 * 3.3 V PCI/PCI-X - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Speed Grade Std. tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 1.55 2.76 0.26 1.19 1.63 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 49 IGLOOe DC and Switching Characteristics Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-72 * Minimum and Maximum DC Input and Output Levels 3.3 V GTL Drive Strength 25 mA5 VIL Min., V -0.3 Max., V VIH Min., V VREF - 0.05 VREF + 0.05 VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 3.6 0.4 - 25 25 268 181 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Output drive strength is below JEDEC specification. VTT GTL 25 Test Point 10 pF Figure 2-13 * AC Loading Table 2-73 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.05 Input High (V) Measuring Point* (V) VREF + 0.05 0.8 VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) 0.8 1.2 10 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -5 0 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-74 * 3.3 V GTL - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 1.83 0.19 2.41 0.67 1.84 1.83 tLZ tHZ tZLS tZHS Units 5.47 5.46 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-75 * 3.3 V GTL - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 2.09 0.26 2.75 1.10 2.10 2.09 tLZ tHZ tZLS tZHS Units 7.91 7.89 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 51 IGLOOe DC and Switching Characteristics 2.5 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-76 * Minimum and Maximum DC Input and Output Levels 2.5 GTL VIL Drive Strength Min., V 25 mA5 -0.3 Max., V VIH Min., V VREF - 0.05 VREF + 0.05 VOL VOH IOL IOH IOSH IOSL IIL1 IIH2 Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 3.6 0.4 - 25 25 169 124 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Output drive strength is below JEDEC specification. VTT GTL 25 Test Point 10 pF Figure 2-14 * AC Loading Table 2-77 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.05 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.05 0.8 0.8 1.2 10 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -5 2 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-78 * 2.5 V GTL - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 1.90 0.19 2.04 0.67 1.94 1.87 tLZ tHZ tZLS tZHS Units 5.57 5.50 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-79 * 2.5 V GTL - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 2.16 0.26 2.35 1.10 2.20 2.13 tLZ tHZ tZLS tZHS Units 8.01 7.94 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 53 IGLOOe DC and Switching Characteristics 3.3 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V Table 2-80 * Minimum and Maximum DC Input and Output Levels 3.3 V GTL+ VIL Drive Strength Min., V Max., V 35 mA -0.3 VIH Min., V VREF - 0.1 VREF + 0.1 VOL VOH IOL IOH IOSH IOSL IIL1 IIH2 Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 3.6 0.6 - 35 35 268 181 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. VTT GTL+ 25 Test Point 10 pF Figure 2-15 * AC Loading Table 2-81 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.1 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 1.0 1.0 1.5 10 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -5 4 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-82 * 3.3 V GTL+ - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.0 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 1.85 0.19 1.35 0.67 1.88 1.81 tLZ tHZ tZLS tZHS Units 5.51 5.44 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-83 * 3.3 V GTL+ - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.0 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 2.11 0.26 1.61 1.10 2.15 2.07 tLZ tHZ tZLS tZHS Units 7.95 7.88 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 55 IGLOOe DC and Switching Characteristics 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-84 * Minimum and Maximum DC Input and Output Levels 2.5 V GTL+ VIL Drive Strength Min., V Max., V 33 mA -0.3 VIH Min., V VREF - 0.1 VREF + 0.1 VOL VOH IOL IOH IOSH IOSL IIL1 IIH2 Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 3.6 0.6 - 33 33 169 124 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. VTT GTL+ 25 Test Point 10 pF Figure 2-16 * AC Loading Table 2-85 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.1 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 1.0 1.0 1.5 10 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -5 6 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-86 * 2.5 V GTL+ - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V VREF = 1.0 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 1.97 0.19 1.29 0.67 2.00 1.84 tLZ tHZ tZLS tZHS Units 5.63 5.47 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-87 * 2.5 V GTL+ - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V VREF = 1.0 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 2.23 0.26 1.55 1.10 2.28 2.11 tLZ tHZ tZLS tZHS Units 8.08 7.91 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 57 IGLOOe DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-88 * Minimum and Maximum DC Input and Output Levels HSTL Class I VIL Drive Strength Min., V Max., V 8 mA -0.3 VIH VOL VOH IOL IOH IOSH IOSL IIL1 IIH2 Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 Min., V VREF - 0.1 VREF + 0.1 3.6 0.4 VCCI - 0.4 8 8 32 39 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. HSTL Class I VTT 50 Test Point 20 pF Figure 2-17 * AC Loading Table 2-89 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.1 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 0.75 0.75 0.75 20 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -5 8 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-90 * HSTL Class I - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 2.74 0.19 1.77 0.67 2.79 2.73 tLZ tHZ tZLS tZHS Units 6.42 6.36 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-91 * HSTL Class I - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 3.10 0.26 1.94 1.10 3.12 3.10 tLZ tHZ tZLS tZHS Units 8.93 8.91 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 59 IGLOOe DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-92 * Minimum and Maximum DC Input and Output Levels HSTL Class II VIL Drive Strength Min., V Max., V 15 mA5 -0.3 VIH VOL VOH IOL IOH IOSH IOSL IIL1 IIH2 Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 Min., V VREF - 0.1 VREF + 0.1 3.6 0.4 VCCI - 0.4 15 15 66 55 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Output drive strength is below JEDEC specification. HSTL Class II VTT 25 Test Point 20 pF Figure 2-18 * AC Loading Table 2-93 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.1 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.1 0.75 0.75 0.75 20 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -6 0 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-94 * HSTL Class II - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 2.62 0.19 1.77 0.67 2.66 2.40 tLZ tHZ tZLS tZHS Units 6.29 6.03 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-95 * HSTL Class II - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 2.93 0.26 1.94 1.10 2.98 2.75 tLZ tHZ tZLS tZHS Units 8.79 8.55 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 61 IGLOOe DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-96 * Minimum and Maximum DC Input and Output Levels SSTL2 Class I VIL Drive Strength Min., V Max., V 15 mA -0.3 VIH VOL Min., V Max., V Max., V VREF - 0.2 VREF + 0.2 3.6 0.54 VOH Min., V IOL IOH IOSH IOSL IIL1 IIH2 mA mA Max., mA3 Max., mA3 A4 A4 VCCI - 0.62 15 15 83 87 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. SSTL2 Class I VTT 50 Test Point 25 30 pF Figure 2-19 * AC Loading Table 2-97 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.2 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.25 1.25 1.25 30 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -6 2 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-98 * SSTL 2 Class I - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 1.91 0.19 1.15 0.67 1.94 1.72 tLZ tHZ tZLS tZHS Units 5.57 5.35 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-99 * SSTL 2 Class I - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 2.17 0.26 1.39 1.10 2.21 2.04 tLZ tHZ tZLS tZHS Units 8.02 7.84 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 63 IGLOOe DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-100 * Minimum and Maximum DC Input and Output Levels SSTL2 Class II VIL Drive Strength Min., V Max., V 18 mA -0.3 VIH Min., V VREF - 0.2 VREF + 0.2 VOL Max., V Max., V 3.6 0.35 VOH Min., V IOL IOH IOSH IOSL IIL1 IIH2 mA mA Max., mA3 Max., mA3 A4 A4 VCCI - 0.43 18 18 169 124 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. SSTL2 Class II VTT 25 Test Point 25 30 pF Figure 2-20 * AC Loading Table 2-101 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.2 Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.25 1.25 1.25 30 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -6 4 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-102 * SSTL 2 Class II - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 1.94 0.19 1.15 0.67 1.97 1.66 tLZ tHZ tZLS tZHS Units 5.60 5.29 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-103 * SSTL 2 Class II - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 2.20 0.26 1.39 1.10 2.24 1.97 tLZ tHZ tZLS tZHS Units 8.05 7.78 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 65 IGLOOe DC and Switching Characteristics SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-104 * Minimum and Maximum DC Input and Output Levels SSTL3 Class I VIL Drive Strength Min., V Max., V 14 mA -0.3 VIH VOL VOH IOL IOH IOSH IOSL IIL1 IIH2 Min., V Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCI - 1.1 14 14 51 54 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. SSTL3 Class I VTT 50 Test Point 25 30 pF Figure 2-21 * AC Loading Table 2-105 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.2 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.5 1.5 1.485 30 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -6 6 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-106 * SSTL 3 Class I - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 2.05 0.19 1.09 0.67 2.09 1.71 tLZ tHZ tZLS tZHS Units 5.72 5.34 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-107 * SSTL 3 Class I - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 2.32 0.26 1.32 1.10 2.37 2.02 tLZ tHZ tZLS tZHS Units 8.17 7.83 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 67 IGLOOe DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-108 * Minimum and Maximum DC Input and Output Levels SSTL3 Class II Drive Strength VIL Min., V Max., V 21 mA -0.3 VIH Min., V VREF - 0.2 VREF + 0.2 VOL VOH IOL IOH IOSH IOSL IIL1 IIH2 Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 3.6 0.5 VCCI - 0.9 21 21 103 109 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. SSTL3 Class II VTT 25 Test Point 25 30 pF Figure 2-22 * AC Loading Table 2-109 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF - 0.2 Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF + 0.2 1.5 1.5 1.485 30 Note: Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. 2 -6 8 v2.0 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-110 * SSTL 3 Class II - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 0.98 1.86 0.19 1.09 0.67 1.89 1.58 tLZ tHZ tZLS tZHS Units 5.52 5.21 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-111 * SSTL 3 Class II - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Speed Grade Std. tDOUT tDP tDIN tPY tEOUT tZL tZH 1.55 2.12 0.26 1.32 1.10 2.16 1.89 tLZ tHZ tZLS tZHS Units 7.97 7.70 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 69 IGLOOe DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by the Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, IGLOOe also supports Bus LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes). Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 140 N Z0 = 50 165 Figure 2-23 * LVDS Circuit Diagram and Board-Level Implementation 2 -7 0 P Z0 = 50 v2.0 FPGA + - 100 N INBUF_LVDS IGLOOe DC and Switching Characteristics Table 2-112 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units 2.375 2.5 2.625 V 0.9 1.075 1.25 V Output High Voltage 1.25 1.425 1.6 V Output Lower Current 0.65 0.91 1.16 mA IOH1 Output High Current 0.65 0.91 1.16 mA VI Input Voltage IIH2,3 Input High Leakage Current IIL2,4 Input Low Leakage Current VODIFF Differential Output Voltage VOCM VCCI Supply Voltage VOL Output Low Voltage VOH IOL1 0 2.925 V 10 A 10 A 250 350 450 mV Output Common Mode Voltage 1.125 1.25 1.375 V VICM Input Common Mode Voltage 0.05 1.25 2.35 VIDIFF Input Differential Voltage 100 350 V mV Notes: 1. IOL /IOH is defined by VODIFF /(resistor network). 2. Currents are measured at 85C junction temperature. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. IIL is the input leakage current per I/O pin over recommended operating conditions where -0.3 V < VIN < VIL. Table 2-113 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) 1.325 Cross point - 1.075 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-114 * LVDS - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade Std. tDOUT tDP tDIN tPY Units 0.98 1.77 0.19 1.62 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-115 * LVDS - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Speed Grade Std. tDOUT tDP tDIN tPY Units 1.55 2.19 0.26 1.88 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 71 IGLOOe DC and Switching Characteristics B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-24. The input and output buffer delays are available in the LVDS section in Table 2-114 on page 2-71 and Table 2-115 on page 2-71. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5"). Receiver Transceiver EN R + RS Zstub Driver D EN T - + RS RS Zstub Zstub - RS Zstub Zstub EN Transceiver EN R - + RS Receiver + RS RS Zstub Zstub EN T - + RS Zstub RS BIBUF_LVDS - RS ... Z0 Z0 Z0 Z0 Z0 Z0 RT Z 0 Z0 Z0 Z0 Z0 Z0 RT Figure 2-24 * B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-25. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different. Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 Z0 = 50 187 W N 100 P Figure 2-25 * LVPECL Circuit Diagram and Board-Level Implementation 2 -7 2 v2.0 + - 100 Z0 = 50 FPGA N INBUF_LVPECL IGLOOe DC and Switching Characteristics Table 2-116 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Max. Min. Max. Min. Max. Units VCCI Supply Voltage VOL Output Low Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V VOH Output High Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V VIL, VIH Input Low, Input High Voltages 0 3.3 0 3.6 0 3.9 V VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V VOCM Output Common Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V VICM Input Common Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V VIDIFF Input Differential Voltage 300 3.0 3.3 3.6 300 V 300 mV Table 2-117 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) 1.94 Cross point - 1.64 * Measuring point = Vtrip. See Table 2-22 on page 2-23 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-118 * LVPECL - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade Std. tDOUT tDP tDIN tPY Units 0.98 1.75 0.19 1.45 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-119 * LVPECL - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Speed Grade Std. tDOUT tDP tDIN tPY Units 1.55 2.16 0.26 1.70 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 73 IGLOOe DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF Preset L DOUT Data_out E F Y Core Array G PRE D Q DFN1E1P1 TRIBUF CLKBUF CLK INBUF Enable PRE D Q C DFN1E1P1 INBUF Data E E EOUT B H I A J K INBUF INBUF D_Enable CLK CLKBUF Enable Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered Figure 2-26 * Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset 2 -7 4 v2.0 Pad Out D IGLOOe DC and Switching Characteristics Table 2-120 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register H, DOUT tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOSUE Enable Setup Time for the Output Data Register G, H tOHE Enable Hold Time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOESUE Enable Setup Time for the Output Enable Register K, H tOEHE Enable Hold Time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tISUE Enable Setup Time for the Input Data Register B, A tIHE Enable Hold Time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A L, DOUT H, EOUT I, EOUT * See Figure 2-26 on page 2-74 for more information. v2.0 2 - 75 IGLOOe DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D CC Core Array Q DFN1E1C1 EE D Q DFN1E1C1 TRIBUF INBUF Data Data_out FF GG INBUF Enable BB EOUT E E CLR CLR LL INBUF CLR CLKBUF CLK HH AA JJ DD D Q DFN1E1C1 KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered E INBUF CLKBUF CLK Enable INBUF D_Enable CLR Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-27 * Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear 2 -7 6 v2.0 Pad Out DOUT Y IGLOOe DC and Switching Characteristics Table 2-121 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOSUE Enable Setup Time for the Output Data Register GG, HH tOHE Enable Hold Time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOESUE Enable Setup Time for the Output Enable Register KK, HH tOEHE Enable Hold Time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tISUE Enable Setup Time for the Input Data Register BB, AA tIHE Enable Hold Time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA LL, DOUT HH, EOUT * See Figure 2-27 on page 2-76 for more information. v2.0 2 - 77 IGLOOe DC and Switching Characteristics Input Register tICKMPWH tICKMPWL CLK 50% 50% Enable 50% 1 50% 50% 50% tIHD tISUD Data 50% 50% 50% 0 tIREMPRE tIRECPRE tIWPRE 50% tIHE Preset tISUE 50% 50% 50% tIWCLR 50% Clear tIRECCLR tIREMCLR 50% 50% tIPRE2Q 50% Out_1 50% tICLR2Q 50% tICLKQ Figure 2-28 * Input Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-122 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Std. Units tICLKQ Clock-to-Q of the Input Data Register Description 0.42 ns tISUD Data Setup Time for the Input Data Register 0.47 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.67 ns tIHE Enable Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.79 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.79 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -7 8 v2.0 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-123 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units 0.68 ns tICLKQ Clock-to-Q of the Input Data Register tISUD Data Setup Time for the Input Data Register 0.97 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tISUE Enable Setup Time for the Input Data Register 1.02 ns tIHE Enable Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 1.19 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 1.19 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 79 IGLOOe DC and Switching Characteristics Output Register tOCKMPWH tOCKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOSUD tOHD 1 Data_out Enable 50% 50% 0 50% tOWPRE tOHE Preset tOSUE tOREMPRE tORECPRE 50% 50% 50% tOWCLR 50% Clear tORECCLR 50% tOREMCLR 50% tOPRE2Q 50% DOUT 50% tOCLR2Q 50% tOCLKQ Figure 2-29 * Output Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-124 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 1.00 ns tOSUD Data Setup Time for the Output Data Register 0.51 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.70 ns tOHE Enable Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.34 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.34 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -8 0 v2.0 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-125 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units 1.52 ns tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register 1.15 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOSUE Enable Setup Time for the Output Data Register 1.11 ns tOHE Enable Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.96 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.96 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 81 IGLOOe DC and Switching Characteristics Output Enable Register tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% CLK tOESUD tOEHD 1 D_Enable Enable Preset 50% 0 50% 50% tOEWPRE 50% tOESUEtOEHE tOEREMPRE tOERECPRE 50% 50% tOEWCLR 50% tOERECCLR tOEREMCLR 50% 50% Clear EOUT 50% tOEPRE2Q tOECLR2Q 50% 50% tOECLKQ Figure 2-30 * Output Enable Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-126 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.75 ns tOESUD Data Setup Time for the Output Enable Register 0.51 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.73 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 1.13 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 1.13 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -8 2 v2.0 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-127 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units 1.10 ns tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register 1.15 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 1.22 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 1.65 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 1.65 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 83 IGLOOe DC and Switching Characteristics DDR Module Specifications Input DDR Module Input DDR INBUF Data A D Out_QF (to core) E Out_QR (to core) FF1 B CLK CLKBUF FF2 C CLR INBUF DDR_IN Figure 2-31 * Input DDR Timing Model Table 2-128 * Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B 2 -8 4 v2.0 IGLOOe DC and Switching Characteristics CLK tDDRISUD Data 1 2 3 4 5 tDDRIHD 6 7 8 9 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF 2 6 4 tDDRICLKQ2 tDDRICLR2Q2 Out_QR 3 5 7 Figure 2-32 * Input DDR Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-129 * Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.48 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.65 ns tDDRISUD1 Data Setup for Input DDR (negedge) 0.50 ns tDDRISUD2 Data Setup for Input DDR (posedge) 0.40 ns tDDRIHD1 Data Hold for Input DDR (negedge) 0.00 ns tDDRIHD2 Data Hold for Input DDR (posedge) 0.00 ns tDDRICLR2Q1 Asynchronous Clear to Out Out_QR for Input DDR 0.82 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.98 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.23 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.31 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.28 ns FDDRIMAX Maximum Frequency for Input DDR MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v2.0 2 - 85 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-130 * Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.76 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.94 ns tDDRISUD1 Data Setup for Input DDR (negedge) 0.93 ns tDDRISUD2 Data Setup for Input DDR (posedge) 0.84 ns tDDRIHD1 Data Hold for Input DDR (negedge) 0.00 ns tDDRIHD2 Data Hold for Input DDR (posedge) 0.00 ns tDDRICLR2Q1 Asynchronous Clear to Out Out_QR for Input DDR 1.23 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 1.42 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.24 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.31 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.28 ns FDDRIMAX Maximum Frequency for Input DDR MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2 -8 6 v2.0 IGLOOe DC and Switching Characteristics Output DDR Module Output DDR A X Data_F (from core) FF1 Out B CLK 0 X CLKBUF C D Data_R (from core) E X 1 X X OUTBUF FF2 B CLR INBUF C X X DDR_OUT Figure 2-33 * Output DDR Timing Model Table 2-131 * Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B v2.0 2 - 87 IGLOOe DC and Switching Characteristics CLK tDDROSUD2 tDDROHD2 Data_F 1 2 tDDROREMCLR Data_R 6 4 3 5 tDDROHD1 7 8 9 10 11 tDDRORECCLR CLR tDDROREMCLR tDDROCLR2Q Out tDDROCLKQ 7 2 Figure 2-34 * Output DDR Timing Diagram 2 -8 8 v2.0 8 3 9 4 10 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-132 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR Description 1.07 ns tDDROSUD1 Data_F Data Setup for Output DDR 0.67 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.67 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 1.38 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.23 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.31 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.28 ns FDDOMAX Maximum Frequency for the Output DDR MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-133 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR Description 1.60 ns tDDROSUD1 Data_F Data Setup for Output DDR 1.09 ns tDDROSUD2 Data_R Data Setup for Output DDR 1.16 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 1.99 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.24 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.31 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.28 ns FDDOMAX Maximum Frequency for the Output DDR MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 89 IGLOOe DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOOe library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. A A A OR2 NOR2 Y A AND2 A Y NAND2 B A B C XOR2 Y A NAND3 B MUX2 B C v2.0 Y 0 Y Figure 2-35 * Sample of Combinatorial Cells XOR3 A MAJ3 S 2 -9 0 Y B A A B C Y B B B Y INV 1 Y IGLOOe DC and Switching Characteristics tPD Fanout = 4 A Net NAND2 or Any Combinatorial Logic Length = 1 VersaTile B A Net Y NAND2 or Any Combinatorial Logic Length = 1 VersaTile B Y tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for a particular combinatorial cell A Net Y NAND2 or Any Combinatorial Logic Length = 1 VersaTile B A Net Y NAND2 or Any Combinatorial Logic Length = 1 VersaTile B VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND VCC tPD tPD (FF) (RR) tPD OUT (FR) 50% tPD (RF) 50% GND Figure 2-36 * Timing Model and Waveforms v2.0 2 - 91 IGLOOe DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-134 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter Std. Units Y = !A tPD 0.80 ns Y=A*B tPD 0.84 ns Y = !(A * B) tPD 0.90 ns Y=A+B tPD 1.19 ns NOR2 Y = !(A + B) tPD 1.10 ns XOR2 Y=AB tPD 1.37 ns MAJ3 Y = MAJ(A , B, C) tPD 1.33 ns XOR3 Y=ABC tPD 1.79 ns MUX2 Y = A !S + B S tPD 1.48 ns AND3 Y=A*B*C tPD 1.21 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-135 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter Std. Units Y = !A tPD 1.35 ns Y=A*B tPD 1.42 ns Y = !(A * B) tPD 1.58 ns Y=A+B tPD 2.10 ns NOR2 Y = !(A + B) tPD 1.94 ns XOR2 Y=AB tPD 2.33 ns MAJ3 Y = MAJ(A , B, C) tPD 2.34 ns XOR3 Y=ABC tPD 3.05 ns MUX2 Y = A !S + B S tPD 2.64 ns AND3 Y=A*B*C tPD 2.10 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2 -9 2 v2.0 IGLOOe DC and Switching Characteristics VersaTile Specifications as a Sequential Module The IGLOOe library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. Data D Q Out Data Out D En DFN1 CLK Q DFN1E1 CLK PRE Data D Q Out Data En DFN1C1 D Q Out DFI1E1P1 CLK CLK CLR Figure 2-37 * Sample of Sequential Cells v2.0 2 - 93 IGLOOe DC and Switching Characteristics tCKMPWH tCKMPWL CLK 50% 50% tSUD 50% Data 50% 50% 50% 50% 50% tHD 50% 0 EN 50% PRE tRECPRE tWPRE tSUE tHE 50% tREMPRE 50% 50% 50% CLR tPRE2Q 50% Out tREMCLR tRECCLR tWCLR 50% 50% tCLR2Q 50% 50% tCLKQ Figure 2-38 * Timing Model and Waveforms Timing Characteristics 1.5 V DC Core Voltage Table 2-136 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Std. Units tCLKQ Clock-to-Q of the Core Register Description 0.89 ns tSUD Data Setup Time for the Core Register 0.81 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 0.73 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.60 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.62 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.23 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.56 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -9 4 v2.0 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-137 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tCLKQ Clock-to-Q of the Core Register 1.61 ns tSUD Data Setup Time for the Core Register 1.17 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 1.29 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.87 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.89 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.24 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.46 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.46 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.95 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.95 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 - 95 IGLOOe DC and Switching Characteristics Global Resource Characteristics AGLE600 Clock Tree Topology Clock delays are device-specific. Figure 2-39 is an example of a global tree used for clock routing. The global tree presented in Figure 2-39 is driven by a CCC located on the west side of the AGLE600 device. It is used to drive all D-flip-flops in the device. Central Global Rib CCC VersaTile Rows Global Spine Figure 2-39 * Example of Global Tree Use in an AGLE600 Device for Clock Routing 2 -9 6 v2.0 IGLOOe DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard-dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-99. Table 2-138 and Table 2-140 present minimum and maximum global clock delays within the device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics 1.5 V DC Core Voltage Table 2-138 * AGLE600 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input LOW Delay for Global Clock 1.48 1.82 ns tRCKH Input HIGH Delay for Global Clock 1.52 1.94 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.42 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-139 * AGLE3000 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Std. Parameter Description 1 Min. Max.2 Units tRCKL Input LOW Delay for Global Clock 2.00 2.34 ns tRCKH Input HIGH Delay for Global Clock 2.09 2.51 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock tRCKMPWL Minimum Pulse Width LOW for Global Clock tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock ns ns 0.42 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v2.0 2 - 97 IGLOOe DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-140 * AGLE600 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input LOW Delay for Global Clock 2.22 2.67 ns tRCKH Input HIGH Delay for Global Clock 2.32 2.93 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock tRCKMPWL Minimum Pulse Width LOW for Global Clock tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock ns ns 0.61 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Table 2-141 * AGLE3000 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Std. Parameter Description 1 Min. Max.2 Units tRCKL Input LOW Delay for Global Clock 2.83 3.27 ns tRCKH Input HIGH Delay for Global Clock 3.00 3.61 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.61 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2 -9 8 v2.0 IGLOOe DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-142 * IGLOOe CCC/PLL Specification For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage Parameter Min. Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Typ. Max. Units 1.5 250 MHz 0.75 250 MHz 100 MHz Serial Clock (SCLK) for Dynamic PLL1 Delay Increments in Programmable Delay Blocks 2, 3 360 ps Number of Programmable Values in Each Programmable Delay Block 32 Input Cycle-to-Cycle Jitter (peak magnitude) 1 ns Max Peak-to-Peak Period Jitter CCC Output Peak-to-Peak Period Jitter FCCC_OUT 1 Global Network Used External FB Used 3 Global Networks Used 0.75 MHz to 24 MHz 0.50% 0.75% 0.70% 24 MHz to 100 MHz 1.00% 1.50% 1.20% 100 MHz to 250 MHz 2.50% 3.75% 2.75% Acquisition Time LockControl = 0 300 s LockControl = 1 6.0 ms LockControl = 0 2.5 ns LockControl = 1 1.5 ns Tracking Jitter Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 2, 3, 4 1.25 15.65 ns Delay Range in Block: Programmable Delay 2 2, 3, 4 0.469 15.65 ns Delay Range in Block: Fixed Delay 2, 3 3.5 ns Notes: 1. Maximum value obtained for a Std. speed grade device in Worst Case Commercial Conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-6 for deratings. 3. TJ = 25C, VCC = 1.5 V 4. For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the Clock Conditioning Circuits in IGLOO and ProASIC3 Devices chapter of the handbook. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. v2.0 2 - 99 IGLOOe DC and Switching Characteristics Table 2-143 * IGLOOe CCC/PLL Specification For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage Parameter Min. Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Typ. Max. Units 1.5 160 MHz 0.75 160 MHz 60 MHz Serial Clock (SCLK) for Dynamic PLL1 Delay Increments in Programmable Delay Blocks2, 3 580 Number of Programmable Values in Each Programmable Delay Block ps 32 Input Cycle-to-Cycle Jitter (peak magnitude) 0.25 ns Max Peak-to-Peak Period Jitter CCC Output Peak-to-Peak Period Jitter FCCC_OUT 1 Global Network Used External FB Used 3 Global Networks Used 0.75 MHz to 24 MHz 0.50% 0.75% 0.70% 24 MHz to 100 MHz 1.00% 1.50% 1.20% 100 MHz to 160 MHz 2.50% 3.75% 2.75% Acquisition Time LockControl = 0 300 s LockControl = 1 6.0 ms LockControl = 0 4 ns LockControl = 1 3 ns 48.5 51.5 % 2.3 20.86 ns 0.863 20.86 ns Tracking Jitter Output Duty Cycle 2, 3 Delay Range in Block: Programmable Delay 1 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay 2, 3 2, 3 5.7 ns Notes: 1. Maximum value obtained for a Std. speed grade device in Worst Case Commercial Conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-6 for deratings. 3. TJ = 25C, VCC = 1.5 V 4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. 2 -1 0 0 v2.0 IGLOOe DC and Switching Characteristics Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min. Figure 2-40 * Peak-to-Peak Jitter Definition v2.0 2 -101 IGLOOe DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM RAM4K9 RAM512X18 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA PIPE REN RCLK ADDRB11 ADDRB10 DOUTB8 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WEN WCLK RESET RESET Figure 2-41 * RAM Models 2 -1 0 2 v2.0 IGLOOe DC and Switching Characteristics Timing Waveforms tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS tENH WEN_B tCKQ1 DO Dn D0 D1 D2 tDOH1 Figure 2-42 * RAM Read for Pass-Through Output tCYC tCKH tCKL CLK t AS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENH tENS WEN_B tCKQ2 DO Dn D0 D1 tDOH2 Figure 2-43 * RAM Read for Pipelined Output v2.0 2 -103 IGLOOe DC and Switching Characteristics tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS tENH WEN_B tDS DI0 DI tDH DI1 D2 Dn DO Figure 2-44 * RAM Write, Output Retained (WMODE = 0) tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS WEN_B tDS DI0 DI DO (pass-through) DO (pipelined) tDH DI1 Dn DI1 DI0 DI0 Dn Figure 2-45 * RAM Write, Output as Write Data (WMODE = 1) 2 -1 0 4 DI2 v2.0 DI1 IGLOOe DC and Switching Characteristics CLK1 tAS tAH A1 A3 tDS A0 tDH D1 D2 D3 ADD1 DI1 tCCKH CLK2 WEN_B1 WEN_B2 tAS ADD2 A0 DI2 D0 tAH A0 A4 D4 tCKQ1 DO2 (pass-through) Dn D0 tCKQ2 DO2 (pipelined) Dn D0 Figure 2-46 * Write Access after Write onto Same Address v2.0 2 -105 IGLOOe DC and Switching Characteristics CLK1 tAS tAH ADD1 DI1 A0 tDS tDH D0 tWRO A2 A3 D2 D3 CLK2 WEN_B1 WEN_B2 tAS tAH A0 ADD2 A1 A4 tCKQ1 DO2 (pass-through) DO2 (pipelined) Dn D0 tCKQ2 Dn D0 Figure 2-47 * Read Access after Write onto Same Address 2 -1 0 6 D1 v2.0 IGLOOe DC and Switching Characteristics CLK1 tAS tAH A0 ADD1 A1 A0 WEN_B1 tCKQ1 DO1 (pass-through) tCKQ1 D0 Dn D1 tCKQ2 DO1 (pipelined) D0 Dn tCCKH CLK2 tAS tAH ADD2 A0 A1 A3 DI2 D1 D2 D3 WEN_B2 Figure 2-48 * Write Access after Read onto Same Address tCYC tCKH tCKL CLK RESET_B tRSTBQ DO Dm Dn Figure 2-49 * RAM Reset v2.0 2 -107 IGLOOe DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-144 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address Setup Time 0.83 ns tAH Address Hold Time 0.16 ns tENS REN_B, WEN_B Setup Time 0.81 ns tENH REN_B, WEN_B Hold Time 0.16 ns tBKS BLK_B Setup Time 1.65 ns tBKH BLK_B Hold Time 0.16 ns tDS Input Data (DI) Setup Time 0.71 ns tDH Input Data (DI) Hold Time 0.36 ns tCKQ1 Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) 3.53 ns Clock HIGH to New Data Valid on DO (flow-through, WMODE = 1) 3.06 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.81 ns tC2CWWL Address collision clk-to-clk delay for reliable write after write on same address; applicable to closing edge 0.23 ns tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.35 ns tC2CWRH Address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 0.41 ns tRSTBQ RESET_B Low to Data Out Low on DO (flow-through) 2.06 ns RESET_B Low to Data Out Low on DO (pipelined) 2.06 ns tREMRSTB RESET_B Removal 0.61 ns tRECRSTB RESET_B Recovery 3.21 ns tMPWRSTB RESET_B Minimum Pulse Width 0.68 ns tCYC Clock Cycle Time 6.24 ns FMAX Maximum Frequency 160 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -1 0 8 v2.0 IGLOOe DC and Switching Characteristics Table 2-145 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Std. Units tAS Address Setup Time Description 0.83 ns tAH Address Hold Time 0.16 ns tENS REN_B, WEN_B Setup Time 0.73 ns tENH REB_B, WEN_B Hold Time 0.08 ns tDS Input Data (DI) Setup Time 0.71 ns tD H Input Data (DI) Hold Time 0.36 ns tCKQ1 Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) 4.21 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.71 ns tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.35 ns tC2CWRH Address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 0.42 ns tRSTBQ RESET_B Low to Data Out Low on DO (flow-through) 2.06 ns RESET_B Low to Data Out Low on DO (pipelined) 2.06 ns tREMRSTB RESET_B Removal 0.61 ns tRECRSTB RESET_B Recovery 3.21 ns tMPWRSTB RESET_B Minimum Pulse Width 0.68 ns tCYC Clock Cycle Time 6.24 ns FMAX Maximum Frequency 160 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v2.0 2 -109 IGLOOe DC and Switching Characteristics Applies to 1.2 V DC Core Voltage Table 2-146 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tAS Address Setup Time 1.53 ns tAH Address Hold Time 0.29 ns tENS REN_B, WEN_B Setup Time 1.50 ns tENH REN_B, WEN_B Hold Time 0.29 ns tBKS BLK_B Setup Time 3.05 ns tBKH BLK_B Hold Time 0.29 ns tDS Input Data (DI) Setup Time 1.33 ns tDH Input Data (DI) Hold Time 0.66 ns tCKQ1 Clock High to New Data Valid on DO (output retained, WMODE = 0) 6.61 ns Clock High to New Data Valid on DO (flow-through, WMODE = 1) 5.72 ns tCKQ2 Clock High to New Data Valid on DO (pipelined) 3.38 ns tC2CWWL Address collision clk-to-clk delay for reliable write after write on same address; applicable to closing edge 0.30 ns tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.89 ns tC2CWRH Address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 1.01 ns tRSTBQ RESET_B Low to Data Out Low on DO (pass-through) 3.86 ns RESET_B Low to Data Out Low on DO (pipelined) 3.86 ns tREMRSTB RESET_B Removal 1.12 ns tRECRSTB RESET_B Recovery 5.93 ns tMPWRSTB RESET_B Minimum Pulse Width 1.18 ns tCYC Clock Cycle Time 10.90 ns FMAX Maximum Frequency 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2 -1 1 0 v2.0 IGLOOe DC and Switching Characteristics Table 2-147 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Std. Units tAS Address Setup Time Description 1.53 ns tAH Address Hold Time 0.29 ns tENS REN_B, WEN_B Setup Time 1.36 ns tENH REB_B, WEN_B Hold Time 0.15 ns tDS Input Data (DI) Setup Time 1.33 ns tD H Input Data (DI) Hold Time 0.66 ns tCKQ1 Clock High to New Data Valid on DO (output retained, WMODE = 0) 7.88 ns tCKQ2 Clock High to New Data Valid on DO (pipelined) 3.20 ns tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.87 ns tC2CWRH Address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 1.04 ns tRSTBQ RESET_B Low to Data Out Low on DO (flow-through) 3.86 ns RESET_B Low to Data Out Low on DO (pipelined) 3.86 ns tREMRSTB RESET_B Removal 1.12 ns tRECRSTB RESET_B Recovery 5.93 ns tMPWRSTB RESET_B Minimum Pulse Width 1.18 ns tCYC Clock Cycle Time 10.90 ns FMAX Maximum Frequency 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. v2.0 2 -111 IGLOOe DC and Switching Characteristics FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-50 * FIFO Model 2 -1 1 2 v2.0 IGLOOe DC and Switching Characteristics Timing Waveforms RCLK/ WCLK tMPWRSTB tRSTCK RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) MATCH (A0) Figure 2-51 * FIFO Reset tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) Figure 2-52 * FIFO EMPTY Flag and AEMPTY Flag Assertion v2.0 2 -113 tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-53 * FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA (Address Counter) RCLK MATCH (EMPTY) NO MATCH 1st Rising Edge After 1st Write NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 2nd Rising Edge After 1st Write tRCKEF EMPTY tCKAF AEMPTY Figure 2-54 * FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA MATCH (FULL) NO MATCH (Address Counter) 1st Rising Edge After 1st WCLK Read NO MATCH NO MATCH NO MATCH Dist = AFF_TH - 1 1st Rising Edge After 2nd Read tWCKF FULL tCKAF AFULL Figure 2-55 * FIFO FULL Flag and AFULL Flag Deassertion IGLOOe DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-148 * FIFO Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description Std. Units tENS REN_B, WEN_B Setup Time 1.99 ns tENH REN_B, WEN_B Hold Time 0.16 ns tBKS BLK_B Setup Time 0.30 ns tBKH BLK_B Hold Time 0.00 ns tDS Input Data (DI) Setup Time 0.76 ns tDH Input Data (DI) Hold Time 0.25 ns tCKQ1 Clock HIGH to New Data Valid on DO (pass-through) 3.33 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.80 ns tRCKEF RCLK HIGH to Empty Flag Valid 3.53 ns tWCKFF WCLK HIGH to Full Flag Valid 3.35 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 12.85 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 3.48 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 12.72 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 2.02 ns RESET_B LOW to Data Out LOW on DO (pipelined) 2.02 ns tREMRSTB RESET_B Removal 0.61 ns tRECRSTB RESET_B Recovery 3.21 ns tMPWRSTB RESET_B Minimum Pulse Width 0.68 ns tCYC Clock Cycle Time 6.24 ns FMAX Maximum Frequency 160 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v2.0 2 -115 IGLOOe DC and Switching Characteristics Applies to 1.2 V DC Core Voltage Table 2-149 * FIFO Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Parameter Description Std. Units tENS REN_B, WEN_B Setup Time 4.13 ns tENH REN_B, WEN_B Hold Time 0.31 ns tBKS BLK_B Setup Time 0.47 ns tBKH BLK_B Hold Time 0.00 ns tDS Input Data (DI) Setup Time 1.56 ns tDH Input Data (DI) Hold Time 0.49 ns tCKQ1 Clock HIGH to New Data Valid on DO (pass-through) 6.80 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 3.62 ns tRCKEF RCLK HIGH to Empty Flag Valid 7.23 ns tWCKFF WCLK HIGH to Full Flag Valid 6.85 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 26.61 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 7.12 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 26.33 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 4.09 ns RESET_B LOW to Data Out LOW on DO (pipelined) 4.09 ns tREMRSTB RESET_B Removal 1.23 ns tRECRSTB RESET_B Recovery 6.58 ns tMPWRSTB RESET_B Minimum Pulse Width 1.18 ns tCYC Clock Cycle Time 10.90 ns FMAX Maximum Frequency 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. 2 -1 1 6 v2.0 IGLOOe DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tSU tHOLD Address tSU tHOLD A0 tHOLD A1 tCKQ2 tCKQ2 D0 Data tCKQ2 D0 D1 Figure 2-56 * Timing Diagram Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-150 * Embedded FlashROM Access Time Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description Std. Units 0.58 ns tSU Address Setup Time tHOLD Address Hold Time 0.00 ns tCK2Q Clock-to-Out 34.14 ns FMAX Maximum Clock Frequency 15 MHz Applies to 1.2 V DC Core Voltage Table 2-151 * Embedded FlashROM Access Time Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Parameter Std. Units tSU Address Setup Time Description 0.59 ns tHOLD Address Hold Time 0.00 ns tCK2Q Clock-to-Out 52.90 ns FMAX Maximum Clock Frequency 10 MHz v2.0 2 -117 IGLOOe DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-16 for more details. Timing Characteristics Applies to 1.2 V DC Core Voltage Table 2-152 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Parameter Std. Units tDISU Test Data Input Setup Time Description 1.50 ns tDIHD Test Data Input Hold Time 3.00 ns tTMSSU Test Mode Select Setup Time 1.50 ns tTMDHD Test Mode Select Hold Time 3.00 ns tTCK2Q Clock to Q (data out) 11.00 ns tRSTB2Q Reset to Q (data out) 30.00 ns FTCKMAX TCK Maximum Frequency 9.00 MHz tTRSTREM ResetB Removal Time 1.18 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values. Applies to 1.5 V DC Core Voltage Table 2-153 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description Std. Units ns tDISU Test Data Input Setup Time 1.00 tDIHD Test Data Input Hold Time 2.00 ns tTMSSU Test Mode Select Setup Time 1.00 ns tTMDHD Test Mode Select Hold Time 2.00 ns tTCK2Q Clock to Q (data out) 8.00 ns tRSTB2Q Reset to Q (data out) 25.00 ns FTCKMAX TCK Maximum Frequency 15.00 MHz tTRSTREM ResetB Removal Time 0.58 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -1 1 8 v2.0 IGLOOe DC and Switching Characteristics Part Number and Revision Date Part Number 51700096-002-4 Revised October 2009 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Advance v0.4 (April 2009) Changes in Current Version (v2.0) Page The version number category changed from Advance to Production, indicating the datasheet contains information based on final characterization. The version number changed from Advance v0.5 to v2.0. N/A 3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V LVCMOS data. N/A IIL and IIH input leakage current information was added to all "Minimum and Maximum DC Input and Output Levels" tables. N/A Values for 1.2 V wide range DC core supply voltage were added to Table 2-2 * Recommended Operating Conditions 1. Table notes regarding 3.3 V wide range and the core voltage required for programming were added to the table. 2-2 The data in Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays (1.5 V DC core supply voltage) and Table 2-7 * Temperature and Voltage Derating Factors for Timing Delays (1.2 V DC core supply voltage) was revised. 2-6 3.3 V LVCMOS wide range data was included in Table 2-12 * Summary of I/O 2-9, 2-10 Input Buffer Power (per pin) - Default I/O Software Settings and Table 2-13 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1. Table notes were added in connection with this data. The temperature was revised from 110C to 100C in Table 2-30 * Duration of Short Circuit Event before Failure and Table 2-32 * I/O Input Rise Time, Fall Time, and Related I/O Reliability*. 2-30, 2-30 The tables in the "Overview of I/O Performance" section and "Detailed I/O DC Characteristics" sectionwere revised to include 3.3 V LVCMOS and 1.2 V LVCMOS wide range. 2-20, 2-27 Most tables were updated in the following sections, revising existing values and adding information for 3.3 V and 1.2 V wide range: 2-31, 2-50, 2-70 "Single-Ended I/O Characteristics" "Voltage-Referenced I/O Characteristics" "Differential I/O Characteristics" Advance v0.3 (July 2008) The value for "Delay range in block: fixed delay" was revised in Table 2-142 * IGLOOe CCC/PLL Specification and Table 2-143 * IGLOOe CCC/PLL Specification. 2-99, 2-100 The timing characteristics tables for RAM4K9 and RAM512X18 were updated, including renaming of the address collision parameters. 2-108 - 2-111 Reference to the -F speed grade was removed from this document, since it is no longer offered for IGLOOe devices. 2-1 v2.0 2 -119 IGLOOe DC and Switching Characteristics Previous Version Changes in Current Version (v2.0) Page Advance v0.2 (June 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. 2-2 Advance v0.1 (January 2008) Tables have been updated to reflect default values in the software. The default I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V I/O set. N/A DDR Tables have two additional data points added to reflect both edges for Input DDR setup and hold time. The power data table has been updated to match SmartPower data rather then simulation values. 2 -1 2 0 Table 2-1 * Absolute Maximum Ratings was updated to add VMV to the VCCI parameter row and remove the word "output" from the parameter description for VCCI. Table note 3 was added. 2-1 Table 2-2 * Recommended Operating Conditions 1 was updated to include the TJ parameter. Table note 9 is new. 2-2 In Table 2-3 * Flash Programming Limits - Retention, Storage, and Operating Temperature1, the maximum operating junction temperature was changed from 110 to 100. 2-3 VMV was removed fromTable 2-4 * Overshoot and Undershoot Limits 1, 3. The title of the table was revised to remove "as measured on quiet I/Os." Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 was deleted. 2-3 The "PLL Behavior at Brownout Condition" section is new. 2-4 Figure 2-2 * V2 Devices - I/O State as a Function of VCCI and VCC Voltage Levels is new. 2-5 EQ 2-2 was updated. The temperature was changed to 100C, and therefore the end result changed. 2-6 The table notes for Table 2-8 * Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode*, Table 2-9 * Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)*, and Table 2-10 * Quiescent Supply Current (IDD), IGLOOe Shutdown Mode (VCC, VCCI = 0 V)* were updated to remove VMV and include PDC6 and PDC7. VCCI and VJTAG were removed from the statement about IDD in the table note for Table 2-9 * Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)*. 2-7 Note 2 of Table 2-11 * Quiescent Supply Current, No IGLOOe Flash*Freeze Mode* was updated to include VCCPLL. Note 4 was updated to include PDC6 and PDC7. 2-8 Table note 3 was added to Table 2-12 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings and referenced for 1.2 V LVCMOS. 2-9 Table 2-13 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 was updated to change PDC3 to PDC7. The table notes were updated to reflect that power was measured on VCCI. Table note 4 is new. 2-10 Table 2-15 * Different Components Contributing to the Static Power Consumption in IGLOO Devices and Table 2-17 * Different Components Contributing to the Static Power Consumption in IGLOO Devices were updated to add PDC6 and PDC7, and to change the definition for PDC5 to bank quiescent power. 2-11, 2-12 v2.0 IGLOOe DC and Switching Characteristics Previous Version Changes in Current Version (v2.0) Page A table subtitle was added for Table 2-17 * Different Components Contributing to the Static Power Consumption in IGLOO Devices 2-12 The "Total Static Power Consumption--PSTAT" section was updated to revise the calculation of PSTAT, including PDC6 and PDC7. 2-13 Footnote 1 was updated to include information about PAC13. The PLL Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to PPLL = PDC4 + PAC13 * FCLKOUT. 2-14 The "Timing Model" was updated to be consistent with the revised timing numbers. 2-16 In Table 2-21 * Summary of Maximum and Minimum DC Input Levels, TJ was changed to TA in notes 1 and 2. 2-22 Table 2-31 * Schmitt Trigger Input Hysteresis was updated to included a hysteresis value for 1.2 V LVCMOS (Schmitt trigger mode). 2-30 All AC Loading figures for single-ended I/O standards were changed from Datapaths at 35 pF to 5 pF. N/A The "1.2 V LVCMOS (JESD8-12A)" section is new. 2-46 Advance v0.4 (December 2007) This document was previously in datasheet Advance v0.4. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is Advance v0.1. N/A Advance v0.3 (September 2007) Table 2-4 * IGLOOe CCC/PLL Specification and Table 2-5 * IGLOOe CCC/PLL Specification were updated. 2-18, 2-19 The "During Flash*Freeze Mode" section was updated to include information about the output of the I/O to the FPGA core. 2-60 Figure 2-38 * Flash*Freeze Mode Type 1 - Timing Diagram was updated to modify the LSICC signal. 2-56 Table 2-32 * Flash*Freeze Pin Location in IGLOOe Family Packages (deviceindependent) was updated for the FG896 package. 2-64 Figure 2-40 * Flash*Freeze Mode Type 2 - Timing Diagram was updated to modify the LSICC Signal. 2-58 Information regarding calculation of the quiescent supply current was added to the "Quiescent Supply Current" section. 3-6 Table 3-8 * Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode was updated. 3-6 Table 3-9 * Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V) was updated. 3-6 Table 3-11 * Quiescent Supply Current, No IGLOOe Flash*Freeze Mode1 was updated. 3-6 Table 3-99 * Minimum and Maximum DC Input and Output Levels was updated. 3-51 Table 3-136 * JTAG 1532 and Table 3-135 * JTAG 1532 were updated. 3-95 The TJ parameter in Table 3-2 * Recommended Operating Conditions was changed to TA, ambient temperature, and table notes 6-8 were added. 3-2 Advance v0.1 (continued) Advance v0.3 (continued) Advance v0.1 v2.0 2 -121 IGLOOe DC and Switching Characteristics Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status datasheet may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. 2 -1 2 2 v2.0 IGLOO(R)e Packaging 3 - Package Pin Assignments 256-Pin FBGA A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v2.0 3-1 Package Pin Assignments 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number AGLE600 Function Pin Number AGLE600 Function Pin Number AGLE600 Function A1 GND C4 VCCPLA E8 IO13NDB0V2 A2 GAA0/IO00NDB0V0 C5 GAC0/IO02NDB0V0 E9 IO21NDB1V0 A3 GAA1/IO00PDB0V0 C6 GAC1/IO02PDB0V0 E10 VCCIB1 A4 GAB0/IO01NDB0V0 C7 IO15NDB0V2 E11 VCCIB1 A5 IO05PDB0V0 C8 IO15PDB0V2 E12 VMV1 A6 IO10PDB0V1 C9 IO20PDB1V0 E13 GBC2/IO38PDB2V0 A7 IO12PDB0V2 C10 IO25NDB1V0 E14 IO37NDB2V0 A8 IO16NDB0V2 C11 IO27PDB1V0 E15 IO41NDB2V0 A9 IO23NDB1V0 C12 GBC0/IO33NDB1V1 E16 IO41PDB2V0 A10 IO23PDB1V0 C13 VCCPLB F1 IO124PDB7V0 A11 IO28NDB1V1 C14 VMV2 F2 IO125PDB7V0 A12 IO28PDB1V1 C15 IO36NDB2V0 F3 IO126PDB7V0 A13 GBB1/IO34PDB1V1 C16 IO42PDB2V0 F4 IO130NDB7V1 A14 GBA0/IO35NDB1V1 D1 IO128PDB7V1 F5 VCCIB7 A15 GBA1/IO35PDB1V1 D2 IO129PDB7V1 F6 GND A16 GND D3 GAC2/IO132PDB7V1 F7 VCC B1 GAB2/IO133PDB7V1 D4 VCOMPLA F8 VCC B2 GAA2/IO134PDB7V 1 D5 GNDQ F9 VCC D6 IO09NDB0V1 F10 VCC B3 GNDQ D7 IO09PDB0V1 F11 GND B4 GAB1/IO01PDB0V0 D8 IO13PDB0V2 F12 VCCIB2 B5 IO05NDB0V0 D9 IO21PDB1V0 F13 IO38NDB2V0 B6 IO10NDB0V1 D10 IO25PDB1V0 F14 IO40NDB2V0 B7 IO12NDB0V2 D11 IO27NDB1V0 F15 IO40PDB2V0 B8 IO16PDB0V2 D12 GNDQ F16 IO45PSB2V1 B9 IO20NDB1V0 D13 VCOMPLB G1 IO124NDB7V0 B10 IO24NDB1V0 D14 GBB2/IO37PDB2V0 G2 IO125NDB7V0 B11 IO24PDB1V0 D15 IO39PDB2V0 G3 IO126NDB7V0 B12 GBC1/IO33PDB1V1 D16 IO39NDB2V0 G4 GFC1/IO120PPB7V0 B13 GBB0/IO34NDB1V1 E1 IO128NDB7V1 G5 VCCIB7 B14 GNDQ E2 IO129NDB7V1 G6 VCC B15 GBA2/IO36PDB2V0 E3 IO132NDB7V1 G7 GND B16 IO42NDB2V0 E4 IO130PDB7V1 G8 GND C1 IO133NDB7V1 E5 VMV0 G9 GND C2 IO134NDB7V1 E6 VCCIB0 G10 GND C3 VMV7 E7 VCCIB0 G11 VCC 3 -2 v2.0 IGLOOe Packaging 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number AGLE600 Function Pin Number AGLE600 Function Pin Number AGLE600 Function G12 VCCIB2 J16 GCA2/IO53PSB3V0 M4 GEC0/IO104NPB6V0 G13 GCC1/IO50PPB2V1 K1 GFC2/IO115PSB6V1 M5 VMV5 G14 IO44NDB2V1 K2 IO113PPB6V1 M6 VCCIB5 G15 IO44PDB2V1 K3 IO112PDB6V1 M7 VCCIB5 G16 IO49NSB2V1 K4 IO112NDB6V1 M8 IO84NDB5V0 H1 GFB0/IO119NPB7V0 K5 VCCIB6 M9 IO84PDB5V0 H2 GFA0/IO118NDB6V1 K6 VCC M10 VCCIB4 H3 GFB1/IO119PPB7V0 K7 GND M11 VCCIB4 H4 VCOMPLF K8 GND M12 VMV3 H5 GFC0/IO120NPB7V0 K9 GND M13 VCCPLD H6 VCC K10 GND M14 GDB1/IO66PPB3V1 H7 GND K11 VCC M15 GDC1/IO65PDB3V1 H8 GND K12 VCCIB3 M16 IO61NDB3V1 H9 GND K13 IO54NPB3V0 N1 IO105PDB6V0 H10 GND K14 IO57NPB3V0 N2 IO105NDB6V0 H11 VCC K15 IO55NPB3V0 N3 GEC1/IO104PPB6V0 H12 GCC0/IO50NPB2V1 K16 IO57PPB3V0 N4 VCOMPLE H13 GCB1/IO51PPB2V1 L1 IO113NPB6V1 N5 GNDQ H14 GCA0/IO52NPB3V0 L2 IO109PPB6V0 N6 GEA2/IO101PPB5V2 H15 VCOMPLC L3 IO108PDB6V0 N7 IO92NDB5V1 H16 GCB0/IO51NPB2V1 L4 IO108NDB6V0 N8 IO90NDB5V1 J1 GFA2/IO117PSB6V1 L5 VCCIB6 N9 IO82NDB5V0 J2 GFA1/IO118PDB6V1 L6 GND N10 IO74NDB4V1 J3 VCCPLF L7 VCC N11 IO74PDB4V1 J4 IO116NDB6V1 L8 VCC N12 GNDQ J5 GFB2/IO116PDB6V1 L9 VCC N13 VCOMPLD J6 VCC L10 VCC N14 VJTAG J7 GND L11 GND N15 GDC0/IO65NDB3V1 J8 GND L12 VCCIB3 N16 GDA1/IO67PDB3V1 J9 GND L13 GDB0/IO66NPB3V1 P1 GEB1/IO103PDB6V0 J10 GND L14 IO60NDB3V1 P2 GEB0/IO103NDB6V0 J11 VCC L15 IO60PDB3V1 P3 VMV6 J12 GCB2/IO54PPB3V0 L16 IO61PDB3V1 P4 VCCPLE J13 GCA1/IO52PPB3V0 M1 IO109NPB6V0 P5 IO101NPB5V2 J14 GCC2/IO55PPB3V0 M2 IO106NDB6V0 P6 IO95PPB5V1 J15 VCCPLC M3 IO106PDB6V0 P7 IO92PDB5V1 v2.0 3-3 Package Pin Assignments 256-Pin FBGA 256-Pin FBGA Pin Number AGLE600 Function Pin Number AGLE600 Function P8 IO90PDB5V1 T10 IO81PDB4V1 P9 IO82PDB5V0 T11 IO70NDB4V0 P10 IO76NDB4V1 T12 GDC2/IO70PDB4V0 P11 IO76PDB4V1 T13 IO68NDB4V0 P12 VMV4 T14 GDA2/IO68PDB4V0 P13 TCK T15 TMS P14 VPUMP T16 GND P15 TRST P16 GDA0/IO67NDB3V1 R1 GEA1/IO102PDB6V0 R2 GEA0/IO102NDB6V 0 R3 GNDQ R4 GEC2/IO99PDB5V2 R5 IO95NPB5V1 R6 IO91NDB5V1 R7 IO91PDB5V1 R8 IO83NDB5V0 R9 IO83PDB5V0 R10 IO77NDB4V1 R11 IO77PDB4V1 R12 IO69NDB4V0 R13 GDB2/IO69PDB4V0 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO100NDB5V2 T3 FF/GEB2/IO100PDB5 V2 T4 IO99NDB5V2 T5 IO88NDB5V0 T6 IO88PDB5V0 T7 IO89NSB5V0 T8 IO80NSB4V1 T9 IO81NDB4V1 3 -4 v2.0 IGLOOe Packaging 484-Pin FBGA A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v2.0 3-5 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number AGLE600 Function Pin Number AGLE600 Function Pin Number AGLE600 Function A1 GND AA15 NC B7 IO07PDB0V1 A2 GND AA16 IO71NDB4V0 B8 IO11NDB0V1 A3 VCCIB0 AA17 IO71PDB4V0 B9 IO17NDB0V2 A4 IO06NDB0V1 AA18 NC B10 IO14PDB0V2 A5 IO06PDB0V1 AA19 NC B11 IO19PDB0V2 A6 IO08NDB0V1 AA20 NC B12 IO22NDB1V0 A7 IO08PDB0V1 AA21 VCCIB3 B13 IO26NDB1V0 A8 IO11PDB0V1 AA22 GND B14 NC A9 IO17PDB0V2 AB1 GND B15 NC A10 IO18NDB0V2 AB2 GND B16 IO30NDB1V1 A11 IO18PDB0V2 AB3 VCCIB5 B17 IO30PDB1V1 A12 IO22PDB1V0 AB4 IO97NDB5V2 B18 IO32PDB1V1 A13 IO26PDB1V0 AB5 IO97PDB5V2 B19 NC A14 IO29NDB1V1 AB6 IO93NDB5V1 B20 NC A15 IO29PDB1V1 AB7 IO93PDB5V1 B21 VCCIB2 A16 IO31NDB1V1 AB8 IO87NDB5V0 B22 GND A17 IO31PDB1V1 AB9 IO87PDB5V0 C1 VCCIB7 A18 IO32NDB1V1 AB10 NC C2 NC A19 NC AB11 NC C3 NC A20 VCCIB1 AB12 IO75NDB4V1 C4 NC A21 GND AB13 IO75PDB4V1 C5 GND A22 GND AB14 IO72NDB4V0 C6 IO04NDB0V0 AA1 GND AB15 IO72PDB4V0 C7 IO04PDB0V0 AA2 VCCIB6 AB16 IO73NDB4V0 C8 VCC AA3 NC AB17 IO73PDB4V0 C9 VCC AA4 IO98PDB5V2 AB18 NC C10 IO14NDB0V2 AA5 IO96NDB5V2 AB19 NC C11 IO19NDB0V2 AA6 IO96PDB5V2 AB20 VCCIB4 C12 NC AA7 IO86NDB5V0 AB21 GND C13 NC AA8 IO86PDB5V0 AB22 GND C14 VCC AA9 IO85PDB5V0 B1 GND C15 VCC AA10 IO85NDB5V0 B2 VCCIB7 C16 NC AA11 IO78PPB4V1 B3 NC C17 NC AA12 IO79NDB4V1 B4 IO03NDB0V0 C18 GND AA13 IO79PDB4V1 B5 IO03PDB0V0 C19 NC AA14 NC B6 IO07NDB0V1 C20 NC 3 -6 v2.0 IGLOOe Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number AGLE600 Function Pin Number AGLE600 Function Pin Number AGLE600 Function C21 NC E11 IO16PDB0V2 G3 NC C22 VCCIB2 E12 IO20NDB1V0 G4 IO128PDB7V1 D1 NC E13 IO24NDB1V0 G5 IO129PDB7V1 D2 NC E14 IO24PDB1V0 G6 D3 NC E15 GBC1/IO33PDB1V1 GAC2/IO132PDB7V 1 D4 GND E16 GBB0/IO34NDB1V1 G7 VCOMPLA D5 GAA0/IO00NDB0V0 E17 GNDQ G8 GNDQ D6 GAA1/IO00PDB0V0 E18 GBA2/IO36PDB2V0 G9 IO09NDB0V1 D7 GAB0/IO01NDB0V0 E19 IO42NDB2V0 G10 IO09PDB0V1 D8 IO05PDB0V0 E20 GND G11 IO13PDB0V2 D9 IO10PDB0V1 E21 NC G12 IO21PDB1V0 D10 IO12PDB0V2 E22 NC G13 IO25PDB1V0 D11 IO16NDB0V2 F1 NC G14 IO27NDB1V0 D12 IO23NDB1V0 F2 IO131NDB7V1 G15 GNDQ D13 IO23PDB1V0 F3 IO131PDB7V1 G16 VCOMPLB D14 IO28NDB1V1 F4 IO133NDB7V1 G17 GBB2/IO37PDB2V0 D15 IO28PDB1V1 F5 IO134NDB7V1 G18 IO39PDB2V0 D16 GBB1/IO34PDB1V1 F6 VMV7 G19 IO39NDB2V0 D17 GBA0/IO35NDB1V1 F7 VCCPLA G20 IO43PDB2V0 D18 GBA1/IO35PDB1V1 F8 GAC0/IO02NDB0V0 G21 IO43NDB2V0 D19 GND F9 GAC1/IO02PDB0V0 G22 NC D20 NC F10 IO15NDB0V2 H1 NC D21 NC F11 IO15PDB0V2 H2 NC D22 NC F12 IO20PDB1V0 H3 VCC E1 NC F13 IO25NDB1V0 H4 IO128NDB7V1 E2 NC F14 IO27PDB1V0 H5 IO129NDB7V1 E3 GND F15 GBC0/IO33NDB1V1 H6 IO132NDB7V1 E4 GAB2/IO133PDB7V 1 F16 VCCPLB H7 IO130PDB7V1 F17 VMV2 H8 VMV0 F18 IO36NDB2V0 H9 VCCIB0 F19 IO42PDB2V0 H10 VCCIB0 F20 NC H11 IO13NDB0V2 F21 NC H12 IO21NDB1V0 F22 NC H13 VCCIB1 G1 IO127NDB7V1 H14 VCCIB1 G2 IO127PDB7V1 H15 VMV1 E5 GAA2/IO134PDB7V 1 E6 GNDQ E7 GAB1/IO01PDB0V0 E8 IO05NDB0V0 E9 IO10NDB0V1 E10 IO12NDB0V2 v2.0 3-7 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number AGLE600 Function Pin Number AGLE600 Function Pin Number AGLE600 Function H16 GBC2/IO38PDB2V0 K8 VCCIB7 L21 IO47NDB2V1 H17 IO37NDB2V0 K9 VCC L22 IO47PDB2V1 H18 IO41NDB2V0 K10 GND M1 NC H19 IO41PDB2V0 K11 GND M2 IO114NPB6V1 H20 VCC K12 GND M3 IO117NDB6V1 H21 NC K13 GND M4 GFA2/IO117PDB6V1 H22 NC K14 VCC M5 GFA1/IO118PDB6V1 J1 IO123NDB7V0 K15 VCCIB2 M6 VCCPLF J2 IO123PDB7V0 K16 GCC1/IO50PPB2V1 M7 IO116NDB6V1 J3 NC K17 IO44NDB2V1 M8 GFB2/IO116PDB6V1 J4 IO124PDB7V0 K18 IO44PDB2V1 M9 VCC J5 IO125PDB7V0 K19 IO49NPB2V1 M10 GND J6 IO126PDB7V0 K20 IO45NPB2V1 M11 GND J7 IO130NDB7V1 K21 IO48NDB2V1 M12 GND J8 VCCIB7 K22 IO46NDB2V1 M13 GND J9 GND L1 NC M14 VCC J10 VCC L2 IO122PDB7V0 M15 GCB2/IO54PPB3V0 J11 VCC L3 IO122NDB7V0 M16 GCA1/IO52PPB3V0 J12 VCC L4 GFB0/IO119NPB7V0 M17 GCC2/IO55PPB3V0 J13 VCC L5 M18 VCCPLC J14 GND GFA0/IO118NDB6V 1 M19 GCA2/IO53PDB3V0 L6 GFB1/IO119PPB7V0 M20 IO53NDB3V0 L7 VCOMPLF M21 IO56PDB3V0 L8 GFC0/IO120NPB7V0 M22 NC L9 VCC N1 IO114PPB6V1 L10 GND N2 IO111NDB6V1 L11 GND N3 NC L12 GND N4 GFC2/IO115PPB6V1 L13 GND N5 IO113PPB6V1 L14 VCC N6 IO112PDB6V1 L15 GCC0/IO50NPB2V1 N7 IO112NDB6V1 L16 GCB1/IO51PPB2V1 N8 VCCIB6 L17 GCA0/IO52NPB3V0 N9 VCC L18 VCOMPLC N10 GND L19 GCB0/IO51NPB2V1 N11 GND L20 IO49PPB2V1 N12 GND J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 3 -8 VCCIB2 IO38NDB2V0 IO40NDB2V0 IO40PDB2V0 IO45PPB2V1 NC IO48PDB2V1 IO46PDB2V1 IO121NDB7V0 IO121PDB7V0 NC IO124NDB7V0 IO125NDB7V0 IO126NDB7V0 GFC1/IO120PPB7V0 v2.0 IGLOOe Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number AGLE600 Function Pin Number AGLE600 Function Pin Number AGLE600 Function N13 GND R5 IO106NDB6V0 T19 GDA1/IO67PDB3V1 N14 VCC R6 IO106PDB6V0 T20 NC N15 VCCIB3 R7 GEC0/IO104NPB6V0 T21 IO64PDB3V1 N16 IO54NPB3V0 R8 VMV5 T22 IO62NDB3V1 N17 IO57NPB3V0 R9 VCCIB5 U1 NC N18 IO55NPB3V0 R10 VCCIB5 U2 IO107PDB6V0 N19 IO57PPB3V0 R11 IO84NDB5V0 U3 IO107NDB6V0 N20 NC R12 IO84PDB5V0 U4 GEB1/IO103PDB6V0 N21 IO56NDB3V0 R13 VCCIB4 U5 N22 IO58PDB3V0 R14 VCCIB4 GEB0/IO103NDB6V 0 P1 NC R15 VMV3 U6 VMV6 P2 IO111PDB6V1 R16 VCCPLD U7 VCCPLE P3 IO115NPB6V1 R17 GDB1/IO66PPB3V1 U8 IO101NPB5V2 P4 IO113NPB6V1 R18 GDC1/IO65PDB3V1 U9 IO95PPB5V1 P5 IO109PPB6V0 R19 IO61NDB3V1 U10 IO92PDB5V1 P6 IO108PDB6V0 R20 VCC U11 IO90PDB5V1 P7 IO108NDB6V0 R21 IO59NDB3V0 U12 IO82PDB5V0 P8 VCCIB6 R22 IO62PDB3V1 U13 IO76NDB4V1 P9 GND T1 NC U14 IO76PDB4V1 P10 VCC T2 IO110NDB6V0 U15 VMV4 P11 VCC T3 NC U16 TCK P12 VCC T4 IO105PDB6V0 U17 VPUMP P13 VCC T5 IO105NDB6V0 U18 TRST P14 GND T6 GEC1/IO104PPB6V0 U19 GDA0/IO67NDB3V1 P15 VCCIB3 T7 VCOMPLE U20 NC P16 GDB0/IO66NPB3V1 T8 GNDQ U21 IO64NDB3V1 P17 IO60NDB3V1 T9 GEA2/IO101PPB5V2 U22 IO63PDB3V1 P18 IO60PDB3V1 T10 IO92NDB5V1 V1 NC P19 IO61PDB3V1 T11 IO90NDB5V1 V2 NC P20 NC T12 IO82NDB5V0 V3 GND P21 IO59PDB3V0 T13 IO74NDB4V1 V4 GEA1/IO102PDB6V 0 P22 IO58NDB3V0 T14 IO74PDB4V1 V5 R1 NC T15 GNDQ GEA0/IO102NDB6V 0 R2 IO110PDB6V0 T16 VCOMPLD V6 GNDQ R3 VCC T17 VJTAG V7 GEC2/IO99PDB5V2 R4 IO109NPB6V0 T18 GDC0/IO65NDB3V1 V8 IO95NPB5V1 v2.0 3-9 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA Pin Number AGLE600 Function Pin Number AGLE600 Function V9 IO91NDB5V1 W22 NC V10 IO91PDB5V1 Y1 VCCIB6 V11 IO83NDB5V0 Y2 NC V12 IO83PDB5V0 Y3 NC V13 IO77NDB4V1 Y4 IO98NDB5V2 V14 IO77PDB4V1 Y5 GND V15 IO69NDB4V0 Y6 IO94NDB5V1 V16 GDB2/IO69PDB4V0 Y7 IO94PDB5V1 V17 TDI Y8 VCC V18 GNDQ Y9 VCC V19 TDO Y10 IO89PDB5V0 V20 GND Y11 IO80PDB4V1 V21 NC Y12 IO78NPB4V1 V22 IO63NDB3V1 Y13 NC W1 NC Y14 VCC W2 NC Y15 VCC W3 NC Y16 NC W4 GND Y17 NC W5 IO100NDB5V2 Y18 GND W6 FF/GEB2/IO100PDB5 V2 Y19 NC Y20 NC W7 IO99NDB5V2 Y21 NC W8 IO88NDB5V0 Y22 VCCIB3 W9 IO88PDB5V0 W10 IO89NDB5V0 W11 IO80NDB4V1 W12 IO81NDB4V1 W13 IO81PDB4V1 W14 IO70NDB4V0 W15 GDC2/IO70PDB4V0 W16 IO68NDB4V0 W17 GDA2/IO68PDB4V0 W18 TMS W19 GND W20 NC W21 NC 3 -1 0 v2.0 IGLOOe Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function A1 GND AA15 IO170PDB4V2 B7 IO14PDB0V1 A2 GND AA16 IO166NDB4V1 B8 IO18NDB0V2 A3 VCCIB0 AA17 IO166PDB4V1 B9 IO24NDB0V2 A4 IO10NDB0V1 AA18 IO160NDB4V0 B10 IO34PDB0V4 A5 IO10PDB0V1 AA19 IO160PDB4V0 B11 IO40PDB0V4 A6 IO16NDB0V1 AA20 IO158NPB4V0 B12 IO46NDB1V0 A7 IO16PDB0V1 AA21 VCCIB3 B13 IO54NDB1V1 A8 IO18PDB0V2 AA22 GND B14 IO62NDB1V2 A9 IO24PDB0V2 AB1 GND B15 IO62PDB1V2 A10 IO28NDB0V3 AB2 GND B16 IO68NDB1V3 A11 IO28PDB0V3 AB3 VCCIB5 B17 IO68PDB1V3 A12 IO46PDB1V0 AB4 IO216NDB5V2 B18 IO72PDB1V3 A13 IO54PDB1V1 AB5 IO216PDB5V2 B19 IO74PDB1V4 A14 IO56NDB1V1 AB6 IO210NDB5V2 B20 IO76NPB1V4 A15 IO56PDB1V1 AB7 IO210PDB5V2 B21 VCCIB2 A16 IO64NDB1V2 AB8 IO208NDB5V1 B22 GND A17 IO64PDB1V2 AB9 IO208PDB5V1 C1 VCCIB7 A18 IO72NDB1V3 AB10 IO197NDB5V0 C2 IO303PDB7V3 A19 IO74NDB1V4 AB11 IO197PDB5V0 C3 IO305PDB7V3 A20 VCCIB1 AB12 IO174NDB4V2 C4 IO06NPB0V0 A21 GND AB13 IO174PDB4V2 C5 GND A22 GND AB14 IO172NDB4V2 C6 IO12NDB0V1 AA1 GND AB15 IO172PDB4V2 C7 IO12PDB0V1 AA2 VCCIB6 AB16 IO168NDB4V1 C8 VCC AA3 IO228PDB5V4 AB17 IO168PDB4V1 C9 VCC AA4 IO224PDB5V3 AB18 IO162NDB4V1 C10 IO34NDB0V4 AA5 IO218NDB5V3 AB19 IO162PDB4V1 C11 IO40NDB0V4 AA6 IO218PDB5V3 AB20 VCCIB4 C12 IO48NDB1V0 AA7 IO212NDB5V2 AB21 GND C13 IO48PDB1V0 AA8 IO212PDB5V2 AB22 GND C14 VCC AA9 IO198PDB5V0 B1 GND C15 VCC AA10 IO198NDB5V0 B2 VCCIB7 C16 IO70NDB1V3 AA11 IO188PPB4V4 B3 IO06PPB0V0 C17 IO70PDB1V3 AA12 IO180NDB4V3 B4 IO08NDB0V0 C18 GND AA13 IO180PDB4V3 B5 IO08PDB0V0 C19 IO76PPB1V4 AA14 IO170NDB4V2 B6 IO14NDB0V1 C20 IO88NDB2V0 v2.0 3 - 11 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function C21 IO94PPB2V1 E13 IO58NDB1V2 G5 IO297PDB7V2 C22 VCCIB2 E14 IO58PDB1V2 G6 GAC2/IO307PDB7V4 D1 IO293PDB7V2 E15 GBC1/IO79PDB1V4 G7 VCOMPLA D2 IO303NDB7V3 E16 GBB0/IO80NDB1V4 G8 GNDQ D3 IO305NDB7V3 E17 GNDQ G9 IO26NDB0V3 D4 GND E18 GBA2/IO82PDB2V0 G10 IO26PDB0V3 D5 GAA0/IO00NDB0V0 E19 IO86NDB2V0 G11 IO36PDB0V4 D6 GAA1/IO00PDB0V0 E20 GND G12 IO42PDB1V0 D7 GAB0/IO01NDB0V0 E21 IO90NDB2V1 G13 IO50PDB1V1 D8 IO20PDB0V2 E22 IO98PDB2V2 G14 IO60NDB1V2 D9 IO22PDB0V2 F1 IO299NPB7V3 G15 GNDQ D10 IO30PDB0V3 F2 IO301NDB7V3 G16 VCOMPLB D11 IO38NDB0V4 F3 IO301PDB7V3 G17 GBB2/IO83PDB2V0 D12 IO52NDB1V1 F4 IO308NDB7V4 G18 IO92PDB2V1 D13 IO52PDB1V1 F5 IO309NDB7V4 G19 IO92NDB2V1 D14 IO66NDB1V3 F6 VMV7 G20 IO102PDB2V2 D15 IO66PDB1V3 F7 VCCPLA G21 IO102NDB2V2 D16 GBB1/IO80PDB1V4 F8 GAC0/IO02NDB0V0 G22 IO105NDB2V2 D17 GBA0/IO81NDB1V4 F9 GAC1/IO02PDB0V0 H1 IO286PSB7V1 D18 GBA1/IO81PDB1V4 F10 IO32NDB0V3 H2 IO291NPB7V2 D19 GND F11 IO32PDB0V3 H3 VCC D20 IO88PDB2V0 F12 IO44PDB1V0 H4 IO295NDB7V2 D21 IO90PDB2V1 F13 IO50NDB1V1 H5 IO297NDB7V2 D22 IO94NPB2V1 F14 IO60PDB1V2 H6 IO307NDB7V4 E1 IO293NDB7V2 F15 GBC0/IO79NDB1V4 H7 IO287PDB7V1 E2 IO299PPB7V3 F16 VCCPLB H8 VMV0 E3 GND F17 VMV2 H9 VCCIB0 E4 GAB2/IO308PDB7V4 F18 IO82NDB2V0 H10 VCCIB0 E5 GAA2/IO309PDB7V4 F19 IO86PDB2V0 H11 IO36NDB0V4 E6 GNDQ F20 IO96PDB2V1 H12 IO42NDB1V0 E7 GAB1/IO01PDB0V0 F21 IO96NDB2V1 H13 VCCIB1 E8 IO20NDB0V2 F22 IO98NDB2V2 H14 VCCIB1 E9 IO22NDB0V2 G1 IO289NDB7V1 H15 VMV1 E10 IO30NDB0V3 G2 IO289PDB7V1 H16 GBC2/IO84PDB2V0 E11 IO38PDB0V4 G3 IO291PPB7V2 H17 IO83NDB2V0 E12 IO44NDB1V0 G4 IO295PDB7V2 H18 IO100NDB2V2 3 -1 2 v2.0 IGLOOe Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function H19 IO100PDB2V2 K11 GND M3 IO272NDB6V4 H20 VCC K12 GND M4 GFA2/IO272PDB6V4 H21 VMV2 K13 GND M5 GFA1/IO273PDB6V4 H22 IO105PDB2V2 K14 VCC M6 VCCPLF J1 IO285NDB7V1 K15 VCCIB2 M7 IO271NDB6V4 J2 IO285PDB7V1 K16 GCC1/IO112PPB2V3 M8 GFB2/IO271PDB6V4 J3 VMV7 K17 IO108NDB2V3 M9 VCC J4 IO279PDB7V0 K18 IO108PDB2V3 M10 GND J5 IO283PDB7V1 K19 IO110NPB2V3 M11 GND J6 IO281PDB7V0 K20 IO106NPB2V3 M12 GND J7 IO287NDB7V1 K21 IO109NDB2V3 M13 GND J8 VCCIB7 K22 IO107NDB2V3 M14 VCC J9 GND L1 IO257PSB6V2 M15 GCB2/IO116PPB3V0 J10 VCC L2 IO276PDB7V0 M16 GCA1/IO114PPB3V0 J11 VCC L3 IO276NDB7V0 M17 GCC2/IO117PPB3V0 J12 VCC L4 GFB0/IO274NPB7V0 M18 VCCPLC J13 VCC L5 GFA0/IO273NDB6V4 M19 GCA2/IO115PDB3V0 J14 GND L6 GFB1/IO274PPB7V0 M20 IO115NDB3V0 J15 VCCIB2 L7 VCOMPLF M21 IO126PDB3V1 J16 IO84NDB2V0 L8 GFC0/IO275NPB7V0 M22 IO124PSB3V1 J17 IO104NDB2V2 L9 VCC N1 IO255PPB6V2 J18 IO104PDB2V2 L10 GND N2 IO253NDB6V2 J19 IO106PPB2V3 L11 GND N3 VMV6 J20 GNDQ L12 GND N4 GFC2/IO270PPB6V4 J21 IO109PDB2V3 L13 GND N5 IO261PPB6V3 J22 IO107PDB2V3 L14 VCC N6 IO263PDB6V3 K1 IO277NDB7V0 L15 GCC0/IO112NPB2V3 N7 IO263NDB6V3 K2 IO277PDB7V0 L16 GCB1/IO113PPB2V3 N8 VCCIB6 K3 GNDQ L17 GCA0/IO114NPB3V0 N9 VCC K4 IO279NDB7V0 L18 VCOMPLC N10 GND K5 IO283NDB7V1 L19 GCB0/IO113NPB2V3 N11 GND K6 IO281NDB7V0 L20 IO110PPB2V3 N12 GND K7 GFC1/IO275PPB7V0 L21 IO111NDB2V3 N13 GND K8 VCCIB7 L22 IO111PDB2V3 N14 VCC K9 VCC M1 GNDQ N15 VCCIB3 K10 GND M2 IO255NPB6V2 N16 IO116NPB3V0 v2.0 3 - 13 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function N17 IO132NPB3V2 R9 VCCIB5 U1 IO240PPB6V0 N18 IO117NPB3V0 R10 VCCIB5 U2 IO238PDB6V0 N19 IO132PPB3V2 R11 IO196NDB5V0 U3 IO238NDB6V0 N20 GNDQ R12 IO196PDB5V0 U4 GEB1/IO235PDB6V0 N21 IO126NDB3V1 R13 VCCIB4 U5 GEB0/IO235NDB6V0 N22 IO128PDB3V1 R14 VCCIB4 U6 VMV6 P1 IO247PDB6V1 R15 VMV3 U7 VCCPLE P2 IO253PDB6V2 R16 VCCPLD U8 IO233NPB5V4 P3 IO270NPB6V4 R17 GDB1/IO152PPB3V4 U9 IO222PPB5V3 P4 IO261NPB6V3 R18 GDC1/IO151PDB3V4 U10 IO206PDB5V1 P5 IO249PPB6V1 R19 IO138NDB3V3 U11 IO202PDB5V1 P6 IO259PDB6V3 R20 VCC U12 IO194PDB5V0 P7 IO259NDB6V3 R21 IO130NDB3V2 U13 IO176NDB4V2 P8 VCCIB6 R22 IO134PDB3V2 U14 IO176PDB4V2 P9 GND T1 IO243PPB6V1 U15 VMV4 P10 VCC T2 IO245NDB6V1 U16 TCK P11 VCC T3 IO243NPB6V1 U17 VPUMP P12 VCC T4 IO241PDB6V0 U18 TRST P13 VCC T5 IO241NDB6V0 U19 GDA0/IO153NDB3V4 P14 GND T6 GEC1/IO236PPB6V0 U20 IO144NDB3V3 P15 VCCIB3 T7 VCOMPLE U21 IO140NDB3V3 P16 GDB0/IO152NPB3V4 T8 GNDQ U22 IO142PDB3V3 P17 IO136NDB3V2 T9 GEA2/IO233PPB5V4 V1 IO239PDB6V0 P18 IO136PDB3V2 T10 IO206NDB5V1 V2 IO240NPB6V0 P19 IO138PDB3V3 T11 IO202NDB5V1 V3 GND P20 VMV3 T12 IO194NDB5V0 V4 GEA1/IO234PDB6V0 P21 IO130PDB3V2 T13 IO186NDB4V4 V5 GEA0/IO234NDB6V0 P22 IO128NDB3V1 T14 IO186PDB4V4 V6 GNDQ R1 IO247NDB6V1 T15 GNDQ V7 GEC2/IO231PDB5V4 R2 IO245PDB6V1 T16 VCOMPLD V8 IO222NPB5V3 R3 VCC T17 VJTAG V9 IO204NDB5V1 R4 IO249NPB6V1 T18 GDC0/IO151NDB3V4 V10 IO204PDB5V1 R5 IO251NDB6V2 T19 GDA1/IO153PDB3V4 V11 IO195NDB5V0 R6 IO251PDB6V2 T20 IO144PDB3V3 V12 IO195PDB5V0 R7 GEC0/IO236NPB6V0 T21 IO140PDB3V3 V13 IO178NDB4V3 R8 VMV5 T22 IO134NDB3V2 V14 IO178PDB4V3 3 -1 4 v2.0 IGLOOe Packaging 484-Pin FBGA 484-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function V15 IO155NDB4V0 Y6 IO220NDB5V3 V16 GDB2/IO155PDB4V0 Y7 IO220PDB5V3 V17 TDI Y8 VCC V18 GNDQ Y9 VCC V19 TDO Y10 IO200PDB5V0 V20 GND Y11 IO192PDB4V4 V21 IO146PDB3V4 Y12 IO188NPB4V4 V22 IO142NDB3V3 Y13 IO187PSB4V4 W1 IO239NDB6V0 Y14 VCC W2 IO237PDB6V0 Y15 VCC W3 IO230PSB5V4 Y16 IO164NDB4V1 W4 GND Y17 IO164PDB4V1 W5 IO232NDB5V4 Y18 GND W6 FF/GEB2/IO232PDB5V 4 Y19 IO158PPB4V0 Y20 IO150PDB3V4 W7 IO231NDB5V4 Y21 IO148NPB3V4 W8 IO214NDB5V2 Y22 VCCIB3 W9 IO214PDB5V2 W10 IO200NDB5V0 W11 IO192NDB4V4 W12 IO184NDB4V3 W13 IO184PDB4V3 W14 IO156NDB4V0 W15 GDC2/IO156PDB4V0 W16 IO154NDB4V0 W17 GDA2/IO154PDB4V0 W18 TMS W19 GND W20 IO150NDB3V4 W21 IO146NDB3V4 W22 IO148PPB3V4 Y1 VCCIB6 Y2 IO237NDB6V0 Y3 IO228NDB5V4 Y4 IO224NDB5V3 Y5 GND v2.0 3 - 15 Package Pin Assignments 896-Pin FBGA A1 Ball Pad Corner 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -1 6 v2.0 IGLOOe Packaging 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function A2 GND AA8 IO245NDB6V1 AB13 IO206PDB5V1 A3 GND AA9 GEB1/IO235PPB6V0 AB14 IO198NDB5V0 A4 IO14NPB0V1 AA10 VCC AB15 IO198PDB5V0 A5 GND AA11 IO226PPB5V4 AB16 IO192NDB4V4 A6 IO07NPB0V0 AA12 VCCIB5 AB17 IO192PDB4V4 A7 GND AA13 VCCIB5 AB18 IO178NDB4V3 A8 IO09NDB0V1 AA14 VCCIB5 AB19 IO178PDB4V3 A9 IO17NDB0V2 AA15 VCCIB5 AB20 IO174NDB4V2 A10 IO17PDB0V2 AA16 VCCIB4 AB21 IO162NPB4V1 A11 IO21NDB0V2 AA17 VCCIB4 AB22 VCC A12 IO21PDB0V2 AA18 VCCIB4 AB23 VCCPLD A13 IO33NDB0V4 AA19 VCCIB4 AB24 VCCIB3 A14 IO33PDB0V4 AA20 IO174PDB4V2 AB25 IO150PDB3V4 A15 IO35NDB0V4 AA21 VCC AB26 IO148PDB3V4 A16 IO35PDB0V4 AA22 IO142NPB3V3 AB27 IO147NDB3V4 A17 IO41NDB1V0 AA23 IO144NDB3V3 AB28 IO145PDB3V3 A18 IO43NDB1V0 AA24 IO144PDB3V3 AB29 IO143PDB3V3 A19 IO43PDB1V0 AA25 IO146NDB3V4 AB30 IO137PDB3V2 A20 IO45NDB1V0 AA26 IO146PDB3V4 AC1 IO254PDB6V2 A21 IO45PDB1V0 AA27 IO147PDB3V4 AC2 IO254NDB6V2 A22 IO57NDB1V2 AA28 IO139NDB3V3 AC3 IO240PDB6V0 A23 IO57PDB1V2 AA29 IO139PDB3V3 AC4 GEC1/IO236PDB6V0 A24 GND AA30 IO133NDB3V2 AC5 IO237PDB6V0 A25 IO69PPB1V3 AB1 IO256NDB6V2 AC6 IO237NDB6V0 A26 GND AB2 IO244PDB6V1 AC7 VCOMPLE A27 GBC1/IO79PPB1V4 AB3 IO244NDB6V1 AC8 GND A28 GND AB4 IO241PDB6V0 AC9 IO226NPB5V4 A29 GND AB5 IO241NDB6V0 AC10 IO222NDB5V3 AA1 IO256PDB6V2 AB6 IO243NPB6V1 AC11 IO216NPB5V2 AA2 IO248PDB6V1 AB7 VCCIB6 AC12 IO210NPB5V2 AA3 IO248NDB6V1 AB8 VCCPLE AC13 IO204NDB5V1 AA4 IO246NDB6V1 AB9 VCC AC14 IO204PDB5V1 AA5 GEA1/IO234PDB6V0 AB10 IO222PDB5V3 AC15 IO194NDB5V0 AA6 GEA0/IO234NDB6V0 AB11 IO218PPB5V3 AC16 IO188NDB4V4 AA7 IO243PPB6V1 AB12 IO206NDB5V1 AC17 IO188PDB4V4 v2.0 3 - 17 Package Pin Assignments 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function AC18 IO182PPB4V3 AD22 VCCIB4 AE26 GDB0/IO152NDB3V4 AC19 IO170NPB4V2 AD23 TCK AE27 GDB1/IO152PDB3V4 AC20 IO164NDB4V1 AD24 VCC AE28 VMV3 AC21 IO164PDB4V1 AD25 TRST AE28 VMV3 AC22 IO162PPB4V1 AD26 VCCIB3 AE29 VCC AC23 GND AD27 GDA0/IO153NDB3V4 AE30 IO149PDB3V4 AC24 VCOMPLD AD28 GDC0/IO151NDB3V4 AF1 GND AC25 IO150NDB3V4 AD29 GDC1/IO151PDB3V4 AF2 IO238PPB6V0 AC26 IO148NDB3V4 AD30 GND AF3 VCCIB6 AC27 GDA1/IO153PDB3V4 AE1 IO242PPB6V1 AF4 IO220NPB5V3 AC28 IO145NDB3V3 AE2 VCC AF5 VCC AC29 IO143NDB3V3 AE3 IO239PDB6V0 AF6 IO228NDB5V4 AC30 IO137NDB3V2 AE4 IO239NDB6V0 AF7 VCCIB5 AD1 GND AE5 VMV6 AF8 IO230PDB5V4 AD2 IO242NPB6V1 AE5 VMV6 AF9 IO229NDB5V4 AD3 IO240NDB6V0 AE6 GND AF10 IO229PDB5V4 AD4 GEC0/IO236NDB6V0 AE7 GNDQ AF11 IO214PPB5V2 AD5 VCCIB6 AE8 IO230NDB5V4 AF12 IO208NDB5V1 AD6 GNDQ AE9 IO224NPB5V3 AF13 IO208PDB5V1 AD6 GNDQ AE10 IO214NPB5V2 AF14 IO200PDB5V0 AD7 VCC AE11 IO212NDB5V2 AF15 IO196NDB5V0 AD8 VMV5 AE12 IO212PDB5V2 AF16 IO186NDB4V4 AD9 VCCIB5 AE13 IO202NPB5V1 AF17 IO186PDB4V4 AD10 IO224PPB5V3 AE14 IO200NDB5V0 AF18 IO180NDB4V3 AD11 IO218NPB5V3 AE15 IO196PDB5V0 AF19 IO180PDB4V3 AD12 IO216PPB5V2 AE16 IO190NDB4V4 AF20 IO168NDB4V1 AD13 IO210PPB5V2 AE17 IO184PDB4V3 AF21 IO168PDB4V1 AD14 IO202PPB5V1 AE18 IO184NDB4V3 AF22 IO160NDB4V0 AD15 IO194PDB5V0 AE19 IO172PDB4V2 AF23 IO158NPB4V0 AD16 IO190PDB4V4 AE20 IO172NDB4V2 AF24 VCCIB4 AD17 IO182NPB4V3 AE21 IO166NDB4V1 AF25 IO154NPB4V0 AD18 IO176NDB4V2 AE22 IO160PDB4V0 AF26 VCC AD19 IO176PDB4V2 AE23 GNDQ AF27 TDO AD20 IO170PPB4V2 AE24 VMV4 AF28 VCCIB3 AD21 IO166PDB4V1 AE25 GND AF29 GNDQ 3 -1 8 v2.0 IGLOOe Packaging 896-Pin FBGA 896-Pin FBGA AGLE3000 Function Pin Number AGLE3000 Function Pin Number AF29 GNDQ AH4 AF30 GND FF/GEB2/IO232PPB5V 4 AH5 VCCIB5 AH6 IO219NDB5V3 AH7 IO219PDB5V3 AH8 IO227NDB5V4 AH9 IO227PDB5V4 AH10 IO225PPB5V3 AH11 IO223PPB5V3 AH12 IO211NDB5V2 AH13 IO211PDB5V2 AH14 IO205PPB5V1 AH15 IO195NDB5V0 AH16 IO185NDB4V3 AH17 IO185PDB4V3 AH18 IO181PDB4V3 AH19 IO177NDB4V2 AH20 IO171NPB4V2 AH21 IO165PPB4V1 AH22 IO161PPB4V0 AH23 IO157NDB4V0 AH24 IO157PDB4V0 AH25 IO155NDB4V0 AH26 VCCIB4 AH27 TDI AH28 VCC AH29 VPUMP AH30 GND AJ1 GND AJ2 GND AJ3 GEA2/IO233PPB5V4 AJ4 VCC AJ5 IO217NPB5V2 AJ6 VCC AJ7 IO215NPB5V2 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 IO238NPB6V0 VCC IO232NPB5V4 GND IO220PPB5V3 IO228PDB5V4 IO231NDB5V4 GEC2/IO231PDB5V4 IO225NPB5V3 IO223NPB5V3 IO221PDB5V3 IO221NDB5V3 IO205NPB5V1 IO199NDB5V0 IO199PDB5V0 IO187NDB4V4 IO187PDB4V4 IO181NDB4V3 IO171PPB4V2 IO165NPB4V1 IO161NPB4V0 IO159NDB4V0 IO159PDB4V0 IO158PPB4V0 GDB2/IO155PDB4V0 GDA2/IO154PPB4V0 GND VJTAG VCC IO149NDB3V4 GND IO233NPB5V4 VCC v2.0 896-Pin FBGA Pin Number AGLE3000 Function AJ8 IO213NDB5V2 AJ9 IO213PDB5V2 AJ10 IO209NDB5V1 AJ11 IO209PDB5V1 AJ12 IO203NDB5V1 AJ13 IO203PDB5V1 AJ14 IO197NDB5V0 AJ15 IO195PDB5V0 AJ16 IO183NDB4V3 AJ17 IO183PDB4V3 AJ18 IO179NPB4V3 AJ19 IO177PDB4V2 AJ20 IO173NDB4V2 AJ21 IO173PDB4V2 AJ22 IO163NDB4V1 AJ23 IO163PDB4V1 AJ24 IO167NPB4V1 AJ25 VCC AJ26 IO156NPB4V0 AJ27 VCC AJ28 TMS AJ29 GND AJ30 GND AK2 GND AK3 GND AK4 IO217PPB5V2 AK5 GND AK6 IO215PPB5V2 AK7 GND AK8 IO207NDB5V1 AK9 IO207PDB5V1 AK10 IO201NDB5V0 AK11 IO201PDB5V0 AK12 IO193NDB4V4 AK13 IO193PDB4V4 3 - 19 Package Pin Assignments 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function AK14 IO197PDB5V0 B20 IO53PDB1V1 C25 IO75PDB1V4 AK15 IO191NDB4V4 B21 IO53NDB1V1 C26 VCCIB1 AK16 IO191PDB4V4 B22 IO61NDB1V2 C27 IO64PPB1V2 AK17 IO189NDB4V4 B23 IO61PDB1V2 C28 VCC AK18 IO189PDB4V4 B24 IO69NPB1V3 C29 GBA1/IO81PPB1V4 AK19 IO179PPB4V3 B25 VCC C30 GND AK20 IO175NDB4V2 B26 GBC0/IO79NPB1V4 D1 IO303PPB7V3 AK21 IO175PDB4V2 B27 VCC D2 VCC AK22 IO169NDB4V1 B28 IO64NPB1V2 D3 IO305NPB7V3 AK23 IO169PDB4V1 B29 GND D4 GND AK24 GND B30 GND D5 GAA1/IO00PPB0V0 AK25 IO167PPB4V1 C1 GND D6 GAC1/IO02PDB0V0 AK26 GND C2 IO309NPB7V4 D7 IO06NPB0V0 AK27 GDC2/IO156PPB4V0 C3 VCC D8 GAB0/IO01NDB0V0 AK28 GND C4 GAA0/IO00NPB0V0 D9 IO05NDB0V0 AK29 GND C5 VCCIB0 D10 IO11NDB0V1 B1 GND C6 IO03PDB0V0 D11 IO11PDB0V1 B2 GND C7 IO03NDB0V0 D12 IO23NDB0V2 B3 GAA2/IO309PPB7V4 C8 GAB1/IO01PDB0V0 D13 IO23PDB0V2 B4 VCC C9 IO05PDB0V0 D14 IO27PDB0V3 B5 IO14PPB0V1 C10 IO15NPB0V1 D15 IO40PDB0V4 B6 VCC C11 IO25NDB0V3 D16 IO47NDB1V0 B7 IO07PPB0V0 C12 IO25PDB0V3 D17 IO47PDB1V0 B8 IO09PDB0V1 C13 IO31NPB0V3 D18 IO55NPB1V1 B9 IO15PPB0V1 C14 IO27NDB0V3 D19 IO65NDB1V3 B10 IO19NDB0V2 C15 IO39NDB0V4 D20 IO65PDB1V3 B11 IO19PDB0V2 C16 IO39PDB0V4 D21 IO71NDB1V3 B12 IO29NDB0V3 C17 IO55PPB1V1 D22 IO71PDB1V3 B13 IO29PDB0V3 C18 IO51PDB1V1 D23 IO73NDB1V4 B14 IO31PPB0V3 C19 IO59NDB1V2 D24 IO73PDB1V4 B15 IO37NDB0V4 C20 IO63NDB1V2 D25 IO74NDB1V4 B16 IO37PDB0V4 C21 IO63PDB1V2 D26 GBB0/IO80NPB1V4 B17 IO41PDB1V0 C22 IO67NDB1V3 D27 GND B18 IO51NDB1V1 C23 IO67PDB1V3 D28 GBA0/IO81NPB1V4 B19 IO59PDB1V2 C24 IO75NDB1V4 D29 VCC 3 -2 0 v2.0 IGLOOe Packaging 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function D30 GBA2/IO82PPB2V0 F5 VMV7 G7 VCC E1 GND F5 VMV7 G8 VMV0 E2 IO303NPB7V3 F6 GND G9 VCCIB0 E3 VCCIB7 F7 GNDQ G10 IO10NDB0V1 E4 IO305PPB7V3 F8 IO12NDB0V1 G11 IO16NDB0V1 E5 VCC F9 IO12PDB0V1 G12 IO22PDB0V2 E6 GAC0/IO02NDB0V0 F10 IO10PDB0V1 G13 IO26PPB0V3 E7 VCCIB0 F11 IO16PDB0V1 G14 IO38NPB0V4 E8 IO06PPB0V0 F12 IO22NDB0V2 G15 IO36NDB0V4 E9 IO24NDB0V2 F13 IO30NDB0V3 G16 IO46NDB1V0 E10 IO24PDB0V2 F14 IO30PDB0V3 G17 IO46PDB1V0 E11 IO13NDB0V1 F15 IO36PDB0V4 G18 IO56NDB1V1 E12 IO13PDB0V1 F16 IO48NDB1V0 G19 IO56PDB1V1 E13 IO34NDB0V4 F17 IO48PDB1V0 G20 IO66NDB1V3 E14 IO34PDB0V4 F18 IO50NDB1V1 G21 IO66PDB1V3 E15 IO40NDB0V4 F19 IO58NDB1V2 G22 VCCIB1 E16 IO49NDB1V1 F20 IO60PDB1V2 G23 VMV1 E17 IO49PDB1V1 F21 IO77NDB1V4 G24 VCC E18 IO50PDB1V1 F22 IO72NDB1V3 G25 GNDQ E19 IO58PDB1V2 F23 IO72PDB1V3 G25 GNDQ E20 IO60NDB1V2 F24 GNDQ G26 VCCIB2 E21 IO77PDB1V4 F25 GND G27 IO86NDB2V0 E22 IO68NDB1V3 F26 VMV2 G28 IO92NDB2V1 E23 IO68PDB1V3 F26 VMV2 G29 IO100PPB2V2 E24 VCCIB1 F27 IO86PDB2V0 G30 GND E25 IO74PDB1V4 F28 IO92PDB2V1 H1 IO294PDB7V2 E26 VCC F29 VCC H2 IO294NDB7V2 E27 GBB1/IO80PPB1V4 F30 IO100NPB2V2 H3 IO300NDB7V3 E28 VCCIB2 G1 GND H4 IO300PDB7V3 E29 IO82NPB2V0 G2 IO296NPB7V2 H5 IO295PDB7V2 E30 GND G3 IO306NDB7V4 H6 IO299PDB7V3 F1 IO296PPB7V2 G4 IO297NDB7V2 H7 VCOMPLA F2 VCC G5 VCCIB7 H8 GND F3 IO306PDB7V4 G6 GNDQ H9 IO08NDB0V0 F4 IO297PDB7V2 G6 GNDQ H10 IO08PDB0V0 v2.0 3 - 21 Package Pin Assignments 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function H11 IO18PDB0V2 J16 IO42PDB1V0 K21 VCC H12 IO26NPB0V3 J17 IO44NDB1V0 K22 IO78PPB1V4 H13 IO28NDB0V3 J18 IO44PDB1V0 K23 IO88NDB2V0 H14 IO28PDB0V3 J19 IO54NDB1V1 K24 IO88PDB2V0 H15 IO38PPB0V4 J20 IO54PDB1V1 K25 IO94PDB2V1 H16 IO42NDB1V0 J21 IO76NPB1V4 K26 IO94NDB2V1 H17 IO52NDB1V1 J22 VCC K27 IO85PDB2V0 H18 IO52PDB1V1 J23 VCCPLB K28 IO85NDB2V0 H19 IO62NDB1V2 J24 VCCIB2 K29 IO93PDB2V1 H20 IO62PDB1V2 J25 IO90PDB2V1 K30 IO93NDB2V1 H21 IO70NDB1V3 J26 IO90NDB2V1 L1 IO286NDB7V1 H22 IO70PDB1V3 J27 GBB2/IO83PDB2V0 L2 IO286PDB7V1 H23 GND J28 IO83NDB2V0 L3 IO298NDB7V3 H24 VCOMPLB J29 IO91PDB2V1 L4 IO298PDB7V3 H25 GBC2/IO84PDB2V0 J30 IO91NDB2V1 L5 IO283PDB7V1 H26 IO84NDB2V0 K1 IO288NDB7V1 L6 IO291NDB7V2 H27 IO96PDB2V1 K2 IO288PDB7V1 L7 IO291PDB7V2 H28 IO96NDB2V1 K3 IO304NDB7V3 L8 IO293PDB7V2 H29 IO89PDB2V0 K4 IO304PDB7V3 L9 IO293NDB7V2 H30 IO89NDB2V0 K5 GAB2/IO308PDB7V4 L10 IO307NPB7V4 J1 IO290NDB7V2 K6 IO308NDB7V4 L11 VCC J2 IO290PDB7V2 K7 IO301PDB7V3 L12 VCC J3 IO302NDB7V3 K8 IO301NDB7V3 L13 VCC J4 IO302PDB7V3 K9 GAC2/IO307PPB7V4 L14 VCC J5 IO295NDB7V2 K10 VCC L15 VCC J6 IO299NDB7V3 K11 IO04PPB0V0 L16 VCC J7 VCCIB7 K12 VCCIB0 L17 VCC J8 VCCPLA K13 VCCIB0 L18 VCC J9 VCC K14 VCCIB0 L19 VCC J10 IO04NPB0V0 K15 VCCIB0 L20 VCC J11 IO18NDB0V2 K16 VCCIB1 L21 IO78NPB1V4 J12 IO20NDB0V2 K17 VCCIB1 L22 IO104NPB2V2 J13 IO20PDB0V2 K18 VCCIB1 L23 IO98NDB2V2 J14 IO32NDB0V3 K19 VCCIB1 L24 IO98PDB2V2 J15 IO32PDB0V3 K20 IO76PPB1V4 L25 IO87PDB2V0 3 -2 2 v2.0 IGLOOe Packaging 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function L26 IO87NDB2V0 N1 IO276PDB7V0 P6 GFC1/IO275PDB7V0 L27 IO97PDB2V1 N2 IO278PDB7V0 P7 GFC0/IO275NDB7V0 L28 IO101PDB2V2 N3 IO280PDB7V0 P8 IO277PDB7V0 L29 IO103PDB2V2 N4 IO284PDB7V1 P9 IO277NDB7V0 L30 IO119NDB3V0 N5 IO279PDB7V0 P10 VCCIB7 M1 IO282NDB7V1 N6 IO285NDB7V1 P11 VCC M2 IO282PDB7V1 N7 IO287NDB7V1 P12 GND M3 IO292NDB7V2 N8 IO281NDB7V0 P13 GND M4 IO292PDB7V2 N9 IO281PDB7V0 P14 GND M5 IO283NDB7V1 N10 VCCIB7 P15 GND M6 IO285PDB7V1 N11 VCC P16 GND M7 IO287PDB7V1 N12 GND P17 GND M8 IO289PDB7V1 N13 GND P18 GND M9 IO289NDB7V1 N14 GND P19 GND M10 VCCIB7 N15 GND P20 VCC M11 VCC N16 GND P21 VCCIB2 M12 GND N17 GND P22 GCC1/IO112PDB2V3 M13 GND N18 GND P23 IO110PDB2V3 M14 GND N19 GND P24 IO110NDB2V3 M15 GND N20 VCC P25 IO109PPB2V3 M16 GND N21 VCCIB2 P26 IO111NPB2V3 M17 GND N22 IO106NDB2V3 P27 IO105PDB2V2 M18 GND N23 IO106PDB2V3 P28 IO105NDB2V2 M19 GND N24 IO108PDB2V3 P29 GCC2/IO117PDB3V0 M20 VCC N25 IO108NDB2V3 P30 IO117NDB3V0 M21 VCCIB2 N26 IO95NDB2V1 R1 GFC2/IO270PDB6V4 M22 NC N27 IO99NDB2V2 R2 GFB1/IO274PPB7V0 M23 IO104PPB2V2 N28 IO99PDB2V2 R3 VCOMPLF M24 IO102PDB2V2 N29 IO107PDB2V3 R4 GFA0/IO273NDB6V4 M25 IO102NDB2V2 N30 IO107NDB2V3 R5 GFB0/IO274NPB7V0 M26 IO95PDB2V1 P1 IO276NDB7V0 R6 IO271NDB6V4 M27 IO97NDB2V1 P2 IO278NDB7V0 R7 GFB2/IO271PDB6V4 M28 IO101NDB2V2 P3 IO280NDB7V0 R8 IO269PDB6V4 M29 IO103NDB2V2 P4 IO284NDB7V1 R9 IO269NDB6V4 M30 IO119PDB3V0 P5 IO279NDB7V0 R10 VCCIB7 v2.0 3 - 23 Package Pin Assignments 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function Pin Number AGLE3000 Function R11 VCC T16 GND U21 VCCIB3 R12 GND T17 GND U22 IO120PDB3V0 R13 GND T18 GND U23 IO128PDB3V1 R14 GND T19 GND U24 IO124PDB3V1 R15 GND T20 VCC U25 IO124NDB3V1 R16 GND T21 VCCIB3 U26 IO126PDB3V1 R17 GND T22 IO109NPB2V3 U27 IO129PDB3V1 R18 GND T23 IO116NDB3V0 U28 IO127PDB3V1 R19 GND T24 IO118NDB3V0 U29 IO125PDB3V1 R20 VCC T25 IO122NPB3V1 U30 IO121NDB3V0 R21 VCCIB2 T26 GCA1/IO114PPB3V0 V1 IO268NDB6V4 R22 GCC0/IO112NDB2V3 T27 GCB0/IO113NPB2V3 V2 IO262PDB6V3 R23 GCB2/IO116PDB3V0 T28 GCA2/IO115PPB3V0 V3 IO260PDB6V3 R24 IO118PDB3V0 T29 VCCPLC V4 IO252PDB6V2 R25 IO111PPB2V3 T30 IO121PDB3V0 V5 IO257NPB6V2 R26 IO122PPB3V1 U1 IO268PDB6V4 V6 IO261NPB6V3 R27 GCA0/IO114NPB3V0 U2 IO264NDB6V3 V7 IO255PDB6V2 R28 VCOMPLC U3 IO264PDB6V3 V8 IO259PDB6V3 R29 GCB1/IO113PPB2V3 U4 IO258PDB6V3 V9 IO259NDB6V3 R30 IO115NPB3V0 U5 IO258NDB6V3 V10 VCCIB6 T1 IO270NDB6V4 U6 IO257PPB6V2 V11 VCC T2 VCCPLF U7 IO261PPB6V3 V12 GND T3 GFA2/IO272PPB6V4 U8 IO265NDB6V3 V13 GND T4 GFA1/IO273PDB6V4 U9 IO263NDB6V3 V14 GND T5 IO272NPB6V4 U10 VCCIB6 V15 GND T6 IO267NDB6V4 U11 VCC V16 GND T7 IO267PDB6V4 U12 GND V17 GND T8 IO265PDB6V3 U13 GND V18 GND T9 IO263PDB6V3 U14 GND V19 GND T10 VCCIB6 U15 GND V20 VCC T11 VCC U16 GND V21 VCCIB3 T12 GND U17 GND V22 IO120NDB3V0 T13 GND U18 GND V23 IO128NDB3V1 T14 GND U19 GND V24 IO132PDB3V2 T15 GND U20 VCC V25 IO130PPB3V2 3 -2 4 v2.0 IGLOOe Packaging 896-Pin FBGA 896-Pin FBGA Pin Number AGLE3000 Function Pin Number AGLE3000 Function V26 IO126NDB3V1 Y1 IO266PDB6V4 V27 IO129NDB3V1 Y2 IO250PDB6V2 V28 IO127NDB3V1 Y3 IO250NDB6V2 V29 IO125NDB3V1 Y4 IO246PDB6V1 V30 IO123PDB3V1 Y5 IO247NDB6V1 W1 IO266NDB6V4 Y6 IO247PDB6V1 W2 IO262NDB6V3 Y7 IO249NPB6V1 W3 IO260NDB6V3 Y8 IO245PDB6V1 W4 IO252NDB6V2 Y9 IO253NDB6V2 W5 IO251NDB6V2 Y10 GEB0/IO235NPB6V0 W6 IO251PDB6V2 Y11 VCC W7 IO255NDB6V2 Y12 VCC W8 IO249PPB6V1 Y13 VCC W9 IO253PDB6V2 Y14 VCC W10 VCCIB6 Y15 VCC W11 VCC Y16 VCC W12 GND Y17 VCC W13 GND Y18 VCC W14 GND Y19 VCC W15 GND Y20 VCC W16 GND Y21 IO142PPB3V3 W17 GND Y22 IO134NDB3V2 W18 GND Y23 IO138NDB3V3 W19 GND Y24 IO140NDB3V3 W20 VCC Y25 IO140PDB3V3 W21 VCCIB3 Y26 IO136PPB3V2 W22 IO134PDB3V2 Y27 IO141NDB3V3 W23 IO138PDB3V3 Y28 IO135NDB3V2 W24 IO132NDB3V2 Y29 IO131NDB3V2 W25 IO136NPB3V2 Y30 IO133PDB3V2 W26 IO130NPB3V2 W27 IO141PDB3V3 W28 IO135PDB3V2 W29 IO131PDB3V2 W30 IO123NDB3V1 v2.0 3 - 25 Package Pin Assignments Part Number and Revision Date Part Number 51700096-003-2 Revised November 2009 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v2.0) Page v1.1 (June 2008) The version changed to v2.0 for IGLOOe datasheet chapters, indicating the datasheet contains information based on final characterization. N/A v1.0 The naming conventions changed for the following pins in the "484-Pin FBGA" for the A3GLE600: 3-6 (January 2008) Pin Number New Function Name J19 IO45PPB2V1 K20 IO45NPB2V1 M2 IO114NPB6V1 N1 IO114PPB6V1 N4 GFC2/IO115PPB6V1 P3 IO115NPB6V1 Advance v0.4 (December 2007) This document was previously in datasheet Advance v0.4. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is v1.0. N/A Advance v0.3 (September 2007) The "484-Pin FBGA" table for AGLE3000 is new. 4-11 The "896-Pin FBGA" package and table for AGLE3000 is new. 4-16 3 -2 6 v2.0 IGLOOe Packaging Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v2.0 3 - 27 Section II - User's Guide Low-Power Flash Technology and Flash*Freeze Mode 1 - FPGA Array Architecture in Low-Power Flash Devices Device Architecture Advanced Flash Switch Unlike SRAM FPGAs, the low-power flash devices use a live-at-power-up ISP flash switch as their programming element. Flash cells are distributed throughout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate VersaTile inputs and outputs. In the flash switch, two transistors share the floating gate, which stores the programming information (Figure 1-1). One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. The latter is used to connect or separate routing nets, or to configure VersaTile logic. It is also used to erase the floating gate. Dedicated high-performance lines are connected as required using the flash switch for fast, low-skew, global signal distribution throughout the device core. Maximum core utilization is possible for virtually any design. The use of the flash switch technology also removes the possibility of firm errors, which are increasingly common in SRAM-based FPGAs. Floating Gate Sensing Switch In Switching Word Switch Out Figure 1-1 * Flash-Based Switch v1.4 1-1 FPGA Array Architecture in Low-Power Flash Devices FPGA Array Architecture Support The flash FPGAs listed in Table 1-1 support the architecture features described in this document. Table 1-1 * Flash-Based FPGAs Family* Series IGLOO(R) (R) ProASIC 3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 1-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 1-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 1 -2 v1.4 FPGA Array Architecture in Low-Power Flash Devices Device Overview The low-power flash devices consist of multiple distinct programmable architectural features (Figure 1-5 on page 1-5 through Figure 1-7 on page 1-6): * FPGA fabric/core (VersaTiles) * Routing and clock resources (VersaNets) * FlashROM * Dedicated SRAM and/or FIFO - 30 k gate and smaller device densities do not support SRAM or FIFO. - Automotive devices do not support FIFO operation. * I/O structures * Flash*Freeze technology and low-power modes Bank 1* I/Os Bank 1 Bank 0 VersaTile User Nonvolatile FlashROM Flash*Freeze Technology Charge Pumps CCC-GL Bank 1 Notes: * Bank 0 for the 30 k devices Flash*Freeze mode is supported on IGLOO devices. Figure 1-2 * IGLOO and ProASIC3 nano Device Architecture Overview with Two I/O Banks (applies to 10 k and 30 k device densities, excluding IGLOO PLUS devices) v1.4 1-3 FPGA Array Architecture in Low-Power Flash Devices Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os ISP AES Decryption User Nonvolatile FlashRom Flash*Freeze Technology Bank 0 Bank 1 VersaTile Charge Pumps Bank 1 Note: Flash*Freeze mode is supported on IGLOO devices. Figure 1-3 * IGLOO Device Architecture Overview with Two I/O Banks with RAM and PLL (60 k and 125 k gate densities) Bank 1 I/Os Bank 1 Bank 0 VersaTile User Nonvolatile FlashROM Flash*Freeze Technology Charge Pumps CCC-GL Bank 1 Note: Flash*Freeze mode is supported on IGLOO devices. Figure 1-4 * IGLOO Device Architecture Overview with Three I/O Banks (AGLN015, AGLN020, A3PN015, and A3PN020) 1 -4 v1.4 FPGA Array Architecture in Low-Power Flash Devices Bank 0 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 1 Bank 3 CCC I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps Bank 2 Note: Flash*Freeze technology only applies to IGLOO and ProASIC3L families. Figure 1-5 * IGLOO, IGLOO nano, ProASIC3 nano, and ProASIC3/L Device Architecture Overview with Four I/O Banks (AGL600 device is shown) Bank 0 Bank 1 Bank 3 CCC* RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os Bank 1 Bank 3 VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps Bank 2 Note: * AGLP030 does not contain a PLL or support AES security. Figure 1-6 * IGLOO PLUS Device Architecture Overview with Four I/O Banks v1.4 1-5 FPGA Array Architecture in Low-Power Flash Devices Bank 0 Bank 1 CCC Bank 2 Bank 7 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os Bank 3 Bank 6 VersaTile ISP AES Decryption User Nonvolatile FlashRom Bank 5 Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 4 Note: Flash*Freeze technology only applies to IGLOOe devices. Figure 1-7 * IGLOOe and ProASIC3E Device Architecture Overview (AGLE600 device is shown) 1 -6 v1.4 FPGA Array Architecture in Low-Power Flash Devices Core Architecture VersaTile The proprietary IGLOO and ProASIC3 device architectures provide granularity comparable to gate arrays. The device core consists of a sea-of-VersaTiles architecture. As illustrated in Figure 1-8, there are four inputs in a logic VersaTile cell, and each VersaTile can be configured using the appropriate flash switch connections: * Any 3-input logic function * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set (on a 4th input) VersaTiles can flexibly map the logic and sequential gates of a design. The inputs of the VersaTile can be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line routing resources. VersaTiles and larger functions can be connected with any of the four levels of routing hierarchy. When the VersaTile is used as an enable D-flip-flop, SET/CLR is supported by a fourth input. The SET/CLR signal can only be routed to this fourth input over the VersaNet (global) network. However, if, in the user's design, the SET/CLR signal is not routed over the VersaNet network, a compile warning message will be given, and the intended logic function will be implemented by two VersaTiles instead of one. The output of the VersaTile is F2 when the connection is to the ultra-fast local lines, or YL when the connection is to the efficient long-line or very-long-line resources. 0 1 Y Pin 1 Data X3 0 1 0 1 F2 YL 0 1 CLK X2 CLR/ Enable X1 CLR XC* Legend: Via (hard connection) Switch (flash connection) Ground * This input can only be connected to the global clock distribution network. Figure 1-8 * Low-Power Flash Device Core VersaTile v1.4 1-7 FPGA Array Architecture in Low-Power Flash Devices Array Coordinates During many place-and-route operations in the Actel Designer software tool, it is possible to set constraints that require array coordinates. Table 1-2 provides array coordinates of core cells and memory blocks for IGLOO and ProASIC3 devices. Table 1-3 provides the information for IGLOO PLUS devices. Table 1-4 on page 1-9 provides the information for IGLOO nano and ProASIC3 nano devices. The array coordinates are measured from the lower left (0, 0). They can be used in region constraints for specific logic groups/blocks, designated by a wildcard, and can contain core cells, memories, and I/Os. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination. It is not listed in Table 1-2. The Designer ChipPlanner tool provides the array coordinates of all I/O locations. I/O and cell coordinates are used for placement constraints. However, I/O placement is easier by package pin assignment. Figure 1-9 on page 1-9 illustrates the array coordinates of a 600 k gate device. For more information on how to use array coordinates for region/placement constraints, see the Designer User's Guide or online help (available in the software) for software tools. Table 1-2 * IGLOO and ProASIC3 Array Coordinates VersaTiles Device Min. Max. Entire Die Bottom Top Min. Max. IGLOO ProASIC3/ ProASIC3L x y x y (x, y) (x, y) (x, y) (x, y) AGL015 A3P015 3 2 34 13 None None (0, 0) (37, 15) AGL030 A3P030 3 3 66 13 None None (0, 0) (69, 15) AGL060 A3P060 3 2 66 25 None (3, 26) (0, 0) (69, 29) AGL125 A3P125 3 2 130 25 None (3, 26) (0, 0) (133, 29) AGL250 A3P250/L 3 2 130 49 None (3, 50) (0, 0) (133, 53) AGL400 A3P400 3 2 194 49 None (3, 50) (0, 0) (197, 53) AGL600 A3P600/L 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) AGL1000 A3P1000/L 3 4 258 99 (3, 2) (3, 100) (0, 0) (261, 103) AGLE600 A3PE600/L, RT3PE600L 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) A3PE1500 3 4 322 123 (3, 2) (3, 124) (0, 0) (325, 127) A3PE3000/L, RT3PE3000L 3 6 450 173 (3, 2) or (3, 4) (3, 174) or (3, 176) (0, 0) (453, 179) AGLE3000 Table 1-3 * IGLOO PLUS Array Coordinates VersaTiles Device 1 -8 Memory Rows Min. Memory Rows Max. Entire Die Bottom Top Min. Max. IGLOO PLUS x y x y (x, y) (x, y) (x, y) (x, y) AGLP030 2 3 67 13 None None (0, 0) (69, 15) AGLP060 2 2 67 25 None (3, 26) (0, 0) (69, 29) AGLP125 2 2 131 25 None (3, 26) (0, 0) (133, 29) v1.4 FPGA Array Architecture in Low-Power Flash Devices Table 1-4 * IGLOO nano and ProASIC3 nano Array Coordinates VersaTiles Device Memory Rows Entire Die Min. Max. Bottom Top Min. Max. IGLOO nano ProASIC3 nano (x, y) (x, y) (x, y) (x, y) (x, y) (x, y) AGLN010 A3P010 (0, 2) (32, 5) None None (0, 0) (34, 5) AGLN015 A3PN015 (0, 2) (32, 9) None None (0, 0) (34, 9) AGLN020 A3PN020 (0, 2) 32, 13) None None (0, 0) (34, 13) AGLN060 A3PN060 (3, 2) (66, 25) None (3, 26) (0, 0) (69, 29) AGLN125 A3PN125 (3, 2) (130, 25) None (3, 26) (0, 0) (133, 29) AGLN250 A3PN250 (3, 2) (130, 49) None (3, 50) (0, 0) (133, 49) Top Row (7, 79) to (189, 79) Bottom Row (5, 78) to (192, 78) (0, 79) I/O Tile (197, 79) Memory (3, 77) Blocks (3, 76) (194, 77) Memory (194, 76) Blocks VersaTile (Core) (3, 75) (194, 75) VersaTile (Core) (194, 4) VersaTile (Core) VersaTile (Core) (3, 4) (194, 3) Memory (194, 2) Blocks Memory (3, 3) Blocks (3, 2) (197, 1) (0, 0) I/O Tile UJTAG FlashROM Top Row (5, 1) to (168, 1) Bottom Row (7, 0) to (165, 0) (197, 0) Top Row (169, 1) to (192, 1) Note: The vertical I/O tile coordinates are not shown. West-side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east-side coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}. Figure 1-9 * Array Coordinates for AGL600, AGLE600, A3P600, and A3PE600 v1.4 1-9 FPGA Array Architecture in Low-Power Flash Devices Routing Architecture The routing structure of low-power flash devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources; efficient long-line resources; high-speed, very-long-line resources; and the high-performance VersaNet networks. The ultra-fast local resources are dedicated lines that allow the output of each VersaTile to connect directly to every input of the eight surrounding VersaTiles (Figure 1-10 on page 1-10). The exception to this is that the SET/CLR input of a VersaTile configured as a D-flip-flop is driven only by the VersaTile global network. The efficient long-line resources provide routing for longer distances and higher-fanout connections. These resources vary in length (spanning one, two, or four VersaTiles), run both vertically and horizontally, and cover the entire device (Figure 1-11 on page 1-11). Each VersaTile can drive signals onto the efficient long-line resources, which can access every input of every VersaTile. Routing software automatically inserts active buffers to limit loading effects. The high-speed, very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length 12 VersaTiles in the vertical direction and length 16 in the horizontal direction from a given core VersaTile (Figure 1-12 on page 1-11). Very long lines in low-power flash devices have been enhanced over those in previous ProASIC families. This provides a significant performance boost for long-reach signals. The high-performance VersaNet global networks are low-skew, high-fanout nets that are accessible from external pins or internal logic. These nets are typically used to distribute clocks, resets, and other high-fanout nets requiring minimum skew. The VersaNet networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input of every VersaTile. For more details on VersaNets, refer to Global Resources in Actel Low-Power Flash Devices. Long Lines L Inputs L L L Ultra-Fast Local Lines (connects a VersaTile to the adjacent VersaTile, I/O buffer, or memory block) Output L L L L L Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection. Figure 1-10 * Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors 1 -1 0 v1.4 FPGA Array Architecture in Low-Power Flash Devices Spans 4 VersaTiles Spans 1 VersaTile Spans 2 VersaTiles VersaTile L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L Spans 1 VersaTile Spans 2 VersaTiles Spans 4 VersaTiles Figure 1-11 * Efficient Long-Line Resources High-Speed, Very-Long-Line Resources Pad Ring SRAM I/O Ring Pad Ring I/O Ring 16x12 Block of VersaTiles Pad Ring Figure 1-12 * Very-Long-Line Resources v1.4 1 - 11 FPGA Array Architecture in Low-Power Flash Devices Related Documents Handbook Documents Global Resources in Actel Low-Power Flash Devices http://www.actel.com/documents/LPD_Glorbal_HBs.pdf User's Guides Designer User's Guide http://www.actel.com/documents/designer_ug.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet. To improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage information. No technical changes were made to the content unless explicitly listed. Part Number 51700094-002-4 Revised December 2008 1 -1 2 v1.4 FPGA Array Architecture in Low-Power Flash Devices List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.3 (October 2008) v1.2 (June 2008) v1.1 (March 2008) v1.0 (January 2008) Changes in Current Version (v1.4) Page IGLOO nano and ProASIC3 nano devices were added to Table 1-1 * Flash-Based FPGAs. 1-2 Figure 1-2 * IGLOO and ProASIC3 nano Device Architecture Overview with Two I/O Banks (applies to 10 k and 30 k device densities, excluding IGLOO PLUS devices) through Figure 1-5 * IGLOO, IGLOO nano, ProASIC3 nano, and ProASIC3/L Device Architecture Overview with Four I/O Banks (AGL600 device is shown) are new. 1-3, 1-4 Table 1-4 * IGLOO nano and ProASIC3 nano Array Coordinates is new. 1-9 The title of this document was changed from "Core Architecture of IGLOO and ProASIC3 Devices" to "FPGA Array Architecture in Low-Power Flash Devices." 1-1 The "FPGA Array Architecture Support" section was revised to include new families and make the information more concise. 1-2 Table 1-2 * IGLOO and ProASIC3 Array Coordinates was updated to include Military ProASIC3/EL and RT ProASIC3 devices. 1-8 The following changes were Table 1-1 * Flash-Based FPGAs: in 1-2 Table 1-1 * Flash-Based FPGAs and the accompanying text was updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "Device Overview" section are new. 1-2 The "Device Overview" section was updated to note that 15 k devices do not support SRAM or FIFO. 1-3 Figure 1-6 * IGLOO PLUS Device Architecture Overview with Four I/O Banks is new. 1-5 Table 1-2 * IGLOO and ProASIC3 Array Coordinates was updated to add A3P015 and AGL015. 1-8 Table 1-3 * IGLOO PLUS Array Coordinates is new. 1-8 made to the family descriptions * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. v1.4 1 - 13 2 - Actel's Flash*Freeze Technology and LowPower Modes Flash*Freeze Technology and Low-Power Modes Actel IGLOO,(R) IGLOO nano, IGLOO PLUS, ProASIC(R)3L, and Radiation-Tolerant (RT) ProASIC3 FPGAs with Flash*Freeze technology are designed to meet the most demanding power and area challenges of today's portable electronics products with a reprogrammable, small-footprint, fullfeatured flash FPGA. These devices offer lower power consumption in static and dynamic modes, utilizing the unique Flash*Freeze technology, than any other FPGA or CPLD. IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 devices offer various power-saving modes that enable every system to utilize modes that achieve the lowest total system power. Low Power Active capability (static idle) allows for ultra-low power consumption while the device is operational in the system by maintaining SRAM, registers, I/Os, and logic functions. Flash*Freeze technology provides an ultra-low-power static mode (Flash*Freeze mode) that retains all SRAM and register information with rapid recovery to Active (operating) mode. IGLOO nano and IGLOO PLUS devices have an additional feature when operating in Flash*Freeze mode, allowing them to retain I/O states as well as SRAM and register states. This mechanism enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept in their original states. In addition, I/Os and clocks connected to the FPGA can still be toggled without impact on device power consumption. While in Flash*Freeze mode, the device retains all core register states and SRAM information. This mode can be configured so that no power is consumed by the I/O banks, clocks, JTAG pins, or PLLs; and the IGLOO and IGLOO PLUS devices consume as little as 5 W, while IGLOO nano devices consume as little as 2 W. Actel offers a state management IP core to aid users in gating clocks and managing data before entering Flash*Freeze mode. This document will guide users in selecting the best low-power mode for their applications, and introduces Actel's Flash*Freeze management IP core. v2.3 2-1 Actel's Flash*Freeze Technology and Low-Power Modes Actel's Flash Families Support the Flash*Freeze Feature The low-power flash FPGAs listed in Table 2-1 support the Flash*Freeze feature and the functions described in this document. Table 2-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 2-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 2-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 2 -2 v2.3 Actel's Flash*Freeze Technology and Low-Power Modes Low-Power Modes Overview Table 2-2 summarizes the low-power modes that achieve power consumption reduction when the FPGA or system is idle. Table 2-2 * Power Modes Summary Mode VCCI VCC Core Clocks ULSICC Macro To Enter Mode To Resume Operation Trigger Active On On On On N/A Initiate clock None - Idle On On On Off N/A Stop clock Initiate clock External Flash*Freeze type 1 On On On On* N/A Assert FF pin Flash*Freeze type 2 On On On On* Sleep On Off Off Off N/A Shut down VCC Shutdown Off Off Off Off N/A Shut down VCC and VCCI supplies Static Deassert FF External pin Used to Assert FF Deassert FF External enter pin and pin Flash*Freeze assert LSICC mode Turn on External VCC supply Turn on VCC and VCCI supplies External * External clocks can be left toggling while the device is in Flash*Freeze mode. Clocks generated by the embedded PLL will be turned off automatically. Static (Idle) Mode In Static (Idle) mode, none of the clock inputs is switching, and static power is the only power consumed by the device. This mode can be achieved by switching off the incoming clocks to the FPGA, thus benefitting from reduced power consumption. In addition, I/Os draw only minimal leakage current. In this mode, embedded SRAM, I/Os, and registers retain their values so the device can enter and exit this mode just by switching the clocks on or off. If the device-embedded PLL is used as the clock source, Static (Idle) mode can easily be entered by pulling the PLL POWERDOWN pin LOW (active Low), which will turn off the PLL. v2.3 2-3 Actel's Flash*Freeze Technology and Low-Power Modes Flash*Freeze Mode IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 FPGAs offer an ultra-low static power mode to reduce power consumption while preserving the state of the registers, SRAM contents, and I/O states (IGLOO nano and IGLOO PLUS only) without switching off any power supplies, inputs, or input clocks. Flash*Freeze technology enables the user to switch to Flash*Freeze mode within 1 s, thus simplifying low-power design implementation. The Flash*Freeze (FF) pin (active Low) is a dedicated pin used to enter or exit Flash*Freeze mode directly; or the pin can be routed internally to the FPGA core and state management IP to allow the user's application to decide if and when it is safe to transition to this mode. If the FF pin is not used, it can be used as a regular I/O. The FF pin has a built-in glitch filter and optional Schmitt trigger (not available for all devices) to prevent entering or exiting Flash*Freeze mode accidentally. There are two ways to use Flash*Freeze mode. In Flash*Freeze type 1, entering and exiting the mode is exclusively controlled by the assertion and deassertion of the FF pin. This enables an external processor or human interface device to directly control Flash*Freeze mode; however, valid data must be preserved using standard procedures (refer to the "Flash*Freeze Mode Device Behavior" section on page 2-9). In Flash*Freeze mode type 2, entering and exiting the mode is controlled by both the FF pin AND user-defined logic. Flash*Freeze management IP may be used in type 2 mode for clock and data management while entering and exiting Flash*Freeze mode. Flash*Freeze Type 1: Control by Dedicated Flash*Freeze Pin Flash*Freeze type 1 is intended for systems where either the device will be reset upon exiting Flash*Freeze mode, or data and clock are managed externally. The device enters Flash*Freeze mode 1 s after the dedicated FF pin is asserted (active Low), and returns to normal operation when the FF pin is deasserted (High) (Figure 2-1 on page 2-5). In this mode, FF pin assertion or deassertion is the only condition that determines entering or exiting Flash*Freeze mode. In Actel Libero(R) Integrated Design Environment (IDE) v8.2 and before, this mode is implemented by enabling Flash*Freeze mode (default setting) in the Compile options of the Actel Designer software. To simplify usage of Flash*Freeze mode, beginning with Libero IDE v8.3, an INBUF_FF I/O macro was introduced. An INBUF_FF I/O buffer must be used to identify the Flash*Freeze input. Actel recommends switching to the new implementation. In Libero IDE v8.3 and later, the user must manually instantiate the INBUF_FF macro in the top level of the design to implement Flash*Freeze Type 1, as shown in Figure 2-1 on page 2-5. 2 -4 v2.3 Actel's Flash*Freeze Technology and Low-Power Modes Figure 2-1 shows the concept of FF pin control in Flash*Freeze mode type 1. Actel IGLOO, IGLOO PLUS, IGLOO nano, ProASIC3L, or RT ProASIC3 Device INBUF_FF Flash*Freeze Mode Control To FPGA Core or Floating Flash*Freeze (FF) Pin Flash*Freeze Signal Enables Entering Flash*Freeze Mode 1 AND Flash*Freeze Mode Flash*Freeze Technology User Design Figure 2-1 * Flash*Freeze Mode Type 1 - Controlled by the Flash*Freeze Pin Figure 2-2 shows the timing diagram for entering and exiting Flash*Freeze mode type 1. Normal Operation Normal Operation Flash*Freeze Mode Flash*Freeze Pin t = 1 s t = 1 s Figure 2-2 * Flash*Freeze Mode Type 1 - Timing Diagram v2.3 2-5 Actel's Flash*Freeze Technology and Low-Power Modes Flash*Freeze Type 2: Control by Dedicated Flash*Freeze Pin and Internal Logic The device can be made to enter Flash*Freeze mode by activating the FF pin together with Actel's Flash*Freeze management IP core (refer to the "Flash*Freeze Management IP" section on page 2-15 for more information) or user-defined control logic (Figure 2-3) within the FPGA core. This method enables the design to perform important activities before allowing the device to enter Flash*Freeze mode, such as transitioning into a safe state, completing the processing of a critical event. Designers are encouraged to take advantage of Actel's Flash*Freeze Management IP to handle clean entry and exit of Flash*Freeze mode (described later in this document). The device will only enter Flash*Freeze mode when the Flash*Freeze pin is asserted (active Low) and the User Low Static ICC (ULSICC) macro input signal, called the LSICC signal, is asserted (High). One condition is not sufficient to enter Flash*Freeze mode type 2; both the FF pin and LSICC signal must be asserted. When Flash*Freeze type 2 is implemented in the design, the ULSICC macro needs to be instantiated by the user. There are no functional differences in the device whether the ULSICC macro is instantiated or not, and whether the LSICC signal is asserted or deasserted. The LSICC signal is used only to control entering Flash*Freeze mode. Figure 2-4 on page 2-7 shows the timing diagram for entering and exiting Flash*Freeze mode type 2. After exiting Flash*Freeze mode type 2 by deasserting the Flash*Freeze pin, the LSICC signal must be deasserted by the user design. This will prevent entering Flash*Freeze mode by asserting the Flash*Freeze pin only. Refer to Table 2-3 for Flash*Freeze (FF) pin and LSICC signal assertion and deassertion values. Table 2-3 * Flash*Freeze Mode Type 1 and Type 2 - Signal Assertion and Deassertion Values Signal Assertion Value Deassertion Value Flash*Freeze (FF) pin Low High LSICC signal High Low Notes: 1. The Flash*Freeze (FF) pin is an active-Low signal, and LSICC is an active-High signal. 2. The LSICC signal is used only in Flash*Freeze mode type 2. Actel IGLOO, IGLOO PLUS, IGLOO nano, ProASIC3L, or RT ProASIC3 Device Flash*Freeze (FF) Pin Connect to Top-Level Port Auto-Connected to IP INBUF_FF Flash*Freeze Signal Enables Entering Flash*Freeze Mode ULSICC Macro Flash*Freeze Management IP AND Flash*Freeze Mode Flash*Freeze Technology User Design Figure 2-3 * Flash*Freeze Mode Type 2 - Controlled by Flash*Freeze Pin and Internal Logic (LSICC signal) 2 -6 v2.3 Actel's Flash*Freeze Technology and Low-Power Modes Normal Operation Normal Operation Flash*Freeze Mode Flash*Freeze Pin LSICC Signal t = 1 s t = 1 s Figure 2-4 * Flash*Freeze Mode Type 2 - Timing Diagram Table 2-4 summarizes the Flash*Freeze mode implementations. Table 2-4 * Flash*Freeze Mode Usage Flash*Freeze Mode Type 1 Description Flash*Freeze mode is controlled only by the FF pin. 2 Flash*Freeze Pin State Instantiate ULSICC Macro LSICC Signal Operating Mode Deasserted No N/A Normal operation Asserted No N/A Flash*Freeze mode Deasserted Normal operation Flash*Freeze mode is "Don't care" controlled by the FF pin and Deasserted LSICC signal. Asserted Yes Yes Yes "Don't care" Normal operation Asserted Flash*Freeze mode Note: Refer to Table 2-3 on page 2-6 for Flash*Freeze pin and LSICC signal assertion and deassertion values. IGLOO, ProASIC3L, and RT ProASIC3 I/O State in Flash*Freeze Mode In IGLOO and ProASIC3L devices, when the device enters Flash*Freeze mode, I/Os become tristated. If the weak pull-up or pull-down feature is used, the I/Os will maintain the configured weak pull-up or pull-down status. This feature enables the design to set the I/O state to a certain level that is determined by the pull-up/-down configuration. Table 2-5 shows the I/O pad state based on the configuration and buffer type. Note that configuring weak pull-up or pull-down for the FF pin is not allowed. The FF pin can be configured as a Schmitt trigger input in IGLOOe, IGLOO nano, IGLOO PLUS, and ProASIC3EL devices. Table 2-5 * IGLOO, ProASIC3L, and RT ProASIC3 Flash*Freeze Mode (type 1 and type 2)--I/O Pad State Buffer Type I/O Pad Weak Pull-Up/-Down I/O Pad State in Flash*Freeze Mode Input/Global Enabled Weak pull-up/pull-down* Disabled Tristate* Enabled Weak pull-up/pull-down Output Bidirectional / Tristate Buffer E=0 (input/tristate) E = 1 (output) Disabled Tristate Enabled Weak pull-up/pull-down* Disabled Tristate* Enabled Weak pull-up/pull-down Disabled Tristate * Internal core logic driven by this input/global buffer will be tied High as long as the device is in Flash*Freeze mode. v2.3 2-7 Actel's Flash*Freeze Technology and Low-Power Modes IGLOO nano and IGLOO PLUS I/O State in Flash*Freeze Mode In IGLOO nano and IGLOO PLUS devices, users have multiple options in how to configure I/Os during Flash*Freeze mode: 1. Hold the previous state 2. Set I/O pad to weak pull-up or pull-down 3. Tristate I/O pads The I/O configuration must be configured by the user in the I/O Attribute Editor or in a PDC constraint file, and can be done on a pin-by-pin basis. The output hold feature will hold the output in the last registered state, using the I/O pad weak pull-up or pull-down resistor when the FF pin is asserted. When inputs are configured with the hold feature enabled, the FPGA core side of the input will hold the last valid state of the input pad before the device entered Flash*Freeze mode. The input pad can be driven to any value, configured as tristate, or configured with the weak pullup or pull-down I/O pad feature during Flash*Freeze mode without affecting the hold state. If the weak pull-up or pull-down feature is used without the output hold feature, the input and output pads will maintain the configured weak pull-up or pull-down status during Flash*Freeze mode and normal operation. If a fixed weak pull-up or pull-down is defined on an output buffer or as bidirectional in output mode, and a hold state is also defined for the same pin, the pin will be configured in hold state mode during Flash*Freeze mode. During normal operation, the pin will be configured with the predefined weak pull-up or pull-down. Any I/Os that do not use the hold state or I/O pad weak pull-up or pull-down features will be tristated during Flash*Freeze mode and the FPGA core will be driven High by inputs. Inputs that are tristated during Flash*Freeze mode may be left floating without any reliability concern or impact to power consumption. Table 2-6 shows the I/O pad state based on the configuration and buffer type. Note that configuring weak pull-up or pull-down for the FF pin is not allowed. Table 2-6 * IGLOO nano and IGLOO PLUS Flash*Freeze Mode (type 1 and type 2)--I/O Pad State Buffer Type Input Output Bidirectional / Tristate Buffer E=0 (input/tristate) E = 1 (output) Hold State I/O Pad Weak Pull-Up/-Down I/O Pad State in Flash*Freeze Mode Enabled Enabled Weak pull-up/pull-down 1 Disabled Enabled Weak pull-up/pull-down 2 Enabled Disabled Tristate 1 Disabled Disabled Tristate 2 Enabled "Don't care" Weak pull to hold state Disabled Enabled Weak pull-up/pull-down Disabled Disabled Tristate Enabled Enabled Weak pull-up/pull-down 1 Disabled Enabled Weak pull-up/pull-down 2 Enabled Disabled Tristate 1 Disabled Disabled Tristate 2 Enabled "Don't care" Weak pull to hold state 3 Disabled Enabled Weak pull-up/pull-down Disabled Disabled Tristate Notes: 1. Internal core logic driven by this input buffer will be set to the value this I/O had when entering Flash*Freeze mode. 2. Internal core logic driven by this input buffer will be tied High as long as the device is in Flash*Freeze mode. 3. For bidirectional buffers: Internal core logic driven by the input portion of the bidirectional buffer will be set to the hold state. 2 -8 v2.3 Actel's Flash*Freeze Technology and Low-Power Modes Flash*Freeze Mode Device Behavior Entering Flash*Freeze Mode * Actel IGLOO, IGLOO nano, IGLOO PLUS, ProASCI3L, and RT ProASIC3 devices are designed and optimized to enter Flash*Freeze mode only when power supplies are stable. If the device is being powered up while the FF pin is asserted (Flash*Freeze mode type 1), or while both FF pin and LSICC signal are asserted (Flash*Freeze mode type 2), the device is expected to enter Flash*Freeze mode within 5 s after the I/Os and FPGA core have reached their activation levels. * If the device is already powered up when the FF pin is asserted, the device will enter Flash*Freeze mode within 1 s (type 1). In Flash*Freeze mode type 2 operation, entering Flash*Freeze mode is completed within 1 s after both FF pin and LSICC signal are asserted. Exiting Flash*Freeze mode is completed within 1 s after deasserting the FF pin only. PLLs * If an embedded PLL is used, entering Flash*Freeze mode will automatically power down the PLL. * The PLL output clocks will stop toggling within 1 s after the assertion of the FF pin in type 1, or after both FF pin and LSICC signal are asserted in type 2. At the same time, I/Os will transition into the state specified in Table 2-6 on page 2-8. The user design must ensure it is safe to enter Flash*Freeze mode. I/Os and Globals * While entering Flash*Freeze mode, inputs, globals, and PLLs will enter their Flash*Freeze state asynchronously to each other. As a result, clock and data glitches and narrow pulses may be generated while entering Flash*Freeze mode, as shown in Figure 2-5. Flash*Freeze Pin External Clock Internal Clock Enters Flash*Freeze Mode Exits Flash*Freeze Mode Figure 2-5 * Narrow Clock Pulses During Flash*Freeze Entrance and Exit * I/O banks are not all deactivated simultaneously when entering Flash*Freeze mode. This can cause clocks and inputs to become disabled at different times, resulting in unexpected data being captured. * Upon entering Flash*Freeze mode, all inputs and globals become tied High internally (except when an input hold state is used on IGLOO nano or IGLOO PLUS devices). If any of these signals are driven Low or tied Low externally, they will experience a Low to High transition internally when entering Flash*Freeze mode. * Upon entering type 2 Flash*Freeze mode, ensure the LSICC signal (active High) does not deassert. This can prevent the device from entering Flash*Freeze mode. * Asynchronous input to output paths may experience output glitches. For example, on a direct in-to-out path, if the current state is '0' and the input bank turns off first, the input and then the output will transition to '1' before the output enters its Flash*Freeze state. This can be prevented by using latches in asynchronous in-to-out paths. * The above situations can cause glitches or invalid data to be clocked into and preserved in the device. Refer to the "Flash*Freeze Design Guide" section on page 2-13 for solutions. v2.3 2-9 Actel's Flash*Freeze Technology and Low-Power Modes During Flash*Freeze Mode * PLLs are turned off during Flash*Freeze mode. * I/O pads are configured according to Table 2-5 on page 2-7 and Table 2-6 on page 2-8. * Inputs and input clocks to the FPGA can toggle without any impact on static power consumption, assuming weak pull-up or pull-down is not selected. * If weak pull-up or pull-down is selected and the input is driven to the opposite direction, power dissipation will occur. * Any toggling signals will be charging and discharging the package pin capacitance. * IGLOO and ProASIC3L outputs will be tristated unless the I/O is configured with weak pull-up or pull-down. The output of the I/O to the FPGA core is logic High regardless of whether the I/O pin is configured with a weak pull-up or pull-down. Refer to Table 2-5 on page 2-7 for more information. * IGLOO nano and IGLOO PLUS output behavior will be based on the configuration defined by the user. Refer to Table 2-6 on page 2-8 for a description of output behavior during Flash*Freeze mode. * The JTAG circuit is active; however, JTAG operations, such as JTAG commands, JTAG bypass, programming, and authentication, cannot be executed. The device must exit Flash*Freeze mode before JTAG commands can be sent. TCK should be static to avoid extra power consumption from the JTAG state machine. * The FF pin must be externally asserted for the device to stay in Flash*Freeze mode. * The FF pin is still active; i.e., the pin is used to exit Flash*Freeze mode when deasserted. Exiting Flash*Freeze Mode I/Os and Globals * While exiting Flash*Freeze mode, inputs and globals will exit their Flash*Freeze state asynchronously to each other. As a result, clock and data glitches and narrow pulses may be generated while exiting Flash*Freeze mode, unless clock gating schemes are used. * I/O banks are not all activated simultaneously when exiting Flash*Freeze mode. This can cause clocks and inputs to become enabled at different times, resulting in unexpected data being captured. * Upon exiting Flash*Freeze mode, inputs and globals will no longer be tied High internally (does not apply to input hold state on IGLOO nano and IGLOO PLUS). If any of these signals are driven Low or tied Low externally, they will experience a High-to-Low transition internally when exiting Flash*Freeze mode. * Applies only to IGLOO nano and IGLOO PLUS: Output hold state is asynchronously controlled by the signal driving the output buffer (output signal). This ensures a clean, glitch-free transition from hold state to output drive. However, any glitches on the output signal during exit from Flash*Freeze mode may result in glitches on the output pad. * The above situations can cause glitches or invalid data to be clocked into and preserved in the device. Refer to the "Flash*Freeze Design Guide" on page 2-13 for solutions. PLLs * If the embedded PLL is used, the design must allow maximum acquisition time (per device datasheet) for the PLL to acquire the lock signal. Flash*Freeze Pin Locations Refer to the Pin Descriptions chapter of the handbook for information regarding Flash*Freeze pin location on the available packages. The Flash*Freeze pin location is independent of the device, allowing migration to larger or smaller devices while maintaining the same pin location on the board. 2 -1 0 v2.3 Actel's Flash*Freeze Technology and Low-Power Modes Sleep and Shutdown Modes Sleep Mode Actel IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 FPGAs support Sleep mode when device functionality is not required. In Sleep mode, VCC (core voltage), VJTAG (JTAG DC voltage), and VPUMP (programming voltage) are grounded, resulting in the FPGA core being turned off to reduce power consumption. While the device is in Sleep mode, the rest of the system can still be operating and driving the input buffers of the device. The driven inputs do not pull up the internal power planes, and the current draw is limited to minimal leakage current. Table 2-7 shows the power supply status in Sleep mode. Table 2-7 * Sleep Mode--Power Supply Requirement for IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 Devices Power Supplies Power Supply State VCC Powered off VCCI = VMV Powered on VJTAG Powered off VPUMP Powered off Refer to the "Power-Up/-Down Behavior" section on page 2-12 for more information about I/O states during Sleep mode and the timing diagram for entering and exiting Sleep mode. Shutdown Mode Shutdown mode is supported for all IGLOO nano and IGLOO PLUS devices as well the following IGLOO/e devices: AGL015, AGL030, AGLE600, AGLE3000, and A3PE3000L. Shutdown mode can be used by turning off all power supplies when the device function is not needed. Cold-sparing and hot-insertion features enable these devices to be powered down without turning off the entire system. When power returns, the live-at-power-up feature enables operation of the device after reaching the voltage activation point. v2.3 2 - 11 Actel's Flash*Freeze Technology and Low-Power Modes Using Sleep and Shutdown Modes in the System Depending on the power supply and the components used in an application, there are many ways to power on or off the power supplies connected to the device. For example, Figure 2-6 shows how a microprocessor can be used to control a power FET. Actel recommends that power FETs with low resistance be used to perform the switching action. Power Supply P-Channel Power FET Microprocessor Power-On/Off Control Signal VCC VJTAG, and, VPUMP Pins IGLOO, IGLOO PLUS, IGLOO nano, or ProASIC3L Devices Figure 2-6 * Controlling Power-On/-Off State Using Microprocessor and Power FET Figure 2-7 shows how a microprocessor can be used with a voltage regulator's shutdown pin to turn on or off the power supplies connected to the device. Microprocessor Shutdown Control Signal for VCCI Shutdown Control Signal for VCC VCCI Power Pin Power Supply Voltage Regulator IGLOO, IGLOO PLUS, IGLOO nano, or ProASIC3L Device VCC , VJTAG, and VPUMP Pins Figure 2-7 * Controlling Power-On/-Off State Using Microprocessor and Voltage Regulator Power-Up/-Down Behavior By design, all IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 I/Os are in tristate mode before device power-up. The I/Os remain tristated until the last voltage supply (VCC or VCCI ) is powered to its activation level. After the last supply reaches its functional level, the outputs exit the tristate mode and drive the logic at the input of the output buffer. The behavior of user I/Os is independent of the VCC and VCCI sequence or the state of other voltage supplies of the FPGA (VPUMP and VJTAG). During power-down, device I/Os become tristated once the first power supply (VCC or VCCI) drops below its deactivation voltage level. The I/O behavior during power-down is also independent of voltage supply sequencing. Figure 2-8 on page 2-13 shows a timing diagram when the VCC power supply crosses the activation and deactivation trip points in a typical application when the VCC power supply ramp-rate is 100 s (ramping from 0 V to 1.5 V in this example). This is the timing diagram for the FPGA entering and exiting Sleep mode, as this function is dependent on powering VCC down or up. Depending on the 2 -1 2 v2.3 Actel's Flash*Freeze Technology and Low-Power Modes ramp-rate of the power supply and board-level configurations, the user can easily calculate how long it will take for the core to become inactive or active. For more information, refer to PowerUp/-Down Behavior of Low-Power Flash Devices. VCC Deactivation Trip Point Vd = 0.75 0.25 V VCC = 1.5 V Activation Trip Point Va = 0.85 0.25 V t = 50 s Sleep Mode t = 56.6 s Figure 2-8 * Entering and Exiting Sleep Mode, Typical Timing Diagram Context Save and Restore in Sleep or Shutdown Mode In Sleep mode or Shutdown mode, the contents of the SRAM, state of the I/Os, and state of the registers are lost when the device is powered off, if no other measure is taken. A low-cost external serial EEPROM can be used to save and restore the contents of the device when entering and exiting Sleep mode or Shutdown mode. In the Embedded SRAM Initialization Using External Serial EEPROM application note, detailed information and a reference design are provided for initializing the embedded SRAM using an external serial EEPROM. The user can easily customize the reference design to save and restore the FPGA state when entering and exiting Sleep mode or Shutdown mode. The microcontroller will need to manage this activity; hence, before powering down VCC , the data will be read from the FPGA and stored externally. In a similar way, after the FPGA is powered up, the microcontroller will allow the FPGA to load the data from external memory and restore its original state. Flash*Freeze Design Guide This section describes how designers can create reliable designs that use ultra-low-power Flash*Freeze modes optimally. The section below provides guidance on how to select the best Flash*Freeze mode for any application. The "Design Solutions" section on page 2-14 gives specific recommendations on how to design and configure clocks, set/reset signals, and I/Os. This section also gives an overview of the design flow and provides details concerning Actel's Flash*Freeze Management IP, which enables clean clock gating and housekeeping. The "Additional Power Conservation Techniques" section on page 2-20 describes board-level considerations for entering and exiting Flash*Freeze mode. Selecting the Right Flash*Freeze Mode Both Flash*Freeze modes will bring an FPGA into an ultra-low-power static mode that retains register and SRAM content and sets I/Os to a predetermined configuration. There are two primary differences that distinguish type 2 mode from type 1, and they must be considered when creating a design using Flash*Freeze technology. First, with type 2 mode, the device has an opportunity to wait for a second signal to enable activation of Flash*Freeze mode. This allows processes to complete prior to deactivating the device, and can be useful to control task completion, data preservation, accidental Flash*Freeze activation, system shutdown, or any other housekeeping function. The second signal may be derived from an external or in-to-out internal source. The second difference between type 1 and type 2 modes is that a design for type 2 mode has an opportunity to cleanly manage clocks and data activity before entering and exiting Flash*Freeze mode. This is particularly important when data preservation is needed, as it ensures valid data is stored prior to entering, and upon exiting, Flash*Freeze mode. Type 1 Flash*Freeze mode is ideally suited for applications with the following design criteria: v2.3 2 - 13 Actel's Flash*Freeze Technology and Low-Power Modes * Entering Flash*Freeze mode is not dependent on any signal other than the external FF pin. * Internal housekeeping is not required prior to entering Flash*Freeze. * The device is reset upon exiting Flash*Freeze mode or internal state saving is not required. * State saving is required, but data and clock management is performed external to the FPGA. In other words, incoming data is externally guaranteed and held valid prior to entering Flash*Freeze mode. Type 2 Flash*Freeze mode is ideally suited for applications with the following design criteria: * Entering Flash*Freeze mode is dependent on an internal or external signal in addition to the external FF pin. * State saving is required and incoming data is not externally guaranteed valid. * The designer wants to use his/her own Flash*Freeze management IP for clock and data management. * The designer wants to use his/her own Flash*Freeze management logic for clock and data management. * Internal housekeeping is required prior to entering Flash*Freeze mode. Housekeeping activities may include loading data to SRAM, system shutdown, completion of current task, or ensuring valid Flash*Freeze pin assertion. There is no downside to type 2 mode, and Actel's Flash*Freeze management IP offers a very low tile count clock and data management solution. Actel's recommendation for most designs is to use type 2 Flash*Freeze mode with Flash*Freeze management IP. Design Solutions Clocks 2 -1 4 * Actel recommends using a completely synchronous design in Type 2 mode with Flash*Freeze management IP cleanly gating all internal and external clocks. This will prevent narrow pulses upon entrance and exit from Flash*Freeze mode (Figure 2-5 on page 2-9). * Upon entering Flash*Freeze mode, external clocks become tied off High, internal to the clock pin (unless hold state is used on IGLOO nano or IGLOO PLUS), and PLLs are turned off. Any clock that is externally Low will realize a Low to High transition internal to the device while entering Flash*Freeze. If clocks will float during Flash*Freeze mode, Actel recommends using the weak pull-up feature. If clocks will continue to drive the device during Flash*Freeze mode, the clock gating (filter) available in Flash*Freeze management IP can help to filter unwanted narrow clock pulses upon Flash*Freeze mode entry and exit. * Clocks may continue to drive FPGA pins while the device is in Flash*Freeze mode, with virtually no power consumption. The weak pull-up/-down configuration will result in unnecessary power consumption if used in this scenario. * Floating clocks can cause totem pole currents on the input I/O circuitry when the device is in active mode. If clocks are externally gated prior to entering Flash*Freeze mode, Actel recommends gating them to a known value (preferably '1', to avoid a possible narrow pulse upon Flash*Freeze mode exit), and not leaving them floating. However, during Flash*Freeze mode, all inputs and clocks are internally tied off to prevent totem pole currents, so they can be left floating. * Upon exiting Flash*Freeze mode, the design must allow maximum acquisition time for the PLL to acquire the lock signal, and for a PLL clock to become active. If a PLL output clock is used as the primary clock for Flash*Freeze management IP, it is important to note that the clock gating circuit will only release other clocks after the primary PLL output clock becomes available. v2.3 Actel's Flash*Freeze Technology and Low-Power Modes Set/Reset Since all I/Os and globals are tied High in Flash*Freeze mode (unless hold state is used on IGLOO nano or IGLOO PLUS), Actel recommends using active low set/reset at the top-level port. If needed, the signal can be inverted internally. * If the intention is to always set/reset in Flash*Freeze mode, a self set/reset circuit may be implemented to accomplish this, as shown in Figure 2-9. Configure an active High set/reset input pin so it uses the internal pull-up during Flash*Freeze mode, and drives Low during active mode. When the device exits Flash*Freeze mode, the input will transition from High to Low, releasing the set/reset. Note that this circuit may release set/reset before all outputs become active, since outputs are enabled up to 200 ns after inputs when exiting Flash*Freeze mode. Input Pull-Up '0' Set/Reset Figure 2-9 * Flash*Freeze Self-Reset Circuit I/Os * Floating inputs can cause totem pole currents on the input I/O circuitry when the device is in active mode. If inputs will be released (undriven) during Flash*Freeze mode, Actel recommends that they are only released after the device enters Flash*Freeze mode. * As mentioned earlier, asynchronous input to output paths are subject to possible glitching when entering Flash*Freeze mode. For example, on a direct in-to-out path, if the current state is '0' and the input bank deactivates first, the input and then the output will transition to '1' before the output enters its Flash*Freeze state. This can be prevented by using latches along with Flash*Freeze management IP to gate asynchronous in-to-out paths prior to entering Flash*Freeze mode. JTAG * The JTAG state machine is powered but not active during Flash*Freeze mode. * TCK should be held in a static state to prevent dynamic power consumption of the JTAG circuit during Flash*Freeze. * Specific JTAG pin tie-off recommendations suitable for Flash*Freeze mode can be found in the Pin Descriptions chapter of the handbook. ULSICC * The User Low Static ICC (ULSICC) macro acts as an access point to the hard Flash*Freeze technology block in the device. The ULSICC macro represents a hard, fixed location block in the device. When the LSICC input of the ULSICC macro is driven Low, the Flash*Freeze pin is blocked, and when LSICC is driven High, the Flash*Freeze pin is enabled. * If the user decides to build his/her own Flash*Freeze type 2 clock and data management logic, note that the LSICC signal on the ULSICC macro is ANDed internally with the Flash*Freeze signal. In order to reliably enter Flash*Freeze, the LSICC signal must remain asserted High while entering and during Flash*Freeze mode. Flash*Freeze Management IP One of the key benefits of Actel's Flash*Freeze mode is the ability to preserve the state of all internal registers, SRAM content, and I/Os (IGLOO nano and IGLOO PLUS only). This feature enables seamless continuation of data processing before and after Flash*Freeze, without the need to reload or reinitialize the FPGA system. Actel's Flash*Freeze management IP, available for type 2 implementation, offers a robust RTL block that ensures clean clock gating of all system clocks before entering and upon exiting Flash*Freeze mode. This IP also gives users the option to perform v2.3 2 - 15 Actel's Flash*Freeze Technology and Low-Power Modes housekeeping prior to entering Flash*Freeze mode. This section will provide an overview of the Flash*Freeze management IP. Additional information on this IP core can be found in the Libero IDE online help. The Flash*Freeze management IP is comprised of three blocks: the Flash*Freeze finite state machine (FSM), the clock gating (filter) block, and the ULSICC macro, as shown in Figure 2-10. Actel IGLOO, IGLOO PLUS, IGLOO nano, ProASIC3L, or RT ProASIC3 Device Flash*Freeze Management IP Clock Gating (filter) CLKINT From Array To Array INBUF CLKINT Flash *Freeze Pin Connect to Top-Level Port Flash*Freeze FSM Housekeeping (optional) INBUF _FF ULSICC Macro Flash*Freeze Technology User Design LEGEND Net Logical Connection Hardwired Connection Figure 2-10 * Flash*Freeze Management IP Block Diagram Flash*Freeze Management FSM The Flash*Freeze FSM block is a simple, robust, fully encoded 3-bit state machine that ensures clean entrance to and exit from Flash*Freeze mode by controlling activities of the clock gating, ULSICC, and optional housekeeping blocks. The state diagram for the FSM is shown in Figure 2-12 on page 2-18, below. In normal operation, the state machine waits for Flash*Freeze pin assertion, and upon detection of a request, it waits for a short period of time to ensure the assertion persists; then it asserts WAIT_HOUSEKEEPING (active High) synchronous to the user's designated system clock. This flag can be used by user logic to perform any needed shutdown processes prior to entering Flash*Freeze mode, such as storing data into SRAM, notifying other system components of the request, or timing/validating the Flash*Freeze request. The FSM also asserts Flash_Freeze_Enabled whenever the device enters Flash*Freeze mode. This occurs after all housekeeping and clock gating functions have completed. The Flash_Freeze_Enabled signal remains asserted, even during Flash*Freeze mode, until the Flash*Freeze pin is deasserted. Use the Flash_Freeze_Enabled signal to drive any logic in the design that needs to be in a particular state during Flash*Freeze mode. The DONE_HOUSEKEEPING (active High) signal should be asserted to notify the FSM when all the housekeeping tasks are completed. If the user chooses not to use housekeeping, the Flash*Freeze management IP core generator in Libero IDE will connect WAIT_HOUSEKEEPING to DONE_HOUSEKEEPING. 2 -1 6 v2.3 Actel's Flash*Freeze Technology and Low-Power Modes Clock Gating Block Once DONE_HOUSEKEEPING is detected, the FSM will initiate the clock gating circuit by asserting ASSERT_GATE (active Low). ASSERT_GATE is named control_user_clock_net in the IP block. Upon assertion of the ASSERT_GATE signal, the clock will be gated in less than two cycles. The clock gating circuit is comprised of a flip-flop, latch, AND gate, and CLKINT, as shown in Figure 2-11. The clock gating block can support gating of up to 17 clocks. F*F FSM ASSERT_GATE Q D Q D Flip-Flop Latch CLK G AND System Clock CLKINT Figure 2-11 * Clock Gating Circuit After initiating the clock gating circuit, the FSM will assert and hold the LSICC signal (active High), feeding the ULSICC macro. This will initiate the 1 s entrance into Flash*Freeze mode. Upon deassertion of the Flash*Freeze pin, the FSM will set ASSERT_GATE High. Once the I/O banks become active, the clock will enter the device and register the ASSERT_GATE signal, cleanly releasing the clock gate. Design Flow1 Actel has developed a convenient and intuitive design flow for configuring and integrating Flash*Freeze technology into an FPGA design. Flash*Freeze type 1 is implemented by instantiating the INBUF_FF macro in the top level of a design. Flash*Freeze type 2 with management IP can be generated by the Libero IDE core generator or SmartGen and instantiated as a single block in the user's design. This single block will include an INBUF_FF macro and the optional Flash*Freeze management IP, which includes the ULSICC macro. If designers do not wish to use this core generator, the INBUF_FF macro and the optional ULSICC macro may be instantiated in the design, and custom Flash*Freeze management IP can be developed by the user. The remainder of this section will cover configuration details of the INBUF_FF macro, the ULSICC macro, and the Flash*Freeze management IP. Additional information on the tools discussed within this section may be found in the Libero IDE online help. INBUF_FF The INBUF_FF macro is a special-purpose input buffer macro that is interpreted downstream in the design flow by Actel's Designer software. When this macro is used, the top-level port will be forced to the dedicated FF pin in the FPGA, and Flash*Freeze mode will be available for use in the device. The following are the design rules for INBUF_FF: 1. * If INBUF_FF is not used in the design, the device will not be configured to support Flash*Freeze mode. * When the INBUF_FF macro is used, the FF pin will establish a hardwired connection to the Flash*Freeze technology circuit in the device, as shown in Figure 2-1 on page 2-5, Figure 2-3 This section applies to Libero IDE / Designer v8.3 and later. Actel recommends that designs created in earlier versions of the software be modified to accommodate this flow by instantiating the INBUF_FF macro or the Flash*Freeze management IP. Refer to the Libero IDE / Designer v8.3 release notes and the Libero IDE online help for more information on migrating designs from older software versions. v2.3 2 - 17 Actel's Flash*Freeze Technology and Low-Power Modes System Reset Deassert ULSICC Flash*Freeze Asserted Wait on Flash*Freeze Flash*Freeze Deasserted Flash*Freeze Deasserted Persistent Flash*Freeze House-Keeping Request to User Logic Safe to Turn Off Clock From User Logic House Keeping Request to User Logic Fail Safe Dummy State 1 Flash*Freeze Deasserted Flash*Freeze Flash*Freeze Asserted Deasserted Stop Clock to User Clock Gating Circuit Turn On User Clock Flash*Freeze Deasserted Trigger ULSICC Gate User Clocks User Clock Fail Safe Dummy State 2 Flash*Freeze Deasserted Flash*Freeze Deasserted Flash*Freeze Asserted Un-Gate User Clocks Trigger ULSICC Gated Clock to User Design ULSICC Figure 2-12 * FSM State Diagram on page 2-6, and Figure 2-10 on page 2-16, and described in the "Flash*Freeze Type 1: Control by Dedicated Flash*Freeze Pin" section on page 2-4. * 2 -1 8 The INBUF_FF must be driven by a top-level input port of the design. * The INBUF_FF AND the ULSICC macro must be used to enable type 2 Flash*Freeze mode. * For type 2 Flash*Freeze mode, the INBUF_FF MUST drive some logic in the design. * For type 1 Flash*Freeze mode, the INBUF_FF may drive some logic in the design, but it may also be left floating. * Only one INBUF_FF may be instantiated in a device. * The FF pin threshold voltages are defined by VCCI and the supported single-ended I/O standard in the corresponding I/O bank. * The FF pin Schmitt trigger option may be configured in the I/O attribute editor in Actel's Designer software. The Schmitt trigger option is only available for IGLOOe, IGLOO nano, IGLOO PLUS, ProASIC3EL, and RT ProASIC3 devices. * A 2 ns glitch filter resides in the Flash*Freeze Technology block to filter unwanted glitches on the FF pin. v2.3 Actel's Flash*Freeze Technology and Low-Power Modes ULSICC The User Low Static ICC (ULSICC) macro allows the FPGA core to access the Flash*Freeze Technology block so that entering and exiting Flash*Freeze mode can be controlled by the user's design. The ULSICC macro enables a hard block with an available LSICC input port, as shown in Figure 2-3 on page 2-6 and Figure 2-10 on page 2-16. Design rules for the ULSICC macro are as follows: * The ULSICC macro by itself cannot enable Flash*Freeze mode. The INBUF_FF AND the ULSICC macro must both be used to enable type 2 Flash*Freeze mode. * The ULSICC controls entering the Flash*Freeze mode by asserting the LSICC input (logic '1') of the ULSICC macro. The FF pin must also be asserted (logic '0') to enter Flash*Freeze mode. * When the LSICC signal is '0', the device cannot enter Flash*Freeze mode; and if already in Flash*Freeze mode, it will exit. * When the ULSICC macro is not instantiated in the user's design, the LSICC port will be tied High. Flash*Freeze Management IP The Flash*Freeze management IP can be configured with the Libero IDE (or SmartGen) core generator in a simple, intuitive interface. With the core configuration tool, users can select the number of clocks to be gated, and select whether or not to implement housekeeping. All port names on the Flash*Freeze management IP block can be renamed by the user. * The clock gating (filter) blocks include CLKINT buffers for each gated clock output (version 8.3). * When housekeeping is NOT used, the WAIT_HOUSEKEEPING signal will be automatically fed back into DONE_HOUSEKEEPING inside the core, and the ports will not be available at the IP core interface. * The INBUF_FF macro is automatically instantiated within the IP core. * The INBUF_FF port (default name is "Flash_Freeze_N") must be connected to a top-level input port of the design. * The ULSICC macro is automatically instantiated within the IP core, and the LSICC signal is driven by the FSM. * Timing analysis can be performed on the clock domain of the source clock (i.e., input to the clock gating filters). For example, if CLKin becomes CLKin_gated, the timing can be performed on the CLKin domain in SmartTime. * The gated clocks can be added to the clock list if the user wishes to analyze these clocks specifically. The user can locate the gated clocks by looking for instance names such as those below: Top/ff1/ff_1_wrapper_inst/user_ff_1_wrapper/Primary_Filter_Instance/ Latch_For_Clock_Gating:Q Top/ff1/ff_1_wrapper_inst/user_ff_1_wrapper/genblk1.genblk2.secondary_filter[0]. seconday_filter_instance/Latch_For_Clock_Gating:Q Top/ff1/ff_1_wrapper_inst/user_ff_1_wrapper/genblk1.genblk2.secondary_filter[1]. seconday_filter_instance/Latch_For_Clock_Gating:Q * There will be added skew and clock insertion delay due to the clock gating circuit. The user should analyze external setup/hold times carefully. The user should also ensure the additional skew across the clock gating filter circuit is accounted for in any paths where the launch register is driven from the filter input clock and captured by a register driven by the gated clock filter output clock. v2.3 2 - 19 Actel's Flash*Freeze Technology and Low-Power Modes Power Analysis SmartPower identifies static and dynamic power consumption problems quickly within a design. It provides a hierarchical view, allowing users to drill down and estimate the power consumption of individual components or events. SmartPower analyzes power consumption for nets, gates, I/Os, memories, clocks, cores, clock domains, power supply rails, peak power during a clock cycle, and switching transitions. SmartPower generates detailed hierarchical reports of the dynamic power consumption of a design for easy inspection. These reports include design-level power summary, average switching activity, and ambient and junction temperature readings. Enter the target clock and data frequencies for a design, and let SmartPower perform a detailed and accurate power analysis. SmartPower supports importing files in the VCD (Value-Change Dump) format as specified in the IEEE 1364 standard. It also supports the Synopsys(R) Switching Activity Interchange Format (SAIF) standard. Support for these formats lets designers generate switching activity information in a variety of simulators and then import this information directly into SmartPower. For portable or battery-operated applications, a power profile feature enables you to measure power and battery life, based on a sequence of operational modes of the design. In most portable and battery-operated applications, the system is seldom fully "on" 100 percent of the time. "On" is a combination of fully active, standby, sleep, or other functional modes. SmartPower allows users to create a power profile for a design by specifying operational modes and the percent of time the device will run in each of the modes. Power is calculated for each of the modes, and total power is calculated based on the weighted average of all modes. SmartPower also provides an estimated battery life based on the power profile. The current capacity for a given battery is entered and used to estimate the life of the battery. The result is an accurate and realistic indication of battery life. More information on SmartPower can be found on the Actel website: http://www.actel.com/products/software/libero/smartpower.aspx. Additional Power Conservation Techniques IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 FPGAs provide many ways to inherently conserve power; however, there are also several design techniques that can be used to reduce power on the board. * * * * * * * * * * * 2 -2 0 Actel recommends that the designer use the minimum number of I/O banks possible and tie any unused power supplies (such as VCCPLL, VCCI, VMV, and VPUMP) to ground. Leave unused I/O ports floating. Unused I/Os are configured by the software as follows: - Output buffer is disabled (with tristate value of high impedance) - Input buffer is disabled (with tristate value of high impedance) Use the lowest available voltage I/O standard, the lowest drive strength, and the slowest slew rate to reduce I/O switching contribution to power consumption. Advanced and pro I/O banks may consume slightly higher static current than standard and standard plus banks--avoid using advanced and pro banks whenever practical. - The small static power benefit obtained by avoiding advanced or pro I/O banks is usually negligible compared to the benefit of using a low-power I/O standard. Deselect RAM blocks that are not being used. Only enable read and write ports on RAM blocks when they are needed. Gating clocks LOW offers improved static power of RAM blocks. Drive the FF port of RAM blocks with the Flash_Freeze_Enabled signal from the Flash*Freeze management IP. Drive inputs to the full voltage level so that all transistors are turned on or off completely. Avoid using pull-ups and pull-downs on I/Os because these resistors draw some current. Avoid driving resistive loads or bipolar transistors, since these draw a continuous current, thereby adding to the static current. When partitioning the design across multiple devices, minimize I/O usage among the devices. v2.3 Actel's Flash*Freeze Technology and Low-Power Modes Conclusion Actel IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 family architectures are designed to achieve ultra-low power consumption based on enhanced nonvolatile and live-atpower-up flash-based technology. Power consumption can be reduced further by using Flash*Freeze, Static (Idle), Sleep, and Shutdown power modes. All these features result in a lowpower, cost-effective, single-chip solution designed specifically for power-sensitive and batteryoperated electronics applications. Related Documents Application Notes Embedded SRAM Initialization Using External Serial EEPROM http://www.actel.com/documents/EmbeddedSRAMInit_AN.pdf Handbook Documents Power-Up/-Down Behavior of Low-Power Flash Devices http://www.actel.com/documents/LPD_PowerUp_HBs.pdf Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions_HBs.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-004-7 Revised November 2009 v2.3 2 - 21 Actel's Flash*Freeze Technology and Low-Power Modes List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v2.3) Page v2.2 (December 2008) The "Sleep Mode" section was revised to state the VJTAG and VPUMP, as well as VCC, are grounded during Sleep mode. 2-11 Figure 2-6 * Controlling Power-On/-Off State Using Microprocessor and Power FET and Figure 2-7 * Controlling Power-On/-Off State Using Microprocessor and Voltage Regulator were revised to show that VJTAG and VPUMP are powered off during Sleep mode. 2-12 IGLOO nano devices were added as a supported family. N/A The "Prototyping for IGLOO and ProASIC3L Devices Using ProASIC3" section was removed, as these devices are now in production. N/A The "Additional Power Conservation Techniques" section was revised to add RT ProASIC3 devices. 2-20 The "Flash*Freeze Management FSM" section was updated with the following information: The FSM also asserts Flash_Freeze_Enabled whenever the device enters Flash*Freeze mode. This occurs after all housekeeping and clock gating functions have completed. 2-16 The title changed from "Flash*Freeze Technology and Low-Power Modes in IGLOO, IGLOO PLUS, and ProASIC3L Devices" to Actel's Flash*Freeze Technology and Low-Power Modes." N/A The "Actel's Flash Families Support the Flash*Freeze Feature" section was updated. 2-2 v2.1 (October 2008) v2.0 (October 2008) v1.3 (June 2008) Significant changes were made to this document to support Libero IDE v8.4 and later functionality. RT ProASIC3 device support information is new. In addition to the other major changes, the following tables and figures were updated or are new: Figure 2-3 * Flash*Freeze Mode Type 2 - Controlled by Flash*Freeze Pin and Internal Logic (LSICC signal) - updated 2-6 Figure 2-5 * Narrow Clock Pulses During Flash*Freeze Entrance and Exit - new 2-9 Figure 2-10 * Flash*Freeze Management IP Block Diagram - new 2-16 Figure 2-12 * FSM State Diagram - new 2-18 Table 2-6 * IGLOO nano and IGLOO PLUS Flash*Freeze Mode (type 1 and type 2)--I/O Pad State - updated 2-8 Please review the entire document carefully. v1.2 (March 2008) The family description for ProASIC3L in Table 2-1 * Flash-Based FPGAs was updated to include 1.5 V. 2-2 v1.1 (February 2008) The part number for this document was changed from 51700094-003-1 to 51700094-004-2. N/A The title of the document was changed to "Flash*Freeze Technology and LowPower Modes in IGLOO, IGLOO PLUS, and ProASIC3L Devices." N/A The "Flash*Freeze Technology and Low-Power Modes" section was updated to remove the parenthetical phrase, "from 25 W," in the second paragraph. The following sentence was added to the third paragraph: "IGLOO PLUS has an additional feature when operating in Flash*Freeze mode, allowing it to retain I/O states as well as SRAM and register states." 2-1 2 -2 2 v2.3 Actel's Flash*Freeze Technology and Low-Power Modes Previous Version v1.1 (continued) Changes in Current Version (v2.3) Page The "Power Conservation Techniques" section was updated to add VJTAG to the parenthetical list of power supplies that should be tied to the ground plane if unused. Additional information was added regarding how the software configures unused I/Os. 2-1 Table 2-1 * Flash-Based FPGAs and the accompanying text was updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 2-2 The "Flash*Freeze Mode" section was revised to include that I/O states are preserved in Flash*Freeze mode for IGLOO PLUS devices. The last sentence in the second paragraph was changed to, "If the FF pin is not used, it can be used as a regular I/O." The following sentence was added for Flash*Freeze mode type 2: "Exiting the mode is controlled by either the FF pin OR the userdefined LSICC signal." 2-4 The "Flash*Freeze Type 1: Control by Dedicated Flash*Freeze Pin" section was revised to change instructions for implementing this mode, including instructions for implementation with Libero IDE v8.3. 2-4 Figure 2-1 * Flash*Freeze Mode Type 1 - Controlled by the Flash*Freeze Pin was updated. 2-5 The "Flash*Freeze Type 2: Control by Dedicated Flash*Freeze Pin and Internal Logic" section was renamed from "Type 2 Software Implementation." 2-6 The "Type 2 Software Implementation for Libero IDE v8.3" section is new. 2-6 Figure 2-3 * Flash*Freeze Mode Type 2 - Controlled by Flash*Freeze Pin and Internal Logic (LSICC signal) was updated. 2-6 Figure 2-4 * Flash*Freeze Mode Type 2 - Timing Diagram was revised to show deasserting LSICC after the device has exited Flash*Freeze mode. 2-7 The "IGLOO nano and IGLOO PLUS I/O State in Flash*Freeze Mode" section was added to include information for IGLOO PLUS devices. Table 2-6 * IGLOO nano and IGLOO PLUS Flash*Freeze Mode (type 1 and type 2)--I/O Pad State is new. 2-7, 2-8 The "During Flash*Freeze Mode" section was revised to include a new bullet pertaining to output behavior for IGLOO PLUS. The bullet on JTAG operation was revised to provide more detail. 2-10 Figure 2-6 * Controlling Power-On/-Off State Using Microprocessor and Power FET and Figure 2-7 * Controlling Power-On/-Off State Using Microprocessor and Voltage Regulator were updated to include IGLOO PLUS. 2-12, 2-12 The first sentence of the "Shutdown Mode" section was updated to list the devices for which it is supported. 2-11 The first paragraph of the "Power-Up/-Down Behavior" section was revised. The second sentence was changed to, "The I/Os remain tristated until the last voltage supply (VCC or VCCI ) is powered to its activation level." The word "activation" replaced the word "functional." The sentence, "During powerdown, device I/Os become tristated once the first power supply (VCC or VCCI) drops below its deactivation voltage level" was revised. The word "deactivation" replaced the word "brownout." 2-12 The "Prototyping for IGLOO and ProASIC3L Devices Using ProASIC3" section was revised to state that prototyping in ProASIC3 does not apply for the IGLOO PLUS family. 2-21 v2.3 2 - 23 Actel's Flash*Freeze Technology and Low-Power Modes Previous Version Changes in Current Version (v2.3) Page Table 2-8 * Prototyping/Migration Solutions, Table 2-9 * Device Migration-- IGLOO Supported Packages in ProASIC3 Devices, and Table 2-10 * Device Migration--ProASIC3L Supported Packages in ProASIC3 Devices were updated with a table note stating that device migration is not supported for IGLOO PLUS devices. 2-21, 2-23 The text following Table 2-10 * Device Migration--ProASIC3L Supported Packages in ProASIC3 Devices was moved to a new section: the "Flash*Freeze Design Guide" section. 2-13 v1.0 (January 2008) Table 2-1 * Flash-Based FPGAs was updated to remove the ProASIC3, ProASIC3E, and Automotive ProASIC3 families, which were incorrectly included. 2-2 51900147-2/5.07 Detailed descriptions of low-power modes are described in the advanced datasheets. This application note was updated to describe how to use the features in an IGLOO/e application. N/A Figure 2-1 * Flash*Freeze Mode Type 1 - Controlled by the Flash*Freeze Pin was updated. 2-5 Figure 2-2 * Flash*Freeze Mode Type 1 - Timing Diagram is new. 2-5 Steps 4 and 5 are new in the "Flash*Freeze Type 2: Control by Dedicated Flash*Freeze Pin and Internal Logic" section. 2-6 In the following sentence, located in the "Flash*Freeze Mode" section, the bold text was changed from active high to active Low. 2-4 v1.1 (continued) 51900147-1/3.07 The Flash*Freeze pin (active low) is a dedicated pin used to enter or exit Flash*Freeze mode directly, or alternatively the pin can be routed internally to the FPGA core to allow the user's logic to decide if it is safe to transition to this mode. 51900147-0/8.06 2 -2 4 Figure 2-2 * Flash*Freeze Mode Type 1 - Timing Diagram was updated. 2-5 Information about ULSICC was added to the "Prototyping for IGLOO and ProASIC3L Devices Using ProASIC3" section. 2-21 In the "Flash*Freeze Mode" section, "active high" was changed to "active low." 2-4 The "Prototyping for IGLOO and ProASIC3L Devices Using ProASIC3" section was updated with information concerning the Flash*Freeze pin. 2-21 v2.3 Global Resources and Clock Conditioning 3 - Global Resources in Actel Low-Power Flash Devices Introduction Actel IGLOO,(R) Fusion, and ProASIC(R)3 FPGA devices offer a powerful, low-delay VersaNet global network scheme and have extensive support for multiple clock domains. In addition to the Clock Conditioning Circuits (CCCs) and phase-locked loops (PLLs), there is a comprehensive global clock distribution network called a VersaNet global network. Each logical element (VersaTile) input and output port has access to these global networks. The VersaNet global networks can be used to distribute low-skew clock signals or high-fanout nets. In addition, these highly segmented VersaNet global networks offer users the flexibility to create low-skew local networks using spines. This document describes VersaNet global networks and discusses how to assign signals to these global networks and spines in a design flow. Details concerning low-power flash device PLLs are described in Clock Conditioning Circuits in IGLOO and ProASIC3 Devices. This document describes the low-power flash devices' global architecture and uses of these global networks in designs. Global Architecture Low-power flash devices offer powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has up to six CCCs, some with PLLs. * In IGLOOe, ProASIC3EL, and ProASIC3E devices, all CCCs have PLLs--hence, 6 PLLs per device. * In IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3, and ProASIC3L devices, the west CCC contains a PLL core (except in 10 k through 30 k devices). * In Fusion devices, the west CCC also contains a PLL core. In the two larger devices (AFS600 and AFS1500), the west and east CCCs each contain a PLL. Each PLL includes delay lines, a phase shifter (0, 90, 180, 270), and clock multipliers/dividers. Each CCC has all the circuitry needed for the selection and interconnection of inputs to the VersaNet global network. The east and west CCCs each have access to three VersaNet global lines on each side of the chip (six global lines total). The CCCs at the four corners each have access to three quadrant global lines in each quadrant of the chip (except in 10 k through 30 k gate devices). The nano 10 k, 15 k, and 20 k devices support four VersaNet global resources, and 30 k devices support six global resources. The 10 k through 30 k devices have simplified CCCs called CCC-GLs. The flexible use of the VersaNet global network allows the designer to address several design requirements. User applications that are clock-resource-intensive can easily route external or gated internal clocks using VersaNet global routing networks. Designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the VersaNet global network. The following sections give an overview of the VersaNet global network, the structure of the global network, and the clock aggregation feature that enables a design to have very low clock skew using spines. v1.4 3-1 Global Resources in Actel Low-Power Flash Devices Global Resource Support in Flash-Based Devices The flash FPGAs listed in Table 3-1 support the global resources and the functions described in this document. Table 3-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities IGLOO nano The industry's lowest-power, smallest-size solution ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO products as listed in Table 3-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 3-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 3 -2 v1.4 Global Resources in Actel Low-Power Flash Devices VersaNet Global Network Distribution One of the architectural benefits of low-power flash architecture is the set of powerful, low-delay VersaNet global networks that can access the VersaTiles, SRAM, and I/O tiles of the device. Each device offers a chip global network with six global lines (except for nano 10 k, 15 k, and 20 k gate devices) that are distributed from the center of the FPGA array. In addition, each device (except the 10 k through 30 k gate device) has four quadrant global networks, each with three regional global line resources. These quadrant global networks can only drive a signal inside their own quadrant. Each core VersaTile has access to nine global line resources--three quadrant and six chip-wide (main) global networks--and a total of 18 globals are available on the device (3 x 4 regional from each quadrant and 6 global). Figure 3-1 shows an overview of the VersaNet global network and device architecture for devices 60 k and above. Figure 3-2 and Figure 3-3 on page 3-4 show simplified VersaNet global networks. The VersaNet global networks are segmented and consist of VersaNet global networks, spines, global ribs, and global multiplexers (MUXes), as shown in Figure 3-1. The global networks are driven from the global rib at the center of the die or quadrant global networks at the north or south side of the die. The global network uses the MUX trees to access the spine, and the spine uses the clock ribs to access the VersaTile. Access is available to the chip or quadrant global networks and the spines through the global MUXes. Access to the spine using the global MUXes is explained in the "Spine Architecture" section on page 3-5. These VersaNet global networks offer fast, low-skew routing resources for high-fanout nets, including clock signals. In addition, these highly segmented global networks offer users the flexibility to create low-skew local networks using spines for up to 252 internal/external clocks or other high-fanout nets in low-power flash devices. Optimal usage of these low-skew networks can result in significant improvement in design performance. Quadrant Global Pads T1 T2 High-Performance Global Network T3 I/ORing Pad Ring Pad Ring Top Spine Global Pads Chip (main) Global Pads Global Spine Global Ribs I/O Ring Bottom Spine Scope of Spine (shaded area plus local RAMs and I/Os) Spine-Selection MUX Embedded RAM Blocks Pad Ring B1 B2 B3 Logic Tiles Note: Not applicable to 10 k through 30 k gate devices Figure 3-1 * Overview of VersaNet Global Network and Device Architecture v1.4 3-3 Global Resources in Actel Low-Power Flash Devices 2 2 2 2 Chip (main) Global Network 2 2 Global Drivers Global Drivers Figure 3-2 * Simplified VersaNet Global Network (30 k gates and below) North Quadrant Global Network Quadrant Global Spine CCC CCC 3 3 3 3 Chip (main) Global 6 Network 6 3 6 6 3 CCC Global Spine 3 CCC 6 6 3 6 3 6 3 South Quadrant Global Network Figure 3-3 * Simplified VersaNet Global Network (60 k gates and above) 3 -4 v1.4 CCC CCC Global Resources in Actel Low-Power Flash Devices Spine Architecture The low-power flash device architecture allows the VersaNet global networks to be segmented. Each of these networks contains spines (the vertical branches of the global network tree) and ribs that can reach all the VersaTiles inside its region. The nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, which has three spines, and the chip (main) global network, which has six spines. Note that the number of quadrant globals and globals/spines per tree varies depending on the specific device. Refer to Table 3-2 on page 3-6 for the clocking resources available for each device. The spines are the vertical branches of the global network tree, shown in Figure 3-3. Each spine in a vertical column of a chip (main) global network is further divided into two spine segments of equal lengths: one in the top and one in the bottom half of the die (except in 10 k through 30 k gate devices). Top and bottom spine segments radiating from the center of a device have the same height. However, just as in the ProASICPLUS(R) family, signals assigned only to the top and bottom spine cannot access the middle two rows of the die. The spines for quadrant clock networks do not cross the middle of the die and cannot access the middle two rows of the architecture. Each spine and its associated ribs cover a certain area of the device (the "scope" of the spine; see Figure 3-3). Each spine is accessed by the dedicated global network MUX tree architecture, which defines how a particular spine is driven--either by the signal on the global network from a CCC, for example, or by another net defined by the user. Details of the chip (main) global network spineselection MUX are presented in Figure 3-5 on page 3-8. The spine drivers for each spine are located in the middle of the die. Quadrant spines can be driven from user I/Os on the north and south sides of the die. The ability to drive spines in the quadrant global networks can have a significant effect on system performance for high-fanout inputs to a design. Access to the top quadrant spine regions is from the top of the die, and access to the bottom quadrant spine regions is from the bottom of the die. The A3PE3000 device has 28 clock trees and each tree has nine spines; this flexible global network architecture enables users to map up to 252 different internal/external clocks in an A3PE3000 device. v1.4 3-5 Global Resources in Actel Low-Power Flash Devices Table 3-2 * Globals/Spines/Rows for IGLOO and ProASIC3 Devices Quadrant Chip Globals Clock Globals (4x3) Trees Globals/ Total Rows Spines Spines VersaTiles in per per in Each Total Each Tree Device Tree VersaTiles Spine ProASIC3/ ProASIC3L Devices IGLOO Devices A3PN010 AGLN010 4 0 1 0 0 260 260 4 A3PN015 AGLN015 4 0 1 0 0 384 384 6 A3PN020 AGLN020 4 0 1 0 0 520 520 6 A3PN060 AGLN060 6 12 4 9 36 384 1,536 12 A3PN125 AGLN125 6 12 8 9 72 384 3,072 12 A3PN250 AGLN250 6 12 8 9 72 768 6,144 24 A3P015 AGL015 6 0 1 9 9 384 384 12 A3P030 AGL030 6 0 2 9 18 384 768 12 A3P060 AGL060 6 12 4 9 36 384 1,536 12 A3P125 AGL125 6 12 8 9 72 384 3,072 12 A3P250/L AGL250 6 12 8 9 72 768 6,144 24 A3P400 AGL400 6 12 12 9 108 768 9,216 24 A3P600/L AGL600 6 12 12 9 108 1,152 13,824 36 A3P1000/L AGL1000 6 12 16 9 144 1,536 24,576 48 A3PE600/L AGLE600 6 12 12 9 108 1,120 13,440 35 6 12 20 9 180 1,888 37,760 59 A3PE3000/L AGLE3000 6 12 28 9 252 2,656 74,368 83 Table 3-3 * Globals/Spines/Rows for IGLOO PLUS Devices A3PE1500 IGLOO PLUS Chip Devices Globals Quadrant Globals Clock (4x3) Trees Globals/ Total Spines Spines VersaTiles per Tree per Device in Each Tree Rows Total in Each VersaTiles Spine AGLP030 6 0 2 9 18 384* 792 12 AGLP060 6 12 4 9 36 384* 1,584 12 AGLP125 6 12 8 9 72 384* 3,120 12 Note: *Clock trees that are located at far left and far right will support more VersaTiles. Table 3-4 * 3 -6 Globals/Spines/Rows for Fusion Devices Clock Trees Globals/ Spines per Tree Total Spines per Device VersaTiles in Each Tree Total VersaTiles Rows in Each Spine Fusion Device Chip Globals Quadrant Globals (4x3) AFS090 6 12 6 9 54 384 2,304 12 AFS250 6 12 8 9 72 768 6,144 24 AFS600 6 12 12 9 108 1,152 13,824 36 AFS1500 6 12 20 9 180 1,920 38,400 60 v1.4 Global Resources in Actel Low-Power Flash Devices Spine Access The physical location of each spine is identified by the letter 'T' (top) or 'B' (bottom) and an accompanying number (Tn or Bn). The number n indicates the horizontal location of the spine; 1 refers to the first spine on the left side of the die. Since there are six chip spines in each spine tree, there are up to six spines available for each combination of 'T' (or 'B') and n (for example, six T1 spines). Similarly, there are three quadrant spines available for each combination of 'T' (or 'B') and n (for example, four T1 spines), as shown in Figure 3-4. A B Global Network C Tn Tn+1 Tn+2 Tn+3 Tn+4 Figure 3-4 * Chip Global Aggregation Spines are also called local clocks, and are accessed by the dedicated global MUX architecture. These MUXes define how a particular spine is driven. Refer to Figure 3-5 on page 3-8 for the global MUX architecture. The MUXes for each chip global spine are located in the middle of the die. Access to the top and bottom chip global spine is available from the middle of the die. There is no control dependency between the top and bottom spines. If a top spine, T1, of a chip global network is assigned to a net, B1 is not wasted and can be used by the global clock network. The signal assigned only to the top or bottom spine cannot access the middle two rows of the architecture. However, if a spine is using the top and bottom at the same time (T1 and B1, for instance), the previous restriction is lifted. The MUXes for each quadrant global spine are located in the north and south sides of the die. Access to the top and bottom quadrant global spines is available from the north and south sides of the die. Since the MUXes for quadrant spines are located in the north and south sides of the die, you should not try to drive T1 and B1 quadrant spines from the same signal. v1.4 3-7 Global Resources in Actel Low-Power Flash Devices Using Clock Aggregation Clock aggregation allows for multi-spine clock domains to be assigned using hardwired connections, without adding any extra skew. A MUX tree, shown in Figure 3-5, provides the necessary flexibility to allow long lines, local resources, or I/Os to access domains of one, two, or four global spines. Signal access to the clock aggregation system is achieved through long-line resources in the central rib in the center of the die, and also through local resources in the north and south ribs, allowing I/Os to feed directly into the clock system. As Figure 3-6 indicates, this access system is contiguous. There is no break in the middle of the chip for the north and south I/O VersaNet access. This is different from the quadrant clocks located in these ribs, which only reach the middle of the rib. Internal/External Signals Internal/External Signals Tree Node MUX Tree Node MUX Internal/External Signal Tree Node MUX Global Rib Internal/External Signal Global Driver MUX Spine Figure 3-5 * Spine Selection MUX of Global Tree Global Spine Global Rib Global Driver and MUX Tree Node MUX I/O Access Internal Signal Access Global Signal Access Figure 3-6 * Clock Aggregation Tree Architecture 3 -8 v1.4 I/O Tiles Global Resources in Actel Low-Power Flash Devices Clock Aggregation Architecture This clock aggregation feature allows a balanced clock tree, which improves clock skew. The physical regions for clock aggregation are defined from left to right and shift by one spine. For chip global networks, there are three types of clock aggregation available, as shown in Figure 3-7: * Long lines that can drive up to four adjacent spines * Long lines that can drive up to two adjacent spines * Long lines that can drive one spine There are three types of clock aggregation available for the quadrant spines, as shown in Figure 3-7: * I/Os or local resources that can drive up to four adjacent spines * I/Os or local resources that can drive up to two adjacent spines * I/Os or local resources that can drive one spine * As an example, A3PE600 and AFS600 devices have twelve spine locations: T1, T2, T3, T4, T5, T6, B1, B2, B3, B4, B5, and B6. Table 3-5 shows the clock aggregation you can have in A3PE600 and AFS600. A B C Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Figure 3-7 * Four Spines Aggregation Table 3-5 * Spine Aggregation in A3PE600 or AFS600 Clock Aggregation Spine 1 spine T1, T2, T3, T4, T5, T6, B1, B2, B3, B4, B5, B6 2 spines T1:T2, T2:T3, T3:T4, T4:T5, T5:T6, B1:B2, B2:B3, B3:B4, B4:B5, B5:B6 4 spines B1:B4, B2:B5, B3:B6, T1:T4, T2:T5, T3:T6 The clock aggregation for the quadrant spines can cross over from the left to right quadrant, but not from top to bottom. The quadrant spine assignment T1:T4 is legal, but the quadrant spine assignment T1:B1 is not legal. Note that this clock aggregation is hardwired. You can always assign signals to spine T1 and B2 by instantiating a buffer, but this may add skew in the signal. v1.4 3-9 Global Resources in Actel Low-Power Flash Devices I/O Banks and Global I/Os The following sections give an overview of naming conventions and other related I/O information. Naming of Global I/Os In low-power flash devices, the global I/Os have access to certain clock conditioning circuitry and have direct access to the global network. Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities to those of regular I/Os. Due to the comprehensive and flexible nature of the I/Os in low-power flash devices, a naming scheme is used to show the details of the I/O. The global I/O uses the generic name Gmn/IOuxwByVz. Refer to the I/O Structure section of the handbook for the device that you are using for more information on this naming convention. Figure 3-8 represents the global input pins connection to the northwest CCC or northwest quadrant global networks for a low-power flash device. Each global buffer, as well as the PLL reference clock, can be driven from one of the following: * 3 dedicated single-ended I/Os using a hardwired connection * 2 dedicated differential I/Os using a hardwired connection * The FPGA core Since each bank can have a different I/O standard, the user should be careful to choose the correct global I/O for the design. There are 54 global pins available to access 18 global networks. For the single-ended and voltage-referenced I/O standards, you can use any of these three available I/Os to access the global network. For differential I/O standards such as LVDS and LVPECL, the I/O macro needs to be placed on GAA0 and GAA1 or a similar location. The unassigned global I/Os can be used as regular I/Os. Note that pin names starting with GF and GC are associated with the chip global networks, and GA, GB, GD, and GE are used for quadrant global networks. Each shaded box represents an INBUF or INBUF_LVDS/LVPECL macro, as appropriate. To Core Sample Pin Names 1 GAA0/IO0NDB0V0 1 GAA1/IO00PDB0V0 + Source for CCC (CLKA or CLKB or CLKC) 1 GAA2/IO13PDB7V1 Routed Clock 2 (from FPGA core) + GAA[0:2]: GA represents global in the northwest corner of the device. A[0:2]: designates specific A clock source. Figure 3-8 * Global I/O Overview 3 -1 0 v1.4 Global Resources in Actel Low-Power Flash Devices Unused Global I/O Configuration The unused clock inputs behave similarly to the unused Pro I/Os. The Actel Designer software automatically configures the unused global pins as inputs with pull-up resistors if they are not used as regular I/O. I/O Banks and Global I/O Standards In low-power flash devices, any I/O or internal logic can be used to drive the global network. However, only the global macro placed at the global pins will use the hardwired connection between the I/O and global network. Global signal (signal driving a global macro) assignment to I/O banks is no different from regular I/O assignment to I/O banks with the exception that you are limited to the pin placement location available. Only global signals compatible with both the VCCI and VREF standards can be assigned to the same bank. Design Recommendations The following sections provide design flow recommendations for using a global network in a design. * "Global Macros and I/O Standards" * "Using Global Macros in Synplicity" on page 3-13 * "Global Promotion and Demotion Using PDC" on page 3-14 * "Spine Assignment" on page 3-15 * "Designer Flow for Global Assignment" on page 3-16 * "Simple Design Example" on page 3-18 * "Global Management in PLL Design" on page 3-20 * "Using Spines of Occupied Global Networks" on page 3-21 Global Macros and I/O Standards Low-power flash devices have six chip global networks and four quadrant clock networks. However, the same clock macros are used for assigning signals to chip globals and quadrant globals. Depending on the clock macro placement or assignment in the Physical Design Constraint (PDC) file or MultiView Navigator (MVN), the signal will use the chip global network or quadrant network. Table 3-6 on page 3-12 lists the clock macros available for low-power flash devices. Refer to the IGLOO, Fusion and ProASIC3 Macro Library Guide for details. v1.4 3 - 11 Global Resources in Actel Low-Power Flash Devices Table 3-6 * Clock Macros Macro Name Description CLKBUF Symbol Input macro for Clock Network CLKBUF Y PAD CLKBUF_x Input macro for Clock Network with specific I/O standard CLKBUF_LVDS/ LVPECL LVDS or LVPECL input macro for Clock Network CLKBUF_X Y PAD PADP PADP Y CLKBUF_LVDS PADN CLKINT CLKBUF_LVPECL Y PADN Internal clock interface A Y CLKINT CLKBIBUF Bidirectional macro with input dedicated to routed Clock Network D E Y PAD CLKBIBUF Use these available macros to assign a signal to the global network. In addition to these global macros, PLL and CLKDLY macros can also drive the global networks. Use I/O-standard-specific clock macros (CLKBUF_x) to instantiate a specific I/O standard for the global signals. Table 3-7 shows the list of these I/O-standard-specific macros. Note that if you use these I/O-standard-specific clock macros, you cannot change the I/O standard later in the design stage. If you use the regular CLKBUF macro, you can use MVN or the PDC file in Designer to change the I/O standard. The default I/O standard for CLKBUF is LVTTL in the current Actel Libero(R) Integrated Design Environment (IDE) and Designer software. Table 3-7 * I/O Standards within CLKBUF Name Description CLKBUF_LVCMOS5 LVCMOS clock buffer with 5.0 V CMOS voltage level CLKBUF_LVCMOS33 LVCMOS clock buffer with 3.3 V CMOS voltage level CLKBUF_LVCMOS25 LVCMOS clock buffer with 2.5 V CMOS voltage level1 CLKBUF_LVCMOS18 LVCMOS clock buffer with 1.8 V CMOS voltage level CLKBUF_LVCMOS15 LVCMOS clock buffer with 1.5 V CMOS voltage level CLKBUF_LVCMOS12 LVCMOS clock buffer with 1.2 V CMOS voltage level CLKBUF_PCI PCI clock buffer CLKBUF_PCIX PCIX clock buffer CLKBUF_GTL25 GTL clock buffer with 2.5 V CMOS voltage level1 CLKBUF_GTL33 GTL clock buffer with 3.3 V CMOS voltage level1 Notes: 1. Supported in only the IGLOOe, ProASIC3E, AFS600, and AFS1500 devices 2. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O technology. 3 -1 2 v1.4 Global Resources in Actel Low-Power Flash Devices Table 3-7 * I/O Standards within CLKBUF (continued) Name Description CLKBUF_GTLP25 GTL+ clock buffer with 2.5 V CMOS voltage level1 CLKBUF_GTLP33 GTL+ clock buffer with 3.3 V CMOS voltage level1 CLKBUF_ HSTL _I HSTL Class I clock buffer1 CLKBUF_ HSTL _II HSTL Class II clock buffer1 CLKBUF_SSTL2_I SSTL2 Class I clock buffer1 CLKBUF_SSTL2_II SSTL2 Class II clock buffer1 CLKBUF_SSTL3_I SSTL3 Class I clock buffer1 CLKBUF_SSTL3_II SSTL3 Class II clock buffer1 Notes: 1. Supported in only the IGLOOe, ProASIC3E, AFS600, and AFS1500 devices 2. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O technology. The current synthesis tool libraries only infer the CLKBUF or CLKINT macros in the netlist. All other global macros must be instantiated manually into your HDL code. The following is an example of CLKBUF_LVCMOS25 global macro instantiations that you can copy and paste into your code: VHDL component clkbuf_lvcmos25 port (pad : in std_logic; y : out std_logic); end component begin -- concurrent statements u2 : clkbuf_lvcmos25 port map (pad => end ext_clk, y => int_clk); Verilog module design (______); input _____; output ______; clkbuf_lvcmos25 u2 (.y(int_clk), .pad(ext_clk); endmodule Using Global Macros in Synplicity The Synplify(R) synthesis tool automatically inserts global buffers for nets with high fanout during synthesis. By default, Synplicity(R) puts six global macros (CLKBUF or CLKINT) in the netlist, including any global instantiation or PLL macro. Synplify always honors your global macro instantiation. If you have a PLL (only primary output is used) in the design, Synplify adds five more global buffers in the netlist. Synplify uses the following global counting rule to add global macros in the netlist: 1. CLKBUF: 1 global buffer 2. CLKINT: 1 global buffer 3. CLKDLY: 1 global buffer 4. PLL: 1 to 3 global buffers - GLA, GLB, GLC, YB, and YC are counted as 1 buffer. - GLB or YB is used or both are counted as 1 buffer. - GLC or YC is used or both are counted as 1 buffer. v1.4 3 - 13 Global Resources in Actel Low-Power Flash Devices CLKA EXTFB POWERDOWN OADIVRST GLA LOCK GLB YB GLC YC Note: OAVDIVRST exists only in the Fusion PLL. Figure 3-9 * PLLs in Low-Power Flash Devices You can use the syn_global_buffers attribute in Synplify to specify a maximum number of global macros to be inserted in the netlist. This can also be used to restrict the number of global buffers inserted. In the Synplicity 8.1 version, a new attribute, syn_global_minfanout, has been added for low-power flash devices. This enables you to promote only the high-fanout signal to global. However, be aware that you can only have six signals assigned to chip global networks, and the rest of the global signals should be assigned to quadrant global networks. So, if the netlist has 18 global macros, the remaining 12 global macros should have fanout that allows the instances driven by these globals to be placed inside a quadrant. Global Promotion and Demotion Using PDC The HDL source file or schematic is the preferred place for defining which signals should be assigned to a clock network using clock macro instantiation. This method is preferred because it is guaranteed to be honored by the synthesis tools and Designer software and stop any replication on this net by the synthesis tool. Note that a signal with fanout may have logic replication if it is not promoted to global during synthesis. In that case, the user cannot promote that signal to global using PDC. See Synplicity Help for details on using this attribute. To help you with global management, Designer allows you to promote a signal to a global network or demote a global macro to a regular macro from the user netlist using the compile options and/or PDC commands. The following are the PDC constraints you can use to promote a signal to a global network: 1. PDC syntax to promote a regular net to a chip global clock: assign_global_clock -net netname The following will happen during promotion of a regular signal to a global network: - If the net is external, the net will be driven by a CLKINT inserted automatically by Compile. - The I/O macro will not be changed to CLKBUF macros. - If the net is an internal net, the net will be driven by a CLKINT inserted automatically by Compile. 2. PDC syntax to promote a net to a quadrant clock: assign_local_clock -net netname -type quadrant UR|UL|LR|LL This follows the same rule as the chip global clock network. The following PDC command demotes the clock nets to regular nets. unassign_global_clock -net netname 3 -1 4 v1.4 Global Resources in Actel Low-Power Flash Devices The following will happen during demotion of a global signal to regular nets: * CLKBUF_x becomes INBUF_x; CLKINT is removed from the netlist. * The essential global macro, such as the output of the Clock Conditioning Circuit, cannot be demoted. * No automatic buffering will happen. Since no automatic buffering happens when a signal is demoted, this net may have a high delay due to large fanout. This may have a negative effect on the quality of the results. Actel recommends that the automatic global demotion only be used on small-fanout nets. Use clock networks for high-fanout nets to improve timing and routability. Spine Assignment The low-power flash device architecture allows the global networks to be segmented and used as clock spines. These spines, also called local clocks, enable the use of PDC or MVN to assign a signal to a spine. PDC syntax to promote a net to a spine/local clock: assign_local_clock -net netname -type [quadrant|chip] Tn|Bn|Tn:Bm If the net is driven by a clock macro, Designer automatically demotes the clock net to a regular net before it is assigned to a spine. Nets driven by a PLL or CLKDLY macro cannot be assigned to a local clock. When assigning a signal to a spine or quadrant global network using PDC (pre-compile), the Designer software will legalize the shared instances. The number of shared instances to be legalized can be controlled by compile options. If these networks are created in MVN (only quadrant globals can be created), no legalization is done (as it is post-compile). Designer does not do legalization between non-clock nets. As an example, consider two nets, net_clk and net_reset, driving the same flip-flop. The following PDC constraints are used: assign_local_clock -net net_clk -type chip T3 assign_local_clock -net net_reset -type chip T1:T2 During Compile, Designer adds a buffer in the reset net and places it in the T1 or T2 region, and places the flip-flop in the T3 spine region (Figure 3-10). After Compile Before Compile D net_clk D CLK CLK net_clk CLR net_reset CLR net_reset T1 T2 Added buffer T3 assign_local_clock -net net_clk -type chip T3 assign_local_clock -net net_reset -type chip T1:T2 Figure 3-10 * Adding a Buffer for Shared Instances v1.4 3 - 15 Global Resources in Actel Low-Power Flash Devices You can control the maximum number of shared instances allowed for the legalization to take place using the Compile Option dialog box shown in Figure 3-11. Refer to Libero IDE / Designer online help for details on the Compile Option dialog box. A large number of shared instances most likely indicates a floorplanning problem that you should address. Figure 3-11 * Shared Instances in the Compile Option Dialog Box Designer Flow for Global Assignment To achieve the desired result, pay special attention to global management during synthesis and place-and-route. The current Synplify tool does not insert more than six global buffers in the netlist by default. Thus, the default flow will not assign any signal to the quadrant global network. However, you can use attributes in Synplify and increase the default global macro assignment in the netlist. Designer v6.2 supports automatic quadrant global assignment, which was not available in Designer v6.1. Layout will make the choice to assign the correct signals to global. However, you can also utilize PDC and perform manual global assignment to overwrite any automatic assignment. The following step-by-step suggestions guide you in the layout of your design and help you improve timing in Designer: 1. Run Compile and check the Compile report. The Compile report has global information in the "Device Utilization" section that describes the number of chip and quadrant signals in the design. A "Net Report" section describes chip global nets, quadrant global nets, local clock nets, a list of nets listed by fanout, and net candidates for local clock assignment. Review this information. Note that YB or YC are counted as global only when they are used in isolation; if you use YB only and not GLB, this net is not shown in the global/quadrant nets report. Instead, it appears in the Global Utilization report. 2. If some signals have a very high fanout and are candidates for global promotion, promote those signals to global using the compile options or PDC commands. Figure 3-12 on page 3-17 shows the Globals Management section of the compile options. Select Promote regular nets whose fanout is greater than and enter a reasonable value for fanouts. 3 -1 6 v1.4 Global Resources in Actel Low-Power Flash Devices Figure 3-12 * Globals Management GUI in Designer 3. Occasionally, the synthesis tool assigns a global macro to clock nets, even though the fanout is significantly less than other asynchronous signals. Select Demote global nets whose fanout is less than and enter a reasonable value for fanouts. This frees up some global networks from the signals that have very low fanouts. This can also be done using PDC. 4. Use local clocks for the signals that do not need to go to the whole chip but should have low skew. This local clocks assignment can only be done using PDC. 5. Assign the I/O buffer using MVN if you have fixed I/O assignment. As shown in Figure 3-7 on page 3-9, there are three sets of global pins that have a hardwired connection to each global network. Do not try to put multiple CLKBUF macros in these three sets of global pins. For example, do not assign two CLKBUFs to GAA0x and GAA2x pins. 6. You must click Commit at the end of MVN assignment. This runs the pre-layout checker and checks the validity of global assignment. 7. Always run Compile with the Keep existing physical constraints option on. This uses the quadrant clock network assignment in the MVN assignment and checks if you have the desired signals on the global networks. 8. Run Layout and check the timing. v1.4 3 - 17 Global Resources in Actel Low-Power Flash Devices Simple Design Example Consider a design consisting of six building blocks (shift registers) and targeted for an A3PE600PQ208 (Figure 3-10 on page 3-15). The example design consists of two PLLs (PLL1 has GLA only; PLL2 has both GLA and GLB), a global reset (ACLR), an enable (EN_ALL), and three external clock domains (QCLK1, QCLK2, and QCLK3) driving the different blocks of the design. Note that the PQ208 package only has two PLLs (which access the chip global network). Because of fanout, the global reset and enable signals need to be assigned to the chip global resources. There is only one free chip global for the remaining global (QCLK1, QCLK2, QCLK3). Place two of these signals on the quadrant global resource. The design example demonstrates manually assignment of QCLK1 and QCLK2 to the quadrant global using the PDC command. PDOWN PLLZ_CLKA PLL2 POWER-DOWN CLKA reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock LOCK GLA GLB REG_PLLCLK2GLA_OUT REG_PLLCLK2GLA \$116 reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock DATA_QCLK1 QCLK1 REG_QCLK1_OUT REG_QCLK1 DATA_PLLCQCLK2 EN_ALL DATA_QCLK2 ACLR QCLK2 reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock REG_QCLK2 REG_QCLK2_OUT reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock REG_PLLCLK2GLB_OUT REG_PLLCLK2GLB reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock DATA_QCLK3 QCLK3 REG_QCLK3_OUT REG_QCLK3 DATA_PLLCLK1 PLL1_CLKA PLL1 POWER-DOWN CLKA \$115 reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock LOCK GLA REG_PLLCLK1 Figure 3-13 * Block Diagram of the Global Management Example Design 3 -1 8 v1.4 REG_PLLCLK1_OUT Global Resources in Actel Low-Power Flash Devices Step 1 Run Synthesis with default options. The Synplicity log shows the following device utilization: Cell usage: cell count area count*area DFN1E1C1 1536 2.0 3072.0 BUFF 278 1.0 278.0 INBUF 10 0.0 0.0 VCC 9 0.0 0.0 GND 9 0.0 0.0 OUTBUF 6 0.0 0.0 CLKBUF 3 0.0 0.0 PLL 2 0.0 0.0 TOTAL 3350.0 1853 Step 2 Run Compile with the Promote regular nets whose fanout is greater than option selected in Designer; you will see the following in the Compile report: Device utilization report: ========================== CORE Used: 1536 Total: 13824 (11.11%) IO (W/ clocks) Used: 19 Total: 147 (12.93%) Differential IO Used: 0 Total: 65 (0.00%) GLOBAL Used: 8 Total: 18 (44.44%) PLL Used: 2 Total: 2 (100.00%) RAM/FIFO Used: 0 Total: 24 (0.00%) FlashROM Used: 0 Total: 1 (0.00%) ........................ The following nets have been assigned to a global resource: Fanout Type Name -------------------------1536 INT_NET Net : EN_ALL_c Driver: EN_ALL_pad_CLKINT Source: AUTO PROMOTED 1536 SET/RESET_NET Net : ACLR_c Driver: ACLR_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : QCLK1_c Driver: QCLK1_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : QCLK2_c Driver: QCLK2_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : QCLK3_c Driver: QCLK3_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : $1N14 Driver: $1I5/Core Source: ESSENTIAL 256 CLK_NET Net : $1N12 Driver: $1I6/Core Source: ESSENTIAL 256 CLK_NET Net : $1N10 Driver: $1I6/Core Source: ESSENTIAL Designer will promote five more signals to global due to high fanout. There are eight signals assigned to global networks. v1.4 3 - 19 Global Resources in Actel Low-Power Flash Devices During Layout, Designer will assign two of the signals to quadrant global locations. Step 3 (optional) You can also assign the QCLK1_c and QCLK2_c nets to quadrant regions using the following PDC commands: assign_local_clock -net QCLK1_c assign_local_clock -net QCLK2_c -type quadrant UL -type quadrant LL Step 4 Import this PDC with the netlist and run Compile again. You will see the following in the Compile report: The following nets have been assigned to a global resource: Fanout Type Name -------------------------1536 INT_NET Net : EN_ALL_c Driver: EN_ALL_pad_CLKINT Source: AUTO PROMOTED 1536 SET/RESET_NET Net : ACLR_c Driver: ACLR_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : QCLK3_c Driver: QCLK3_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : $1N14 Driver: $1I5/Core Source: ESSENTIAL 256 CLK_NET Net : $1N12 Driver: $1I6/Core Source: ESSENTIAL 256 CLK_NET Net : $1N10 Driver: $1I6/Core Source: ESSENTIAL The following nets have been assigned to a quadrant clock resource using PDC: Fanout Type Name -------------------------256 CLK_NET Net : QCLK1_c Driver: QCLK1_pad_CLKINT Region: quadrant_UL 256 CLK_NET Net : QCLK2_c Driver: QCLK2_pad_CLKINT Region: quadrant_LL Step 5 Run Layout. Global Management in PLL Design This section describes the legal global network connections to PLLs in the low-power flash devices. For detailed information on using PLLs, refer to Clock Conditioning Circuits in IGLOO and ProASIC3 Devices. Actel recommends that you use the dedicated global pins to directly drive the reference clock input of the associated PLL for reduced propagation delays and clock distortion. However, low-power flash devices offer the flexibility to connect other signals to reference clock inputs. Each PLL is associated with three global networks (Figure 3-8 on page 3-10). There are some limitations, such as when trying to use the global and PLL at the same time: 3 -2 0 * If you use a PLL with only primary output, you can still use the remaining two free global networks. * If you use three globals associated with a PLL location, you cannot use the PLL on that location. * If the YB or YC output is used standalone, it will occupy one global, even though this signal does not go to the global network. v1.4 Global Resources in Actel Low-Power Flash Devices Using Spines of Occupied Global Networks When a signal is assigned to a global network, the flash switches are programmed to set the MUX select lines (explained in the "Clock Aggregation Architecture" section on page 3-9) to drive the spines of that network with the global net. However, if the global net is restricted from reaching into the scope of a spine, the MUX drivers of that spine are available for other high-fanout or critical signals (Figure 3-14). For example, if you want to limit the CLK1_c signal to the left half of the chip and want to use the right side of the same global network for CLK2_c, you can add the following PDC commands: define_region -name region1 -type inclusive 0 0 34 29 assign_net_macros region1 CLK1_c assign_local_clock -net CLK2_c -type chip B2 Figure 3-14 * Design Example Using Spines of Occupied Global Networks Conclusion IGLOO, Fusion, and ProASIC3 devices contain 18 global networks: 6 chip global networks and 12 quadrant global networks. These global networks can be segmented into local low-skew networks called spines. The spines provide low-skew networks for the high-fanout signals of a design. These allow you up to 252 different internal/external clocks in an A3PE3000 device. This document describes the architecture for the global network, plus guidelines and methodologies in assigning signals to globals and spines. v1.4 3 - 21 Global Resources in Actel Low-Power Flash Devices Related Documents Handbook Documents Clock Conditioning Circuits in IGLOO and ProASIC3 Devices http://www.actel.com/LPD_CCC_HBs.pdf I/O Structures in IGLOO PLUS Devices http://www.actel.com/documents/IGLOOPLUS_IO_HBs.pdf I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf I/O Structures in IGLOOe and ProASIC3E Devices http://www.actel.com/documents/IGLOOe_PA3E_IO_HBs.pdf User's Guides IGLOO, Fusion, and ProASIC3 Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-005-4 Revised December 2008 3 -2 2 v1.4 Global Resources in Actel Low-Power Flash Devices List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.3 (October 2008) v1.2 (June 2008) v1.1 (March 2008) v1.0 (January 2008) Changes in Current Version (v1.4) Page The "Global Architecture" section was updated to include 10 k devices, and to include information about VersaNet global support for IGLOO nano devices. 3-1 The Table 3-1 * Flash-Based FPGAs was updated to include IGLOO nano and ProASIC3 nano devices. 3-2 The "VersaNet Global Network Distribution" section was updated to include 10 k devices and to note an exception in global lines for nano devices. 3-3 Figure 3-2 * Simplified VersaNet Global Network (30 k gates and below) is new. 3-4 The "Spine Architecture" section was updated to clarify support for 10 k and nano devices. 3-5 Table 3-2 * Globals/Spines/Rows for IGLOO and ProASIC3 Devices was updated to include IGLOO nano and ProASIC3 nano devices. 3-6 The figure in the CLKBUF_LVDS/LVPECL row of Table 3-6 * Clock Macros was updated to change CLKBIBUF to CLKBUF. 3-12 A third bullet was added to the beginning of the "Global Architecture" section: In Fusion devices, the west CCC also contains a PLL core. In the two larger devices (AFS600 and AFS1500), the west and east CCCs each contain a PLL. 3-1 The "Global Resource Support in Flash-Based Devices" section was revised to include new families and make the information more concise. 3-2 Table 3-2 * Globals/Spines/Rows for IGLOO and ProASIC3 Devices was updated to include A3PE600/L in the device column. 3-6 Table note 1 was revised in Table 3-7 * I/O Standards within CLKBUF to include AFS600 and AFS1500. 3-12 The following changes were made to the family descriptions in Table 3-1 * Flash-Based FPGAs: 3-2 * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. The "Global Architecture" section was updated to include the IGLOO PLUS family. The bullet was revised to include that the west CCC does not contain a PLL core in 15 k and 30 k devices. Instances of "A3P030 and AGL030 devices" were replaced with "15 k and 30 k gate devices." 3-1 Table 3-1 * Flash-Based FPGAs and the accompanying text was updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 3-2 The "VersaNet Global Network Distribution" section, "Spine Architecture" section, the note in Figure 3-1 * Overview of VersaNet Global Network and Device Architecture, and the note in Figure 3-3 * Simplified VersaNet Global Network (60 k gates and above) were updated to include mention of 15 k gate devices. 3-3, 3-4 v1.4 3 - 23 Global Resources in Actel Low-Power Flash Devices Previous Version v1.0 (continued) 51900087-1/3.05 51900087-0/1.05 3 -2 4 Changes in Current Version (v1.4) Page Table 3-2 * Globals/Spines/Rows for IGLOO and ProASIC3 Devices was updated to add the A3P015 device, and to revise the values for clock trees, globals/spines per tree, and globals/spines per device for the A3P030 and AGL030 devices. 3-6 Table 3-3 * Globals/Spines/Rows for IGLOO PLUS Devices is new. 3-6 CLKBUF_LVCMOS12 was added to Table 3-7 * I/O Standards within CLKBUF. 3-12 The "Handbook Documents" section was updated to include the three different I/O Structures chapters for ProASIC3 and IGLOO device families. 3-22 Figure 3-3 * Simplified VersaNet Global Network (60 k gates and above) was updated. 3-4 The "Naming of Global I/Os" section was updated. 3-10 The "Using Global Macros in Synplicity" section was updated. 3-13 The "Global Promotion and Demotion Using PDC" section was updated. 3-14 The "Designer Flow for Global Assignment" section was updated. 3-16 The "Simple Design Example" section was updated. 3-18 Table 3-2 * Globals/Spines/Rows for IGLOO and ProASIC3 Devices was updated. 3-6 v1.4 4 - Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Introduction This document outlines the following device information: Clock Conditioning Circuit (CCC) features, PLL core specifications, functional descriptions, software configuration information, detailed usage information, recommended board-level considerations, and other considerations concerning clock conditioning circuits and global networks in low-power flash devices or mixedsignal FPGAs. Overview of Clock Conditioning Circuitry In Fusion, IGLOO,(R) and ProASIC(R)3 devices, the CCCs are used to implement frequency division, frequency multiplication, phase shifting, and delay operations. The CCCs are available in six chip locations--each of the four chip corners and the middle of the east and west chip sides. For devicespecific variations, refer to the "Device-Specific Layout" section on page 4-17. The CCC is composed of the following: * PLL core * 3 phase selectors * 6 programmable delays and 1 fixed delay that advances/delays phase * 5 programmable frequency dividers that provide frequency multiplication/division (not shown in Figure 4-5 on page 4-10 because they are automatically configured based on the user's required frequencies) * 1 dynamic shift register that provides CCC dynamic reconfiguration capability Figure 4-1 provides a simplified block diagram of the physical implementation of the building blocks in each of the CCCs. 3 Global I/Os To Core Multiplexer Tree CLKA To Global Network A From Core 3 Global I/Os To Core CLKB From Core 3 Global I/Os To Core CCC Function Block (with or without PLL) CLKC To Global Network B To Global Network C From Core Multiple Signals Single Signals Figure 4-1 * Overview of the CCCs Offered in Fusion, IGLOO, and ProASIC3 v1.4 4-1 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Each CCC can implement up to three independent global buffers (with or without programmable delay) or a PLL function (programmable frequency division/multiplication, phase shift, and delays) with up to three global outputs. Unused global outputs of a PLL can be used to implement independent global buffers, up to a maximum of three global outputs for a given CCC. CCC Programming The CCC block is fully configurable, either via flash configuration bits set in the programming bitstream or through an asynchronous interface. This asynchronous dedicated shift register interface is dynamically accessible from inside the low-power flash devices to permit parameter changes, such as PLL divide ratios and delays, during device operation. To increase the versatility and flexibility of the clock conditioning system, the CCC configuration is determined either by the user during the design process, with configuration data being stored in flash memory as part of the device programming procedure, or by writing data into a dedicated shift register during normal device operation. This latter mode allows the user to dynamically reconfigure the CCC without the need for core programming. The shift register is accessed through a simple serial interface. Refer to UJTAG Applications in Actel's Low-Power Flash Devices or the application note Using Global Resources in Actel Fusion Devices. Global Resources Low-power flash and mixed-signal devices provide three global routing networks (GLA, GLB, and GLC) for each of the CCC locations. There are potentially many I/O locations; each global I/O location can be chosen from only one of three possibilities. This is controlled by the multiplexer tree circuitry in each global network. Once the I/O location is selected, the user has the option to utilize the CCCs before the signals are connected to the global networks. The CCC in each location (up to six) has the same structure, so generating the CCC macros is always done with an identical software GUI. The CCCs in the corner locations drive the quadrant global networks, and the CCCs in the middle of the east and west chip sides drive the chip global networks. The quadrant global networks span only a quarter of the device, while the chip global networks span the entire device. For more details on global resources offered in low-power flash devices, refer to Global Resources in Actel Low-Power Flash Devices. A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, or CLKC-GLC) of a given CCC. A PLL macro uses the CLKA CCC input to drive its reference clock. It uses the GLA and, optionally, the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global output cannot be reused if the YB (or YC) output is used. Refer to the "PLL Macro Signal Descriptions" section on page 4-8 for more information. Each global buffer, as well as the PLL reference clock, can be driven from one of the following: 4 -2 * 3 dedicated single-ended I/Os using a hardwired connection * 2 dedicated differential I/Os using a hardwired connection * The FPGA core v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs CCC Support in Actel's Flash Devices The flash FPGAs listed in Table 4-1 support the CCC feature and the functions described in this document. Table 4-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities IGLOO nano The industry's lowest-power, smallest-size solution ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 4-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 4-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. v1.4 4-3 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Global Buffers with No Programmable Delays Access to the global / quadrant global networks can be configured directly from the global I/O buffer, bypassing the CCC functional block (as indicated by the dotted lines in Figure 4-1 on page 4-1). Internal signals driven by the FPGA core can use the global / quadrant global networks by connecting via the routed clock input of the multiplexer tree. There are many specific CLKBUF macros supporting the wide variety of single-ended I/O inputs (CLKBUF) and differential I/O standards (CLKBUF_LVDS/LVPECL) in the low-power flash families. They are used when connecting global I/Os directly to the global/quadrant networks. When an internal signal needs to be connected to the global/quadrant network, the CLKINT macro is used to connect the signal to the routed clock input of the network's MUX tree. To utilize direct connection from global I/Os or from internal signals to the global/quadrant networks, CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros are used (Figure 4-2). * The CLKBUF and CLKBUF_LVPECL/LVDS1 macros are composite macros that include an I/O macro driving a global buffer, which uses a hardwired connection. * The CLKBUF, CLKBUF_LVPECL/LVDS1 and CLKINT macros are pass-through clock sources and do not use the PLL or provide any programmable delay functionality. * The CLKINT macro provides a global buffer function driven internally by the FPGA core. The available CLKBUF macros are described in the IGLOO, Fusion, and ProASIC3 Macro Library Guide. Clock Source CLKBUF_LVDS/LVPECL Macro PADN Y PADP Clock Conditioning CLKBIBUF Macro D Y CLKINT Macro A Y E None Output GLA, GLB, or GLC PAD CLKBIBUF CLKBUF Macro PAD Y Figure 4-2 * CCC Options: Global Buffers with No Programmable Delay Global Buffer with Programmable Delay Clocks requiring clock adjustments can utilize the programmable delay cores before connecting to the global / quadrant global networks. A maximum of 18 CCC global buffers can be instantiated in a device--three per CCC and up to six CCCs per device. Each CCC functional block contains a programmable delay element for each of the global networks (up to three), and users can utilize these features by using the corresponding macro (Figure 4-3 on page 4-5). 1. 4 -4 B-LVDS and M-LVDS are supported with the LVDS macro. v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Clock Source Clock Conditioning Output Input LVDS/LVPECL Macro PADN GLA CLK Y GL PADP or GLB or DLYGL[4:0] INBUF* Macro Y PAD GLC Note: For INBUF* driving a PLL macro or CLKDLY macro, the I/O will be hard-routed to the CCC; i.e., will be placed by software to a dedicated Global I/O. Figure 4-3 * CCC Options: Global Buffers with Programmable Delay The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to delay the clock input using a programmable delay. The CLKDLY macro takes the selected clock input and adds a user-defined delay element. This macro generates an output clock phase shift from the input clock. The CLKDLY macro can be driven by an INBUF* macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the software will automatically place the dedicated global I/O in the appropriate locations. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards supported by the low-power flash family. The available INBUF macros are described in the IGLOO, Fusion, and ProASIC3 Macro Library Guide. The CLKDLY macro can be driven directly from the FPGA core. The CLKDLY macro can also be driven from an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate the clock input driven by the hardwired I/O connection. The visual CLKDLY configuration in the SmartGen area of the Actel Libero(R) Integrated Design Environment (IDE) and Designer tools allows the user to select the desired amount of delay and configures the delay elements appropriately. SmartGen also allows the user to select the input clock source. SmartGen will automatically instantiate the special macro, PLLINT, when needed. CLKDLY Macro Signal Descriptions The CLKDLY macro supports one input and one output. Each signal is described in Table 4-2. Table 4-2 * Signal Input and Output Description of the CLKDLY Macro Name I/O CLK Reference Clock Input GL Global Output Description Reference clock input Output Primary output clock to respective global/quadrant clock networks v1.4 4-5 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs CLKDLY Macro Usage When a CLKDLY macro is used in a CCC location, the programmable delay element is used to allow the clock delays to go to the global network. In addition, the user can bypass the PLL in a CCC location integrated with a PLL, but use the programmable delay that is associated with the global network by instantiating the CLKDLY macro. The same is true when using programmable delay elements in a CCC location with no PLLs (the user needs to instantiate the CLKDLY macro). There is no difference between the programmable delay elements used for the PLL and the CLKDLY macro. The CCC will be configured to use the programmable delay elements in accordance with the macro instantiated by the user. As an example, if the PLL is not used in a particular CCC location, the designer is free to specify up to three CLKDLY macros in the CCC, each of which can have its own input frequency and delay adjustment options. If the PLL core is used, assuming output to only one global clock network, the other two global clock networks are free to be used by either connecting directly from the global inputs or connecting from one or two CLKDLY macros for programmable delay. The programmable delay elements are shown in the block diagram of the PLL block shown in Figure 4-5 on page 4-10. Note that any CCC locations with no PLL present contain only the programmable delay blocks going to the global networks (labeled "Programmable Delay Type 2"). Refer to the "Clock Delay Adjustment" section on page 4-25 for a description of the programmable delay types used for the PLL. Also refer to Table 4-13 on page 4-31 for Programmable Delay Type 1 step delay values, and Table 4-14 on page 4-32 for Programmable Delay Type 2 step delay values. CCC locations with a PLL present can be configured to utilize only the programmable delay blocks (Programmable Delay Type 2) going to the global networks A, B, and C. Global network A can be configured to use only the programmable delay element (bypassing the PLL) if the PLL is not used in the design. Figure 4-5 on page 4-10 shows a block diagram of the PLL, where the programmable delay elements are used for the global networks (Programmable Delay Type 2). 4 -6 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Global Buffers with PLL Function Clocks requiring frequency synthesis or clock adjustments can utilize the PLL core before connecting to the global / quadrant global networks. A maximum of 18 CCC global buffers can be instantiated in a device--three per CCC and up to six CCCs per device. Each PLL core can generate up to three global/quadrant clocks, while a clock delay element provides one. The PLL functionality of the clock conditioning block is supported by the PLL macro. Clock Source Clock Conditioning Input LVDS/LVPECL Macro Output PLL Macro GLA PADN Y PADP INBUF* Macro PAD Y CLKA EXTFB POWERDOWN OADIVRST 1 OADIVHALF1 OADIV[4:0] 2 OAMUX[2:0] 2 DLYGLA[4:0] 2 OBDIV[4:0] 2 OBMUX[2:0] 2 2 DLYYB[4:0] 2 DLYGLB[4:0] OCDIV[4:0] 2 2 OCMUX[2:0] DLYYC[4:0] 2 DLYGLC[4:0] 2 2 FINDIV[6:0] FBDIV[6:0] 2 FBDLY[4:0] 2 FBSEL[1:0] 2 XDLYSEL2 VCOSEL[2:0] 2 GLA LOCK GLB YB GLC YC or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) Notes: 1. For Fusion only. 2. Refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for more information. 3. For INBUF* driving a PLL macro or CLKDLY macro, the I/O will be hard-routed to the CCC; i.e., will be placed by software to a dedicated Global I/O. Figure 4-4 * CCC Options: Global Buffers with PLL The PLL macro provides five derived clocks (three independent) from a single reference clock. The PLL macro also provides power-down input and lock output signals. The additional inputs shown on the macro are configuration settings, which are configured through the use of SmartGen. For manual setting of these bits refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for details. Figure 4-5 on page 4-10 illustrates the various clock output options and delay elements. v1.4 4-7 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs PLL Macro Signal Descriptions The PLL macro supports two inputs and up to six outputs. Table 4-3 gives a description of each signal. Table 4-3 * Signal Input and Output Signals of the PLL Block I/O Description CLKA Reference Clock Name Input Reference clock input for PLL core; input clock for primary output clock, GLA OADIVRST Reset Signal for the Output Divider A Input For Fusion only. OADIVRST can be used when you bypass the PLL core (i.e., OAMUX = 001). The purpose of the OADIVRST signals is to reset the output of the final clock divider to synchronize it with the input to that divider when the PLL is bypassed. The signal is active on a low to high transition. The signal must be low for at least one divider input. If PLL core is used, this signal is "don't care" and the internal circuitry will generate the reset signal for the synchronization purpose. OADIVHALF Output A Division by Half Input For Fusion only. Active high. Division by half feature. This feature can only be used when users bypass the PLL core (i.e., OAMUX = 001) and the RC Oscillator (RCOSC) drives the CLKA input. This can be used to divide the 100 MHz RC oscillator by a factor of 1.5, 2.5, 3.5, 4.5 ... 14.5). Refer to Table 4-17 on page 4-33 for more information. EXTFB External Feedback Input Allows an external signal to be compared to a reference clock in the PLL core's phase detector. Input Active low input that selects power-down mode and disables the PLL. With the POWERDOWN signal asserted, the PLL core sends 0 V signals on all of the outputs. POWERDOWN Power Down GLA Primary Output Output Primary output clock to respective global/quadrant clock networks GLB Secondary 1 Output Output Secondary 1 output clock to respective global/quadrant clock networks YB Core 1 Output GLC Secondary 2 Output Output Secondary 2 output clock to respective global/quadrant clock networks YC Core 2 Output Output Core 2 output clock to local routing network LOCK PLL Lock Indicator Output Active high signal indicating that steady-state lock has been achieved between CLKA and the PLL feedback signal Output Core 1 output clock to local routing network Input Clock The inputs to the input reference clock (CLKA) of the PLL can come from global input pins, regular I/O pins, or internally from the core. For Fusion families, the input reference clock can also be from the embedded RC oscillator or crystal oscillator. Global Output Clocks GLA (Primary), GLB (Secondary 1), and GLC (Secondary 2) are the outputs of Global Multiplexer 1, Global Multiplexer 2, and Global Multiplexer 3, respectively. These signals (GLx) can be used to drive the high-speed global and quadrant networks of the low-power flash devices. A global multiplexer block consists of the input routing for selecting the input signal for the GLx clock and the output multiplexer, as well as delay elements associated with that clock. Core Output Clocks YB and YC are known as Core Outputs and can be used to drive internal logic without using global network resources. This is especially helpful when global network resources must be conserved and utilized for other timing-critical paths. 4 -8 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs YB and YC are identical to GLB and GLC, respectively, with the exception of a higher selectable final output delay. The SmartGen PLL Wizard will configure these outputs according to user specifications and can enable these signals with or without the enabling of Global Output Clocks. The above signals can be enabled in the following output groupings in both internal and external feedback configurations of the static PLL: * One output - GLA only * Two outputs - GLA + (GLB and/or YB) * Three outputs - GLA + (GLB and/or YB) + (GLC and/or YC) PLL Macro Block Diagram As illustrated, the PLL supports three distinct output frequencies from a given input clock. Two of these (GLB and GLC) can be routed to the B and C global network access, respectively, and/or routed to the device core (YB and YC). There are five delay elements to support phase control on all five outputs (GLA, GLB, GLC, YB, and YC). There are delay elements in the feedback loop that can be used to advance the clock relative to the reference clock. The PLL macro reference clock can be driven in the following ways: 1. By an INBUF* macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. 2. Directly from the FPGA core. 3. From an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired I/O connection described earlier. During power-up, the PLL outputs will toggle around the maximum frequency of the voltagecontrolled oscillator (VCO) gear selected. Toggle frequencies can range from 40 MHz to 250 MHz. This will continue as long as the clock input (CLKA) is constant (HIGH or LOW). This can be prevented by LOW assertion of the POWERDOWN signal. The visual PLL configuration in SmartGen, a component of the Libero IDE and Designer tools, will derive the necessary internal divider ratios based on the input frequency and desired output frequencies selected by the user. v1.4 4-9 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs SmartGen also allows the user to select the various delays and phase shift values necessary to adjust the phases between the reference clock (CLKA) and the derived clocks (GLA, GLB, GLC, YB, and YC). SmartGen allows the user to select the input clock source. SmartGen automatically instantiates the special macro, PLLINT, when needed. CLKA PLL Core Programmable Delay Four-Phase Output Phase Select Programmable Delay Type 2 GLA Programmable Delay Type 2 GLB Programmable Delay Type 1 YB Programmable Delay Type 2 GLC Programmable Delay Type 1 YC Programmable Delay Type 1 EXTFB Phase Select Phase Select Note: Clock divider and clock multiplier blocks are not shown in this figure or in SmartGen. They are automatically configured based on the user's required frequencies. Figure 4-5 * CCC with PLL Block Global Input Selections Low-power flash devices provide the flexibility of choosing one of the three global input pad locations available to connect to a CCC functional block or to a global / quadrant global network. Figure 4-6 and Figure 4-7 on page 4-11 show the detailed architecture of each global input structure for 30 k gate devices and below, as well as 60 k gate devices and above, respectively. For 60 k gate devices and above (Figure 4-6), if the single-ended I/O standard is chosen, there is flexibility to choose one of the global input pads (the first, second, and fourth input). Once chosen, the other I/O locations are used as regular I/Os. If the differential I/O standard is chosen, the first and second inputs are considered as paired, and the third input is paired with a regular I/O. The user then has the choice of selecting one of the two sets to be used as the clock input source to the CCC functional block. There is also the option to allow an internal clock signal to feed the global network or the CCC functional block. A multiplexer tree selects the appropriate global input for routing to the desired location. Note that the global I/O pads do not need to feed the global network; they can also be used as regular I/O pads. 4 -1 0 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Dedicated I/O Pad To Core Sample Pin Names Drives the global network directly (GLA or GLC) GEC0/IO37RSB1 Routed Clock (from FPGA core) Figure 4-6 * Clock Input Sources (30 k gates devices and below) Each shaded box represents an INBUF or INBUF_LVDS/LVPECL macro, as appropriate. To Core Sample Pin Names 1 GAA0/IO0NDB0V0 1 GAA1/IO00PDB0V0 + Source for CCC (CLKA or CLKB or CLKC) 1 GAA2/IO13PDB7V1 Routed Clock 2 (from FPGA core) + GAA[0:2]: GA represents global in the northwest corner of the device. A[0:2]: designates specific A clock source. Notes: 1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric. Refer to User I/O Naming Conventions in I/O Structures in IGLOO and ProASIC3 Devices. 2. Instantiate the routed clock source input as follows: a) Connect the output of a logic element to the clock input of a PLL, CLKDLY, or CLKINT macro. b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS/B-LVDS/M-LVDS/DDR) in a relevant global pin location. Figure 4-7 * Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT (60 k gates devices and above) v1.4 4 - 11 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Each global buffer, as well as the PLL reference clock, can be driven from one of the following: * 3 dedicated single-ended I/Os using a hardwired connection * 2 dedicated differential I/Os using a hardwired connection * The FPGA core Since the architecture of the devices varies as size increases, the following list details I/O types supported for globals: IGLOO and ProASIC3 * LVDS-based clock sources are available only on 250 k gate devices and above. * 60 k and 125 k gate devices support single-ended clock sources only. * 15 k and 30 k gate devices support these inputs for CCC only and do not contain a PLL. * nano devices: - 10 k, 15 k, and 20 k devices do not contain PLLs in the CCCs, and support only CLKBUF and CLKINT. - 60 k, 125 k, and 250 k devices support one PLL in the middle left CCC position. In the absence of the PLL, this CCC can be used by CLKBUF, CLKINT, and CLKDLY macros. The corner CCCs support CLKBUF, CLKINT, and CLKDLY. Fusion * AFS600 and AFS1500: All single-ended, differential, and voltage-referenced I/O standards (Pro I/O). * AFS090 and AFS250: All single-ended and differential I/O standards. Clock Sources for PLL and CLKDLY Macros The input reference clock (CLKA for a PLL macro, CLK for a CLKDLY macro) can be accessed from different sources via the associated clock multiplexer tree. Each CCC has the option of choosing the source of the input clock from one of the following: * Hardwired I/O * External I/O * Core Logic * RC Oscillator (Fusion only) * Crystal Oscillator (Fusion only) The SmartGen macro builder tool allows users to easily create the PLL and CLKDLY macros with the desired settings. Actel strongly recommends using SmartGen to generate the CCC macros. Hardwired I/O Clock Source Hardwired I/O refers to global input pins that are hardwired to the multiplexer tree, which directly accesses the CCC global buffers. These global input pins have designated pin locations and are indicated with the I/O naming convention Gmn (m refers to any one of the positions where the PLL core is available, and n refers to any one of the three global input MUXes and the pin number of the associated global location, m). Choosing this option provides the benefit of directly connecting to the CCC reference clock input, which provides less delay. See Figure 4-8 on page 4-13 for an example illustration of the connections, shown in red. If a CLKDLY macro is initiated to utilize the programmable delay element of the CCC, the clock input can be placed at one of nine dedicated global input pin locations. In other words, if Hardwired I/O is chosen as the input source, the user can decide to place the input pin in one of the GmA0, GmA1, GmA2, GmB0, GmB1, GmB2, GmC0, GmC1, or GmC2 locations of the low-power flash devices. When a PLL macro is used to utilize the 4 -1 2 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs PLL core in a CCC location, the clock input of the PLL can only be connected to one of three GmA* global pin locations: GmA0, GmA1, or GmA2. To Core Gmn0 Gmn1 Multiplexer Tree _ + PLL or CLKDLY Macro To Global (or local) Routing Network CLKA IOuxwByVz Gmn2 _ + Routed Clock (from FPGA core) Gmn* = Global Input Pin IOuxwByVz = Regular I/O Pin PLLINT Note: Fusion CCCs have additional source selections (RCOSC, XTAL). Figure 4-8 * Illustration of Hardwired I/O (global input pins) Usage for IGLOO and ProASIC3 devices 60 k Gates and Larger To Core Dedicated I/O Pad Sample Pin Names GEC0/IO37RSB1 Directly Drives Global Network (GLA or GLC) Routed Clock (from the FPGA core) Figure 4-9 * Illustration of Hardwired I/O (global input pins) Usage for IGLOO and ProASIC3 devices 30 k Gates and Smaller External I/O Clock Source External I/O refers to regular I/O pins. The clock source is instantiated with one of the various INBUF options and accesses the CCCs via internal routing. The user has the option of assigning this input to any of the I/Os labeled with the I/O convention IOuxwByVz. Refer to User I/O Naming Conventions in I/O Structures in IGLOO and ProASIC3 Devices, and for Fusion, refer to the Fusion Mixed-Signal Programmable System Chip datasheet for more information. Figure 4-10 gives a brief explanation of external I/O usage. Choosing this option provides the freedom of selecting any user I/O location but introduces additional delay because the signal connects to the routed clock input through internal routing before connecting to the CCC reference clock input. For the External I/O option, the routed signal would be instantiated with a PLLINT macro before connecting to the CCC reference clock input. This instantiation is conveniently done automatically by SmartGen when this option is selected. Actel recommends using the SmartGen tool to generate the CCC macro. The instantiation of the PLLINT macro results in the use of the routed clock input of the I/O to connect to the PLL clock input. If not using SmartGen, manually instantiate a PLLINT macro before the PLL reference clock to indicate that the regular I/O driving the PLL reference clock should be used (see Figure 4-10 on page 4-14 for an example illustration of the connections, shown in red). v1.4 4 - 13 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs In the above two options, the clock source must be instantiated with one of the various INBUF macros. The reference clock pins of the CCC functional block core macros must be driven by regular input macros (INBUFs), not clock input macros. To Core Gmn* Gmn* Multiplexer Tree _ + PLL or CLKDLY Macro CLKA To Global (or Local) Routing Network IOuxwByVz* Gmn* _ + Routed Clock (from FPGA Core) PLLINT Gmn* = Global Input Pin IOuxwByVz = Regular I/O Pin IOuxwByVz* Figure 4-10 * Illustration of External I/O Usage For Fusion devices, the input reference clock can also be from the embedded RC oscillator and crystal oscillator. In this case, the CCC configuration is the same as the hardwired I/O clock source, and users are required to instantiate the RC oscillator or crystal oscillator macro and connect its output to the input reference clock of the CCC block. 4 -1 4 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Core Logic Clock Source Core logic refers to internal routed nets. Internal routed signals access the CCC via the FPGA Core Fabric. Similar to the External I/O option, whenever the clock source comes internally from the core itself, the routed signal is instantiated with a PLLINT macro before connecting to the CCC clock input (see Figure 4-11 for an example illustration of the connections, shown in red). To Core Gmn* Gmn* Multiplexer Tree _ + PLL or CLKDLY Macro CLKA To Global (or Local) Routing Network IOuxwByVz* Gmn* Routed Clock (from FPGA Core) _ + PLLINT Gmn* = Global Input Pin IOuxwByVz = Regular I/O Pin From Internal Signals Figure 4-11 * Illustration of Core Logic Usage For Fusion devices, the input reference clock can also be from the embedded RC oscillator and crystal oscillator. In this case, the CCC configuration is the same as the hardwired I/O clock source, and users are required to instantiate the RC oscillator or crystal oscillator macro and connect its output to the input reference clock of the CCC block. v1.4 4 - 15 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Available I/O Standards Table 4-4 * Available I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros CLKBUF_LVCMOS5 CLKBUF_LVCMOS33 1 CLKBUF_LVCMOS25 2 CLKBUF_LVCMOS18 CLKBUF_LVCMOS15 CLKBUF_PCI CLKBUF_PCIX 3 CLKBUF_GTL25 2,3 CLKBUF_GTL33 2,3 CLKBUF_GTLP25 2,3 CLKBUF_GTLP33 2,3 CLKBUF_HSTL_I 2,3 CLKBUF_HSTL_II 2,3 CLKBUF_SSTL3_I 2,3 CLKBUF_SSTL3_II 2,3 CLKBUF_SSTL2_I 2,3 CLKBUF_SSTL2_II 2,3 CLKBUF_LVDS 4 CLKBUF_LVPECL Notes: 1. By default, the CLKBUF macro uses 3.3 V LVTTL I/O technology. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. 2. I/O standards only supported in ProASIC3E and IGLOOe families. 3. I/O standards only supported in the following Fusion devices: AFS600 and AFS1500. 4. B-LVDS and M-LVDS standards are supported by CLKBUF_LVDS. Global Synthesis Constraints The Synplify(R) synthesis tool, by default, allows six clocks in a design for Fusion, IGLOO, and ProASIC3. When more than six clocks are needed in the design, a user synthesis constraint attribute, syn_global_buffers, can be used to control the maximum number of clocks (up to 18) that can be inferred by the synthesis engine. High-fanout nets will be inferred with clock buffers and/or internal clock buffers. If the design consists of CCC global buffers, they are included in the count of clocks in the design. The subsections below discuss the clock input source (global buffers with no programmable delays) and the clock conditioning functional block (global buffers with programmable delays and/or PLL function) in detail. 4 -1 6 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Device-Specific Layout Two kinds of CCCs are offered in low-power flash devices: CCCs with integrated PLLs, and CCCs without integrated PLLs (simplified CCCs). Table 4-5 lists the number of CCCs in various devices. Table 4-5 * Number of CCCs by Device Size and Package Device CCCs with CCCs without Integrated Integrated PLLs PLLs (simplified CCC) ProASIC3 IGLOO Package A3PN010 AGLN010 All 0 2 A3PN015 AGLN015 All 0 2 A3PN020 AGLN020 All 0 2 AGLN060 CS81 0 6 AGLN060 All other packages 1 5 AGLN125 CS81 0 6 AGLN125 All other packages 1 5 AGLN250 CS81 0 6 AGLN250 All other packages 1 5 A3P015 AGL015 All 0 2 A3P030 AGL030/AGLP030 All 0 2 A3PN060 A3PN125 A3PN250 AGL060/AGLP060 CS121/CS201 0 6 A3P060 AGL060/AGLP060 All other packages 1 5 A3P125 AGL125/AGLP125 All 1 5 A3P250/L AGL250 All 1 5 A3P400 AGL400 All 1 5 A3P600/L AGL600 All 1 5 A3P1000/L AGL1000 All 1 5 A3PE600 AGLE600 PQ208 2 4 A3PE600/L All other packages 6 0 A3PE1500 PQ208 2 4 A3PE1500 All other packages 6 0 PQ208 2 4 All other packages 6 0 AFS090 All 1 5 AFS250, M1AFS250 All 1 5 A3PE3000/L A3PE3000/L AGLE3000 Fusion Devices AFS600, M7AFS600, M1AFS600 All 2 4 AFS1500, M1AFS1500 All 2 4 Note: nano 10 k, 15 k, and 20 k offer 6 global MUXes instead of CCCs. v1.4 4 - 17 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs This section outlines the following device information: CCC features, PLL core specifications, functional descriptions, software configuration information, detailed usage information, recommended board-level considerations, and other considerations concerning global networks in low-power flash devices. Clock Conditioning Circuits with Integrated PLLs Each of the CCCs with integrated PLLs includes the following: * 1 PLL core, which consists of a phase detector, a low-pass filter, and a four-phase voltagecontrolled oscillator * 3 global multiplexer blocks that steer signals from the global pads and the PLL core onto the global networks * 6 programmable delays and 1 fixed delay for time advance/delay adjustments * 5 programmable frequency divider blocks to provide frequency synthesis (automatically configured by the SmartGen macro builder tool) Clock Conditioning Circuits without Integrated PLLs There are two types of simplified CCCs without integrated PLLs in low-power flash devices. 1. The simplified CCC with programmable delays, which is composed of the following: - 3 global multiplexer blocks that steer signals from the global pads and the programmable delay elements onto the global networks - 3 programmable delay elements to provide time delay adjustments 2. The simplified CCC (referred to as CCC-GL) without programmable delay elements, which is composed of the following: - 4 -1 8 A global multiplexer block that steer signals from the global pads onto the global networks v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs CCC Locations CCCs located in the middle of the east and west sides of the device access the three VersaNet global networks on each side (six total networks), while the four CCCs located in the four corners access three quadrant global networks (twelve total networks). See Figure 4-12. Northwest Quadrant Global Networks CCC Location B Quadrant Global Spine CCC Location A 3 3 3 Chip-Wide (main) Global Networks 6 6 3 6 6 3 CCC Location C CCC Location F 3 Global Spine 3 CCC Location E 6 6 3 6 3 6 3 CCC Location D Southeast Quadrant Global Networks Figure 4-12 * Global Network Architecture for 60 k Gate Devices and Above v1.4 4 - 19 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs The following explains the locations of the CCCs in IGLOO and ProASIC3 devices: In Figure 4-14 on page 4-21 through Figure 4-15 on page 4-21, CCCs with integrated PLLs are indicated in red, and simplified CCCs are indicated in yellow. There is a letter associated with each location of the CCC, in clockwise order. The upper left corner CCC is named "A," the upper right is named "B," and so on. These names finish up at the middle left with letter "F." IGLOO and ProASIC3 CCC Locations In all IGLOO and ProASIC3 devices (except 10 k through 30 k gate devices, which do not contain PLLs), six CCCs are located in the same positions as the IGLOOe and ProASIC3E CCCs. Only one of the CCCs has an integrated PLL and is located in the middle of the west (middle left) side of the device. The other five CCCs are simplified CCCs and are located in the four corners and the middle of the east side of the device (Figure 4-13). A B Bank 0 CCC Bank 3 Bank 1 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os C F VersaTile Bank 3 Bank 1 ISP AES Decryption User Nonvolatile FlashROM (FROM) RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps D E Bank 2 = CCC with integrated PLL = Simplified CCC with programmable delay elements (no PLL) Figure 4-13 * CCC Locations in IGLOO and ProASIC3 Family Devices (except 10 k through 30 k gate devices) Note: The number and architecture of the banks are different for some devices. 10 k through 30 k gate devices do not support PLL features. In these devices, there are two CCC-GLs at the lower corners (one at the lower right, and one at the lower left). These CCC-GLs do not have programmable delays. 4 -2 0 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs IGLOOe and ProASIC3E CCC Locations IGLOOe and ProASIC3E devices have six CCCs--one in each of the four corners and one each in the middle of the east and west sides of the device (Figure 4-14). All six CCCs are integrated with PLLs, except in PQFP-208 package devices. PQFP-208 package devices also have six CCCs, of which two include PLLs and four are simplified CCCs. The CCCs with PLLs are implemented in the middle of the east and west sides of the device (middle right and middle left). The simplified CCCs without PLLs are located in the four corners of the device (Figure 4-15). CCC A B RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os C F VersaTile ISP AES Decryption User Nonvolatile FlashRom Flash*Freeze Technology RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps E D = CCC with integrated PLL Figure 4-14 * CCC Locations in IGLOOe and ProASIC3E Family Devices (except PQFP-208 package) Bank 0 A B RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 1 Bank 3 CCC I/Os C F Bank 1 Bank 3 VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps D E Bank 2 = CCC with integrated PLL = Simplified CCC with programmable delay elements (no PLL) Figure 4-15 * CCC Locations in ProASIC3E Family Devices (PQFP-208 package) v1.4 4 - 21 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Fusion CCC Locations Fusion devices have six CCCs: one in each of the four corners and one each in the middle of the east and west sides of the device (Figure 4-16 and Figure 4-17). The device can have one integrated PLL in the middle of the west side of the device or two integrated PLLs in the middle of the east and west sides of the device (middle right and middle left). A B Bank 0 CCC Bank 3 Bank 1 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os C F VersaTile Bank 3 Bank 1 ISP AES Decryption User Nonvolatile FlashROM (FROM) RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps D E Bank 2 = CCC with integrated PLL = Simplified CCC with programmable delay elements (no PLL) Figure 4-16 * CCC Locations in Fusion Family Devices (AFS090, AFS250, M1AFS250) Bank 0 A B RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 1 Bank 3 CCC I/Os C F Bank 1 Bank 3 VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps D E Bank 2 = CCC with integrated PLL = Simplified CCC with programmable delay elements (no PLL) Figure 4-17 * CCC Locations in Fusion Family Devices (except AFS090, AFS250, M1AFS250) 4 -2 2 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs PLL Core Specifications PLL core specifications can be found in the DC and Switching Characteristics chapter of the appropriate family datasheet. Loop Bandwidth Common design practice for systems with a low-noise input clock is to have PLLs with small loop bandwidths to reduce the effects of noise sources at the output. Table 4-6 shows the PLL loop bandwidth, providing a measure of the PLL's ability to track the input clock and jitter. Table 4-6 * -3 dB Frequency of the PLL Typical Maximum Minimum (Ta = +125C, VCCA = 1.4 V) (Ta = +25C, VCCA = 1.5 V) (Ta = -55C, VCCA = 1.6 V) -3 dB Frequency 15 kHz 25 kHz 45 kHz PLL Core Operating Principles This section briefly describes the basic principles of PLL operation. The PLL core is composed of a phase detector (PD), a low-pass filter (LPF), and a four-phase voltage-controlled oscillator (VCO). Figure 4-18 illustrates a basic single-phase PLL core with a divider and delay in the feedback path. Frequency Reference Input FIN Phase Detector Voltage Controlled Oscillator Low-Pass Filter Divide by M Counter Frequency Output M x FIN Delay Figure 4-18 * Simplified PLL Core with Feedback Divider and Delay The PLL is an electronic servo loop that phase-aligns the PD feedback signal with the reference input. To achieve this, the PLL dynamically adjusts the VCO output signal according to the average phase difference between the input and feedback signals. The first element is the PD, which produces a voltage proportional to the phase difference between its inputs. A simple example of a digital phase detector is an Exclusive-OR gate. The second element, the LPF, extracts the average voltage from the phase detector and applies it to the VCO. This applied voltage alters the resonant frequency of the VCO, thus adjusting its output frequency. Consider Figure 4-18 with the feedback path bypassing the divider and delay elements. If the LPF steadily applies a voltage to the VCO such that the output frequency is identical to the input frequency, this steady-state condition is known as lock. Note that the input and output phases are also identical. The PLL core sets a LOCK output signal HIGH to indicate this condition. Should the input frequency increase slightly, the PD detects the frequency/phase difference between its reference and feedback input signals. Since the PD output is proportional to the phase difference, the change causes the output from the LPF to increase. This voltage change increases the resonant frequency of the VCO and increases the feedback frequency as a result. The PLL dynamically adjusts in this manner until the PD senses two phase-identical signals and steady-state lock is achieved. The opposite (decreasing PD output signal) occurs when the input frequency decreases. v1.4 4 - 23 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Now suppose the feedback divider is inserted in the feedback path. As the division factor M (shown in Figure 4-19) is increased, the average phase difference increases. The average phase difference will cause the VCO to increase its frequency until the output signal is phase-identical to the input after undergoing division. In other words, lock in both frequency and phase is achieved when the output frequency is M times the input. Thus, clock division in the feedback path results in multiplication at the output. A similar argument can be made when the delay element is inserted into the feedback path. To achieve steady-state lock, the VCO output signal will be delayed by the input period less the feedback delay. For periodic signals, this is equivalent to time-advancing the output clock by the feedback delay. Another key parameter of a PLL system is the acquisition time. Acquisition time is the amount of time it takes for the PLL to achieve lock (i.e., phase-align the feedback signal with the input reference clock). For example, suppose there is no voltage applied to the VCO, allowing it to operate at its free-running frequency. Should an input reference clock suddenly appear, a lock would be established within the maximum acquisition time. Functional Description This section provides detailed descriptions of PLL block functionality: clock dividers and multipliers, clock delay adjustment, phase adjustment, and dynamic PLL configuration. Clock Dividers and Multipliers The PLL block contains five programmable dividers. Figure 4-19 shows a simplified PLL block. n CLKA PLL Core m Fixed Delay System Delay 270 180 90 0 u D1 Feedback Delay Output Delay D2 Output Delay D2 v w 4 -2 4 v1.4 YB GLC Secondary 2 D1 Output Delay Figure 4-19 * PLL Block Diagram GLB Secondary 1 D1 Output Delay Output Delay D2 D1 = Programmable Delay Type 1 D2 = Programmable Delay Type 2 GLA Primary YC Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Dividers n and m (the input divider and feedback divider, respectively) provide integer frequency division factors from 1 to 128. The output dividers u, v, and w provide integer division factors from 1 to 32. Frequency scaling of the reference clock CLKA is performed according to the following formulas: fGLA = fCLKA x m / (n x u) - GLA Primary PLL Output Clock EQ 4-1 fGLB = fYB = fCLKA x m / (n x v) - GLB Secondary 1 PLL Output Clock(s) EQ 4-2 fGLC = fYC = fCLKA x m / (n x w) - GLC Secondary 2 PLL Output Clock(s) EQ 4-3 SmartGen provides a user-friendly method of generating the configured PLL netlist, which includes automatically setting the division factors to achieve the closest possible match to the requested frequencies. Since the five output clocks share the n and m dividers, the achievable output frequencies are interdependent and related according to the following formula: fGLA = fGLB x (v / u) = fGLC x (w / u) EQ 4-4 Clock Delay Adjustment There are a total of seven configurable delay elements implemented in the PLL architecture. Two of the delays are located in the feedback path, entitled System Delay and Feedback Delay. System Delay provides a fixed delay of 2 ns (typical), and Feedback Delay provides selectable delay values from 0.6 ns to 5.56 ns in 160 ps increments (typical). For PLLs, delays in the feedback path will effectively advance the output signal from the PLL core with respect to the reference clock. Thus, the System and Feedback delays generate negative delay on the output clock. Additionally, each of these delays can be independently bypassed if necessary. The remaining five delays perform traditional time delay and are located at each of the outputs of the PLL. Besides the fixed global driver delay of 0.755 ns for each of the global networks, the global multiplexer outputs (GLA, GLB, and GLC) each feature an additional selectable delay value from 0.025 ns to 0.76 ns in the first step, and then to 5.56 ns in 160 ps increments. The additional YB and YC signals have access to a selectable delay from 0.6 ns to 5.56 ns in 160 ps increments (typical). This is the same delay value as the CLKDLY macro. It is similar to CLKDLY, which bypasses the PLL core just to take advantage of the phase adjustment option with the delay value. The following parameters must be taken into consideration to achieve minimum delay at the outputs (GLA, GLB, GLC, YB, and YC) relative to the reference clock: routing delays from the PLL core to CCC outputs, core outputs and global network output delays, and the feedback path delay. The feedback path delay acts as a time advance of the input clock and will offset any delays introduced beyond the PLL core output. The routing delays are determined from back-annotated simulation and are configuration-dependent. Phase Adjustment The output from the PLL core can be phase-adjusted with respect to the reference input clock, CLKA. The user can select a 0, 90, 180, or 270 phase shift independently for each of the outputs YA, GLB/YB, and GLC/YC. Note that each of these phase-adjusted signals might also undergo further frequency division and/or time adjustment via the remaining dividers and delays located at the outputs of the PLL. v1.4 4 - 25 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Dynamic PLL Configuration The CCCs can be configured both statically and dynamically. In addition to the ports available in the Static CCC, the Dynamic CCC has the dynamic shift register signals that enable dynamic reconfiguration of the CCC. With the Dynamic CCC, the ports CLKB and CLKC are also exposed. All three clocks (CLKA, CLKB, and CLKC) can be configured independently. The CCC block is fully configurable. The following two sources can act as the CCC configuration bits. Flash Configuration Bits The flash configuration bits are the configuration bits associated with programmed flash switches. These bits are used when the CCC is in static configuration mode. Once the device is programmed, these bits cannot be modified. They provide the default operating state of the CCC. Dynamic Shift Register Outputs This source does not require core reprogramming and allows core-driven dynamic CCC reconfiguration. When the dynamic register drives the configuration bits, the user-defined core circuit takes full control over SDIN, SDOUT, SCLK, SSHIFT, and SUPDATE. The configuration bits can consequently be dynamically changed through shift and update operations in the serial register interface. Access to the logic core is accomplished via the dynamic bits in the specific tiles assigned to the PLLs. Figure 4-20 illustrates a simplified block diagram of the MUX architecture in the CCCs. SDIN SDOUT SCLK SSHIFT SUPDATE <80:0>* Dynamic Shift Register RESET_ENABLE <80> <79:0> Flash Programming Configuration Bits <79:0>* MODE Configuration Bits * For Fusion, bit <88:81> is also needed. Figure 4-20 * The CCC Configuration MUX Architecture The selection between the flash configuration bits and the bits from the configuration register is made using the MODE signal shown in Figure 4-20. If the MODE signal is logic HIGH, the dynamic shift register configuration bits are selected. There are 81 control bits to configure the different functions of the CCC. Each group of control bits is assigned a specific location in the configuration shift register. For a list of the 81 configuration bits (C[80:0]) in the CCC and a description of each, refer to "PLL Configuration Bits Description" on page 4-28. The configuration register can be serially loaded with the new configuration data and programmed into the CCC using the following ports: 4 -2 6 * SDIN: The configuration bits are serially loaded into a shift register through this port. The LSB of the configuration data bits should be loaded first. * SDOUT: The shift register contents can be shifted out (LSB first) through this port using the shift operation. * SCLK: This port should be driven by the shift clock. * SSHIFT: The active-high shift enable signal should drive this port. The configuration data will be shifted into the shift register if this signal is HIGH. Once SSHIFT goes LOW, the data shifting will be halted. v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs * SUPDATE: The SUPDATE signal is used to configure the CCC with the new configuration bits when shifting is complete. To access the configuration ports of the shift register (SDIN, SDOUT, SSHIFT, etc.), the user should instantiate the CCC macro in his design with appropriate ports. Actel recommends that users choose SmartGen to generate the CCC macros with the required ports for dynamic reconfiguration. Users must familiarize themselves with the architecture of the CCC core and its input, output, and configuration ports to implement the desired delay and output frequency in the CCC structure. Figure 4-21 shows a model of the CCC with configurable blocks and switches. CLKA /n C<6:0> 270 180 90 0 PLL Core (7) (6) (5) (4) /m M U X A GLA D /u C<50:46> (2) Internal C<13:7> C<18:14> (1) C<31:29> (0) (2) D (1) D M U X B C<44:40> C<45> D /v YB C<39:38> C<23:19> C<34:32> D GLB CLKB C<55:51> Internal M U X C D /w YC C<70:66> C<28:24> C<37:35> D GLC CLKC C<60:56> Internal Figure 4-21 * CCC Block Control Bits - Graphical Representation of Assignments v1.4 4 - 27 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Loading the Configuration Register The most important part of CCC dynamic configuration is to load the shift register properly with the configuration bits. There are different ways to access and load the configuration shift register: * JTAG interface * Logic core * Specific I/O tiles JTAG Interface The JTAG interface requires no additional I/O pins. The JTAG TAP controller is used to control the loading of the CCC configuration shift register. Low-power flash devices provide a user interface macro between the JTAG pins and the device core logic. This macro is called UJTAG. A user should instantiate the UJTAG macro in his design to access the configuration register ports via the JTAG pins. For more information on CCC dynamic reconfiguration using UJTAG, refer to UJTAG Applications in Actel's Low-Power Flash Devices. Logic Core If the logic core is employed, the user must design a module to provide the configuration data and control the shifting and updating of the CCC configuration shift register. In effect, this is a userdesigned TAP controller, which requires additional chip resources. Specific I/O Tiles If specific I/O tiles are used for configuration, the user must provide the external equivalent of a TAP controller. This does not require additional core resources but does use pins. Shifting the Configuration Data To enter a new configuration, all 81 bits must shift in via SDIN. After all bits are shifted, SSHIFT must go LOW and SUPDATE HIGH to enable the new configuration. For simulation purposes, bits <71:73> and <77:80> are "don't care." The SUPDATE signal must be LOW during any clock cycle where SSHIFT is active. After SUPDATE is asserted, it must go back to the LOW state until a new update is required. PLL Configuration Bits Description Table 4-7 * Config. Bits <88:87> Configuration Bit Descriptions for the CCC Blocks Signal Name 1 GLMUXCFG [1:0] Description NGMUX configuration The configuration bits specify the input clocks to the NGMUX (refer to Table 4-16 on page 4-32).2 86 OCDIVHALF1 Division by half When the PLL is bypassed, the 100 MHz RC oscillator can be divided by the divider factor in Table 4-17 on page 4-33. 85 OBDIVHALF1 Division by half When the PLL is bypassed, the 100 MHz RC oscillator can be divided by a 0.5 factor (refer to Table 4-17 on page 4-33). 84 OADIVHALF1 Division by half When the PLL is bypassed, the 100 MHz RC oscillator can be divided by certain 0.5 factor (refer to Table 4-15 on page 4-32). Notes: 1. The <88:81> configuration bits are only for the Fusion dynamic CCC. 2. This value depends on the input clock source, so Layout must complete before these bits can be set. After completing Layout in Designer, generate the "CCC_Configuration" report by choosing Tools > Report > CCC_Configuration. The report contains the appropriate settings for these bits. 4 -2 8 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Table 4-7 * Config. Bits Configuration Bit Descriptions for the CCC Blocks (continued) Signal Name Description 83 RXCSEL1 CLKC input selection Select the CLKC input clock source between RC oscillator and crystal oscillator (refer to Table 4-15 on page 4-32).2 82 RXBSEL1 CLKB input selection Select the CLKB input clock source between RC oscillator and crystal oscillator (refer to Table 4-15 on page 4-32).2 81 RXASEL1 CLKA input selection Select the CLKA input clock source between RC oscillator and crystal oscillator (refer to Table 4-15 on page 4-32).2 80 RESETEN Reset Enable Enables (active high) the synchronization of PLL output dividers after dynamic reconfiguration (SUPDATE). The Reset Enable signal is READONLY and should not be modified via dynamic reconfiguration. 79 DYNCSEL Clock Input C Dynamic Select Configures clock input C to be sent to GLC for dynamic control.2 78 DYNBSEL Clock Input B Dynamic Select Configures clock input B to be sent to GLB for dynamic control.2 77 DYNASEL Clock Input A Dynamic Select Configures clock input A for dynamic PLL configuration.2 VCO Gear Control Three-bit VCO Gear Control for four frequency ranges (refer to Table 4-18 on page 4-33 and Table 4-19 on page 4-33). <76:74> VCOSEL[2:0] 73 STATCSEL MUX Select on Input C MUX selection for clock input C2 72 STATBSEL MUX Select on Input B MUX selection for clock input B2 71 STATASEL MUX Select on Input A MUX selection for clock input A2 <70:66> DLYC[4:0] YC Output Delay Sets the output delay value for YC. <65:61> DLYB[4:0] YB Output Delay Sets the output delay value for YB. <60:56> DLYGLC[4:0] GLC Output Delay Sets the output delay value for GLC. <55:51> DLYGLB[4:0] GLB Output Delay Sets the output delay value for GLB. <50:46> DLYGLA[4:0] Primary Output Delay Primary GLA output delay System Delay Select When selected, inserts System Delay in the feedback path in Figure 4-19 on page 4-24. Sets the feedback delay value for the feedback element in Figure 4-19 on page 4-24. 45 XDLYSEL <44:40> FBDLY[4:0] Feedback Delay <39:38> FBSEL[1:0] Primary Feedback Delay Select Controls the feedback MUX: no delay, include programmable delay element, or use external feedback. <37:35> OCMUX[2:0] Secondary 2 Output Select Selects from the VCO's four phase outputs for GLC/YC. Notes: 1. The <88:81> configuration bits are only for the Fusion dynamic CCC. 2. This value depends on the input clock source, so Layout must complete before these bits can be set. After completing Layout in Designer, generate the "CCC_Configuration" report by choosing Tools > Report > CCC_Configuration. The report contains the appropriate settings for these bits. v1.4 4 - 29 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Table 4-7 * Configuration Bit Descriptions for the CCC Blocks (continued) Config. Bits Signal <34:32> OBMUX[2:0] Secondary 1 Output Select Selects from the VCO's four phase outputs for GLB/YB. <31:29> OAMUX[2:0] GLA Output Select Selects from the VCO's four phase outputs for GLA. <28:24> OCDIV[4:0] Secondary 2 Output Divider Sets the divider value for the GLC/YC outputs. Also known as divider w in Figure 4-19 on page 4-24. The divider value will be OCDIV[4:0] + 1. <23:19> OBDIV[4:0] Secondary 1 Output Divider Sets the divider value for the GLB/YB outputs. Also known as divider v in Figure 4-19 on page 4-24. The divider value will be OBDIV[4:0] + 1. <18:14> OADIV[4:0] Primary Output Divider Sets the divider value for the GLA output. Also known as divider u in Figure 4-19 on page 4-24. The divider value will be OADIV[4:0] + 1. <13:7> FBDIV[6:0] Feedback Divider Sets the divider value for the PLL core feedback. Also known as divider m in Figure 4-19 on page 4-24. The divider value will be FBDIV[6:0] + 1. <6:0> FINDIV[6:0] Input Divider Input Clock Divider (/n). Sets the divider value for the input delay on CLKA. The divider value will be FINDIV[6:0] + 1. Name Description Notes: 1. The <88:81> configuration bits are only for the Fusion dynamic CCC. 2. This value depends on the input clock source, so Layout must complete before these bits can be set. After completing Layout in Designer, generate the "CCC_Configuration" report by choosing Tools > Report > CCC_Configuration. The report contains the appropriate settings for these bits. Table 4-8 to Table 4-14 on page 4-32 provide descriptions of the configuration data for the configuration bits. Table 4-8 * Input Clock Divider, FINDIV[6:0] (/n) FINDIV<6:0> State Divisor New Frequency Factor 0 1 1.00000 1 2 0.50000 ... ... ... 127 128 0.0078125 Divisor New Frequency Factor 0 1 1 1 2 2 Table 4-9 * Feedback Clock Divider, FBDIV[6:0] (/m) FBDIV<6:0> State ... ... ... 127 128 128 4 -3 0 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Table 4-10 * Output Frequency Dividers A Output Divider, OADIV <4:0> (/u); B Output Divider, OBDIV <4:0> (/v); C Output Divider, OCDIV <4:0> (/w) OADIV<4:0>; OBDIV<4:0>; CDIV<4:0> State Divisor New Frequency Factor 0 1 1.00000 1 2 0.50000 ... ... ... 31 32 0.03125 Table 4-11 * MUXA, MUXB, MUXC OAMUX<2:0>; OBMUX<2:0>; OCMUX<2:0> State MUX Input Selected 0 None. Six-input MUX and PLL are bypassed. Clock passes only through global MUX and goes directly into HC ribs. 1 Not available 2 PLL feedback delay line output 3 Not used 4 PLL VCO 0 phase shift 5 PLL VCO 90 phase shift 6 PLL VCO 180 phase shift 7 PLL VCO 270 phase shift Table 4-12 * 2-Bit Feedback MUX FBSEL<1:0> State MUX Input Selected 0 Ground. Used for power-down mode in power-down logic block. 1 PLL VCO 0 phase shift 2 PLL delayed VCO 0 phase shift 3 N/A Table 4-13 * Programmable Delay Selection for Feedback Delay and Secondary Core Output Delays FBDLY<4:0>; DLYYB<4:0>; DLYYC<4:0> State Delay Value 0 Typical delay = 600 ps 1 Typical delay = 760 ps 2 Typical delay = 920 ps ... ... 31 Typical delay = 5.56 ns v1.4 4 - 31 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Table 4-14 * Programmable Delay Selection for Global Clock Output Delays DLYGLA<4:0>; DLYGLB<4:0>; DLYGLC<4:0> State Delay Value 0 Typical delay = 225 ps 1 Typical delay = 760 ps 2 Typical delay = 920 ps ... ... 31 Typical delay = 5.56 ns Table 4-15 * Fusion Dynamic CCC Clock Source Selection RXASEL 1 1 DYNASEL Source of CLKA 0 RC Oscillator 1 Crystal Oscillator DYNBSEL Source of CLKB 1 0 RC Oscillator 1 1 Crystal Oscillator RXBSEL RXBSEL DYNCSEL Source of CLKC 1 0 RC Oscillator 1 1 Crystal Oscillator Table 4-16 * Fusion Dynamic CCC NGMUX Configuration GLMUXCFG<1:0> 00 01 10 4 -3 2 NGMUX Select Signal Supported Input Clocks to NGMUX 0 GLA 1 GLC 0 GLA 1 GLINT 0 GLC 1 GLINT v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Table 4-17 * Fusion Dynamic CCC Division by Half Configuration OADIVHALF / OBDIVHALF / OCDIVHALF OADIV<4:0> / OBDIV<4:0> / OCDIV<4:0> (in decimal) Divider Factor 2 1.5 4 2.5 6 3.5 28.6 8 4.5 22.2 10 5.5 18.2 12 6.5 15.4 14 7.5 13.3 16 8.5 11.8 18 9.5 10.5 20 10.5 9.5 22 11.5 8.7 24 12.5 8.0 26 13.5 7.4 28 14.5 6.9 0-31 1-32 1 0 Input Clock Frequency Output Clock Frequency (MHz) 100 MHz RC Oscillator 66.7 Other Clock Sources 40.0 Depends on other divider settings Table 4-18 * Configuration Bit <76:75> / VCOSEL<2:1> Selection for All Families VCOSEL[2:1] 00 Min. (MHz) Voltage 01 10 11 Max. (MHz) Min. (MHz) Max. (MHz) Min. (MHz) Max. (MHz) Min. (MHz) Max. (MHz) IGLOO and IGLOO PLUS 1.2 V 5% 24 35 30 70 60 140 135 160 1.5 V 5% 24 43.75 30 87.5 60 175 135 250 ProASIC3L, RT ProASIC3, and Military ProASIC3/L 1.2 V 5% 24 35 30 70 60 140 135 250 1.5 V 5% 24 43.75 30 70 60 175 135 350 24 43.75 33.75 87.5 67.5 175 135 350 ProASIC3 and Fusion 1.5 V 5% Table 4-19 * Configuration Bit <74> / VCOSEL<0> Selection for All Families VCOSEL[0] Description 0 Fast PLL lock acquisition time with high tracking jitter. Refer to the corresponding datasheet for specific value and definition. 1 Slow PLL lock acquisition time with low tracking jitter. Refer to the corresponding datasheet for specific value and definition. v1.4 4 - 33 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Software Configuration SmartGen automatically generates the desired CCC functional block by configuring the control bits, and allows the user to select two CCC modes: Static PLL and Delayed Clock (CLKDLY). Static PLL Configuration The newly implemented Visual PLL Configuration Wizard feature provides the user a quick and easy way to configure the PLL with the desired settings (Figure 4-22). The user can invoke SmartGen to set the parameters and generate the netlist file with the appropriate flash configuration bits set for the CCCs. As mentioned in "PLL Macro Block Diagram" on page 4-9, the input reference clock CLKA can be configured to be driven by Hardwired I/O, External I/O, or Core Logic. The user enters the desired settings for all the parameters (output frequency, output selection, output phase adjustment, clock delay, feedback delay, and system delay). Notice that the actual values (divider values, output frequency, delay values, and phase) are shown to aid the user in reaching the desired design frequency in real time. These values are typical-case data. Best- and worst-case data can be observed through static timing analysis in SmartTime within Designer. For dynamic configuration, the CCC parameters are defined using either the external JTAG port or an internally defined serial interface via the built-in dynamic shift register. This feature provides the ability to compensate for changes in the external environment. VCO Clock Frequency Programmable Output Delay Elements Input Selection Fixed System Delay Output Selection Feedback Selection (Feedback MUX) Figure 4-22 * Visual PLL Configuration Wizard 4 -3 4 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Feedback Configuration The PLL provides both internal and external feedback delays. Depending on the configuration, various combinations of feedback delays can be achieved. Internal Feedback Configuration This configuration essentially sets the feedback multiplexer to route the VCO output of the PLL core as the input to the feedback of the PLL. The feedback signal can be processed with the fixed system and the adjustable feedback delay, as shown in Figure 4-23. The dividers are automatically configured by SmartGen based on the user input. Indicated below is the System Delay pull-down menu. The System Delay can be bypassed by setting it to 0. When set, it adds a 2 ns delay to the feedback path (which results in delay advancement of the output clock by 2 ns). Figure 4-23 * Internal Feedback with Selectable System Delay Figure 4-24 shows the controllable Feedback Delay. If set properly in conjunction with the fixed System Delay, the total output delay can be advanced significantly. Figure 4-24 * Internal Feedback with Selectable Feedback Delay v1.4 4 - 35 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs External Feedback Configuration For certain applications, such as those requiring generation of PCB clocks that must be matched with existing board delays, it is useful to implement an external feedback, EXTFB. The Phase Detector of the PLL core will receive CLKA and EXTFB as inputs. EXTFB may be processed by the fixed System Delay element as well as the M divider element. The EXTFB option is currently not supported. After setting all the required parameters, users can generate one or more PLL configurations with HDL or EDIF descriptions by clicking the Generate button. SmartGen gives the option of saving session results and messages in a log file: **************** Macro Parameters **************** Name Family Output Format Type Input Freq(MHz) CLKA Source Feedback Delay Value Index Feedback Mux Select XDLY Mux Select Primary Freq(MHz) Primary PhaseShift Primary Delay Value Index Primary Mux Select Secondary1 Freq(MHz) Use GLB Use YB GLB Delay Value Index YB Delay Value Index Secondary1 PhaseShift Secondary1 Mux Select Secondary2 Freq(MHz) Use GLC Use YC GLC Delay Value Index YC Delay Value Index Secondary2 PhaseShift Secondary2 Mux Select : : : : : : : : : : : : : : : : : : : : : : : : : : : test_pll ProASIC3E VHDL Static PLL 10.000 Hardwired I/O 1 2 No 33.000 0 1 4 66.000 YES YES 1 1 0 4 101.000 YES NO 1 1 0 4 ... ... ... Primary Clock frequency 33.333 Primary Clock Phase Shift 0.000 Primary Clock Output Delay from CLKA 0.180 Secondary1 Secondary1 Secondary1 Secondary1 Clock Clock Clock Clock frequency 66.667 Phase Shift 0.000 Global Output Delay from CLKA 0.180 Core Output Delay from CLKA 0.625 Secondary2 Clock frequency 100.000 Secondary2 Clock Phase Shift 0.000 Secondary2 Clock Global Output Delay from CLKA 0.180 Below is an example Verilog HDL description of a legal PLL core configuration generated by SmartGen: module test_pll(POWERDOWN,CLKA,LOCK,GLA); 4 -3 6 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs input POWERDOWN, CLKA; output LOCK, GLA; wire VCC, GND; VCC VCC_1_net(.Y(VCC)); GND GND_1_net(.Y(GND)); PLL Core(.CLKA(CLKA), .EXTFB(GND), .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB(), .YB(), .GLC(), .YC(), .OADIV0(GND), .OADIV1(GND), .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), .OAMUX1(GND), .OAMUX2(VCC), .DLYGLA0(GND), .DLYGLA1(GND), .DLYGLA2(GND), .DLYGLA3(GND) , .DLYGLA4(GND), .OBDIV0(GND), .OBDIV1(GND), .OBDIV2(GND), .OBDIV3(GND), .OBDIV4(GND), .OBMUX0(GND), .OBMUX1(GND), .OBMUX2(GND), .DLYYB0(GND), .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND), .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(GND), .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(GND), .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), .DLYGLC2(GND), .DLYGLC3(GND) , .DLYGLC4(GND), .FINDIV0(VCC), .FINDIV1(GND), .FINDIV2( VCC), .FINDIV3(GND), .FINDIV4(GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(VCC), .FBDIV1(GND), .FBDIV2(VCC), .FBDIV3(GND), .FBDIV4(GND), .FBDIV5(GND), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2(GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1(GND), .XDLYSEL(GND), .VCOSEL0(GND), .VCOSEL1(GND), .VCOSEL2(GND)); defparam Core.VCOFREQUENCY = 33.000; endmodule The "PLL Configuration Bits Description" section on page 4-28 provides descriptions of the PLL configuration bits for completeness. The configuration bits are shown as busses only for purposes of illustration. They will actually be broken up into individual pins in compilation libraries and all simulation models. For example, the FBSEL[1:0] bus will actually appear as pins FBSEL1 and FBSEL0. The setting of these select lines for the static PLL configuration is performed by the software and is completely transparent to the user. v1.4 4 - 37 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Dynamic PLL Configuration To generate a dynamically reconfigurable CCC, the user should select Dynamic CCC in the configuration section of the SmartGen GUI (Figure 4-25). This will generate both the CCC core and the configuration shift register / control bit MUX. Figure 4-25 * SmartGen GUI Even if dynamic configuration is selected in SmartGen, the user must still specify the static configuration data for the CCC (Figure 4-26). The specified static configuration is used whenever the MODE signal is set to LOW and the CCC is required to function in the static mode. The static configuration data can be used as the default behavior of the CCC where required. Figure 4-26 * Dynamic CCC Configuration in SmartGen 4 -3 8 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs When SmartGen is used to define the configuration that will be shifted in via the serial interface, SmartGen prints out the values of the 81 configuration bits. For ease of use, several configuration bits are automatically inferred by SmartGen when the dynamic PLL core is generated; however, <71:73> (STATASEL, STATBSEL, STATCSEL) and <77:79> (DYNASEL, DYNBSEL, DYNCSEL) depend on the input clock source of the corresponding CCC. Users must first run Layout in Designer to determine the exact setting for these ports. After Layout is complete, generate the "CCC_Configuration" report by choosing Tools > Reports > CCC_Configuration in the Designer software. Refer to "PLL Configuration Bits Description" on page 4-28 for descriptions of the PLL configuration bits. For simulation purposes, bits <71:73> and <78:80> are "don't care." Therefore, it is strongly suggested that SmartGen be used to generate the correct configuration bit settings for the dynamic PLL core. After setting all the required parameters, users can generate one or more PLL configurations with HDL or EDIF descriptions by clicking the Generate button. SmartGen gives the option of saving session results and messages in a log file: **************** Macro Parameters **************** Name Family Output Format Type Input Freq(MHz) CLKA Source Feedback Delay Value Index Feedback Mux Select XDLY Mux Select Primary Freq(MHz) Primary PhaseShift Primary Delay Value Index Primary Mux Select Secondary1 Freq(MHz) Use GLB Use YB GLB Delay Value Index YB Delay Value Index Secondary1 PhaseShift Secondary1 Mux Select Secondary1 Input Freq(MHz) CLKB Source Secondary2 Freq(MHz) Use GLC Use YC GLC Delay Value Index YC Delay Value Index Secondary2 PhaseShift Secondary2 Mux Select Secondary2 Input Freq(MHz) CLKC Source : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : dyn_pll_hardio ProASIC3E VERILOG Dynamic CCC 30.000 Hardwired I/O 1 1 No 33.000 0 1 4 40.000 YES NO 1 1 0 0 40.000 Hardwired I/O 50.000 YES NO 1 1 0 0 50.000 Hardwired I/O Configuration Bits: FINDIV[6:0] 0000101 FBDIV[6:0] 0100000 OADIV[4:0] 00100 OBDIV[4:0] 00000 OCDIV[4:0] 00000 OAMUX[2:0] 100 OBMUX[2:0] 000 OCMUX[2:0] 000 FBSEL[1:0] 01 FBDLY[4:0] 00000 XDLYSEL 0 DLYGLA[4:0] 00000 v1.4 4 - 39 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs DLYGLB[4:0] DLYGLC[4:0] DLYYB[4:0] DLYYC[4:0] VCOSEL[2:0] 00000 00000 00000 00000 100 Primary Clock Frequency 33.000 Primary Clock Phase Shift 0.000 Primary Clock Output Delay from CLKA 1.695 Secondary1 Clock Frequency 40.000 Secondary1 Clock Phase Shift 0.000 Secondary1 Clock Global Output Delay from CLKB 0.200 Secondary2 Clock Frequency 50.000 Secondary2 Clock Phase Shift 0.000 Secondary2 Clock Global Output Delay from CLKC 0.200 ###################################### # Dynamic Stream Data ###################################### -------------------------------------|NAME |SDIN |VALUE |TYPE | -------------------------------------|FINDIV |[6:0] |0000101 |EDIT | |FBDIV |[13:7] |0100000 |EDIT | |OADIV |[18:14] |00100 |EDIT | |OBDIV |[23:19] |00000 |EDIT | |OCDIV |[28:24] |00000 |EDIT | |OAMUX |[31:29] |100 |EDIT | |OBMUX |[34:32] |000 |EDIT | |OCMUX |[37:35] |000 |EDIT | |FBSEL |[39:38] |01 |EDIT | |FBDLY |[44:40] |00000 |EDIT | |XDLYSEL |[45] |0 |EDIT | |DLYGLA |[50:46] |00000 |EDIT | |DLYGLB |[55:51] |00000 |EDIT | |DLYGLC |[60:56] |00000 |EDIT | |DLYYB |[65:61] |00000 |EDIT | |DLYYC |[70:66] |00000 |EDIT | |STATASEL|[71] |X |MASKED | |STATBSEL|[72] |X |MASKED | |STATCSEL|[73] |X |MASKED | |VCOSEL |[76:74] |100 |EDIT | |DYNASEL |[77] |X |MASKED | |DYNBSEL |[78] |X |MASKED | |DYNCSEL |[79] |X |MASKED | |RESETEN |[80] |1 |READONLY | Below is the resultant Verilog HDL description of a legal dynamic PLL core configuration generated by SmartGen: module dyn_pll_macro(POWERDOWN, CLKA, LOCK, GLA, GLB, GLC, SDIN, SCLK, SSHIFT, SUPDATE, MODE, SDOUT, CLKB, CLKC); input POWERDOWN, CLKA; output LOCK, GLA, GLB, GLC; input SDIN, SCLK, SSHIFT, SUPDATE, MODE; output SDOUT; input CLKB, CLKC; wire VCC, GND; VCC VCC_1_net(.Y(VCC)); GND GND_1_net(.Y(GND)); 4 -4 0 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs DYNCCC Core(.CLKA(CLKA), .EXTFB(GND), .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .CLKB(CLKB), .GLB(GLB), .YB(), .CLKC(CLKC), .GLC(GLC), .YC(), .SDIN(SDIN), .SCLK(SCLK), .SSHIFT(SSHIFT), .SUPDATE(SUPDATE), .MODE(MODE), .SDOUT(SDOUT), .OADIV0(GND), .OADIV1(GND), .OADIV2(VCC), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), .OAMUX1(GND), .OAMUX2(VCC), .DLYGLA0(GND), .DLYGLA1(GND), .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(GND), .OBDIV1(GND), .OBDIV2(GND), .OBDIV3(GND), .OBDIV4(GND), .OBMUX0(GND), .OBMUX1(GND), .OBMUX2(GND), .DLYYB0(GND), .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND), .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(GND), .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(GND), .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(VCC), .FINDIV1(GND), .FINDIV2(VCC), .FINDIV3(GND), .FINDIV4(GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(GND), .FBDIV1(GND), .FBDIV2(GND), .FBDIV3(GND), .FBDIV4(GND), .FBDIV5(VCC), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2(GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1(GND), .XDLYSEL(GND), .VCOSEL0(GND), .VCOSEL1(GND), .VCOSEL2(VCC)); defparam Core.VCOFREQUENCY = 165.000; endmodule Delayed Clock Configuration The CLKDLY macro can be generated with the desired delay and input clock source (Hardwired I/O, External I/O, or Core Logic), as in Figure 4-27. Figure 4-27 * Delayed Clock Configuration Dialog Box After setting all the required parameters, users can generate one or more PLL configurations with HDL or EDIF descriptions by clicking the Generate button. SmartGen gives the option of saving session results and messages in a log file: **************** Macro Parameters **************** Name Family Output Format Type Delay Index CLKA Source : : : : : : delay_macro ProASIC3 Verilog Delayed Clock 2 Hardwired I/O Total Clock Delay = 0.935 ns. The resultant CLKDLY macro Verilog netlist is as follows: module delay_macro(GL,CLK); output GL; input CLK; v1.4 4 - 41 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs wire VCC, GND; VCC VCC_1_net(.Y(VCC)); GND GND_1_net(.Y(GND)); CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(VCC), .DLYGL1(GND), .DLYGL2(VCC), .DLYGL3(GND), .DLYGL4(GND)); endmodule Detailed Usage Information Clock Frequency Synthesis Deriving clocks of various frequencies from a single reference clock is known as frequency synthesis. The PLL has an input frequency range from 1.5 to 350 MHz. This frequency is automatically divided down to a range between 1.5 MHz and 5.5 MHz by input dividers (not shown in Figure 4-18 on page 4-23) between PLL macro inputs and PLL phase detector inputs. The VCO output is capable of an output range from 24 to 350 MHz. With dividers before the input to the PLL core and following the VCO outputs, the VCO output frequency can be divided to provide the final frequency range from 0.75 to 350 MHz. Using SmartGen, the dividers are automatically set to achieve the closest possible matches to the specified output frequencies. Users should be cautious when selecting the desired PLL input and output frequencies and the I/O buffer standard used to connect to the PLL input and output clocks. Depending on the I/O standards used for the PLL input and output clocks, the I/O frequencies have different maximum limits. Refer to the family datasheets for specifications of maximum I/O frequencies for supported I/O standards. Desired PLL input or output frequencies will not be achieved if the selected frequencies are higher than the maximum I/O frequencies allowed by the selected I/O standards. Users should be careful when selecting the I/O standards used for PLL input and output clocks. Performing post-layout simulation can help detect this type of error, which will be identified with pulse width violation errors. Users are strongly encouraged to perform post-layout simulation to ensure the I/O standard used can provide the desired PLL input or output frequencies. Users can also choose to cascade PLLs together to achieve the high frequencies needed for their applications. Details of cascading PLLs are discussed in the "Cascading CCCs" section on page 4-47. In SmartGen, the actual generated frequency (under typical operating conditions) will be displayed beside the requested output frequency value. This provides the ability to determine the exact frequency that can be generated by SmartGen, in real time. The log file generated by SmartGen is a useful tool in determining how closely the requested clock frequencies match the user specifications. For example, assume a user specifies 101 MHz as one of the secondary output frequencies. If the best output frequency that could be achieved were 100 MHz, the log file generated by SmartGen would indicate the actual generated frequency. Simulation Verification The integration of the generated PLL and CLKDLY modules is similar to any VHDL component or Verilog module instantiation in a larger design; i.e., there is no special requirement that users need to take into account to successfully synthesize their designs. For simulation purposes, users need to refer to the VITAL or Verilog library that includes the functional description and associated timing parameters. Refer to the Software Tools section of the Actel website to obtain the family simulation libraries. If Actel Designer is installed, these libraries are stored in the following locations: <Designer_Installation_Directory>\lib\vtl\95\proasic3.vhd <Designer_Installation_Directory>\lib\vtl\95\proasic3e.vhd <Designer_Installation_Directory>\lib\vlog\proasic3.v <Designer_Installation_Directory>\lib\vlog\proasic3e.v 4 -4 2 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs For Libero IDE users, there is no need to compile the simulation libraries, as they are conveniently pre-compiled in the ModelSim(R) Actel simulation tool. The following is an example of a PLL configuration utilizing the clock frequency synthesis and clock delay adjustment features. The steps include generating the PLL core with SmartGen, performing simulation for verification with ModelSim, and performing static timing analysis with SmartTime in Designer. Parameters of the example PLL configuration: Input Frequency - 20 MHz Primary Output Requirement - 20 MHz with clock advancement of 3.02 ns Secondary 1 Output Requirement - 40 MHz with clock delay of 2.515 ns Figure 4-28 shows the SmartGen settings. Notice that the overall delays are calculated automatically, allowing the user to adjust the delay elements appropriately to obtain the desired delays. Figure 4-28 * SmartGen Settings After confirming the correct settings, generate a structural netlist of the PLL and verify PLL core settings by checking the log file: Name Family Output Format Type Input Freq(MHz) CLKA Source Feedback Delay Value Index Feedback Mux Select XDLY Mux Select Primary Freq(MHz) Primary PhaseShift Primary Delay Value Index Primary Mux Select Secondary1 Freq(MHz) Use GLB Use YB : : : : : : : : : : : : : : : : test_pll_delays ProASIC3E VHDL Static PLL 20.000 Hardwired I/O 21 2 No 20.000 0 1 4 40.000 YES NO v1.4 4 - 43 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs ... ... ... Primary Clock frequency 20.000 Primary Clock Phase Shift 0.000 Primary Clock Output Delay from CLKA -3.020 Secondary1 Clock frequency 40.000 Secondary1 Clock Phase Shift 0.000 Secondary1 Clock Global Output Delay from CLKA 2.515 Next, perform simulation in ModelSim to verify the correct delays. Figure 4-29 shows the simulation results. The delay values match those reported in the SmartGen PLL Wizard. Primary Clock Output Time Advancement from CLKA Secondary1 Clock Global Output Delay from CLKA Figure 4-29 * ModelSim Simulation Results The timing can also be analyzed using SmartTime in Designer. The user should import the synthesized netlist to Designer, perform Compile and Layout, and then invoke SmartTime. Go to Tools > Options and change the maximum delay operating conditions to Typical Case. Then expand the Clock-to-Out paths of GLA and GLB and the individual components of the path delays are shown. The path of GLA is shown in Figure 4-30 on page 4-45 displaying the same delay value. 4 -4 4 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Figure 4-30 * Static Timing Analysis Using SmartTime Place-and-Route Stage Considerations Several considerations must be noted to properly place the CCC macros for layout. For CCCs with clock inputs configured with the Hardwired I/O-Driven option: * PLL macros must have the clock input pad coming from one of the GmA* locations. * CLKDLY macros must have the clock input pad coming from one of the Global I/Os. If a PLL with a Hardwired I/O input is used at a CCC location and a Hardwired I/O-Driven CLKDLY macro is used at the same CCC location, the clock input of the CLKDLY macro must be chosen from one of the GmB* or GmC* pin locations. If the PLL is not used or is an External I/O-Driven or Core Logic-Driven PLL, the clock input of the CLKDLY macro can be sourced from the GmA*, GmB*, or GmC* pin locations. For CCCs with clock inputs configured with the External I/O-Driven option, the clock input pad can be assigned to any regular I/O location (IO******** pins). Note that since global I/O pins can also be used as regular I/Os, regardless of CCC function (CLKDLY or PLL), clock inputs can also be placed in any of these I/O locations. By default, the Designer layout engine will place global nets in the design at one of the six chip globals. When the number of globals in the design is greater than six, the Designer layout engine will automatically assign additional globals to the quadrant global networks of the low-power flash devices. If the user wishes to decide which global signals should be assigned to chip globals (six available) and which to the quadrant globals (three per quadrant for a total of 12 available), the assignment can be achieved with PinEditor, ChipPlanner, or by importing a placement v1.4 4 - 45 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs constraint file. Layout will fail if the global assignments are not allocated properly. See the "Physical Constraints for Quadrant Clocks" section for information on assigning global signals to the quadrant clock networks. Promoted global signals will be instantiated with CLKINT macros to drive these signals onto the global network. This is automatically done by Designer when the Auto-Promotion option is selected. If the user wishes to assign the signals to the quadrant globals instead of the default chip globals, this can done by using ChipPlanner, by declaring a physical design constraint (PDC), or by importing a PDC file. Physical Constraints for Quadrant Clocks If it is necessary to promote global clocks (CLKBUF, CLKINT, PLL, CLKDLY) to quadrant clocks, the user can define PDCs to execute the promotion. PDCs can be created using PDC commands (precompile) or the MultiView Navigator (MVN) interface (post-compile). The advantage of using the PDC flow over the MVN flow is that the Compile stage is able to automatically promote any regular net to a global net before assigning it to a quadrant. There are three options to place a quadrant clock using PDC commands: * Place a clock core (not hardwired to an I/O) into a quadrant clock location. * Place a clock core (hardwired to an I/O) into an I/O location (set_io) or an I/O module location (set_location) that drives a quadrant clock location. * Assign a net driven by a regular net or a clock net to a quadrant clock using the following command: assign_local_clock -net <net name> -type quadrant <quadrant clock region> where <net name> is the name of the net assigned to the local user clock region. <quadrant clock region> defines which quadrant the net should be assigned to. Quadrant clock regions are defined as UL (upper left), UR (upper right), LL (lower left), and LR (lower right). Note: If the net is a regular net, the software inserts a CLKINT buffer on the net. For example: assign_local_clock -net localReset -type quadrant UR Keep in mind the following when placing quadrant clocks using MultiView Navigator: Hardwired I/O-Driven CCCs * Find the associated clock input port under the Ports tab, and place the input port at one of the Gmn* locations using PinEditor or I/O Attribute Editor, as shown in Figure 4-31. Figure 4-31 * Port Assignment for a CCC with Hardwired I/O Clock Input 4 -4 6 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs * Use quadrant global region assignments by finding the clock net associated with the CCC macro under the Nets tab and creating a quadrant global region for the net, as shown in Figure 4-32. Figure 4-32 * Quadrant Clock Assignment for a Global Net External I/O-Driven CCCs The above-mentioned recommendation for proper layout techniques will ensure the correct assignment. It is possible that, especially with External I/O-Driven CCC macros, placement of the CCC macro in a desired location may not be achieved. For example, assigning an input port of an External I/O-Driven CCC near a particular CCC location does not guarantee global assignments to the desired location. This is because the clock inputs of External I/O-Driven CCCs can be assigned to any I/O location; therefore, it is possible that the CCC connected to the clock input will be routed to a location other than the one closest to the I/O location, depending on resource availability and placement constraints. Clock Placer The clock placer is a placement engine for low-power flash devices that places global signals on the chip global and quadrant global networks. Based on the clock assignment constraints for the chip global and quadrant global clocks, it will try to satisfy all constraints, as well as creating quadrant clock regions when necessary. If the clock placer fails to create the quadrant clock regions for the global signals, it will report an error and stop Layout. The user must ensure that the constraints set to promote clock signals to quadrant global networks are valid. Cascading CCCs The CCCs in low-power flash devices can be cascaded. Cascading CCCs can help achieve more accurate PLL output frequency results than those achievable with a single CCC. In addition, this technique is useful when the user application requires the output clock of the PLL to be a multiple of the reference clock by an integer greater than the maximum feedback divider value of the PLL (divide by 128) to achieve the desired frequency. For example, the user application may require a 280 MHz output clock using a 2 MHz input reference clock, as shown in Figure 4-33 on page 4-48. v1.4 4 - 47 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Figure 4-33 * Cascade PLL Configuration Using internal feedback, we know from EQ 4-1 on page 4-25 that the maximum achievable output frequency from the primary output is fGLA = fCLKA x m / (n x u) = 2 MHz x 128 / (1 x 1) = 256 MHz EQ 4-5 Figure 4-34 shows the settings of the initial PLL. When configuring the initial PLL, specify the input to be either Hardwired I/O-Driven or External I/O-Driven. This generates a netlist with the initial PLL routed from an I/O. Do not specify the input to be Core Logic-Driven, as this prohibits the connection from the I/O pin to the input of the PLL. Figure 4-34 * First-Stage PLL Showing Input of 2 MHz and Output of 256 MHz A second PLL can be connected serially to achieve the required frequency. EQ 4-1 on page 4-25 to EQ 4-3 on page 4-25 are extended as follows: fGLA2 = fGLA x m2 / (n2 x u2) = fCLKA1 x m1 x m2 / (n1 x u1 x n2 x u2) - Primary PLL Output Clock EQ 4-6 fGLB2 = fYB2 = fCLKA1 x m1 x m2 / (n1 x n2 x v1 x v2) - Secondary 1 PLL Output Clock(s) EQ 4-7 fGLC2 = fYC2 = fCLKA1 x m1 x m2 / (n1 x n2 x w1 x w2) - Secondary 2 PLL Output Clock(s) EQ 4-8 In the example, the final output frequency (foutput) from the primary output of the second PLL will be as follows (EQ 4-9): foutput = fGLA2 = fGLA x m2 / (n2 x u2) = 256 MHz x 70 / (64 x 1) = 280 MHz EQ 4-9 Figure 4-35 on page 4-49 shows the settings of the second PLL. When configuring the second PLL (or any subsequent-stage PLLs), specify the input to be Core Logic-Driven. This generates a netlist with the second PLL routed internally from the core. Do not specify the input to be Hardwired I/O- Driven or External I/O-Driven, as these options prohibit the connection from the output of the first PLL to the input of the second PLL. 4 -4 8 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Figure 4-35 * Second-Stage PLL Showing Input of 256 MHz from First Stage and Final Output of 280 MHz Figure 4-36 shows the simulation results, where the first PLL's output period is 3.9 ns (~256 MHz), and the stage 2 (final) output period is 3.56 ns (~280 MHz). Stage 1 Output Clock Period Stage 2 Output Clock Period Figure 4-36 * ModelSim Simulation Results v1.4 4 - 49 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Recommended Board-Level Considerations The power to the PLL core is supplied by VCCPLA/B/C/D/E/F (VCCPLx) , and the associated ground connections are supplied by VCOMPLA/B/C/D/E/F (VCOMPLx). When the PLLs are not used, the Actel Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Optionally, the PLL can be turned on/off during normal device operation via the POWERDOWN port (see Table 4-3 on page 4-8). PLL Power Supply Decoupling Scheme The PLL core is designed to tolerate noise levels on the PLL power supply as specified in the datasheets. When operated within the noise limits, the PLL will meet the output peak-to-peak jitter specifications specified in the datasheets. User applications should always ensure the PLL power supply is powered from a noise-free or low-noise power source. However, in situations where the PLL power supply noise level is higher than the tolerable limits, various decoupling schemes can be designed to suppress noise to the PLL power supply. An example is provided in Figure 4-37. The VCCPLx and VCOMPLx pins correspond to the PLL analog power supply and ground. Actel strongly recommends that two ceramic capacitors (10 nF in parallel with 100 nF) be placed close to the power pins (less than 1 inch away). A third generic 10 F electrolytic capacitor is recommended for low-frequency noise and should be placed farther away due to its large physical size. Actel recommends that a 6.8 H inductor be placed between the supply source and the capacitors to filter out any low-/medium- and high-frequency noise. In addition, the PCB layers should be controlled so the VCCPLx and VCOMPLx planes have the minimum separation possible, thus generating a good-quality RF capacitor. For more recommendations, refer to the Board-Level Considerations application note. Recommended 100 nF capacitor: * Producer BC Components, type X7R, 100 nF, 16 V * BC Components part number: 0603B104K160BT * Digi-Key part number: BC1254CT-ND * Digi-Key part number: BC1254TR-ND Recommended 10 nF capacitor: * Surface-mount ceramic capacitor * Producer BC Components, type X7R, 10 nF, 50 V * BC Components part number: 0603B103K500BT * Digi-Key part number: BC1252CT-ND * Digi-Key part number: BC1252TR-ND VCCPLx IGLOO/e or ProASIC3/E Device 10 nF 100 nF 10 F Power Supply VCOMPLx Figure 4-37 * Decoupling Scheme for One PLL (should be replicated for each PLL used) 4 -5 0 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Conclusion The advanced CCCs of the IGLOO and ProASIC3 devices are ideal for applications requiring precise clock management. They integrate easily with the internal low-skew clock networks and provide flexible frequency synthesis, clock deskewing, and/or time-shifting operations. Related Documents Application Notes Board-Level Considerations http://www.actel.com/documents/BoardLevelCons_AN.pdf Handbook Documents UJTAG Applications in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_UJTAG_HBs.pdf Global Resources in Actel Low-Power Flash Devices http://www.actel.com/documents/LPD_Global_HBs.pdf User I/O Naming Conventions in I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf User's Guides IGLOO, Fusion, and ProASIC3 Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-006-4 Revised December 2008 v1.4 4 - 51 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.3 (October 2008) v1.2 (June 2008) Changes in the Current Version (v1.4) Page The"CCC Support in Actel's Flash Devices" section was updated to include IGLOO nano and ProASIC3 nano devices. 4-3 Figure 4-2 * CCC Options: Global Buffers with No Programmable Delay was revised to add the CLKBIBUF macro. 4-4 The description of the reference clock was revised in Table 4-2 * Input and Output Description of the CLKDLY Macro. 4-5 Figure 4-6 * Clock Input Sources (30 k gates devices and below) is new. Figure 4-7 * Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT (60 k gates devices and above) applies to 60 k gate devices and above. 4-11 The "IGLOO and ProASIC3" section was updated to include information for IGLOO nano devices. 4-12 A note regarding Fusion CCCs was added to Figure 4-8 * Illustration of Hardwired I/O (global input pins) Usage for IGLOO and ProASIC3 devices 60 k Gates and Larger and the name of the figure was changed from Figure 4-8 * Illustration of Hardwired I/O (global input pins) Usage. Figure 4-9 * Illustration of Hardwired I/O (global input pins) Usage for IGLOO and ProASIC3 devices 30 k Gates and Smaller is new. 4-13 Table 4-5 * Number of CCCs by Device Size and Package was updated to include IGLOO nano and ProASIC3 nano devices. Entries were added to note differences for the CS81, CS121, and CS201 packages. 4-17 The "Clock Conditioning Circuits without Integrated PLLs" section was rewritten. 4-18 The "IGLOO and ProASIC3 CCC Locations" section was updated for nano devices. 4-20 Figure 4-13 * CCC Locations in the 15 k and 30 k Gate Devices was deleted. 4-20 This document was updated to include Fusion and RT ProASIC3 device information. Please review the document very carefully. N/A The "CCC Support in Actel's Flash Devices" section was updated. 4-3 In the "Global Buffer with Programmable Delay" section, the following sentence was changed from: 4-4 "In this case, the I/O must be placed in one of the dedicated global I/O locations." To "In this case, the software will automatically place the dedicated global I/O in the appropriate locations." 4 -5 2 Figure 4-4 * CCC Options: Global Buffers with PLL was updated to include OADIVRST and OADIVHALF. 4-7 In Figure 4-5 * CCC with PLL Block "fixed delay" was changed to "programmable delay". 4-7 Table 4-3 * Input and Output Signals of the PLL Block was updated to include OADIVRST and OADIVHALF descriptions. 4-8 Table 4-7 * Configuration Bit Descriptions for the CCC Blocks was updated to include configuration bits 88 to 81. Note 2 is new. In addition, the description for bit <76:74> was updated. 4-28 Table 4-15 * Fusion Dynamic CCC Clock Source Selection and Table 4-16 * Fusion Dynamic CCC NGMUX Configuration are new. 4-32 v1.4 Clock Conditioning Circuits in Low-Power Flash Devices and Mixed-Signal FPGAs Previous Version Changes in the Current Version (v1.4) Page v1.2 (continued) Table 4-17 * Fusion Dynamic CCC Division by Half Configuration and Table 4-18 * Configuration Bit <76:75> / VCOSEL<2:1> Selection for All Families are new. 4-33 v1.1 (March 2008) The following changes were made to the family descriptions Table 4-1 * Overview of the CCCs Offered in Fusion, IGLOO, and ProASIC3: in 4-1 Table 4-1 * Flash-Based FPGAs and the associated text were updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 4-3 The "Global Input Selections" section was updated to include 15 k gate devices as supported I/O types for globals, for CCC only. 4-10 Table 4-5 * Number of CCCs by Device Size and Package was revised to include ProASIC3L, IGLOO PLUS, A3P015, AGL015, AGLP030, AGLP060, and AGLP125. 4-17 The "IGLOO and ProASIC3 CCC Locations" section was revised to include 15 k gate devices in the exception statements, as they do not contain PLLs. 4-20 Information about unlocking the PLL was removed from the "Dynamic PLL Configuration" section. 4-26 In the "Dynamic PLL Configuration" section, information was added about running Layout and determining the exact setting of the ports. 4-38 In Table 4-7 * Configuration Bit Descriptions for the CCC Blocks, the following bits were updated to delete "transport to the user" and reference the footnote at the bottom of the table: 79 to 71. 4-28 * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. v1.0 (January 2008) 51900133-0/5.06 v1.4 4 - 53 Embedded Memories 5 - FlashROM in Actel's Low-Power Flash Devices Introduction The Fusion, IGLOO,(R) and ProASIC(R)3 families of low-power flash-based devices have a dedicated nonvolatile FlashROM memory of 1,024 bits, which provides a unique feature in the FPGA market. The FlashROM can be read, modified, and written using the JTAG (or UJTAG) interface. It can be read but not modified from the FPGA core. Only low-power flash devices contain on-chip user nonvolatile memory (NVM). Architecture of User Nonvolatile FlashROM Low-power flash devices have 1 kbit of user-accessible nonvolatile flash memory on-chip that can be read from the FPGA core fabric. The FlashROM is arranged in eight banks of 128 bits (16 bytes) during programming. The 128 bits in each bank are addressable as 16 bytes during the read-back of the FlashROM from the FPGA core. Figure 5-1 shows the FlashROM logical structure. The FlashROM can only be programmed via the IEEE 1532 JTAG port. It cannot be programmed directly from the FPGA core. When programming, each of the eight 128-bit banks can be selectively reprogrammed. The FlashROM can only be reprogrammed on a bank boundary. Programming involves an automatic, on-chip bank erase prior to reprogramming the bank. The FlashROM supports synchronous read. The address is latched on the rising edge of the clock, and the new output data is stable after the falling edge of the same clock cycle. For more information, refer to the timing diagrams in the DC and Switching Characteristics chapter of the appropriate datasheet. The FlashROM can be read on byte boundaries. The upper three bits of the FlashROM address from the FPGA core define the bank being accessed. The lower four bits of the FlashROM address from the FPGA core define which of the 16 bytes in the bank is being accessed. Byte Number in Bank Bank Number 3 MSB of ADDR (READ) 15 14 13 12 11 4 LSB of ADDR (READ) 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 5-1 * FlashROM Architecture v1.4 5-1 FlashROM in Actel's Low-Power Flash Devices FlashROM Support in Flash-Based Devices The flash FPGAs listed in Table 5-1 support the FlashROM feature and the functions described in this document. Table 5-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 5-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 5-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 5 -2 v1.4 FlashROM in Actel's Low-Power Flash Devices Bank 0 Bank 1 CCC SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block OSC I/Os CCC/PLL VersaTile Bank 4 Bank 2 User Nonvolatile FlashROM ISP AES Decryption Flash Memory Blocks Analog Quad Analog Quad Analog Quad Analog Quad Charge Pumps ADC Analog Quad Analog Quad SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Flash Memory Blocks Analog Quad Analog Quad Analog Quad Analog Quad CCC Bank 3 Figure 5-2 * Fusion Device Architecture Overview (AFS600) CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block ISP AES Decryption Nonvolatile Memory FlashROM Charge Pumps Figure 5-3 * ProASIC3 and IGLOO Device Architecture v1.4 5-3 FlashROM in Actel's Low-Power Flash Devices FlashROM Applications The SmartGen core generator is used to configure FlashROM content. You can configure each page independently. SmartGen enables you to create and modify regions within a page; these regions can be 1 to 16 bytes long (Figure 5-4). Page Number 15 14 13 12 Byte Number in Page 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 5-4 * FlashROM Configuration The FlashROM content can be changed independently of the FPGA core content. It can be easily accessed and programmed via JTAG, depending on the security settings of the device. The SmartGen core generator enables each region to be independently updated (described in the "Programming and Accessing FlashROM" section on page 5-6). This enables you to change the FlashROM content on a per-part basis while keeping some regions "constant" for all parts. These features allow the FlashROM to be used in diverse system applications. Consider the following possible uses of FlashROM: 5 -4 * Internet protocol (IP) addressing (wireless or fixed) * System calibration settings * Restoring configuration after unpredictable system power-down * Device serialization and/or inventory control * Subscription-based business models (e.g., set-top boxes) * Secure key storage * Asset management tracking * Date stamping * Version management v1.4 FlashROM in Actel's Low-Power Flash Devices FlashROM Security Low-power flash devices have an on-chip Advanced Encryption Standard (AES) decryption core, combined with an enhanced version of the Actel flash-based lock technology (FlashLock(R)). Together, they provide unmatched levels of security in a programmable logic device. This security applies to both the FPGA core and FlashROM content. These devices use the 128-bit AES (Rijndael) algorithm to encrypt programming files for secure transmission to the on-chip AES decryption core. The same algorithm is then used to decrypt the programming file. This key size provides approximately 3.4 x 1038 possible 128-bit keys. A computing system that could find a DES key in a second would take approximately 149 trillion years to crack a 128-bit AES key. The 128-bit FlashLock feature in low-power flash devices works via a FlashLock security Pass Key mechanism, where the user locks or unlocks the device with a user-defined key. Refer to Security in Low-Power Flash Devices. If the device is locked with certain security settings, functions such as device read, write, and erase are disabled. This unique feature helps to protect against invasive and noninvasive attacks. Without the correct Pass Key, access to the FPGA is denied. To gain access to the FPGA, the device first must be unlocked using the correct Pass Key. During programming of the FlashROM or the FPGA core, you can generate the security header programming file, which is used to program the AES key and/or FlashLock Pass Key. The security header programming file can also be generated independently of the FlashROM and FPGA core content. The FlashLock Pass Key is not stored in the FlashROM. Low-power flash devices with AES-based security allow for secure remote field updates over public networks such as the Internet, and ensure that valuable intellectual property (IP) remains out of the hands of IP thieves. Figure 5-5 shows this flow diagram. Programming Data Flash Device FlashROM FPGA Core AES Encryption Same AES Key AES-128 Decryption Core Untrusted Medium Encrypted Data Encrypted Data Figure 5-5 * Programming FlashROM Using AES v1.4 5-5 FlashROM in Actel's Low-Power Flash Devices Programming and Accessing FlashROM The FlashROM content can only be programmed via JTAG, but it can be read back selectively through the JTAG programming interface, the UJTAG interface, or via direct FPGA core addressing. The pages of the FlashROM can be made secure to prevent read-back via JTAG. In that case, readback on these secured pages is only possible by the FPGA core fabric or via UJTAG. A 7-bit address from the FPGA core defines which of the eight pages (three MSBs) is being read, and which of the 16 bytes within the selected page (four LSBs) are being read. The FlashROM content can be read on a random basis; the access time is 10 ns for a device supporting commercial specifications. The FPGA core will be powered down during writing of the FlashROM content. FPGA power-down during FlashROM programming is managed on-chip, and FPGA core functionality is not available during programming of the FlashROM. Table 5-2 summarizes various FlashROM access scenarios. Table 5-2 * FlashROM Read/Write Capabilities by Access Mode Access Mode FlashROM Read FlashROM Write JTAG Yes Yes UJTAG Yes No FPGA core Yes No Figure 5-6 shows the accessing of the FlashROM using the UJTAG macro. This is similar to FPGA core access, where the 7-bit address defines which of the eight pages (three MSBs) is being read and which of the 16 bytes within the selected page (four LSBs) are being read. Refer to UJTAG Applications in Actel's Low-Power Flash Devices for details on using the UJTAG macro to read the FlashROM. Figure 5-7 on page 5-7 and Figure 5-8 on page 5-7 show the FlashROM access from the JTAG port. The FlashROM content can be read on a random basis. The three-bit address defines which page is being read or updated. UJTAG Address Generation and Data Serialization UIREG [7:0] Enable FlashROM RESET TDO TDI URSTB UDRUPD UDRCK TMS TCK TRST UDRCAP UDRSH Control CLK SDI Addr [6:0] Addr [6:0] Data [7:0] Data[7:0] SDO UTDI UTDO Figure 5-6 * Block Diagram of Using UJTAG to Read FlashROM Contents 5 -6 v1.4 FlashROM in Actel's Low-Power Flash Devices 7-Bit Address from Core 1110000 7 6 5 3 MSB of ADDR (READ) 3-Bit Page Address Word Number in Page Page Number 111 4-Bit Word Address 0000 4 3 2 1 0 15 14 13 12 11 4 LSB of ADDR (READ) 10 9 8 7 6 5 4 3 2 1 0 8-Bit Data 8-Bit Data to FPGA Core 8-Bit Data from Page 7 Word 0 Figure 5-7 * Accessing FlashROM Using FPGA Core ...........................00001:128 Bit Data To/From JTAG Interface 4-Bit Page Address from JTAG Interface Page Number Word Number in Page 15 14 13 12 11 4 LSB of ADDR (READ) 10 9 8 7 6 5 4 3 2 1 0 3 MSB of ADDR (READ) 7 6 5 4 3 2 1 0 Figure 5-8 * Accessing FlashROM Using JTAG Port v1.4 5-7 FlashROM in Actel's Low-Power Flash Devices FlashROM Design Flow The Actel Libero(R) Integrated Design Environment (IDE) software has extensive FlashROM support, including FlashROM generation, instantiation, simulation, and programming. Figure 5-9 shows the user flow diagram. In the design flow, there are three main steps: 1. FlashROM generation and instantiation in the design 2. Simulation of FlashROM design 3. Programming file generation for FlashROM design SmartGen UFC File FlashROM Netlist User Design MEM File Simulator Synthesis User Netlist BackAnnotated Netlist Designer Core Map Security Header Options FlashPoint Programmer Programming Files Figure 5-9 * FlashROM Design Flow 5 -8 v1.4 FlashROM in Actel's Low-Power Flash Devices FlashROM Generation and Instantiation in the Design The SmartGen core generator, available in Libero IDE and Designer, is the only tool that can be used to generate the FlashROM content. SmartGen has several user-friendly features to help generate the FlashROM contents. Instead of selecting each byte and assigning values, you can create a region within a page, modify the region, and assign properties to that region. The FlashROM user interface, shown in Figure 5-10 on page 5-9, includes the configuration grid, existing regions list, and properties field. The properties field specifies the region-specific information and defines the data used for that region. You can assign values to the following properties: 1. Static Fixed Data--Enables you to fix the data so it cannot be changed during programming time. This option is useful when you have fixed data stored in this region, which is required for the operation of the design in the FPGA. Key storage is one example. 2. Static Modifiable Data--Select this option when the data in a particular region is expected to be static data (such as a version number, which remains the same for a long duration but could conceivably change in the future). This option enables you to avoid changing the value every time you enter new data. 3. Read from File--This provides the full flexibility of FlashROM usage to the customer. If you have a customized algorithm for generating the FlashROM data, you can specify this setting. You can then generate a text file with data for as many devices as you wish to program, and load that into the FlashPoint programming file generation software to get programming files that include all the data. SmartGen will optionally pass the location of the file where the data is stored if the file is specified in SmartGen. Each text file has only one type of data format (binary, decimal, hex, or ASCII text). The length of each data file must be shorter than or equal to the selected region length. If the data is shorter than the selected region length, the most significant bits will be padded with 0s. For multiple text files for multiple regions, the first lines are for the first device. In SmartGen, Load Sim. Value From File allows you to load the first device data in the MEM file for simulation. 4. Auto Increment/Decrement--This scenario is useful when you specify the contents of FlashROM for a large number of devices in a series. You can specify the step value for the serial number and a maximum value for inventory control. During programming file generation, the actual number of devices to be programmed is specified and a start value is fed to the software. Figure 5-10 * SmartGen GUI of the FlashROM v1.4 5-9 FlashROM in Actel's Low-Power Flash Devices SmartGen allows you to generate the FlashROM netlist in VHDL, Verilog, or EDIF format. After the FlashROM netlist is generated, the core can be instantiated in the main design like other SmartGen cores. Note that the macro library name for FlashROM is UFROM. The following is a sample FlashROM VHDL netlist that can be instantiated in the main design: library ieee; use ieee.std_logic_1164.all; library fusion; entity FROM_a is port( ADDR : in std_logic_vector(6 downto 0); DOUT : out std_logic_vector(7 downto 0)); end FROM_a; architecture DEF_ARCH of FROM_a is component UFROM generic (MEMORYFILE:string); port(DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7 : out std_logic; ADDR0, ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR6 : in std_logic := 'U') ; end component; component GND port( Y : out std_logic); end component; signal U_7_PIN2 : std_logic ; begin GND_1_net : GND port map(Y => U_7_PIN2); UFROM0 : UFROM generic map(MEMORYFILE => "FROM_a.mem") port map(DO0 => DOUT(0), DO1 => DOUT(1), DO2 => DOUT(2), DO3 => DOUT(3), DO4 => DOUT(4), DO5 => DOUT(5), DO6 => DOUT(6), DO7 => DOUT(7), ADDR0 => ADDR(0), ADDR1 => ADDR(1), ADDR2 => ADDR(2), ADDR3 => ADDR(3), ADDR4 => ADDR(4), ADDR5 => ADDR(5), ADDR6 => ADDR(6)); end DEF_ARCH; SmartGen generates the following files along with the netlist. These are located in the SmartGen folder for the Libero IDE project. 1. MEM (Memory Initialization) file 2. UFC (User Flash Configuration) file 3. Log file The MEM file is used for simulation, as explained in the "Simulation of FlashROM Design" section. The UFC file, generated by SmartGen, has the FlashROM configuration for single or multiple devices and is used during STAPL generation. It contains the region properties and simulation values. Note that any changes in the MEM file will not be reflected in the UFC file. Do not modify the UFC to change FlashROM content. Instead, use the SmartGen GUI to modify the FlashROM content. See the "Programming File Generation for FlashROM Design" section on page 5-11 for a description of how the UFC file is used during the programming file generation. The log file has information regarding the file type and file location. 5 -1 0 v1.4 FlashROM in Actel's Low-Power Flash Devices Simulation of FlashROM Design The MEM file has 128 rows of 8 bits, each representing the contents of the FlashROM used for simulation. For example, the first row represents page 0, byte 0; the next row is page 0, byte 1; and so the pattern continues. Note that the three MSBs of the address define the page number, and the four LSBs define the byte number. So, if you send address 0000100 to FlashROM, this corresponds to the page 0 and byte 4 location, which is the fifth row in the MEM file. SmartGen defaults to 0s for any unspecified location of the FlashROM. Besides using the MEM file generated by SmartGen, you can create a binary file with 128 rows of 8 bits each and use this as a MEM file. Actel recommends that you use different file names if you plan to generate multiple MEM files. During simulation, Libero IDE passes the MEM file used as the generic file in the netlist, along with the design files and testbench. If you want to use different MEM files during simulation, you need to modify the generic file reference in the netlist. ..................... UFROM0: UFROM --generic map(MEMORYFILE => "F:\Appsnotes\FROM\test_designs\testa\smartgen\FROM_a.mem") --generic map(MEMORYFILE => "F:\Appsnotes\FROM\test_designs\testa\smartgen\FROM_b.mem") ......................... The VITAL and Verilog simulation models accept the generics passed by the netlist, read the MEM file, and perform simulation with the data in the file. Programming File Generation for FlashROM Design FlashPoint is the programming software used to generate the programming files for flash devices. Depending on the applications, you can use the FlashPoint software to generate a STAPL file with different FlashROM contents. In each case, optional AES decryption is available. To generate a STAPL file that contains the same FPGA core content and different FlashROM contents, the FlashPoint software needs an Array Map file for the core and UFC file(s) for the FlashROM. This final STAPL file represents the combination of the logic of the FPGA core and FlashROM content. FlashPoint generates the STAPL files you can use to program the desired FlashROM page and/or FPGA core of the FPGA device contents. FlashPoint supports the encryption of the FlashROM content and/or FPGA Array configuration data. In the case of using the FlashROM for device serialization, a sequence of unique FlashROM contents will be generated. When generating a programming file with multiple unique FlashROM contents, you can specify in FlashPoint whether to include all FlashROM content in a single STAPL file or generate a different STAPL file for each FlashROM (Figure 5-11). The programming software (FlashPro) handles the single STAPL file that contains the FlashROM content from multiple devices. It enables you to program the FlashROM content into a series of devices sequentially (Figure 5-11). See the FlashPro User's Guide for information on serial programming. UFC File for Single FlashROM Contents FPGA Array Map File UFC File for Multiple FlashROM Contents FPGA Array Map File FlashPoint FlashPoint Security Settings Security Settings Single STAPL File Single STAPL File Single STAPL File Figure 5-11 * Single or Multiple Programming File Generation v1.4 5 - 11 FlashROM in Actel's Low-Power Flash Devices Figure 5-12 shows the programming file generator, which enables different STAPL file generation methods. When you select Program FlashROM and choose the UFC file, the FlashROM Settings window appears, as shown in Figure 5-13. In this window, you can select the FlashROM page you want to program and the data value for the configured regions. This enables you to use a different page for different programming files. Figure 5-12 * Programming File Generator Figure 5-13 * Setting FlashROM during Programming File Generation The programming hardware and software can load the FlashROM with the appropriate STAPL file. Programming software handles the single STAPL file that contains multiple FlashROM contents for multiple devices, and programs the FlashROM in sequential order (e.g., for device serialization). 5 -1 2 v1.4 FlashROM in Actel's Low-Power Flash Devices This feature is supported in the programming software. After programming with the STAPL file, you can run DEVICE_INFO to check the FlashROM content. DEVICE_INFO displays the FlashROM content, serial number, Design Name, and checksum, as shown below: EXPORT IDCODE[32] = 123261CF EXPORT SILSIG[32] = 00000000 User information : CHECKSUM: 61A0 Design Name: TOP Programming Method: STAPL Algorithm Version: 1 Programmer: UNKNOWN ========================================= FlashROM Information : EXPORT Region_7_0[128] = FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ========================================= Security Setting : Encrypted FlashROM Programming Enabled. Encrypted FPGA Array Programming Enabled. ========================================= The Libero IDE file manager recognizes the UFC and MEM files and displays them in the appropriate view. Libero IDE also recognizes the multiple programming files if you choose the option to generate multiple files for multiple FlashROM contents in Designer. These features enable a user-friendly flow for the FlashROM generation and programming in Libero IDE. Custom Serialization Using FlashROM You can use FlashROM for device serialization or inventory control by using the Auto Inc region or Read From File region. FlashPoint will automatically generate the serial number sequence for the Auto Inc region with the Start Value, Max Value, and Step Value provided. If you have a unique serial number generation scheme that you prefer, the Read From File region allows you to import the file with your serial number scheme programmed into the region. See the FlashPro User's Guide for custom serialization file format information. The following steps describe how to perform device serialization or inventory control using FlashROM: 1. Generate FlashROM using SmartGen. From the Properties section in the FlashROM Settings dialog box, select the Auto Inc or Read From File region. For the Auto Inc region, specify the desired step value. You will not be able to modify this value in the FlashPoint software. 2. Go through the regular design flow and finish place-and-route. 3. Select Programming File in Designer and open Generate Programming File (Figure 5-12 on page 5-12). 4. Click Program FlashROM, browse to the UFC file, and click Next. The FlashROM Settings window appears, as shown in Figure 5-13 on page 5-12. 5. Select the FlashROM page you want to program and the data value for the configured regions. The STAPL file generated will contain only the data that targets the selected FlashROM page. 6. Modify properties for the serialization. - For the Auto Inc region, specify the Start and Max values. - For the Read From File region, select the file name of the custom serialization file. 7. Select the FlashROM programming file type you want to generate from the two options below: - Single programming file for all devices: generates one programming file with all FlashROM values. - One programming file per device: generates a separate programming file for each FlashROM value. v1.4 5 - 13 FlashROM in Actel's Low-Power Flash Devices 8. Enter the number of devices you want to program and generate the required programming file. 9. Open the programming software and load the programming file. The programming software, FlashPro3 and Silicon Sculptor II, supports the device serialization feature. If, for some reason, the device fails to program a part during serialization, the software allows you to reuse or skip the serial data. Refer to the FlashPro User's Guide for details. Conclusion The Fusion, IGLOO, and ProASIC3 families are the only FPGAs that offer on-chip FlashROM support. This document presents information on the FlashROM architecture, possible applications, programming, access through the JTAG and UJTAG interface, and integration into your design. In addition, the Libero IDE tool set enables easy creation and modification of the FlashROM content. The nonvolatile FlashROM block in the FPGA can be customized, enabling multiple applications. Additionally, the security offered by the low-power flash devices keeps both the contents of FlashROM and the FPGA design safe from system over-builders, system cloners, and IP thieves. Related Documents Handbook Documents Security in Low-Power Flash Devices www.actel.com/documents/LPD_Security_HBs.pdf UJTAG Applications in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_UJTAG_HBs.pdf User's Guides FlashPro User's Guide http://www.actel.com/documents/FlashPro_UG.pdf 5 -1 4 v1.4 FlashROM in Actel's Low-Power Flash Devices Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-007-4 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.4) Page v1.3 (October 2008) IGLOO nano and ProASIC3 nano devices were added to Table 5-1 * Flash-Based FPGAs. 5-2 v1.2 (June 2008) The "FlashROM Support in Flash-Based Devices" section was revised to include new families and make the information more concise. 5-2 Figure 5-2 * Fusion Device Architecture Overview (AFS600) was replaced. Figure 5-5 * Programming FlashROM Using AES was revised to change "Fusion" to "Flash Device." 5-3, 5-5 The FlashPoint User's Guide was removed from the "User's Guides" section, as its content is now part of the FlashPro User's Guide. 5-14 The following changes were Table 5-1 * Flash-Based FPGAs: in 5-2 The chapter was updated to include the IGLOO PLUS family and information regarding 15 k gate devices. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. N/A v1.1 (March 2008) v1.0 (January 2008) made to the family descriptions * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. v1.4 5 - 15 6 - SRAM and FIFO Memories in Actel's LowPower Flash Devices Introduction As design complexity grows, greater demands are placed upon an FPGA's embedded memory. Actel Fusion,(R) IGLOO,(R) and ProASIC(R)3 devices provide the flexibility of true dual-port and two-port SRAM blocks. The embedded memory, along with built-in, dedicated FIFO control logic, can be used to create cascading RAM blocks and FIFOs without using additional logic gates. IGLOO, IGLOO PLUS, and ProASIC3L FPGAs contain an additional feature that allows the device to be put in a low-power mode called Flash*Freeze. In this mode, the core draws minimal power (on the order of 2 to 127 W) and still retains values on the embedded SRAM/FIFO and registers. Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying power management and the use of SRAM/FIFOs. Device Architecture The low-power flash devices feature up to 504 kbits of RAM in 4,608-bit blocks (Figure 6-1 on page 6-2 and Figure 6-2 on page 6-3). The total embedded SRAM for each device can be found in the datasheets. These memory blocks are arranged along the top and bottom of the device to allow better access from the core and I/O (in some devices, they are only available on the north side of the device). Every RAM block has a flexible, hardwired, embedded FIFO controller, enabling the user to implement efficient FIFOs without sacrificing user gates. In the IGLOO and ProASIC3 families of devices, the following memories are supported: * 30 k gate devices and smaller do not support SRAM and FIFO. * 60 k and 125 k gate devices support memories on the north side of the device only. * 250 k devices and larger support memories on the north and south sides of the device. In Fusion devices, the following memories are supported: * AFS090 and AFS250 support memories on the north side of the device only. * AFS600 and AFS1500 support memories on the north and south sides of the device. v1.5 6-1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption 1 User Nonvolatile FlashRom Flash*Freeze Technology 2 Charge Pumps Bank 2 Notes: 1. AES decryption not supported in 30 k gate devices and smaller. 2. Flash*Freeze is supported in all IGLOO devices and the ProASIC3L devices. Figure 6-1 * IGLOO and ProASIC3 Device Architecture Overview 6 -2 v1.5 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block SRAM and FIFO Memories in Actel's Low-Power Flash Devices Bank 1 Bank 0 CCC/PLL RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block OSC I/Os CCC VersaTile Bank 4 Bank 2 ISP AES Decryption User Nonvolatile FlashROM (FROM) Flash Array Analog Quad Analog Quad Analog Quad Charge Pumps ADC Analog Quad Analog Quad Analog Quad RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Flash Array Analog Quad Analog Quad Analog Quad Analog Quad Bank 3 Figure 6-2 * Fusion Device Architecture Overview (AFS600) v1.5 6-3 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SRAM/FIFO Support in Flash-Based Devices The flash FPGAs listed in Table 6-1 support SRAM and FIFO blocks and the functions described in this document. Table 6-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 6-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 6-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 6 -4 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SRAM and FIFO Architecture To meet the needs of high-performance designs, the memory blocks operate strictly in synchronous mode for both read and write operations. The read and write clocks are completely independent, and each can operate at any desired frequency up to 250 MHz. * 4kx1, 2kx2, 1kx4, 512x9 (dual-port RAM--2 read / 2 write or 1 read / 1 write) * 512x9, 256x18 (2-port RAM--1 read / 1 write) * Sync write, sync pipelined / nonpipelined read Automotive ProASIC3 devices support single-port SRAM capabilities or dual-port SRAM only under specific conditions. Dual-port mode is supported if the clocks to the two SRAM ports are the same and 180 out of phase (i.e., the port A clock is the inverse of the port B clock). The Actel Libero(R) Integrated Design Environment (IDE) software macro libraries support a dual-port macro only. For use of this macro as a single-port SRAM, the inputs and clock of one port should be tied off (grounded) to prevent errors during design compile. For use in dual-port mode, the same clock with an inversion between the two clock pins of the macro should be used in the design to prevent errors during compile. The memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY). Simultaneous dual-port read/write and write/write operations at the same address are allowed when certain timing requirements are met. During RAM operation, addresses are sourced by the user logic, and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. The low-power flash device architecture enables the read and write sizes of RAMs to be organized independently, allowing for bus conversion. For example, the write size can be set to 256x18 and the read size to 512x9. Both the write width and read width for the RAM blocks can be specified independently with the WW (write width) and RW (read width) pins. The different DxW configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1. When widths of one, two, or four are selected, the ninth bit is unused. For example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. The RAM blocks employ little-endian byte order for read and write operations. Memory Blocks and Macros Memory blocks can be configured with many different aspect ratios, but are generically supported in the macro libraries as one of two memory elements: RAM4K9 or RAM512X18. The RAM4K9 is configured as a true dual-port memory block, and the RAM512X18 is configured as a two-port memory block. Dual-port memory allows the RAM to both read from and write to either port independently. Two-port memory allows the RAM to read from one port and write to the other using a common clock or independent read and write clocks. If needed, the RAM4K9 blocks can be configured as two-port memory blocks. The memory block can be configured as a FIFO by combining the basic memory block with dedicated FIFO controller logic. The FIFO macro is named FIFO4KX18 (Figure 6-3 on page 6-6). Clocks for the RAM blocks can be driven by the VersaNet (global resources) or by regular nets. When using local clock segments, the clock segment region that encompasses the RAM blocks can drive the RAMs. In the dual-port configuration (RAM4K9), each memory block port can be driven by either rising-edge or falling-edge clocks. Each port can be driven by clocks with different edges. Though only a rising-edge clock can drive the physical block itself, the Actel Designer software will automatically bubble-push the inversion to properly implement the falling-edge trigger for the RAM block. v1.5 6-5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices RAM512x18 RAM4K9 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB0 DOUTB0 DINB8 DINB7 RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL0 AFVAL11 AFVAL10 REN RCLK DOUTB8 DOUTB7 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 PIPE ADDRB11 ADDRB10 FIFO4K18 AFVAL0 WADDR8 WADDR7 REN RBLK RCLK WADDR0 WD17 WD16 WD17 WD16 WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WD0 WW1 WW0 WEN WBLK WCLK RPIPE WEN WCLK RESET RESET Note: Automotive ProASIC3 devices restrict RAM4K9 to a single port or to dual ports with the same clock 180 out of phase (inverted) between clock pins. In single-port mode, inputs to port B should be tied to ground to prevent errors during compile. For FIFO4K18, the same clock 180 out of phase (inverted) between clock pins should be used. Figure 6-3 * Supported Basic RAM Macros 6 -6 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SRAM Features RAM4K9 Macro RAM4K9 is the dual-port configuration of the RAM block (Figure 6-4). The RAM4K9 nomenclature refers to both the deepest possible configuration and the widest possible configuration the dualport RAM block can assume, and does not denote a possible memory aspect ratio. The RAM block can be configured to the following aspect ratios: 4,096x1, 2,048x2, 1,024x4, and 512x9. RAM4K9 is fully synchronous and has the following features: * Two ports that allow fully independent reads and writes at different frequencies * Selectable pipelined or nonpipelined read * Active-low block enables for each port * Toggle control between read and write mode for each port * Active-low asynchronous reset * Pass-through write data or hold existing data on output. In pass-through mode, the data written to the write port will immediately appear on the read port. * Designer software will automatically facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. DINA DOUTA ADDRA BLKA WENA CLKA Write Data Write Data Read Data Read Data Address Address RAM4K9 BLK BLK WEN WEN CLK CLK DINB DOUTB ADDRB BLKB WENB CLKB Reset Note: For timing diagrams of the RAM signals, refer to the appropriate family datasheet. Figure 6-4 * RAM4K9 Simplified Configuration Signal Descriptions for RAM4K9 Note: Automotive ProASIC3 devices support single-port SRAM capabilities, or dual-port SRAM only under specific conditions. Dual-port mode is supported if the clocks to the two SRAM ports are the same and 180 out of phase (i.e., the port A clock is the inverse of the port B clock). Since Actel Libero IDE macro libraries support a dual-port macro only, certain modifications must be made. These are detailed below. The following signals are used to configure the RAM4K9 memory element: WIDTHA and WIDTHB These signals enable the RAM to be configured in one of four allowable aspect ratios (Table 6-2 on page 6-8). Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, WIDTHB should be tied to ground. v1.5 6-7 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Table 6-2 * Allowable Aspect Ratio Settings for WIDTHA[1:0] WIDTHA[1:0] WIDTHB[1:0] DxW 00 00 4kx1 01 01 2kx2 10 10 1kx4 11 11 512x9 Note: The aspect ratio settings are constant and cannot be changed on the fly. BLKA and BLKB These signals are active-low and will enable the respective ports when asserted. When a BLKx signal is deasserted, that port's outputs hold the previous value. Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, BLKB should be tied to ground. WENA and WENB These signals switch the RAM between read and write modes for the respective ports. A LOW on these signals indicates a write operation, and a HIGH indicates a read. Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, WENB should be tied to ground. CLKA and CLKB These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver. Note: For Automotive ProASIC3 devices, dual-port mode is supported if the clocks to the two SRAM ports are the same and 180 out of phase (i.e., the port A clock is the inverse of the port B clock). For use of this macro as a single-port SRAM, the inputs and clock of one port should be tied off (grounded) to prevent errors during design compile. PIPEA and PIPEB These signals are used to specify pipelined read on the output. A LOW on PIPEA or PIPEB indicates a nonpipelined read, and the data appears on the corresponding output in the same clock cycle. A HIGH indicates a pipelined read, and data appears on the corresponding output in the next clock cycle. Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, PIPEB should be tied to ground. For use in dual-port mode, the same clock with an inversion between the two clock pins of the macro should be used in the design to prevent errors during compile. WMODEA and WMODEB These signals are used to configure the behavior of the output when the RAM is in write mode. A LOW on these signals makes the output retain data from the previous read. A HIGH indicates passthrough behavior, wherein the data being written will appear immediately on the output. This signal is overridden when the RAM is being read. Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, WMODEB should be tied to ground. RESET This active-low signal resets the control logic, forces the output hold state registers to zero, disables reads and writes from the SRAM block, and clears the data hold registers when asserted. It does not reset the contents of the memory array. While the RESET signal is active, read and write operations are disabled. As with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. ADDRA and ADDRB These are used as read or write addresses, and they are 12 bits wide. When a depth of less than 4 k is specified, the unused high-order bits must be grounded (Table 6-3 on page 6-9). 6 -8 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, ADDRB should be tied to ground. Table 6-3 * Address Pins Unused/Used for Various Supported Bus Widths ADDRx DxW Unused Used 4kx1 None [11:0] 2kx2 [11] [10:0] 1kx4 [11:10] [9:0] 512x9 [11:9] [8:0] Note: The "x" in ADDRx implies A or B. DINA and DINB These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all configurations. When a data width less than nine is specified, unused high-order signals must be grounded (Table 6-4). Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, DINB should be tied to ground. DOUTA and DOUTB These are the nine-bit output data signals. Not all nine bits are valid in all configurations. As with DINA and DINB, high-order bits may not be used (Table 6-4). The output data on unused pins is undefined. Table 6-4 * Unused/Used Input and Output Data Pins for Various Supported Bus Widths DINx/DOUTx DxW Unused Used 4kx1 [8:1] [0] 2kx2 [8:2] [1:0] 1kx4 [8:4] [3:0] 512x9 None [8:0] Note: The "x" in DINx or DOUTx implies A or B. RAM512X18 Macro RAM512X18 is the two-port configuration of the same RAM block (Figure 6-5 on page 6-10). Like the RAM4K9 nomenclature, the RAM512X18 nomenclature refers to both the deepest possible configuration and the widest possible configuration the two-port RAM block can assume. In twoport mode, the RAM block can be configured to either the 512x9 aspect ratio or the 256x18 aspect ratio. RAM512X18 is also fully synchronous and has the following features: * Dedicated read and write ports * Active-low read and write enables * Selectable pipelined or nonpipelined read * Active-low asynchronous reset * Designer software will automatically facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. v1.5 6-9 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Write Data WD WADDR Read Data RD Write Address Read Address RADDR RAM512X18 WEN WCLK Write Enable Read Enable Write CLK Read CLK REN RCLK Reset Note: For timing diagrams of the RAM signals, refer to the appropriate family datasheet. Figure 6-5 * 512X18 Two-Port RAM Block Diagram Signal Descriptions for RAM512X18 RAM512X18 has slightly different behavior from RAM4K9, as it has dedicated read and write ports. WW and RW These signals enable the RAM to be configured in one of the two allowable aspect ratios (Table 6-5). Table 6-5 * Aspect Ratio Settings for WW[1:0] WW[1:0] RW[1:0] DxW 01 01 512x9 10 10 256x18 00, 11 Reserved 00, 11 WD and RD These are the input and output data signals, and they are 18 bits wide. When a 512x9 aspect ratio is used for write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for read, RD[17:9] are undefined. WADDR and RADDR These are read and write addresses, and they are nine bits wide. When the 256x18 aspect ratio is used for write or read, WADDR[8] and RADDR[8] are unused and must be grounded. WCLK and RCLK These signals are the write and read clocks, respectively. They can be clocked on the rising or falling edge of WCLK and RCLK. WEN and REN These signals are the write and read enables, respectively. They are both active-low by default. These signals can be configured as active-high. RESET This active-low signal resets the control logic, forces the output hold state registers to zero, disables reads and writes from the SRAM block, and clears the data hold registers when asserted. It does not reset the contents of the memory array. While the RESET signal is active, read and write operations are disabled. As with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. 6 -1 0 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices PIPE This signal is used to specify pipelined read on the output. A LOW on PIPE indicates a nonpipelined read, and the data appears on the output in the same clock cycle. A HIGH indicates a pipelined read, and data appears on the output in the next clock cycle. SRAM Usage The following descriptions refer to the usage of both RAM4K9 and RAM512X18. Clocking The dual-port SRAM blocks are only clocked on the rising edge. SmartGen allows falling-edgetriggered clocks by adding inverters to the netlist, hence achieving dual-port SRAM blocks that are clocked on either edge (rising or falling). For dual-port SRAM, each port can be clocked on either edge and by separate clocks by port. Note that for Automotive ProASIC3, the same clock, with an inversion between the two clock pins of the macro, should be used in design to prevent errors during compile. Low-power flash devices support inversion (bubble-pushing) throughout the FPGA architecture, including the clock input to the SRAM modules. Inversions added to the SRAM clock pin on the design schematic or in the HDL code will be automatically accounted for during design compile without incurring additional delay in the clock path. The two-port SRAM can be clocked on the rising or falling edge of WCLK and RCLK. If negative-edge RAM and FIFO clocking is selected for memory macros, clock edge inversion management (bubble-pushing) is automatically used within the development tools, without performance penalty. Modes of Operation There are two read modes and one write mode: * Read Nonpipelined (synchronous--1 clock edge): In the standard read mode, new data is driven onto the RD bus in the same clock cycle following RA and REN valid. The read address is registered on the read port clock active edge, and data appears at RD after the RAM access time. Setting PIPE to OFF enables this mode. * Read Pipelined (synchronous--2 clock edges): The pipelined mode incurs an additional clock delay from address to data but enables operation at a much higher frequency. The read address is registered on the read port active clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting PIPE to ON enables this mode. * Write (synchronous--1 clock edge): On the write clock active edge, the write data is written into the SRAM at the write address when WEN is HIGH. The setup times of the write address, write enables, and write data are minimal with respect to the write clock. RAM Initialization Each SRAM block can be individually initialized on power-up by means of the JTAG port using the UJTAG mechanism. The shift register for a target block can be selected and loaded with the proper bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single operation. FIFO Features The FIFO4KX18 macro is created by merging the RAM block with dedicated FIFO logic (Figure 6-6 on page 6-12). Since the FIFO logic can only be used in conjunction with the memory block, there is no separate FIFO controller macro. As with the RAM blocks, the FIFO4KX18 nomenclature does not refer to a possible aspect ratio, but rather to the deepest possible data depth and the widest possible data width. FIFO4KX18 can be configured into the following aspect ratios: 4,096x1, 2,048x2, 1,024x4, 512x9, and 256x18. In addition to being fully synchronous, the FIFO4KX18 also has the following features: * Four FIFO flags: Empty, Full, Almost-Empty, and Almost-Full * Empty flag is synchronized to the read clock * Full flag is synchronized to the write clock * Both Almost-Empty and Almost-Full flags have programmable thresholds v1.5 6 - 11 SRAM and FIFO Memories in Actel's Low-Power Flash Devices * Active-low asynchronous reset * Active-low block enable * Active-low write enable * Active-high read enable * Ability to configure the FIFO to either stop counting after the empty or full states are reached or to allow the FIFO counters to continue * Designer software will automatically facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. WD Write Data Full Flag FULL AFULL WEN WCLK Read Data RD Empty Flag Almost-Full Flag EMPTY Almost-Empty Flag FIFO4KX18 Write Enable Read Enable Write Clock AEMPTY REN Read Clock RCLK Reset Figure 6-6 * FIFO4KX18 Block Diagram RBLK REN RPIPE FREN FWEN RD RW[2:0] WW[2:0] RD[17:0] WD[17:0] RCLK WCLK RAM RADD[J:0] WADD[J:0] REN WEN WD RCLK WCLK CNT 12 E = ESTOP AFVAL FULL AFULL AEMPTY WBLK WEN CNT 12 SUB 12 AEVAL E = FSTOP EMPTY Reset Figure 6-7 * RAM Block with Embedded FIFO Controller The FIFOs maintain a separate read and write address. Whenever the difference between the write address and the read address is greater than or equal to the almost-full value (AFVAL), the AlmostFull flag is asserted. Similarly, the Almost-Empty flag is asserted whenever the difference between the write address and read address is less than or equal to the almost-empty value (AEVAL). 6 -1 2 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Due to synchronization between the read and write clocks, the Empty flag will deassert after the second read clock edge from the point that the write enable asserts. However, since the Empty flag is synchronized to the read clock, it will assert after the read clock reads the last data in the FIFO. Also, since the Full flag is dependent on the actual hardware configuration, it will assert when the actual physical implementation of the FIFO is full. For example, when a user configures a 128x18 FIFO, the actual physical implementation will be a 256x18 FIFO element. Since the actual implementation is 256x18, the Full flag will not trigger until the 256x18 FIFO is full, even though a 128x18 FIFO was requested. For this example, the AlmostFull flag can be used instead of the Full flag to signal when the 128th data word is reached. To accommodate different aspect ratios, the almost-full and almost-empty values are expressed in terms of data bits instead of data words. SmartGen translates the user's input, expressed in data words, into data bits internally. SmartGen allows the user to select the thresholds for the AlmostEmpty and Almost-Full flags in terms of either the read data words or the write data words, and makes the appropriate conversions for each flag. After the empty or full states are reached, the FIFO can be configured so the FIFO counters either stop or continue counting. For timing numbers, refer to the appropriate family datasheet. Signal Descriptions for FIFO4K18 The following signals are used to configure the FIFO4K18 memory element: WW and RW These signals enable the FIFO to be configured in one of the five allowable aspect ratios (Table 6-6). Table 6-6 * Aspect Ratio Settings for WW[2:0] WW[2:0] RW[2:0] DxW 000 000 4kx1 001 001 2kx2 010 010 1kx4 011 011 512x9 100 100 256x18 101, 110, 111 Reserved 101, 110, 111 WBLK and RBLK These signals are active-low and will enable the respective ports when LOW. When the RBLK signal is HIGH, that port's outputs hold the previous value. WEN and REN Read and write enables. WEN is active-low and REN is active-high by default. These signals can be configured as active-high or -low. WCLK and RCLK These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver. Note: For the Automotive ProASIC3 FIFO4K18, for the same clock, 180 out of phase (inverted) between clock pins should be used. RPIPE This signal is used to specify pipelined read on the output. A LOW on RPIPE indicates a nonpipelined read, and the data appears on the output in the same clock cycle. A HIGH indicates a pipelined read, and data appears on the output in the next clock cycle. RESET This active-low signal resets the control logic and forces the output hold state registers to zero when asserted. It does not reset the contents of the memory array (Table 6-7 on page 6-14). v1.5 6 - 13 SRAM and FIFO Memories in Actel's Low-Power Flash Devices While the RESET signal is active, read and write operations are disabled. As with any asynchronous RESET signal, care must be taken not to assert it too close to the edges of active read and write clocks. WD This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a data width less than 18 is specified, unused higher-order signals must be grounded (Table 6-7). RD This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the WD bus, high-order bits become unusable if the data width is less than 18. The output data on unused pins is undefined (Table 6-7). Table 6-7 * Input Data Signal Usage for Different Aspect Ratios DxW WD/RD Unused 4kx1 WD[17:1], RD[17:1] 2kx2 WD[17:2], RD[17:2] 1kx4 WD[17:4], RD[17:4] 512x9 WD[17:9], RD[17:9] 256x18 - ESTOP, FSTOP ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the EMPTY flag goes HIGH). A HIGH on this signal inhibits the counting. FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e., the FULL flag goes HIGH). A HIGH on this signal inhibits the counting. For more information on these signals, refer to the "ESTOP and FSTOP Usage" section on page 6-15. FULL, EMPTY When the FIFO is full and no more data can be written, the FULL flag asserts HIGH. The FULL flag is synchronous to WCLK to inhibit writing immediately upon detection of a full condition and to prevent overflows. Since the write address is compared to a resynchronized (and thus timedelayed) version of the read address, the FULL flag will remain asserted until two WCLK active edges after a read operation eliminates the full condition. When the FIFO is empty and no more data can be read, the EMPTY flag asserts HIGH. The EMPTY flag is synchronous to RCLK to inhibit reading immediately upon detection of an empty condition and to prevent underflows. Since the read address is compared to a resynchronized (and thus timedelayed) version of the write address, the EMPTY flag will remain asserted until two RCLK active edges after a write operation removes the empty condition. For more information on these signals, refer to the "FIFO Flag Usage Considerations" section on page 6-15. AFULL, AEMPTY These are programmable flags and will be asserted on the threshold specified by AFVAL and AEVAL, respectively. When the number of words stored in the FIFO reaches the amount specified by AEVAL while reading, the AEMPTY output will go HIGH. Likewise, when the number of words stored in the FIFO reaches the amount specified by AFVAL while writing, the AFULL output will go HIGH. AFVAL, AEVAL The AEVAL and AFVAL pins are used to specify the almost-empty and almost-full threshold values. They are 12-bit signals. For more information on these signals, refer to the "FIFO Flag Usage Considerations" section on page 6-15. 6 -1 4 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices FIFO Usage ESTOP and FSTOP Usage The ESTOP pin is used to stop the read counter from counting any further once the FIFO is empty (i.e., the EMPTY flag goes HIGH). Likewise, the FSTOP pin is used to stop the write counter from counting any further once the FIFO is full (i.e., the FULL flag goes HIGH). The FIFO counters in the device start the count at zero, reach the maximum depth for the configuration (e.g., 511 for a 512x9 configuration), and then restart at zero. An example application for ESTOP, where the read counter keeps counting, would be writing to the FIFO once and reading the same content over and over without doing another write. FIFO Flag Usage Considerations The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values. The FIFO contains separate 12-bit write address (WADDR) and read address (RADDR) counters. WADDR is incremented every time a write operation is performed, and RADDR is incremented every time a read operation is performed. Whenever the difference between WADDR and RADDR is greater than or equal to AFVAL, the AFULL output is asserted. Likewise, whenever the difference between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is asserted. To handle different read and write aspect ratios, AFVAL and AEVAL are expressed in terms of total data bits instead of total data words. When users specify AFVAL and AEVAL in terms of read or write words, the SmartGen tool translates them into bit addresses and configures these signals automatically. SmartGen configures the AFULL flag to assert when the write address exceeds the read address by at least a predefined value. In a 2kx8 FIFO, for example, a value of 1,500 for AFVAL means that the AFULL flag will be asserted after a write when the difference between the write address and the read address reaches 1,500 (there have been at least 1,500 more writes than reads). It will stay asserted until the difference between the write and read addresses drops below 1,500. The AEMPTY flag is asserted when the difference between the write address and the read address is less than a predefined value. In the example above, a value of 200 for AEVAL means that the AEMPTY flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. It will stay asserted until that difference rises above 200. Note that the FIFO can be configured with different read and write widths; in this case, the AFVAL setting is based on the number of write data entries, and the AEVAL setting is based on the number of read data entries. For aspect ratios of 512x9 and 256x18, only 4,096 bits can be addressed by the 12 bits of AFVAL and AEVAL. The number of words must be multiplied by 8 and 16 instead of 9 and 18. The SmartGen tool automatically uses the proper values. To avoid halfwords being written or read, which could happen if different read and write aspect ratios were specified, the FIFO will assert FULL or EMPTY as soon as at least one word cannot be written or read. For example, if a two-bit word is written and a four-bit word is being read, the FIFO will remain in the empty state when the first word is written. This occurs even if the FIFO is not completely empty, because in this case, a complete word cannot be read. The same is applicable in the full state. If a four-bit word is written and a two-bit word is read, the FIFO is full and one word is read. The FULL flag will remain asserted because a complete word cannot be written at this point. Variable Aspect Ratio and Cascading Variable aspect ratio and cascading allow users to configure the memory in the width and depth required. The memory block can be configured as a FIFO by combining the basic memory block with dedicated FIFO controller logic. The FIFO macro is named FIFO4KX18. Low-power flash device RAM can be configured as 1, 2, 4, 9, or 18 bits wide. By cascading the memory blocks, any multiple of those widths can be created. The RAM blocks can be from 256 to 4,096 bits deep, depending on the aspect ratio, and the blocks can also be cascaded to create deeper areas. Refer to the aspect ratios available for each macro cell in the "SRAM Features" section on page 6-7. The largest continuous configurable memory area is equal to half the total memory available on the device, because the RAM is separated into two groups, one on each side of the device. The Actel SmartGen core generator will automatically configure and cascade both RAM and FIFO blocks. Cascading is accomplished using dedicated memory logic and does not consume user gates for depths up to 4,096 bits deep and widths up to 18, depending on the configuration. Deeper memory will utilize some user gates to multiplex the outputs. v1.5 6 - 15 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Generated RAM and FIFO macros can be created as either structural VHDL or Verilog for easy instantiation into the design. Users of Actel Libero IDE can create a symbol for the macro and incorporate it into a design schematic. Table 6-10 on page 6-17 shows the number of memory blocks required for each of the supported depth and width memory configurations, and for each depth and width combination. For example, a 256-bit deep by 32-bit wide two-port RAM would consist of two 256x18 RAM blocks. The first 18 bits would be stored in the first RAM block, and the remaining 14 bits would be implemented in the other 256x18 RAM block. This second RAM block would have four bits of unused storage. Similarly, a dual-port memory block that is 8,192 bits deep and 8 bits wide would be implemented using 16 memory blocks. The dual-port memory would be configured in a 4,096x1 aspect ratio. These blocks would then be cascaded two deep to achieve 8,192 bits of depth, and eight wide to achieve the eight bits of width. Table 6-8 and Table 6-9 show the maximum potential width and depth configuration for each device. Note that 15 k and 30 k gate devices do not support RAM or FIFO. Table 6-8 * Memory Availability per IGLOO and ProASIC3 Device Maximum Potential Width1 Maximum Potential Depth2 Device IGLOO IGLOO nano IGLOO PLUS ProASIC3 ProASIC3 nano ProASIC3L RAM Blocks Depth Width Depth Width AGL060 AGLN060 AGLP060 A3P060 A3PN060 4 256 72 (4x18) 16,384 (4,096x4) 1 AGL125 AGLN125 AGLP125 A3P125 A3PN125 8 256 144 (8x18) 32,768 (4,094x8) 1 AGL250 AGLN250 A3P250/L A3PN250 8 256 144 (8x18) 32,768 (4,096x8) 1 AGL400 A3P400 12 256 216 (12x18) 49,152 (4,096x12) 1 AGL600 A3P600/L 24 256 432 (24x18) 98,304 (4,096x24) 1 AGL1000 A3P1000/L 32 256 576 (32x18) 131,072 (4,096x32) 1 AGLE600 A3PE600 24 256 432 (24x18) 98,304 (4,096x24) 1 A3PE1500 60 256 1,080 (60x18) 245,760 (4,096x60) 1 A3PE3000/L 112 256 2,016 (112x18) 458,752 (4,096x112) 1 AGLE3000 Notes: 1. Maximum potential width uses the two-port configuration. 2. Maximum potential depth uses the dual-port configuration. Table 6-9 * Memory Availability per Fusion Device Maximum Potential Width1 Device RAM Blocks Depth Width AFS090 6 256 AFS250 8 256 AFS600 24 AFS1500 60 Depth Width 108 (6x18) 24,576 (4,094x6) 1 144 (8x18) 32,768 (4,094x8) 1 256 432 (24x18) 98,304 (4,096x24) 1 256 1,080 (60x18) 245,760 (4,096x60) 1 Notes: 1. Maximum potential width uses the two-port configuration. 2. Maximum potential depth uses the dual-port configuration. 6 -1 6 Maximum Potential Depth2 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Table 6-10 * RAM and FIFO Memory Block Consumption Depth 256 Two-Port 1 Number Block Configuration 2 Number Block Configuration 4 Number Block Configuration 8 Number Block Configuration 9 Number Block Configuration Width 16 Number Block Configuration 18 Number Block Configuration 32 Number Block Configuration 36 Number Block Configuration 64 Number Block Configuration 72 Number Block Configuration Note: Dual-Port 512 1,024 2,048 4,096 8,192 16,384 32,768 65,536 Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port 1 1 1 1 1 1 2 4 8 16 x 1 Any Any Any 1,024 x 4 2,048 x 2 4,096 x 1 2 x (4,096 x 1) Cascade Deep 4 x (4,096 x 1) Cascade Deep 8 x (4,096 x 1) Cascade Deep 16 x (4,096 x 1) Cascade Deep 16 32 1 1 1 1 1 2 4 8 Any Any Any 1,024x4 2,048 x 2 2 x (4,096 x 1) Cascaded Wide 4 x (4,096 x 1) Cascaded 2 Deep and 2 Wide 8 x (4,096 x 1) Cascaded 4 Deep and 2 Wide 1 1 1 1 2 4 8 16 Any Any Any 1,024 x 4 2 x (2,048 x 2) Cascaded Wide 4 x (4,096 x 1) Cascaded Wide 4 x (4,096 x 1) Cascaded 2 Deep and 4 Wide 16 x (4,096 x 1) Cascaded 4 Deep and 4 Wide 16 x (4,096 x 1) 32 x (4,096 x 1) Cascaded 8 Deep Cascaded 16 Deep and 2 Wide and 2 Wide 32 1 1 1 2 4 8 16 32 64 Any Any Any 2 x (1,024 x 4) Cascaded Wide 4 x (2,048 x 2) Cascaded Wide 8 x (4,096 x 1) Cascaded Wide 16 x (4,096 x 1) Cascaded 2 Deep and 8 Wide 32 x (4,096 x 1) Cascaded 4 Deep and 8 Wide 64 x (4,096 x 1) Cascaded 8 Deep and 8 Wide 1 1 1 2 4 8 16 32 Any Any Any 2 x (512 x 9) Cascaded Deep 4 x (512 x 9) Cascaded Deep 8 x (512 x 9) Cascaded Deep 16 x (512 x 9) Cascaded Deep 32 x (512 x 9) Cascaded Deep 1 1 1 4 8 16 32 64 256 x 18 256 x 18 256 x 18 4 x (1,024 x 4) Cascaded Wide 8 x (2,048 x 2) Cascaded Wide 16 x (4,096 x 1) Cascaded Wide 32 x (4,096 x 1) Cascaded 2 Deep and 16 Wide 32 x (4,096 x 1) Cascaded 4 Deep and 16 Wide 18 32 1 2 2 4 8 256 x 8 2 x (512 x 9) Cascaded Wide 2 x (512 x 9) Cascaded Wide 4 x (512 x 9) Cascaded 2 Deep and 2 Wide 8 x (512 x 9) Cascaded 4 Deep and 2 Wide 16 x (512 x 9) 16 x (512 x 9) Cascaded 8 Deep Cascaded 16 Deep and 2 Wide and 2 Wide 2 4 4 8 16 32 64 2 x (256 x 18) Cascaded Wide 4 x (512 x 9) Cascaded Wide 4 x (512 x 9) Cascaded Wide 8 x (1,024 x 4) Cascaded Wide 16 x (2,048 x 2) Cascaded Wide 32 x (4,096 x 1) Cascaded Wide 64 x (4,096 x 1) Cascaded 2 Deep and 32 Wide 2 4 4 8 16 32 2 x (256 x 18) Cascaded Wide 4 x (512 x 9) Cascaded Wide 4 x (512 x 9) Cascaded Wide 4 x (512 x 9) Cascaded 2 Deep and 4 Wide 16 x (512 x 9) Cascaded 4 Deep and 4 Wide 16 x (512 x 9) Cascaded 8 Deep and 4 Wide 4 8 8 16 32 64 4 x (256 x 18) Cascaded Wide 8 x (512 x 9) Cascaded Wide 8 x (512 x 9) Cascaded Wide 16 x (1,024 x 4) Cascaded Wide 32 x (2,048 x 2) Cascaded Wide 64 x (4,096 x 1) Cascaded Wide 4 8 8 16 32 4 x (256 x 18) Cascaded Wide 8 x (512 x 9) Cascaded Wide 8 x (512 x 9) Cascaded Wide 16 x (512 x 9) Cascaded Wide 16 x (512 x 9) Cascaded 4 Deep and 8 Wide 64 32 x (4,096 x 1) 64 x (4,096 x 1) Cascaded 8 Deep Cascaded 16 Deep and 4 Wide and 4 Wide Memory configurations represented by grayed cells are not supported. v1.5 6 - 17 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Initializing the RAM/FIFO The SRAM blocks can be initialized with data to use as a lookup table (LUT). Data initialization can be accomplished either by loading the data through the design logic or through the UJTAG interface. The UJTAG macro is used to allow access from the JTAG port to the internal logic in the device. By sending the appropriate initialization string to the JTAG Test Access Port (TAP) Controller, the designer can put the JTAG circuitry into a mode that allows the user to shift data into the array logic through the JTAG port using the UJTAG macro. For a more detailed explanation of the UJTAG macro, refer to UJTAG Applications in Actel's Low-Power Flash Devices. A user interface is required to receive the user command, initialization data, and clock from the UJTAG macro. The interface must synchronize and load the data into the correct RAM block of the design. The main outputs of the user interface block are the following: * Memory block chip select: Selects a memory block for initialization. The chip selects signals for each memory block that can be generated from different user-defined pockets or simple logic, such as a ring counter (see below). * Memory block write address: Identifies the address of the memory cell that needs to be initialized. * Memory block write data: The interface block receives the data serially from the UTDI port of the UJTAG macro and loads it in parallel into the write data ports of the memory blocks. * Memory block write clock: Drives the WCLK of the memory block and synchronizes the write data, write address, and chip select signals. Figure 6-8 shows the user interface between UJTAG and the memory blocks. RAM1 WD WADDR WCLK UJTAG TRST TDO TDI TRST TDO TDI TMS TMS TCK TCK UIREG[7:0] URSTB User Interface IR[7:0] Reset UDRUPD DR_UPDATE UDRSH UDRCAP UDRCK UTDI UTDO DR_SHIFT DR_CAPTURE DR_CLK DIN DOUT WDATA WADDR WCLK WEN1 WEN RAM2 WD WADDR WCLK WEN2 WEN WEN3 RAM3 WD WADDR WCLK WEN Figure 6-8 * Interfacing TAP Ports and SRAM Blocks An important component of the interface between the UJTAG macro and the RAM blocks is a serial-in/parallel-out shift register. The width of the shift register should equal the data width of the RAM blocks. The RAM data arrives serially from the UTDI output of the UJTAG macro. The data must be shifted into a shift register clocked by the JTAG clock (provided at the UDRCK output of the UJTAG macro). Then, after the shift register is fully loaded, the data must be transferred to the write data port of the RAM block. To synchronize the loading of the write data with the write address and write clock, the output of the shift register can be pipelined before driving the RAM block. The write address can be generated in different ways. It can be imported through the TAP using a different instruction opcode and another shift register, or generated internally using a simple 6 -1 8 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices counter. Using a counter to generate the address bits and sweep through the address range of the RAM blocks is recommended, since it reduces the complexity of the user interface block and the board-level JTAG driver. Moreover, using an internal counter for address generation speeds up the initialization procedure, since the user only needs to import the data through the JTAG port. The designer may use different methods to select among the multiple RAM blocks. Using counters along with demultiplexers is one approach to set the write enable signals. Basically, the number of RAM blocks needing initialization determines the most efficient approach. For example, if all the blocks are initialized with the same data, one enable signal is enough to activate the write procedure for all of them at the same time. Another alternative is to use different opcodes to initialize each memory block. For a small number of RAM blocks, using counters is an optimal choice. For example, a ring counter can be used to select from multiple RAM blocks. The clock driver of this counter needs to be controlled by the address generation process. Once the addressing of one block is finished, a clock pulse is sent to the (ring) counter to select the next memory block. Figure 6-9 illustrates a simple block diagram of an interface block between UJTAG and RAM blocks. Serial-to-Port Shift Register UTDI SIN POUT UDRSH Enable SOUT UDRCK CLK UTDO Data Reg. Q D n n CLK UDRUPDI UIREG WDATA WCLK In Compare Result with Defined Opcode En Reset CLK URSTB Chip Select WEN1 Ring Counter WEN2 WENi m En Reset CLK Addr Counter Q m WADDR Binary Counter Figure 6-9 * Block Diagram of a Sample User Interface In the circuit shown in Figure 6-9, the shift register is enabled by the UDRSH output of the UJTAG macro. The counters and chip select outputs are controlled by the value of the TAP Instruction Register. The comparison block compares the UIREG value with the "start initialization" opcode value (defined by the user). If the result is true, the counters start to generate addresses and activate the WEN inputs of appropriate RAM blocks. The UDRUPD output of the UJTAG macro, also shown in Figure 6-9, is used for generating the write clock (WCLK) and synchronizing the data register and address counter with WCLK. UDRUPD is HIGH when the TAP Controller is in the Data Register Update state, which is an indication of completing the loading of one data word. Once the TAP Controller goes into the Data Register Update state, the UDRUPD output of the UJTAG macro goes HIGH. Therefore, the pipeline register and the address counter place the proper data and address on the outputs of the interface block. Meanwhile, WCLK is defined as the inverted UDRUPD. This will provide enough time (equal to the UDRUPD HIGH time) for the data and address to be placed at the proper ports of the RAM block before the rising edge of WCLK. The inverter is not required if the RAM blocks are clocked at the falling edge of the write clock. An example of this is described in the "Example of RAM Initialization" section on page 6-20. v1.5 6 - 19 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Example of RAM Initialization This section of the document presents a sample design in which a 4x4 RAM block is being initialized through the JTAG port. A test feature has been implemented in the design to read back the contents of the RAM after initialization to verify the procedure. The interface block of this example performs two major functions: initialization of the RAM block and running a test procedure to read back the contents. The clock output of the interface is either the write clock (for initialization) or the read clock (for reading back the contents). The Verilog code for the interface block is included in the "Sample Verilog Code" section on page 6-21. For simulation purposes, users can declare the input ports of the UJTAG macro for easier assignment in the testbench. However, the UJTAG input ports should not be declared on the top level during synthesis. If the input ports of the UJTAG are declared during synthesis, the synthesis tool will instantiate input buffers on these ports. The input buffers on the ports will cause Compile to fail in Designer. Figure 6-10 shows the simulation results for the initialization step of the example design. The CLK_OUT signal, which is the clock output of the interface block, is the inverted DR_UPDATE output of the UJTAG macro. It is clear that it gives sufficient time (while the TAP Controller is in the Data Register Update state) for the write address and data to become stable before loading them into the RAM block. Figure 6-11 presents the test procedure of the example. The data read back from the memory block matches the written data, thus verifying the design functionality. Figure 6-10 * Simulation of Initialization Step Figure 6-11 * Simulation of the Test Procedure of the Example 6 -2 0 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices The ROM emulation application is based on RAM block initialization. If the user's main design has access only to the read ports of the RAM block (RADDR, RD, RCLK, and REN), and the contents of the RAM are already initialized through the TAP, then the memory blocks will emulate ROM functionality for the core design. In this case, the write ports of the RAM blocks are accessed only by the user interface block, and the interface is activated only by the TAP Instruction Register contents. Users should note that the contents of the RAM blocks are lost in the absence of applied power. However, the 1 kbit of flash memory, FlashROM, in low-power flash devices can be used to retain data after power is removed from the device. Refer to FlashROM in Actel's Low-Power Flash Devices for more information. Sample Verilog Code Interface Block define Initialize_start 8'h22 //INITIALIZATION START COMMAND VALUE define Initialize_stop 8'h23 //INITIALIZATION START COMMAND VALUE module interface(IR, rst_n, data_shift, clk_in, data_update, din_ser, dout_ser, test, test_out,test_clk,clk_out,wr_en,rd_en,write_word,read_word,rd_addr, wr_addr); input [7:0] IR; input [3:0] read_word; //RAM DATA READ BACK input rst_n, data_shift, clk_in, data_update, din_ser; //INITIALIZATION SIGNALS input test, test_clk; //TEST PROCEDURE CLOCK AND COMMAND INPUT output [3:0] test_out; //READ DATA output [3:0] write_word; //WRITE DATA output [1:0] rd_addr; //READ ADDRESS output [1:0] wr_addr; //WRITE ADDRESS output dout_ser; //TDO DRIVER output clk_out, wr_en, rd_en; wire wire wire wire wire [3:0] write_word; [1:0] rd_addr; [1:0] wr_addr; [3:0] Q_out; enable, test_active; reg clk_out; //SELECT CLOCK FOR INITIALIZATION OR READBACK TEST always @(enable or test_clk or data_update) begin case ({test_active}) 1 : clk_out = test_clk ; 0 : clk_out = !data_update; default : clk_out = 1'b1; endcase end assign assign assign assign assign assign test_active = test && (IR == 8'h23); enable = (IR == 8'h22); wr_en = !enable; rd_en = !test_active; test_out = read_word; dout_ser = Q_out[3]; //4-bit SIN/POUT SHIFT REGISTER shift_reg data_shift_reg (.Shiften(data_shift), .Shiftin(din_ser), .Clock(clk_in), .Q(Q_out)); //4-bit PIPELINE REGISTER D_pipeline pipeline_reg (.Data(Q_out), .Clock(data_update), .Q(write_word)); v1.5 6 - 21 SRAM and FIFO Memories in Actel's Low-Power Flash Devices // addr_counter counter_1 (.Clock(data_update), .Q(wr_addr), .Aset(rst_n), .Enable(enable)); addr_counter counter_2 (.Clock(test_clk), .Q(rd_addr), .Aset(rst_n), .Enable( test_active)); endmodule Interface Block / UJTAG Wrapper This example is a sample wrapper, which connects the interface block to the UJTAG and the memory blocks. // WRAPPER module top_init (TDI, TRSTB, TMS, TCK, TDO, test, test_clk, test_ out); input TDI, TRSTB, TMS, TCK; output TDO; input test, test_clk; output [3:0] test_out; wire wire wire wire wire [7:0] IR; reset, DR_shift, DR_cap, init_clk, DR_update, data_in, data_out; clk_out, wen, ren; [3:0] word_in, word_out; [1:0] write_addr, read_addr; UJTAG UJTAG_U1 (.UIREG0(IR[0]), .UIREG1(IR[1]), .UIREG2(IR[2]), .UIREG3(IR[3]), .UIREG4(IR[4]), .UIREG5(IR[5]), .UIREG6(IR[6]), .UIREG7(IR[7]), .URSTB(reset), .UDRSH(DR_shift), .UDRCAP(DR_cap), .UDRCK(init_clk), .UDRUPD(DR_update), .UT-DI(data_in), .TDI(TDI), .TMS(TMS), .TCK(TCK), .TRSTB(TRSTB), .TDO(TDO), .UT-DO(data_out)); mem_block RAM_block (.DO(word_out), .RCLOCK(clk_out), .WCLOCK(clk_out), .DI(word_in), .WRB(wen), .RDB(ren), .WAD-DR(write_addr), .RADDR(read_addr)); interface init_block (.IR(IR), .rst_n(reset), .data_shift(DR_shift), .clk_in(init_clk), .data_update(DR_update), .din_ser(data_in), .dout_ser(data_out), .test(test), .test_out(test_out), .test_clk(test_clk), .clk_out(clk_out), .wr_en(wen), .rd_en(ren), .write_word(word_in), .read_word(word_out), .rd_addr(read_addr), .wr_addr(write_addr)); endmodule Address Counter module addr_counter (Clock, Q, Aset, Enable); input Clock; output [1:0] Q; input Aset; input Enable; reg [1:0] Qaux; always @(posedge Clock or negedge Aset) begin if (!Aset) Qaux <= 2'b11; else if (Enable) Qaux <= Qaux + 1; end assign Q = Qaux; endmodule 6 -2 2 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Pipeline Register module D_pipeline (Data, Clock, Q); input [3:0] Data; input Clock; output [3:0] Q; reg [3:0] Q; always @ (posedge Clock) Q <= Data; endmodule 4x4 RAM Block (created by SmartGen Core Generator) module mem_block(DI,DO,WADDR,RADDR,WRB,RDB,WCLOCK,RCLOCK); input [3:0] DI; output [3:0] DO; input [1:0] WADDR, RADDR; input WRB, RDB, WCLOCK, RCLOCK; wire WEBP, WEAP, VCC, GND; VCC VCC_1_net(.Y(VCC)); GND GND_1_net(.Y(GND)); INV WEBUBBLEB(.A(WRB), .Y(WEBP)); RAM4K9 RAMBLOCK0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(GND), .ADDRA8(GND), .ADDRA7(GND), .ADDRA6(GND), .ADDRA5(GND), .ADDRA4(GND), .ADDRA3(GND), .ADDRA2(GND), .ADDRA1(RADDR[1]), .ADDRA0(RADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(GND), .ADDRB8(GND), .ADDRB7(GND), .ADDRB6(GND), .ADDRB5(GND), .ADDRB4(GND), .ADDRB3(GND), .ADDRB2(GND), .ADDRB1(WADDR[1]), .ADDRB0(WADDR[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(GND), .DINA0(GND), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND), .DINB3(DI[3]), .DINB2(DI[2]), .DINB1(DI[1]), .DINB0(DI[0]), .WIDTHA0(GND), .WIDTHA1(VCC), .WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND), .BLKA(WEAP), .BLKB(WEBP), .WENA(VCC), .WENB(GND), .CLKA(RCLOCK), .CLKB(WCLOCK), .RESET(VCC), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(DO[3]), .DOUTA2(DO[2]), .DOUTA1(DO[1]), .DOUTA0(DO[0]), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(), .DOUTB0()); INV WEBUBBLEA(.A(RDB), .Y(WEAP)); endmodule v1.5 6 - 23 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Software Support The SmartGen core generator is the easiest way to select and configure the memory blocks (Figure 6-12). SmartGen automatically selects the proper memory block type and aspect ratio, and cascades the memory blocks based on the user's selection. SmartGen also configures any additional signals that may require tie-off. SmartGen will attempt to use the minimum number of blocks required to implement the desired memory. When cascading, SmartGen will configure the memory for width before configuring for depth. For example, if the user requests a 256x8 FIFO, SmartGen will use a 512x9 FIFO configuration, not 256x18. Figure 6-12 * SmartGen Core Generator Interface 6 -2 4 v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SmartGen enables the user to configure the desired RAM element to use either a single clock for read and write, or two independent clocks for read and write. The user can select the type of RAM as well as the width/depth and several other parameters (Figure 6-13). Figure 6-13 * SmartGen Memory Configuration Interface SmartGen also has a Port Mapping option that allows the user to specify the names of the ports generated in the memory block (Figure 6-14). Figure 6-14 * Port Mapping Interface for SmartGen-Generated Memory v1.5 6 - 25 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SmartGen also configures the FIFO according to user specifications. Users can select no flags, static flags, or dynamic flags. Static flag settings are configured using configuration flash and cannot be altered without reprogramming the device. Dynamic flag settings are determined by register values and can be altered without reprogramming the device by reloading the register values either from the design or through the UJTAG interface described in the "Initializing the RAM/FIFO" section on page 6-18. SmartGen can also configure the FIFO to continue counting after the FIFO is full. In this configuration, the FIFO write counter will wrap after the counter is full and continue to write data. With the FIFO configured to continue to read after the FIFO is empty, the read counter will also wrap and re-read data that was previously read. This mode can be used to continually read back repeating data patterns stored in the FIFO (Figure 6-15). Figure 6-15 * SmartGen FIFO Configuration Interface FIFOs configured using SmartGen can also make use of the port mapping feature to configure the names of the ports. Limitations Users should be aware of the following limitations when configuring SRAM blocks for low-power flash devices: 6 -2 6 * SmartGen does not track the target device in a family, so it cannot determine if a configured memory block will fit in the target device. * Dual-port RAMs with different read and write aspect ratios are not supported. * Cascaded memory blocks can only use a maximum of 64 blocks of RAM. * The Full flag of the FIFO is sensitive to the maximum depth of the actual physical FIFO block, not the depth requested in the SmartGen interface. v1.5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Conclusion Fusion, IGLOO, and ProASIC3 devices provide users with extremely flexible SRAM blocks for most design needs, with the ability to choose between an easy-to-use dual-port memory or a wide-word two-port memory. Used with the built-in FIFO controllers, these memory blocks also serve as highly efficient FIFOs that do not consume user gates when implemented. The Actel SmartGen core generator provides a fast and easy way to configure these memory elements for use in designs. Related Documents Handbook Documents UJTAG Applications in Actel's Low-Power Flash Devices www.actel.com/documents/LPD_UJTAG_HBs.pdf FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-008-5 Revised December 2008 v1.5 6 - 27 SRAM and FIFO Memories in Actel's Low-Power Flash Devices List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.4 (October 2008) v1.3 (August 2008) v1.2 (June 2008) v1.1 (March 2008) v1.0 (January 2008) 6 -2 8 Changes in the Current Version (v1.5) Page IGLOO nano and ProASIC3 nano devices were added to Table 6-1 * FlashBased FPGAs. 6-4 IGLOO nano and ProASIC3 nano devices Table 6-8 * Interfacing TAP Ports and SRAM Blocks. to 6-18 The "SRAM/FIFO Support in Flash-Based Devices" section was revised to include new families and make the information more concise. 6-4 The "SRAM and FIFO Architecture" section was modified to remove "IGLOO and ProASIC3E" from the description of what the memory block includes, as this statement applies to all memory blocks. 6-5 Wording in the "Clocking" section was revised to change "IGLOO and ProASIC3 devices support inversion" to "Low-power flash devices support inversion." The reference to IGLOO and ProASIC3 development tools in the last paragraph of the section was changed to refer to development tools in general. 6-11 The "ESTOP and FSTOP Usage" section was updated to refer to FIFO counters in devices in general rather than only IGLOO and ProASIC3E devices. 6-15 The note was removed from Figure 6-7 * RAM Block with Embedded FIFO Controller and placed in the WCLK and RCLK description. 6-12 The "WCLK and RCLK" description was revised. 6-13 The following changes were made to the family descriptions in Table 6-1 * Flash-Based FPGAs: 6-4 were added * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. The "Introduction" section was updated to include the IGLOO PLUS family. 6-1 The "Device Architecture" section was updated to state that 15 k gate devices do not support SRAM and FIFO. 6-1 The first note in Figure 6-1 * IGLOO and ProASIC3 Device Architecture Overview was updated to include mention of 15 k gate devices, and IGLOO PLUS was added to the second note. 6-3 Table 6-1 * Flash-Based FPGAs and associated text were updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 6-4 The text introducing Table 6-8 * Memory Availability per IGLOO and ProASIC3 Device was updated to replace "A3P030 and AGL030" with "15 k and 30 k gate devices." Table 6-8 * Memory Availability per IGLOO and ProASIC3 Device was updated to remove AGL400 and AGLE1500 and include IGLOO PLUS and ProASIC3L devices. 6-16 v1.5 I/O Descriptions and Usage 7 - I/O Structures in IGLOOe and ProASIC3E Devices Introduction Low-power flash devices feature a flexible I/O structure, supporting a range of mixed voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V) through bank-selectable voltages. IGLOO(R)e, ProASIC(R)3EL, and ProASIC3E families support Pro I/Os. Users designing I/O solutions are faced with a number of implementation decisions and configuration choices that can directly impact the efficiency and effectiveness of their final design. The flexible I/O structure, supporting a wide variety of voltages and I/O standards, enables users to meet the growing challenges of their many diverse applications. The Actel Libero(R) Integrated Design Environment (IDE) provides an easy way to implement I/O that will result in robust I/O design. This document first describes the two different I/O types in terms of the standards and features they support. It then explains the individual features and how to implement them in Actel's Libero IDE. I/O / Q0 1 Input Register 2 Input Register To FPGA Core Y Pull-Up/-Down Resistor Control CLR/PRE I/O / Q1 3 Input ICE Register PAD Scan CLR/PRE I/O / ICLK Scan Scan A I/O / D0 Signal Drive Strength and Slew Rate Control E = Enable Pin 4 Output OCE Register From FPGA Core CLR/PRE I/O / D1 / ICE ICE I/O / OCLK 5 Output Register CLR/PRE I/O / OE OCE I/O / CLR or I/O / PRE / OCE 6 Output Enable Register CLR/PRE Figure 7-1 * I/O Block Logical Representation v1.4 7-1 I/O Structures in IGLOOe and ProASIC3E Devices Low-Power Flash Device I/O Support The low-power flash FPGAs listed in Table 7-1 support I/Os and the functions described in this document. Table 7-1 * Series Flash-Based FPGAs Family* Description IGLOO IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards ProASIC3 ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 7-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 7-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 7 -2 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices Pro I/Os--IGLOOe, ProASIC3EL, and ProASIC3E Table 7-2 shows the voltages and compatible I/O standards for Pro I/Os. I/Os provide programmable slew rates, drive strengths, and weak pull-up and pull-down circuits. All I/O standards, except 3.3 V PCI and 3.3 V PCI-X, are capable of hot-insertion. 3.3 V PCI and 3.3 V PCI-X are 5 V-tolerant. See the "5 V Input Tolerance" section on page 7-20 for possible implementations of 5 V tolerance. Singleended input buffers support both the Schmitt trigger and programmable delay options on a per- I/O basis. All I/Os are in a known state during power-up, and any power-up sequence is allowed without current impact. Refer to the "I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)" section in the datasheet for more information. During power-up, before reaching activation levels, the I/O input and output buffers are disabled while the weak pull-up is enabled. Activation levels are described in the datasheet. Table 7-2 * Supported I/O Standards A3PE600 A3PE1500 A3PE3000/ A3PE3000L AGLE600 AGLE1500 AGLE3000 Single-Ended LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V, LVCMOS 2.5/5.0 V, 3.3 V PCI/PCI-X Differential LVPECL, LVDS, B-LVDS, M-LVDS Voltage-Referenced GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II v1.4 7-3 I/O Structures in IGLOOe and ProASIC3E Devices I/O Banks and I/O Standards Compatibility I/Os are grouped into I/O voltage banks. Each I/O voltage bank has dedicated I/O supply and ground voltages (VMV/GNDQ for input buffers and VCCI/GND for output buffers). Because of these dedicated supplies, only I/Os with compatible standards can be assigned to the same I/O voltage bank. Table 7-3 on page 7-5 shows the required voltage compatibility values for each of these voltages. There are eight I/O banks (two per side). Every I/O bank is divided into minibanks. Any user I/O in a VREF minibank (a minibank is the region of scope of a VREF pin) can be configured as a VREF pin (Figure 7-2). Only one VREF pin is needed to control the entire VREF minibank. The location and scope of the VREF minibanks can be determined by the I/O name. For details, see the user I/O naming conventions for "IGLOOe and ProASIC3E" on page 7-33. Table 7-5 on page 7-5 shows the I/O standards supported by IGLOOe and ProASIC3E devices, and the corresponding voltage levels. I/O standards are compatible if they comply with the following: * Their VCCI and VMV values are identical. * Both of the standards need a VREF, and their VREF values are identical. * All inputs and disabled outputs are voltage tolerant up to 3.3 V. For more information about I/O and global assignments to I/O banks in a device, refer to the specific pin table for the device in the packaging section of the datasheet, and see the user I/O naming conventions for "IGLOOe and ProASIC3E" on page 7-33. Bank 2 CCC/PLL "B" I/O Common VREF signal for all I/Os in VREF minibanks I/O VCCI GND VCC I/O Bank 3 CCC/PLL "C" Up to five VREF minibanks within an I/O bankF I/O I/O I/O JTAG CCC/PLL "D" Any I/O in a VREF minibank can be used to provide the reference voltage to the common VREF signal for the VREF minibank. I/O Pad VCCI VREF signal scope is between 8 and 18 I/Os. GND VCC I/O I/O Figure 7-2 * Typical IGLOOe and ProASIC3E I/O Bank Detail Showing VREF Minibanks 7 -4 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices Table 7-3 * VCCI Voltages and Compatible IGLOOe and ProASIC3E Standards VCCI and VMV (typical) Compatible Standards 3.3 V LVTTL/LVCMOS 3.3, PCI 3.3, SSTL3 (Class I and II), GTL+ 3.3, GTL 3.3, LVPECL 2.5 V LVCMOS 2.5, LVCMOS 2.5/5.0, SSTL2 (Class I and II), GTL+ 2.5, GTL 2.5, LVDS, DDR LVDS, B-LVDS, and M-LVDS 1.8 V LVCMOS 1.8 1.5 V LVCMOS 1.5, HSTL (Class I and II) VREF Voltages and Compatible IGLOOe and ProASIC3E Standards Table 7-4 * VREF (typical) Compatible Standards 1.5 V SSTL3 (Class I and II) 1.25 V SSTL2 (Class I and II) 1.0 V GTL+ 2.5, GTL+ 3.3 0.8 V GTL 2.5, GTL 3.3 0.75 V HSTL (Class I and II) LVPECL (3.3 V) LVDS, B-LVDS, and M-LVDS, DDR (2.5 V 5%) SSTL3 Class I and II (3.3 V) SSTL2 Class I and II (2.5 V) HSTL Class I and II (1.5 V) GTL (2.5 V) GTL (3.3 V) GTL+ (2.5 V) GTL+ (3.3 V) 3.3 V PCI/PCI-X LVCMOS 1.5 V LVCMOS 1.8 V - LVCMOS 2.5 V 3.3 V LVTTL/LVCMOS 3.3 V Minibank Voltage (typical) Legal IGLOOe and ProASIC3E I/O Usage Matrix within the Same Bank I/O Bank Voltage (typical) Table 7-5 * 0.80 V 1.00 V 1.50 V 2.5 V - 0.80 V 1.00 V 1.25 V 1.8 V - 1.5 V - 0.75 V Note: White box: Allowable I/O standard combination Gray box: Illegal I/O standard combination v1.4 7-5 I/O Structures in IGLOOe and ProASIC3E Devices Features Supported on Every I/O Table 7-6 lists all features supported by transmitter/receiver for single-ended and differential I/Os. Table 7-7 on page 7-7 lists the performance of each I/O technology. Table 7-6 * IGLOOe and ProASIC3E I/O Features Feature All I/O Description * High performance (Table 7-7 on page 7-7) * Electrostatic discharge protection * I/O register combining option Single-Ended and Voltage-Referenced * Transmitter Features Hot-swap in every mode except PCI or 5 V-input-tolerant (these modes use clamp diodes and do not allow hot-swap) * Activation of hot-insertion (disabling the clamp diode) is selectable by I/Os. Single-Ended Receiver Features * Output slew rate: 2 slew rates * Weak pull-up and pull-down resistors * Output drive: 5 drive strengths * Programmable output loading * Skew between output buffer enable/disable time: 2 ns delay on rising edge and 0 ns delay on falling edge (see "Selectable Skew between Output Buffer Enable and Disable Times" section on page 7-24 for more information) * LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs * 5 V-input-tolerant receiver (Table 7-13 on page 7-19) * Schmitt trigger option * Programmable delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay increments (at 25C, 1.5 V) * Separate ground plane for GNDQ pin and power plane for VMV pin are used for input buffer to reduce output-induced noise. Voltage-Referenced Differential Receiver * Features Programmable delay: 0 ns if bypassed, 0.46 ns with '000' setting, 4.66 ns with '111' setting, 0.6-ns intermediate delay increments (at 25C, 1.5 V) * Separate ground plane for GNDQ pin and power plane for VMV pin are used for input buffer to reduce output-induced noise. CMOS-Style LVDS, B-LVDS, M-LVDS, or * LVPECL Transmitter Two I/Os and external resistors are used to provide a CMOS-style LVDS, DDR LVDS, B-LVDS, and M-LVDS/LVPECL transmitter solution. * Activation of hot-insertion (disabling the clamp diode) is selectable by I/Os. * High slew rate * Weak pull-up and pull-down resistors * Programmable output loading LVDS, DDR LVDS, B-LVDS, and * M-LVDS/LVPECL Differential Receiver Features 7 -6 Programmable delay: 0 ns if bypassed, 0.46 ns with '000' setting, 4.66 ns with '111' setting, 0.6-ns intermediate delay increments (at 25C, 1.5 V) v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices Table 7-7 * Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in ProASIC3E Devices (maximum drive strength and high slew selected) Maximum Performance ProASIC3E IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage LVTTL/LVCMOS 3.3 V 200 MHz 180 MHz TBD LVCMOS 2.5 V 250 MHz 230 MHz TBD LVCMOS 1.8 V 200 MHz 180 MHz TBD LVCMOS 1.5 V 130 MHz 120 MHz TBD Specification IGLOOe V2, 1.2 V DC Core Supply Voltage PCI 200 MHz 180 MHz TBD PCI-X 200 MHz 180 MHz TBD HSTL-I 300 MHz 275 MHz TBD HSTL-II 300 MHz 275 MHz TBD SSTL2-I 300 MHz 275 MHz TBD SSTL2-II 300 MHz 275 MHz TBD SSTL3-I 300 MHz 275 MHz TBD SSTL3-II 300 MHz 275 MHz TBD GTL+ 3.3 V 300 MHz 275 MHz TBD GTL+ 2.5 V 300 MHz 275 MHz TBD GTL 3.3 V 300 MHz 275 MHz TBD GTL 2.5 V 300 MHz 275 MHz TBD LVDS 350 MHz 300 MHz TBD M-LVDS 200 MHz 180 MHz TBD B LVDS 200 MHz 180 MHz TBD LVPECL 350 MHz 300 MHz TBD v1.4 7-7 I/O Structures in IGLOOe and ProASIC3E Devices I/O Architecture I/O Tile The I/O tile provides a flexible, programmable structure for implementing a large number of I/O standards. In addition, the registers available in the I/O tile can be used to support highperformance register inputs and outputs, with register enable if desired (Figure 7-3). The registers can also be used to support the JESD-79C Double Data Rate (DDR) standard within the I/O structure (see DDR for Actel's Low-Power Flash Devices for more information). As depicted in Figure 7-3, all I/O registers share one CLR port. The output register and output enable register share one CLK port. I/O / Q0 1 Input Register 2 Input Register To FPGA Core Y Pull-Up/-Down Resistor Control CLR/PRE I/O / Q1 3 Input ICE Register PAD CLR/PRE I/O / ICLK Signal Drive Strength and Slew Rate Control A I/O / D0 4 Output OCE Register From FPGA Core CLR/PRE I/O / D1 / ICE ICE I/O / OCLK CLR/PRE I/O / OE OCE I/O / CLR or I/O / PRE / OCE 6 Output Enable Register CLR/PRE Figure 7-3 * I/O Block Logical Representation 7 -8 5 Output Register v1.4 E = Enable Pin I/O Structures in IGLOOe and Pro ASIC3E Devices I/O Bank Structure Low-power flash device I/Os are divided into multiple technology banks. The number of banks is device-dependent. The IGLOOe, ProASIC3EL, and ProASIC3E devices have eight banks (two per side); and IGLOO, ProASIC3L, and ProASIC3 devices have two to four banks. Each bank has its own VCCI power supply pin. Multiple I/O standards can co-exist within a single I/O bank. In IGLOOe, ProASIC3EL, and ProASIC3E devices, each I/O bank is subdivided into VREF minibanks. These are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All I/Os in a given minibank share a common VREF line (only one VREF pin is needed per VREF minibank). Therefore, if an I/O in a VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use the voltage assigned to that pin. If the location of the VREF pin is selected manually in the software, the user must satisfy VREF rules (refer to I/O Software Control in Low-Power Flash Devices). If the user does not pick the VREF pin manually, the software automatically assigns it. Figure 7-4 is a snapshot of a section of the I/O ring, showing the basic elements of an I/O tile, as viewed from the Designer place-and-route tool's MultiView Navigator (MVN). I/O Pad/Buffer I/O Logic (assigned) { Other Minibanks N Side P Side (assigned) (unassigned) Diffio Tile Minibank Figure 7-4 * Snapshot of an I/O Tile Low-power flash device I/Os are implemented using two tile types: I/O and differential I/O (diffio). The diffio tile is built up using two I/O tiles, which form an I/O pair (P side and N side). These I/O pairs are used according to differential I/O standards. Both the P and N sides of the diffio tile include an I/O buffer and two I/O logic blocks (auxiliary and main logic). Every minibank (E devices only) is built up from multiple diffio tiles. The number of the minibank depends on the different-size dies. Refer to the "Pro I/Os--IGLOOe, ProASIC3EL, and ProASIC3E" section on page 7-3 for an illustration of the minibank structure. Figure 7-5 on page 7-10 shows a simplified diagram of the I/O buffer circuitry. The Output Enable signal (OE) enables the output buffer to pass the signal from the core logic to the pin. The output buffer contains ESD protection circuitry, an n-channel transistor that shunts all ESD surges (up to the limit of the device ESD specification) to GND. This transistor also serves as an output pull-down resistor. Each output buffer also contains programmable slew rate, drive strength, programmable power-up state (pull-up/-down resistor), hot-swap, 5 V tolerance, and clamp diode control circuitry. Multiple flash switches (not shown in Figure 7-5 on page 7-10) are programmed by user selections in the software to activate different I/O features. v1.4 7-9 I/O Structures in IGLOOe and ProASIC3E Devices Output Buffer Hot-Swap, 5 V Tolerance, and Clamp Diode Control VCCI VCCI VCCI Weak Pull-Up Control (from core) OE (from core logic) Output Buffer Logic and Enable Skew Circuit ESD Protection1 Clamp Diode I/O PAD Drive Strength and Output Slew Rate Control Clamp Diode Output Signal (from core logic) Weak PullDown Control (from core) ESD Protection1 Input Buffer Input Buffer Standard2 and Schmitt Trigger Control Input Signal to Core Logic Programmable Input Delay Control Notes: 1. All NMOS transistors connected to the I/O pad serve as ESD protection. 2. See Table 7-2 on page 7-3 for available I/O standards. Figure 7-5 * Simplified I/O Buffer Circuitry I/O Registers Each I/O module contains several input, output, and enable registers. Refer to Figure 7-5 for a simplified representation of the I/O block. The number of input registers is selected by a set of switches (not shown in Figure 7-3 on page 7-8) between registers to implement single-ended or differential data transmission to and from the FPGA core. The Designer software sets these switches for the user. A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O register combining must satisfy certain rules. 7 -1 0 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices I/O Standards Single-Ended Standards These I/O standards use a push-pull CMOS output stage with a voltage referenced to system ground to designate logical states. The input buffer configuration, output drive, and I/O supply voltage (VCCI) vary among the I/O standards (Figure 7-6). VCCI OUT IN VCCI Device 1 Device 2 GND GND Figure 7-6 * Single-Ended I/O Standard Topology The advantage of these standards is that a common ground can be used for multiple I/Os. This simplifies board layout and reduces system cost. Their low-edge-rate (dv/dt) data transmission causes less electromagnetic interference (EMI) on the board. However, they are not suitable for high-frequency (>200 MHz) switching due to noise impact and higher power consumption. LVTTL (Low-Voltage TTL) This is a general-purpose standard (EIA/JESD8-B) for 3.3 V applications. It uses an LVTTL input buffer and a push-pull output buffer. The LVTTL output buffer can have up to six different programmable drive strengths. The default drive strength is 12 mA. VCCI is 3.3 V. Refer to "I/O Programmable Features" on page 7-15 for details. LVCMOS (Low-Voltage CMOS) The low-power flash devices provide four different kinds of LVCMOS: LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 1.8 V, and LVCMOS 1.5 V. LVCMOS 3.3 V is an extension of the LVCMOS standard (JESD8-B- compliant) used for general-purpose 3.3 V applications. LVCMOS 2.5 V is an extension of the LVCMOS standard (JESD8-5-compliant) used for general-purpose 2.5 V applications. LVCMOS 2.5 V for the 30 k gate devices has a clamp diode to VCCI, but for all other devices there is no clamp diode. There is yet another standard supported by IGLOO and ProASIC3 devices (except A3P030): LVCMOS 2.5/5.0 V. This standard is similar to LVCMOS 2.5 V, with the exception that it can support up to 3.3 V on the input side (2.5 V output drive). LVCMOS 1.8 V is an extension of the LVCMOS standard (JESD8-7-compliant) used for generalpurpose 1.8 V applications. LVCMOS 1.5 V is an extension of the LVCMOS standard (JESD8-11- compliant) used for general-purpose 1.5 V applications. The VCCI values for these standards are 3.3 V, 2.5 V, 1.8 V, and 1.5 V, respectively. All these versions use a 3.3 V-tolerant CMOS input buffer and a push-pull output buffer. Like LVTTL, the output buffer has up to seven different programmable drive strengths (2, 4, 6, 8, 12, 16, and 24 mA). Refer to "I/O Programmable Features" on page 7-15 for details. 3.3 V PCI (Peripheral Component Interface) This standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. With the aid of an external resistor, this I/O standard can be 5 V-compliant for low-power flash devices. It does not have programmable drive strength. v1.4 7 - 11 I/O Structures in IGLOOe and ProASIC3E Devices 3.3 V PCI-X (Peripheral Component Interface Extended) An enhanced version of the PCI specification, 3.3 V PCI-X can support higher average bandwidths; it increases the speed that data can move within a computer from 66 MHz to 133 MHz. It is backward-compatible, which means devices can operate at conventional PCI frequencies (33 MHz and 66 MHz). PCI-X is more fault-tolerant than PCI. It also does not have programmable drive strength. Voltage-Referenced Standards I/Os using these standards are referenced to an external reference voltage (VREF) and are supported on E devices only. HSTL Class I and II (High-Speed Transceiver Logic) These are general-purpose, high-speed 1.5 V bus standards (EIA/JESD 8-6) for signaling between integrated circuits. The signaling range is 0 V to 1.5 V, and signals can be either single-ended or differential. HSTL requires a differential amplifier input buffer and a push-pull output buffer. The reference voltage (VREF) is 0.75 V. These standards are used in the memory bus interface with data switching capability of up to 400 MHz. The other advantages of these standards are low power and fewer EMI concerns. HSTL has four classes, of which low-power flash devices support Class I and II. These classes are defined by standard EIA/JESD 8-6 from the Electronic Industries Alliance (EIA): * Class I - Unterminated or symmetrically parallel-terminated * Class II - Series-terminated * Class III - Asymmetrically parallel-terminated * Class IV - Asymmetrically double-parallel-terminated SSTL2 Class I and II (Stub Series Terminated Logic 2.5 V) These are general-purpose 2.5 V memory bus standards (JESD 8-9) for driving transmission lines, designed specifically for driving the DDR SDRAM modules used in computer memory. SSTL2 requires a differential amplifier input buffer and a push-pull output buffer. The reference voltage (VREF) is 1.25 V. SSTL3 Class I and II (Stub Series Terminated Logic 3.3 V) These are general-purpose 3.3 V memory bus standards (JESD 8-8) for driving transmission lines. SSTL3 requires a differential amplifier input buffer and a push-pull output buffer. The reference voltage (VREF) is 1.5 V. VCCI OUT IN Device 2 Device 1 GND VREF Figure 7-7 * SSTL and HSTL Topology 7 -1 2 VCCI v1.4 GND VREF I/O Structures in IGLOOe and Pro ASIC3E Devices GTL 2.5 V (Gunning Transceiver Logic 2.5 V) This is a low-power standard (JESD 8-3) for electrical signals used in CMOS circuits that allows for low electromagnetic interference at high transfer speeds. It has a voltage swing between 0.4 V and 1.2 V and typically operates at speeds of between 20 and 40 MHz. VCCI must be connected to 2.5 V. The reference voltage (VREF) is 0.8 V. GTL 3.3 V (Gunning Transceiver Logic 3.3 V) This is the same as GTL 2.5 V above, except VCCI must be connected to 3.3 V. GTL+ (Gunning Transceiver Logic Plus) This is an enhanced version of GTL that has defined slew rates and higher voltage levels. It requires a differential amplifier input buffer and an open-drain output buffer. Even though the output is open-drain, VCCI must be connected to either 2.5 V or 3.3 V. The reference voltage (VREF) is 1 V. Differential Standards These standards require two I/Os per signal (called a "signal pair"). Logic values are determined by the potential difference between the lines, not with respect to ground. This is why differential drivers and receivers have much better noise immunity than single-ended standards. The differential interface standards offer higher performance and lower power consumption than their single-ended counterparts. Two I/O pins are used for each data transfer channel. Both differential standards require resistor termination. VCCI OUTp INp DEVICE 1 OUTn INn GND VREF VCCI DEVICE 2 GND VREF Figure 7-8 * Differential Topology LVPECL (Low-Voltage Positive Emitter Coupled Logic) LVPECL requires that one data bit be carried through two signal lines; therefore, two pins are needed per input or output. It also requires external resistor termination. The voltage swing between the two signal lines is approximately 850 mV. When the power supply is +3.3 V, it is commonly referred to as Low-Voltage PECL (LVPECL). Refer to the device datasheet for the full implementation of the LVPECL transmitter and receiver. LVDS (Low-Voltage Differential Signal) LVDS is a moderate-speed differential signaling system, in which the transmitter generates two different voltages that are compared at the receiver. LVDS uses a differential driver connected to a terminated receiver through a constant-impedance transmission line. It requires that one data bit be carried through two signal lines; therefore, the user will need two pins per input or output. It also requires external resistor termination. The voltage swing between the two signal lines is approximately 350 mV. VCCI is 2.5 V. Low-power flash devices contain dedicated circuitry supporting a high-speed LVDS standard that has its own user specification. Refer to the device datasheet for the full implementation of the LVDS transmitter and receiver. v1.4 7 - 13 I/O Structures in IGLOOe and ProASIC3E Devices B-LVDS/M-LVDS Bus LVDS (B-LVDS) refers to bus interface circuits based on LVDS technology. Multipoint LVDS (M-LVDS) specifications extend the LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The driver requires series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus, since the driver can be located anywhere on the bus. These configurations can be implemented using TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 7-9. The input and output buffer delays are available in the LVDS sections in the datasheet. Example: For a bus consisting of 20 equidistant loads, the terminations given in EQ 7-1 provide the required differential voltage, in worst case industrial operating conditions, at the farthest receiver: RS = 60 , RT = 70 , given ZO = 50 (2") and Zstub = 50 (~1.5"). EQ 7-1 Receiver Transceiver EN + R RS Driver D EN - + RS T RS - + RS Receiver EN EN RS Transceiver + RS R RS Zstub Zstub Zstub Zstub Zstub Zstub Zstub Z0 Z0 Z0 Z0 EN - + RS Zstub RS ... Zstub Z0 RT BIBUF_LVDS RS Zstub Z0 Z0 Z0 Z0 Z0 Z0 Figure 7-9 * A B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers 7 -1 4 T v1.4 Z0 RT I/O Structures in IGLOOe and Pro ASIC3E Devices I/O Features Low-power flash devices support multiple I/O features that make board design easier. For example, an I/O feature like Schmitt Trigger in the ProASIC3E input buffer saves the board space that would be used by an external Schmitt trigger for a slow or noisy input signal. These features are also programmable for each I/O, which in turn gives flexibility in interfacing with other components. The following is a detailed description of all available features in low-power flash devices. I/O Programmable Features Low-power flash devices offer many flexible I/O features to support a wide variety of board designs. Some of the features are programmable, with a range for selection. Table 7-8 lists programmable I/O features and their ranges. Table 7-8 * Programmable I/O Features (user control via I/O Attribute Editor) Feature Description Range Slew Control Output slew rate HIGH, LOW Output Drive (mA) Output drive strength Skew Control Output tristate enable delay option Resistor Pull Resistor pull circuit Input Delay Input delay OFF, 0-7 Schmitt Trigger Schmitt trigger for input only ON, OFF 2, 4, 6, 8, 12, 16, 24 ON, OFF Up, Down, None Note: Limitations of these features with respect to different devices are discussed in later sections. Hot-Swap Support A pull-up clamp diode must not be present in the I/O circuitry if the hot-swap feature is used. The 3.3 V PCI standard requires a pull-up clamp diode on the I/O, so it cannot be selected if hot-swap capability is required. The A3P030 device does not support 3.3 V PCI, so it is the only device in the ProASIC3 family that supports the hot-swap feature. All devices in the ProASIC3E family are hotswappable. All standards except LVCMOS 2.5/5.0 V and 3.3 V PCI/PCI-X support the hot-swap feature. The hot-swap feature appears as a read-only check box in the I/O Attribute Editor that shows whether an I/O is hot-swappable or not. Refer to Power-Up/-Down Behavior of Low-Power Flash Devices for details on hot-swapping. Hot-swapping (also called hot-plugging) is the operation of hot insertion or hot removal of a card in a powered-up system. The levels of hot-swap support and examples of related applications are described in Table 7-9 on page 7-16 to Table 7-12 on page 7-17. The I/Os also need to be configured in hot-insertion mode if hot-plugging compliance is required. The AGL030 and A3P030 devices have an I/O structure that allows the support of Level 3 and Level 4 hot-swap with only two levels of staging. v1.4 7 - 15 I/O Structures in IGLOOe and ProASIC3E Devices Table 7-9 * Hot-Swap Level 1 Description Cold-swap Power Applied to Device No Bus State - Card Ground Connection - Device Circuitry Connected to Bus Pins - Example Application System and card with Actel FPGA chip are powered down, and the card is plugged into the system. Then the power supplies are turned on for the system but not for the FPGA on the card. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices: Compliant Other IGLOO/ProASIC3 devices: Compliant if bus switch used to isolate FPGA I/Os from rest of system IGLOOe/ProASIC3E devices: Compliant I/Os can, but do not have to be set to hot-insertion mode. Table 7-10 * Hot-Swap Level 2 Description Hot-swap while reset Power Applied to Device Yes Bus State Held in reset state Card Ground Connection Reset must be maintained for 1 ms before, during, and after insertion/removal. Device Circuitry Connected to Bus Pins - Example Application In the PCI hot-plug specification, reset control circuitry isolates the card busses until the card supplies are at their nominal operating levels and stable. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices, all IGLOOe/ProASIC3E devices: Compliant I/Os can but do not have to be set to hot-insertion mode. Other IGLOO/ProASIC3 devices: Compliant 7 -1 6 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices Table 7-11 * Hot-Swap Level 3 Description Hot-swap while bus idle Power Applied to Device Yes Bus State Held idle (no ongoing I/O processes during insertion/removal) Card Ground Connection Reset must be maintained for 1 ms before, during, and after insertion/removal. Device Circuitry Connected to Bus Pins Must remain glitch-free during power-up or power-down Example Application Board bus shared with card bus is "frozen," and there is no toggling activity on the bus. It is critical that the logic states set on the bus signal not be disturbed during card insertion/removal. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices, all IGLOOe/ProASIC3E devices: Compliant with two levels of staging (first: GND; second: all other pins) Other IGLOO/ProASIC3 devices: Compliant: Option A - Two levels of staging (first: GND; second: all other pins) together with bus switch on the I/Os Option B - Three levels of staging (first: GND; second: supplies; third: all other pins) Table 7-12 * Hot-Swap Level 4 Description Hot-swap on an active bus Power Applied to Device Yes Bus State Bus may have active I/O processes ongoing, but device being inserted or removed must be idle. Card Ground Connection Reset must be maintained for 1 ms before, during, and after insertion/removal. Device Circuitry Connected to Bus Pins Must remain glitch-free during power-up or power-down Example Application There is activity on the system bus, and it is critical that the logic states set on the bus signal not be disturbed during card insertion/removal. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices, all IGLOOe/ProASIC3E devices: Compliant with two levels of staging (first: GND; second: all other pins) Other IGLOO/ProASIC3 devices: Compliant: Option A - Two levels of staging (first: GND; second: all other pins) together with bus switch on the I/Os Option B - Three levels of staging (first: GND; second: supplies; third: all other pins) v1.4 7 - 17 I/O Structures in IGLOOe and ProASIC3E Devices IGLOOe and ProASIC3E For devices requiring Level 3 and/or Level 4 compliance, the board drivers connected to the I/Os must have 10 k (or lower) output drive resistance at hot insertion, and 1 k (or lower) output drive resistance at hot removal. This resistance is the transmitter resistance sending a signal toward the I/O, and no additional resistance is needed on the board. If that cannot be assured, three levels of staging can be used to achieve Level 3 and/or Level 4 compliance. Cards with two levels of staging should have the following sequence: * Grounds * Powers, I/Os, and other pins Cold-Sparing Support Cold-sparing refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Cold-sparing is supported on ProASIC3E devices only when the user provides resistors from each power supply to ground. The resistor value is calculated based on the decoupling capacitance on a given power supply. The RC constant should be greater than 3 s. To remove resistor current during operation, it is suggested that the resistor be disconnected (e.g., with an NMOS switch) from the power supply after the supply has reached its final value. Refer to the Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the ProASIC3 and ProASIC3E handbooks for details on cold-sparing. Cold-sparing means that a subsystem with no power applied (usually a circuit board) is electrically connected to the system that is in operation. This means that all input buffers of the subsystem must present very high input impedance with no power applied so as not to disturb the operating portion of the system. The 30 k gate devices fully support cold-sparing, since the I/O clamp diode is always off (see Table 7-13 on page 7-19). If the 30 k gate device is used in applications requiring cold-sparing, a discharge path from the power supply to ground should be provided. This can be done with a discharge resistor or a switched resistor. This is necessary because the 30 k gate devices do not have built-in I/O clamp diodes. For other IGLOOe and ProASIC3E devices, since the I/O clamp diode is always active, cold-sparing can be accomplished either by employing a bus switch to isolate the device I/Os from the rest of the system or by driving each I/O pin to 0 V. If the resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitance is in parallel with the resistor). The RC time constant should ensure full discharge of supplies before cold-sparing functionality is required. The resistor is necessary to ensure that the power pins are discharged to ground every time there is an interruption of power to the device. IGLOOe and ProASIC3E devices support cold-sparing for all I/O configurations. Standards, such as PCI, that require I/O clamp diodes can also achieve cold-sparing compliance, since clamp diodes get disconnected internally when the supplies are at 0 V. When targeting low-power applications, I/O cold-sparing may add additional current if a pin is configured with either a pull-up or pull-down resistor and driven in the opposite direction. A small static current is induced on each I/O pin when the pin is driven to a voltage opposite to the weak pull resistor. The current is equal to the voltage drop across the input pin divided by the pull resistor. Refer to the "Detailed I/O DC Characteristics" section of the appropriate family datasheet for the specific pull resistor value for the corresponding I/O standard. For example, assuming an LVTTL 3.3 V input pin is configured with a weak pull-up resistor, a current will flow through the pull-up resistor if the input pin is driven LOW. For LVTTL 3.3 V, the pull-up resistor is ~45 k, and the resulting current is equal to 3.3 V / 45 k = 73 A for the I/O pin. This is true also when a weak pull-down is chosen and the input pin is driven HIGH. This current can be avoided by driving the input LOW when a weak pull-down resistor is used and driving it HIGH when a weak pull-up resistor is used. 7 -1 8 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices This current draw can occur in the following cases: * * In Active and Static modes: - Input buffers with pull-up, driven LOW - Input buffers with pull-down, driven HIGH - Bidirectional buffers with pull-up, driven LOW - Bidirectional buffers with pull-down, driven HIGH - Output buffers with pull-up, driven LOW - Output buffers with pull-down, driven HIGH - Tristate buffers with pull-up, driven LOW - Tristate buffers with pull-down, driven HIGH In Flash*Freeze mode: - Input buffers with pull-up, driven LOW - Input buffers with pull-down, driven HIGH - Bidirectional buffers with pull-up, driven LOW - Bidirectional buffers with pull-down, driven HIGH Electrostatic Discharge Protection Low-power flash devices are tested per JEDEC Standard JESD22-A114-B. These devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all device pads against damage from ESD as well as from excessive voltage transients. All IGLOO and ProASIC3 devices are tested to the following models: the Human Body Model (HBM) with a tolerance of 2,000 V, the Machine Model (MM) with a tolerance of 250 V, and the Charged Device Model (CDM) with a tolerance of 200 V. Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its negative (N) side connected to VCCI. The second diode has its P side connected to GND and its N side connected to the pad. During operation, these diodes are normally biased in the off state, except when transient voltage is significantly above VCCI or below GND levels. In 30 k gate devices, the first diode is always off. In other devices, the clamp diode is always on and cannot be switched off. By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 7-13 for more information about the I/O standards and the clamp diode. The second diode is always connected to the pad, regardless of the I/O configuration selected. Table 7-13 * I/O Hot-Swap and 5 V Input Tolerance Capabilities in IGLOOe and ProASIC3E Devices I/O Assignment 3.3 V LVTTL/LVCMOS Clamp Diode Hot Insertion 5 V Input Tolerance Input Buffer Output Buffer No Yes Yes1 Enabled/Disabled Enabled/Disabled 3.3 V PCI, 3.3 V PCI-X Yes No Yes1 LVCMOS 2.5 V 2 No Yes No Enabled/Disabled LVCMOS 2.5 V / 5.0 V 2 Yes No Yes3 Enabled/Disabled LVCMOS 1.8 V No Yes No Enabled/Disabled LVCMOS 1.5 V No Yes No Enabled/Disabled Voltage-Referenced Input Buffer No Yes No Enabled/Disabled Differential, LVDS/B-LVDS/M-LVDS/LVPECL No Yes No Enabled/Disabled Notes: 1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor. 2. In the SmartGen Core Reference Guide, select the LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25 macro for the LVCMOS 2.5 V I/O standard. 3. Can be implemented with an external resistor and an internal clamp diode. v1.4 7 - 19 I/O Structures in IGLOOe and ProASIC3E Devices 5 V Input and Output Tolerance IGLOO and ProASIC3 devices are both 5 V-input- and 5 V-output-tolerant if certain I/O standards are selected. Table 7-6 on page 7-6 shows the I/O standards that support 5 V input tolerance. Only 3.3 V LVTTL/LVCMOS standards support 5 V output tolerance. Refer to the appropriate family datasheet for detailed description and configuration information. This feature is not shown in the I/O Attribute Editor. 5 V Input Tolerance I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V, and LVCMOS 2.5 V / 5.0 V configurations are used (see Table 7-13 on page 7-19). There are four recommended solutions for achieving 5 V receiver tolerance (see Figure 7-10 on page 7-21 to Figure 7-13 on page 7-23 for details of board and macro setups). All the solutions meet a common requirement of limiting the voltage at the input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is 3.6 V, and any voltage above 3.6 V may cause long-term gate oxide failures. Solution 1 The board-level design must ensure that the reflected waveform at the pad does not exceed the limits provided in the recommended operating conditions in the datasheet. This is a requirement to ensure long-term reliability. This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the two external resistors as explained below. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. This solution requires two board resistors, as demonstrated in Figure 7-10 on page 7-21. Here are some examples of possible resistor values (based on a simplified simulation model with no line effects and 10 transmitter output resistance, where Rtx_out_high = [VCCI - VOH] / IOH and Rtx_out_low = VOL / IOL). Example 1 (high speed, high current): Rtx_out_high = Rtx_out_low = 10 R1 = 36 (5%), P(r1)min = 0.069 R2 = 82 (5%), P(r2)min = 0.158 Imax_tx = 5.5 V / (82 x 0.95 + 36 x 0.95 + 10) = 45.04 mA tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Example 2 (low-medium speed, medium current): Rtx_out_high = Rtx_out_low = 10 R1 = 220 (5%), P(r1)min = 0.018 R2 = 390 (5%), P(r2)min = 0.032 Imax_tx = 5.5 V / (220 x 0.95 + 390 x 0.95 + 10) = 9.17 mA tRISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V when the transmitter sends a logic 1. This range of Vin_dc(rx) must be assured for any combination of transmitter supply (5 V 0.5 V), transmitter output resistance, and board resistor tolerances. Temporary overshoots are allowed according to the overshoot and undershoot table in the datasheet. 7 -2 0 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices Solution 1 I/O Input 3.3 V 5.5 V Rext1 Rext2 Requires two board resistors, LVCMOS 3.3 V I/Os Figure 7-10 * Solution 1 Solution 2 The board-level design must ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-term reliability. This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the external resistors and Zener, as shown in Figure 7-11. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Solution 2 I/O Input 3.3 V 5.5 V Rext1 Zener 3.3 V Requires one board resistor, one Zener 3.3 V diode, LVCMOS 3.3 V I/Os Figure 7-11 * Solution 2 v1.4 7 - 21 I/O Structures in IGLOOe and ProASIC3E Devices Solution 3 The board-level design must ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-term reliability. This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in Figure 7-12. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Solution 3 I/O Input Bus Switch IDTQS32X23 3.3 V 5.5 V 5.5 V Requires a bus switch on the board, LVTTL/LVCMOS 3.3 V I/Os. Figure 7-12 * Solution 3 7 -2 2 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices Solution 4 The board-level design must ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-term reliability. Solution 4 I/O Input 2.5 V 5.5 V On-Chip Clamp Diode 2.5 V Rext Requires one board resistor. Available for LVCMOS 2.5 V / 5.0 V. Figure 7-13 * Solution 4 Table 7-14 * Comparison Table for 5 V-Compliant Receiver Solutions Solution Board Components 1 Two resistors 2 Resistor and Zener 3.3 V 3 Bus switch 4 Speed Low to Medium High 2,3,4,5 Minimum resistor value Current Limitations High1 Medium Limited by transmitter's drive strength Limited by transmitter's drive strength N/A Maximum diode current at 100% duty cycle, signal constantly at 1 R = 47 at TJ = 70C 52.7 mA at TJ = 70C / 10-year lifetime R = 150 at TJ = 85C 16.5 mA at TJ = 85C / 10-year lifetime R = 420 at TJ = 100C 5.9 mA at TJ = 100C / 10-year lifetime For duty cycles other than 100%, the currents can be increased by a factor of 1 / (duty cycle). Example: 20% duty cycle at 70C Maximum current = (1 / 0.2) x 52.7 mA = 5 x 52.7 mA = 263.5 mA Notes: 1. Speed and current consumption increase as the board resistance values decrease. 2. Resistor values ensure I/O diode long-term reliability. 3. At 70C, customers could still use 420 on every I/O. 4. At 85C, a 5 V solution on every other I/O is permitted, since the resistance is lower (150 ) and the current is higher. Also, the designer can still use 420 and use the solution on every I/O. 5. At 100C, the 5 V solution on every I/O is permitted, since 420 are used to limit the current to 5.9 mA. v1.4 7 - 23 I/O Structures in IGLOOe and ProASIC3E Devices 5 V Output Tolerance IGLOO and ProASIC3 I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is also critical that there be NO external I/O pull-up resistor to 5 V, since this resistor would pull the I/O pad voltage beyond the 3.6 V absolute maximum value and consequently cause damage to the I/O. When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, the I/Os can directly drive signals into 5 V TTL receivers. In fact, VOL = 0.4 V and VOH = 2.4 V in both 3.3 V LVTTL and 3.3 V LVCMOS modes exceeds the VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level 1 and level 0 will be recognized correctly by 5 V TTL receivers. Schmitt Trigger A Schmitt trigger is a buffer used to convert a slow or noisy input signal into a clean one before passing it to the FPGA. Using Schmitt trigger buffers guarantees a fast, noise-free input signal to the FPGA. ProASIC3E devices have Schmitt triggers built into their I/O circuitry. The Schmitt trigger is available for the LVTTL, LVCMOS, and 3.3 V PCI I/O standards. This feature can be implemented by using a Physical Design Constraints (PDC) command (Table 7-6 on page 7-6) or by selecting a check box in the I/O Attribute Editor in Designer. The check box is cleared by default. Selectable Skew between Output Buffer Enable and Disable Times Low-power flash devices have a configurable skew block in the output buffer circuitry that can be enabled to delay output buffer assertion without affecting deassertion time. Since this skew block is only available for the OE signal, the feature can be used in tristate and bidirectional buffers. A typical 1.2 ns delay is added to the OE signal to prevent potential bus contention. Refer to the appropriate family datasheet for detailed timing diagrams and descriptions. The Skew feature is available for all I/O standards. This feature can be implemented by using a PDC command (Table 7-6 on page 7-6) or by selecting a check box in the I/O Attribute Editor in Designer. The check box is cleared by default. The configurable skew block is used to delay output buffer assertion (enable) without affecting deassertion (disable) time. Output Enable ENABLE (IN) (from FPGA core) MUX ENABLE (OUT) Skew Circuit I/O Output Buffers Skew Select Figure 7-14 * Block Diagram of Output Enable Path 7 -2 4 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices ENABLE (IN) ENABLE (OUT) Less than 0.1 ns Less than 0.1 ns Figure 7-15 * Timing Diagram (option 1: bypasses skew circuit) ENABLE (IN) ENABLE (OUT) 1.2 ns (typical) Less than 0.1 ns Figure 7-16 * Timing Diagram (option 2: enables skew circuit) At the system level, the skew circuit can be used in applications where transmission activities on bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention and subsequent data loss and/or transmitter over-stress due to transmitter-to-transmitter current shorts. Figure 7-17 presents an example of the skew circuit implementation in a bidirectional communication system. Figure 7-18 on page 7-26 shows how bus contention is created, and Figure 7-19 on page 7-26 shows how it can be avoided with the skew circuit. Transmitter ENABLE/ DISABLE Transmitter 1: ProASIC3 I/O Skew or Bypass Skew EN (r1) Routing Delay (t1) Transmitter 2: Generic I/O EN (b2) EN (b1) Routing Delay (t2) ENABLE(t2) ENABLE (t1) Bidirectional Data Bus Figure 7-17 * Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using IGLOO or ProASIC3 Devices v1.4 7 - 25 I/O Structures in IGLOOe and ProASIC3E Devices EN (b1) EN (b2) ENABLE (r1) ENABLE (t1) Transmitter 1: OFF Transmitter 1: ON Transmitter 1: OFF ENABLE (t2) Transmitter 2: ON Transmitter 2: OFF Bus Contention Figure 7-18 * Timing Diagram (bypasses skew circuit) EN (b1) EN (b2) ENABLE (t1) Transmitter 1: OFF Transmitter 1: ON ENABLE (t2) Transmitter 2: ON Transmitter 2: OFF Result: No Bus Contention Figure 7-19 * Timing Diagram (with skew circuit selected) 7 -2 6 v1.4 Transmitter 1: OFF I/O Structures in IGLOOe and Pro ASIC3E Devices I/O Register Combining Every I/O has several embedded registers in the I/O tile that are close to the I/O pads. Rather than using the internal register from the core, the user has the option of using these registers for faster clock-to-out timing, and external hold and setup. When combining these registers at the I/O buffer, some architectural rules must be met. Provided these rules are met, the user can enable register combining globally during Compile (as shown in the "Compiling the Design" section in the I/O Software Control in Low-Power Flash Devices section of the handbook). This feature is supported by all I/O standards. Rules for Registered I/O Function: 1. The fanout between an I/O pin (D, Y, or E) and a register must be equal to one for combining to be considered on that pin. 2. All registers (Input, Output, and Output Enable) connected to an I/O must share the same clear or preset function: - If one of the registers has a CLR pin, all the other registers that are candidates for combining in the I/O must have a CLR pin. - If one of the registers has a PRE pin, all the other registers that are candidates for combining in the I/O must have a PRE pin. - If one of the registers has neither a CLR nor a PRE pin, all the other registers that are candidates for combining must have neither a CLR nor a PRE pin. - If the clear or preset pins are present, they must have the same polarity. - If the clear or preset pins are present, they must be driven by the same signal (net). 3. Registers connected to an I/O on the Output and Output Enable pins must have the same clock and enable function: - Both the Output and Output Enable registers must have an E pin (clock enable), or none at all. - If the E pins are present, they must have the same polarity. The CLK pins must also have the same polarity. In some cases, the user may want registers to be combined with the input of a bibuf while maintaining the output as-is. This can be achieved by using PDC commands as follows: set_io <signal name> -REGISTER yes ------register will combine set_preserve <signal name> ----register will not combine Weak Pull-Up and Weak Pull-Down Resistors When the I/O is pulled up, it is connected to the VCCI of its corresponding I/O bank. When it is pulled down, it is connected to GND. Refer to the datasheet for more information. For low-power applications, configuration of the pull-up or pull-down of the I/O can be used to set the I/O to a known state while the device is in Flash*Freeze mode. Refer to Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices for more information. The Flash*Freeze (FF) pin cannot be configured with a weak pull-down or pull-up I/O attribute, as the signal needs to be driven at all times. Output Slew Rate Control The slew rate is the amount of time an input signal takes to get from logic LOW to logic HIGH or vice versa. It is commonly defined as the propagation delay between 10% and 90% of the signal's voltage swing. Slew rate control is available for the output buffers of low-power flash devices. The output buffer has a programmable slew rate for both HIGH-to-LOW and LOW-to-HIGH transitions. Slew rate control is available for LVTTL, LVCMOS, and PCI-X I/O standards. The other I/O standards have a preset slew value. v1.4 7 - 27 I/O Structures in IGLOOe and ProASIC3E Devices The slew rate can be implemented by using a PDC command (Table 7-6 on page 7-6), setting it "High" or "Low" in the I/O Attribute Editor in Designer, or instantiating a special I/O macro. The default slew rate value is "High." IGLOOe and ProASIC3E devices support output slew rate control: high and low. Actel recommends the high slew rate option to minimize the propagation delay. This high-speed option may introduce noise into the system if appropriate signal integrity measures are not adopted. Selecting a low slew rate reduces this kind of noise but adds some delays in the system. Low slew rate is recommended when bus transients are expected. Output Drive The output buffers of IGLOOe and ProASIC3E devices can provide multiple drive strengths to meet signal integrity requirements. The LVTTL and LVCMOS (except 1.2 V LVCMOS) standards have selectable drive strengths. Other standards have a preset value. Drive strength should also be selected according to the design requirements and noise immunity of the system. The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and LVCMOS 1.5 V. All other I/O standards have a high output slew rate by default. For other IGLOOe and ProASIC3E devices, refer to Table 7-15 for more information about the slew rate and drive strength specification. There will be a difference in timing between the Standard Plus I/O banks and the Advanced I/O banks. Refer to the I/O timing tables in the datasheet for the standards supported by each device. Table 7-15 * IGLOOe and ProASIC3E I/O Standards--Output Drive and Slew Rate I/O Standards 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVTTL/LVCMOS 3.3 V High Low LVCMOS 2.5 V High Low LVCMOS 2.5/5.0 V High Low LVCMOS 1.8 V - High Low LVCMOS 1.5 V - - High Low 7 -2 8 v1.4 Slew I/O Structures in IGLOOe and Pro ASIC3E Devices Simultaneously Switching Outputs (SSOs) and Printed Circuit Board Layout Each I/O voltage bank has a separate ground and power plane for input and output circuits (VMV/GNDQ for input buffers and VCCI/GND for output buffers). This isolation is necessary to minimize simultaneous switching noise from the input and output (SSI and SSO). The switching noise (ground bounce and power bounce) is generated by the output buffers and transferred into input buffer circuits, and vice versa. Since voltage bounce originates on the package inductance, the VMV and VCCI supplies have separate package pin assignments. For the same reason, GND and GNDQ also have separate pin assignments. The VMV and VCCI pins must be shorted to each other on the board. Also, the GND and GNDQ pins must be shorted to each other on the board. This will prevent unwanted current draw from the power supply. SSOs can cause signal integrity problems on adjacent signals that are not part of the SSO bus. Both inductive and capacitive coupling parasitics of bond wires inside packages and of traces on PCBs will transfer noise from SSO busses onto signals adjacent to those busses. Additionally, SSOs can produce ground bounce noise and VCCI dip noise. These two noise types are caused by rapidly changing currents through GND and VCCI package pin inductances during switching activities (EQ 7-2 and EQ 7-3). Ground bounce noise voltage = L(GND) x di/dt EQ 7-2 VCCI dip noise voltage = L(VCCI) x di/dt EQ 7-3 Any group of four or more input pins switching on the same clock edge is considered an SSO bus. The shielding should be done both on the board and inside the package unless otherwise described. In-package shielding can be achieved in several ways; the required shielding will vary depending on whether pins next to the SSO bus are LVTTL/LVCMOS inputs, LVTTL/LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL inputs and outputs. Board traces in the vicinity of the SSO bus have to be adequately shielded from mutual coupling and inductive noise that can be generated by the SSO bus. Also, noise generated by the SSO bus needs to be reduced inside the package. PCBs perform an important function in feeding stable supply voltages to the IC and, at the same time, maintaining signal integrity between devices. Key issues that need to be considered are as follows: * Power and ground plane design and decoupling network design * Transmission line reflections and terminations For extensive data per package on the SSO and PCB issues, refer to the ProASIC3/E SSO and Pin Placement and Guidelines chapter of the handbook. v1.4 7 - 29 I/O Structures in IGLOOe and ProASIC3E Devices I/O Software Support In Actel's Libero IDE software, default settings have been defined for the various I/O standards supported. Changes can be made to the default settings via the use of attributes; however, not all I/O attributes are applicable for all I/O standards. Table 7-16 lists the valid I/O attributes that can be manipulated by the user for each I/O standard. Single-ended I/O standards in low-power flash devices support up to five different drive strengths. I/O Standard SLEW (output only) OUT_DRIVE (output only) SKEW (all macros with OE) RES_PULL OUT_LOAD (output only) COMBINE_REGISTER IN_DELAY (input only) IN_DELAY_VAL (input only) SCHMITT_TRIGGER (input only) HOT_SWAPPABLE Table 7-16 * IGLOOe and ProASIC3E I/O Attributes vs. I/O Standard Applications LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 2.5/5.0 V LVCMOS 1.8 V LVCMOS 1.5 V PCI (3.3 V) GTL+ (3.3 V) GTL+ (2.5 V) GTL (3.3 V) GTL (2.5 V) HSTL Class I HSTL Class II SSTL2 Class I and II SSTL3 Class I and II LVDS, B-LVDS, M-LVDS PCI-X (3.3 V) LVPECL Table 7-17 on page 7-31 lists the default values for the above selectable I/O attributes as well as those that are preset for each I/O standard. Refer to Table 7-16 for SLEW and OUT_DRIVE settings. Table 7-18 on page 7-32 lists the voltages for the supported I/O standards. 7 -3 0 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices RES_PULL OUT_LOAD (output only) COMBINE_REGISTER IN_DELAY (input only) IN_DELAY_VAL (input only) SCHMITT_TRIGGER (input only) None 35 pF - Off 0 Off Off None 35 pF - Off 0 Off Off None 35 pF - Off 0 Off LVCMOS 1.8 V Off None 35 pF - Off 0 Off LVCMOS 1.5 V Off None 35 pF - Off 0 Off PCI (3.3 V) Off None 10 pF - Off 0 Off PCI-X (3.3 V) Off None 10 pF - Off 0 Off GTL+ (3.3 V) Off None 10 pF - Off 0 Off GTL+ (2.5 V) Off None 10 pF - Off 0 Off GTL (3.3 V) Off None 10 pF - Off 0 Off GTL (2.5 V) Off None 10 pF - Off 0 Off HSTL Class I Off None 20 pF - Off 0 Off HSTL Class II Off None 20 pF - Off 0 Off SSTL2 Class I and II Off None 30 pF - Off 0 Off SSTL3 Class I and II Off None 30 pF - Off 0 Off LVDS, B-LVDS, M-LVDS Off None 0 pF - Off 0 Off LVPECL Off None 0 pF - Off 0 Off LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 2.5/5.0 V OUT_DRIVE (output only) Off I/O Standard SLEW (output only) SKEW (tribuf and bibuf only) Table 7-17 * IGLOOe and ProASIC3E I/O Default Attributes See Table 7-15 on page 7-28 See Table 7-15 on page 7-28 v1.4 7 - 31 I/O Structures in IGLOOe and ProASIC3E Devices Table 7-18 * Supported IGLOOe, ProASIC3L, and ProASIC3E I/O Standards and Corresponding VREF and VTT Voltages Input/Output Supply Voltage (VMVTYP/VCCI_TYP) Input Reference Voltage (VREF_TYP) Board Termination Voltage (VTT_TYP) LVTTL/ L VCMOS 3.3 V 3.30 V - - LVCMOS 2.5 V 2.50 V - - LVCMOS 2.5/5.0 V Input 2.50 V - - LVCMOS 1.8 V 1.80 V - - LVCMOS 1.5 V 1.50 V - - PCI 3.3 V 3.30 V - - PCI-X 3.3 V 3.30 V - - GTL+ 3.3 V 3.30 V 1.00 V 1.50 V GTL+ 2.5 V 2.50 V 1.00 V 1.50 V GTL 3.3 V 3.30 V 0.80 V 1.20 V GTL 2.5 V 2.50 V 0.80 V 1.20 V HSTL Class I 1.50 V 0.75 V 0.75 V HSTL Class II 1.50 V 0.75 V 0.75 V SSTL3 Class I 3.30 V 1.50 V 1.50 V SSTL3 Class II 3.30 V 1.50 V 1.50 V SSTL2 Class I 2.50 V 1.25 V 1.25 V SSTL2 Class II 2.50 V 1.25 V 1.25 V LVDS, DDR LVDS, B-LVDS, M-LVDS 2.50 V - - LVPECL 3.30 V - - I/O Standard 7 -3 2 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices IGLOOe and ProASIC3E Due to the comprehensive and flexible nature of IGLOOe and ProASIC3E device user I/Os, a naming scheme is used to show the details of each I/O (Figure 7-20 on page 7-34). The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os. I/O Nomenclature = FF/Gmn/IOuxwByVz Gmn is only used for I/Os that also have CCC access--i.e., global pins. FF = Indicates the I/O dedicated for the Flash*Freeze mode activation pin in IGLOOe only G = Global m = Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west middle) n = Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0, C1, or C2. Refer to Global Resources in Actel Low-Power Flash Devices for information about the three input pins per clock source MUX at CCC location m. u = I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise direction x = P (Positive) or N (Negative) for differential pairs, or R (Regular--single-ended) for the I/Os that support single-ended and voltage-referenced I/O standards only w = D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency does not meet the requirements for a true differential pair. B = Bank y = Bank number (0-7). The bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise direction. V = VREF z = VREF minibank number (0-4). A given voltage-referenced signal spans 16 pins (typically) in an I/O bank. Voltage banks may have multiple VREF minibanks. v1.4 7 - 33 VCOMPLA CCC/PLL VCCPLA "A" GNDQ VMV1 VCC GND VCCIB1 Bank 0 CCC/PLL "B" Bank 1 Bank 2 Bank 7 AGLE600/A3PE600 A3PE1500 AGLE3000A3PE3000 CCC/PLL "F" CCC/PLL "C" Bank 6 Bank 3 VCC VCCIB6 GND CCC/PLL "E" Bank 5 JTAG VMV6 GNDQ VCOMPLE VCCPLE VCCPLB VCOMPLB GNDQ VMV2 GNDQ VMV7 VCCIB7 GND VCC VCC VCOMPLF VCCPLF VCC GND VCCIB0 VMV0 GNDQ I/O Structures in IGLOOe and ProASIC3E Devices Bank 4 JTAG CCC/PLL "D" VCC GND VCCIB2 VCC VCOMPLC VCCPLC VCC GND VCCIB3 VMV3 VJTAG TRST TDO GNDQ VMV4 TMS TDI TCK GNDQ VCCIB4 GND VCC VCCIB5 GND VCC VMV5 GNDQ VPUMP VCOMPLD VCCPLD Figure 7-20 * User I/O Naming Conventions of IGLOOe and ProASIC3E Devices - Top View Board-Level Considerations Low-power flash devices have robust I/O features that can help in reducing board-level components. The devices offer single-chip solutions, which makes the board layout simpler and more immune to signal integrity issues. Although, in many cases, these devices resolve board-level issues, special attention should always be given to overall signal integrity. This section covers important board-level considerations to facilitate optimum device performance. Termination Proper termination of all signals is essential for good signal quality. Nonterminated signals, especially clock signals, can cause malfunctioning of the device. For general termination guidelines, refer to the Board-Level Considerations application note for Actel FPGAs. Also refer to Pin Descriptions for termination requirements for specific pins. Low-power flash I/Os are equipped with on-chip pull-up/-down resistors. The user can enable these resistors by instantiating them either in the top level of the design (refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for the available I/O macros with pull-up/-down) or in the I/O Attribute Editor in Designer if generic input or output buffers are instantiated in the top level. Unused I/O pins are configured as inputs with pull-up resistors. As mentioned earlier, low-power flash devices have multiple programmable drive strengths, and the user can eliminate unwanted overshoot and undershoot by adjusting the drive strengths. 7 -3 4 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices Power-Up Behavior Low-power flash devices are power-up/-down friendly; i.e., no particular sequencing is required for power-up and power-down. This eliminates extra board components for power-up sequencing, such as a power-up sequencer. During power-up, all I/Os are tristated, irrespective of I/O macro type (input buffers, output buffers, I/O buffers with weak pull-ups or weak pull-downs, etc.). Once I/Os become activated, they are set to the user-selected I/O macros. Refer to the Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the ProASIC3 and ProASIC3E handbooks for details. Drive Strength Low-power flash devices have up to seven programmable output drive strengths. The user can select the drive strength of a particular output in the I/O Attribute Editor or can instantiate a specialized I/O macro, such as OUTBUF_S_12 (slew = low, out_drive = 12 mA). The maximum available drive strength is 24 mA per I/O. Though no I/O should be forced to source or sink more than 24 mA indefinitely, I/Os may handle a higher amount of current (refer to the device IBIS model for maximum source/sink current) during signal transition (AC current). Every device package has its own power dissipation limit; hence, power calculation must be performed accurately to determine how much current can be tolerated per I/O within that limit. I/O Interfacing Low-power flash devices are 5 V-input- and 5 V-output-tolerant without adding any extra circuitry. Along with other low-voltage I/O macros, this 5 V tolerance makes these devices suitable for many types of board component interfacing. Table 7-19 shows some high-level interfacing examples using low-power flash devices. Table 7-19 * High-Level Interface Examples Clock Interface I/O Type Frequency Type Signals In Signals Out Data I/O GM Src Sync 125 MHz LVTTL 8 8 125 Mbps TBI Src Sync 125 MHz LVTTL 10 10 125 Mbps XSBI Src Sync 644 MHz LVDS 16 16 644 Mbps XGMI Src Sync DDR 156 MHz HSTL1 32 32 312 Mbps FlexBus 3 Sys Sync 104 MHz LVTTL 32 32 104 Pos-PHY3/SPI-3 Sys Sync 104 LVTTL 8,16,32 8,16,32 104 Mbps FlexBus 4/SPI-4.1 Src Sync 200 MHz HSTL1 16,64 16,64 200 Mbps Pos-PHY4/SPI-4.2 Src Sync DDR 311 MHz LVDS 16 16 622 Mbps SFI-4.1 Src Sync 622 MHz LVDS 16 16 622 Mbps CSIX L1 Sys Sync 250 MHz HSTL1 32,64,96,128 32,64,96,128 250 Mbps Hyper Transport Sys Sync DDR 800 MHz LVDS 2,4,8,16 2,4,8,16 1.6 Gbps Rapid I/O Parallel Sys Sync DDR 250 MHz - 1 GHz LVDS 8,16 8,16 2 Gbps LVDS 4 4 622 Mbps Star Fabric CDR Note: Sys Sync = System Synchronous Clocking, Src Sync = Source Synchronous Clocking, and CDR = Clock and Data Recovery. v1.4 7 - 35 I/O Structures in IGLOOe and ProASIC3E Devices Conclusion IGLOOe and ProASIC3E support for multiple I/O standards minimizes board-level components and makes possible a wide variety of applications. The Actel Designer software, integrated with Actel Libero IDE, presents a clear visual display of I/O assignments, allowing users to verify I/O and boardlevel design requirements before programming the device. The IGLOOe and ProASIC3E device I/O features and functionalities ensure board designers can produce low-cost and low-power FPGA applications fulfilling the complexities of contemporary design needs. Related Documents Handbook Documents Board-Level Considerations http://www.actel.com/documents/BoardLevelCons_AN.pdf DDR for Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_DDR_HBs.pdf Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices http://www.actel.com/documents/LPD_FlashFreeze_HBs.pdf Global Resources in Actel Low-Power Flash Devices http://www.actel.com/documents/LPD_Global_HBs.pdf Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions_HBs.pdf Power-Up/-Down Behavior of Low-Power Flash Devices http://www.actel.com/documents/LPD_PowerUp_HBs.pdf ProASIC3/E SSO and Pin Placement and Guidelines http://www.actel.com/documents/PA3_E_SSO_HBs.pdf User's Guides Actel Libero IDE User's Guide http://www.actel.com/documents/libero_ug.pdf IGLOO, Fusion, and ProASIC3 Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf SmartGen Core Reference Guide http://www.actel.com/documents/genguide_ug.pdf 7 -3 6 v1.4 I/O Structures in IGLOOe and Pro ASIC3E Devices Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-024-3 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v1.4) Page The terminology in the "Low-Power Flash Device I/O Support" section was revised. 7-2 (October 2008) v1.2 (June 2008) The "Low-Power Flash Device I/O Support" section was revised to include new families and make the information more concise. 7-2 v1.1 (March 2008) The following changes were Table 7-1 * Flash-Based FPGAs: in 7-2 This document was previously part of I/O Structures in IGLOO and ProASIC3 Devices. To provide information specific to IGLOOe, ProASIC3E, and ProASIC3EL, the content was separated and made into a new document. N/A v1.3 v1.0 (January 2008) made to the family descriptions * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. For information on other low-power flash family I/O structures, refer to the following documents: I/O Structures in IGLOO and ProASIC3 Devices contains information specific to IGLOO, ProASIC3, and ProASIC3L I/O features. I/O Structures in IGLOO PLUS Devices contains information specific to IGLOO PLUS I/O features. v1.4 7 - 37 8 - I/O Software Control in Low-Power Flash Devices Actel Fusion,(R) IGLOO,(R) and ProASIC(R)3 I/Os provide more design flexibility, allowing the user to control specific features by enabling certain I/O standards. Some features are selectable only for certain I/O standards, whereas others are available for all I/O standards. For example, slew control is not supported by differential I/O standards. Conversely, I/O register combining is supported by all I/O standards. For detailed information about which I/O standards and features are available on each device and each I/O type, refer to the I/O Structures section of the handbook for the device you are using. Figure 8-1 shows the various points in the software design flow where a user can provide input or control of the I/O selection and parameters. A detailed description is provided throughout this document. Design Entry 1. I/O Macro Using SmartGen 2. I/O Buffer Cell Schematic Entry 3. Instantiating I/O Library Macro in HDL Code 4. Generic Buffer Using 1, 2, 3 Method 5. Synthesis 6. Compile 6.1 I/O Assignments by PDC Import 7. I/O Assignments by Multi-View Navigator (MVN) I/O Standard Selection for Generic I/O Macro I/O Standards and VREF Assignment by I/O Bank Assigner I/O Attribute Selection for I/O Standards 8. Layout and Other Steps Figure 8-1 * User I/O Assignment Flow Chart v1.4 8-1 I/O Software Control in Low-Power Flash Devices Flash FPGAs I/O Support The flash FPGAs listed in Table 8-1 support I/Os and the functions described in this document. Table 8-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 8-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 8-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 8 -2 v1.4 I/O Software Control in Low-Power Flash Devices Software-Controlled I/O Attributes Users may modify these programmable I/O attributes using the I/O Attribute Editor. Modifying an I/O attribute may result in a change of state in Designer. Table 8-2 details which steps have to be rerun as a function of modified I/O attribute. Table 8-2 * Designer State (resulting from I/O attribute modification) Designer States I/O Attribute Compile Layout Fuse Timing Power Slew Control No No Yes Yes Yes Output Drive (mA) No No Yes Yes Yes Skew Control No No Yes Yes Yes Resistor Pull No No Yes Yes Yes Input Delay No No Yes Yes Yes Schmitt Trigger No No Yes Yes Yes OUT_LOAD No No No Yes Yes COMBINE_REGISTER Yes Yes N/A N/A N/A Notes: 1. No = Remains the same, Yes = Re-run the step, N/A = Not applicable 2. Skew control and input delay do not apply to IGLOO nano, IGLOO PLUS, and ProASIC3 nano devices. v1.4 8-3 I/O Software Control in Low-Power Flash Devices Implementing I/Os in Actel Software Actel Libero(R) Integrated Design Environment (IDE) is integrated with design entry tools such as the SmartGen macro builder, the ViewDraw schematic entry tool, and an HDL editor. It is also integrated with the synthesis and Designer tools. In this section, all necessary steps to implement the I/Os are discussed. Design Entry There are three ways to implement I/Os in a design: 1. Use the SmartGen macro builder to configure I/Os by generating specific I/O library macros and then instantiating them in top-level code. This is especially useful when creating I/O bus structures. 2. Use an I/O buffer cell in a schematic design. 3. Manually instantiate specific I/O macros in the top-level code. If technology-specific macros, such as INBUF_LVCMOS33 and OUTBUF_PCI, are used in the HDL code or schematic, the user will not be able to change the I/O standard later on in Designer. If generic I/O macros are used, such as INBUF, OUTBUF, TRIBUF, CLKBUF, and BIBUF, the user can change the I/O standard using the Designer I/O Attribute Editor tool. Using SmartGen for I/O Configuration The SmartGen tool in Libero IDE provides a GUI-based method of configuring the I/O attributes. The user can select certain I/O attributes while configuring the I/O macro in SmartGen. The steps to configure an I/O macro with specific I/O attributes are as follows: 1. Open Libero IDE. 2. On the left-hand side of the Catalog View, select I/O, as shown in Figure 8-2. Figure 8-2 * SmartGen Catalog 8 -4 v1.4 I/O Software Control in Low-Power Flash Devices 3. Expand the I/O section and double-click one of the options (Figure 8-3). Figure 8-3 * Expanded I/O Section 4. Double-click any of the varieties. The I/O Create Core window opens (Figure 8-4). Figure 8-4 * I/O Create Core Window As seen in Figure 8-4, there are five tabs to configure the I/O macro: Input Buffers, Output Buffers, Bidirectional Buffers, Tristate Buffers, and DDR. Input Buffers There are two variations: Regular and Special. If the Regular variation is selected, only the Width (1 to 128) needs to be entered. The default value for Width is 1. The Special variation has Width, Technology, Voltage Level, and Resistor Pull-Up/-Down options (see Figure 8-4). All the I/O standards and supply voltages (VCCI) supported for the device family are available for selection. v1.4 8-5 I/O Software Control in Low-Power Flash Devices Output Buffers There are two variations: Regular and Special. If the Regular variation is selected, only the Width (1 to 128) needs to be entered. The default value for Width is 1. The Special variation has Width, Technology, Output Drive, and Slew Rate options. Bidirectional Buffers There are two variations: Regular and Special. The Regular variation has Enable Polarity (Active High, Active Low) in addition to the Width option. The Special variation has Width, Technology, Output Drive, Slew Rate, and Resistor Pull-Up/-Down options. Tristate Buffers Same as Bidirectional Buffers. DDR There are eight variations: DDR with Regular Input Buffers, Special Input Buffers, Regular Output Buffers, Special Output Buffers, Regular Tristate Buffers, Special Tristate Buffers, Regular Bidirectional Buffers, and Special Bidirectional Buffers. These variations resemble the options of the previous I/O macro. For example, the Special Input Buffers variation has Width, Technology, Voltage Level, and Resistor Pull-Up/-Down options. DDR is not available on IGLOO PLUS devices. 5. Once the desired configuration is selected, click the Generate button. The Generate Core window opens (Figure 8-5). 6. Enter a name for the macro. Click OK. The core will be generated and saved to the appropriate location within the project files (Figure 8-6 on page 8-7). Figure 8-5 * Generate Core Window 7. Instantiate the I/O macro in the top-level code. The user must instantiate the DDR_REG or DDR_OUT macro in the design. Use SmartGen to generate both these macros and then instantiate them in your top level. To combine the DDR macros with the I/O, the following rules must be met: 8 -6 v1.4 I/O Software Control in Low-Power Flash Devices Rules for the DDR I/O Function * The fanout between an I/O pin (D or Y) and a DDR (DDR_REG or DDR_OUT) macro must be equal to one for the combining to happen on that pin. * If a DDR_REG macro and a DDR_OUT macro are combined on the same bidirectional I/O, they must share the same clear signal. * Registers will not be combined in an I/O in the presence of DDR combining on the same I/O. Using the I/O Buffer Schematic Cell Libero IDE includes the ViewDraw schematic entry tool. Using ViewDraw, the user can insert any supported I/O buffer cell in the top-level schematic. Figure 8-6 shows a top-level schematic with different I/O buffer cells. When synthesized, the netlist will contain the same I/O macro. Figure 8-6 * I/O Buffer Schematic Cell Usage v1.4 8-7 I/O Software Control in Low-Power Flash Devices Instantiating in HDL code All the supported I/O macros can be instantiated in the top-level HDL code (refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for a detailed list of all I/O macros). The following is an example: library ieee; use ieee.std_logic_1164.all; library proasic3e; entity TOP is port(IN2, IN1 : in std_logic; OUT1 : out std_logic); end TOP; architecture DEF_ARCH of TOP is component INBUF_LVCMOS5U port(PAD : in std_logic := 'U'; Y : out std_logic); end component; component INBUF_LVCMOS5 port(PAD : in std_logic := 'U'; Y : out std_logic); end component; component OUTBUF_SSTL3_II port(D : in std_logic := 'U'; PAD : out std_logic); end component; Other component ..... signal x, y, z.......other signals : std_logic; begin I1 : INBUF_LVCMOS5U port map(PAD => IN1, Y =>x); I2 : INBUF_LVCMOS5 port map(PAD => IN2, Y => y); I3 : OUTBUF_SSTL3_II port map(D => z, PAD => OUT1); other port mapping... end DEF_ARCH; Synthesizing the Design Libero IDE integrates with the Synplify(R) synthesis tool. Other synthesis tools can also be used with Libero IDE. Refer to the Actel Libero IDE User's Guide or Libero IDE online help for details on how to set up the Libero IDE tool profile with synthesis tools from other vendors. During synthesis, the following rules apply: * * Generic macros: - Users can instantiate generic INBUF, OUTBUF, TRIBUF, and BIBUF macros. - Synthesis will automatically infer generic I/O macros. - The default I/O technology for these macros is LVTTL. - Users will need to use the I/O Attribute Editor in Designer to change the default I/O standard if needed (see Figure 8-7 on page 8-9). Technology-specific I/O macros: - 8 -8 Technology-specific I/O macros, such as INBUF_LVCMO25 and OUTBUF_GTL25, can be instantiated in the design. Synthesis will infer these I/O macros in the netlist. v1.4 I/O Software Control in Low-Power Flash Devices - The I/O standard of technology-specific I/O macros cannot be changed in the I/O Attribute Editor (see Figure 8-7). - The user MUST instantiate differential I/O macros (LVDS/LVPECL) in the design. This is the only way to use these standards in the design. - To implement the DDR I/O function, the user must instantiate a DDR_REG or DDR_OUT macro. This is the only way to use a DDR macro in the design. Figure 8-7 * Assigning a Different I/O Standard to the Generic I/O Macro Performing Place-and-Route on the Design The netlist created by the synthesis tool should now be imported into Designer and compiled. During Compile, the user can specify the I/O placement and attributes by importing the PDC file. The user can also specify the I/O placement and attributes using ChipPlanner and the I/O Attribute Editor under MVN. Defining I/O Assignments in the PDC File A PDC file is a Tcl script file specifying physical constraints. This file can be imported to and exported from Designer. Table 8-3 shows I/O assignment constraints supported in the PDC file. Table 8-3 * Command PDC I/O Constraints Action Example Comment I/O Banks Setting Constraints set_iobank set_vref Sets the I/O supply voltage, VCCI, and the input reference voltage, VREF, for the specified I/O bank. set_iobank bankname [-vcci vcci_voltage] [-vref vref_voltage] Must use in case of mixed I/O voltage (VCCI) design set_iobank Bank7 -vcci 1.50 -vref 0.75 Assigns a VREF pin to a set_vref -bank [bankname] [pinnum] bank. Must use if voltagereferenced I/Os are used set_vref -bank Bank0 685 704 723 742 761 Note: Refer to the Actel Libero IDE User's Guide for detailed rules on PDC naming and syntax conventions. v1.4 8-9 I/O Software Control in Low-Power Flash Devices Table 8-3 * PDC I/O Constraints (continued) Command Action Example Comment set_vref_defaults Sets the default VREF set_vref_defaults bankname pins for the specified set_vref_defaults bank2 bank. This command is ignored if the bank does not need a VREF pin. I/O Attribute Constraint set_io Sets the attributes of an set_io portname [-pinname value] I/O [-fixed value] [-iostd value] [-out_drive value] [-slew value] [-res_pull value] [-schmitt_trigger value] [-in_delay value] [-skew value] [-out_load value] [-register value] set_io IN2 -pinname 28 -fixed yes -iostd LVCMOS15 -out_drive 12 -slew high -RES_PULL None -SCHMITT_TRIGGER Off -IN_DELAY Off -skew off -REGISTER No If the I/O macro is generic (e.g., INBUF) or technologyspecific (INBUF_LVCMOS25), then all I/O attributes can be assigned using this constraint. If the netlist has an I/O macro that specifies one of its attributes, that attribute cannot be changed using this constraint, though other attributes can be changed. Example: OUTBUF_S_24 (low slew, output drive 24 mA) Slew and output cannot be changed. drive I/O Region Placement Constraints define_region If any number of I/Os must Defines either a define_region be assigned to a particular rectangular region or a -name [region_name] -type [region_type] x1 y1 x2 y2 I/O region, such a region can rectilinear region be created with this define_region -name test constraint. -type inclusive 0 15 2 29 assign_region Assigns a set of macros assign_region [region name] [macro_name...] to a specified region assign_region test U12 This constraint assigns I/O macros to the I/O regions. When assigning an I/O macro, PDC naming conventions must be followed if the macro name contains special characters; e.g., if the macro name is \\$1I19\\, the correct use of escape characters is \\\\\$1I19\\\\. Note: Refer to the Actel Libero IDE User's Guide for detailed rules on PDC naming and syntax conventions. 8 -1 0 v1.4 I/O Software Control in Low-Power Flash Devices Compiling the Design During Compile, a PDC I/O constraint file can be imported along with the netlist file. If only the netlist file is compiled, certain I/O assignments need to be completed before proceeding to Layout. All constraints that can be entered in PDC can also be entered using ChipPlanner, I/O Attribute Editor, and PinEditor. There are certain rules that must be followed in implementing I/O register combining and the I/O DDR macro (refer to the I/O Registers section of the handbook for the device that you are using and the "DDR" section on page 8-6 for details). Provided these rules are met, the user can enable or disable I/O register combining by using the PDC command set_io portname -register yes|no in the I/O Attribute Editor or selecting a check box in the Compile Options dialog box (see Figure 8-8). The Compile Options dialog box appears when the design is compiled for the first time. It can also be accessed by choosing Options > Compile during successive runs. I/O register combining is off by default. The PDC command overrides the setting in the Compile Options dialog box. Figure 8-8 * Setting Register Combining During Compile Understanding the Compile Report The I/O bank report is generated during Compile and displayed in the log window. This report lists the I/O assignments necessary before Layout can proceed. When Designer is started, the I/O Bank Assigner tool is run automatically if the Layout command is executed. The I/O Bank Assigner takes care of the necessary I/O assignments. However, these assignments can also be made manually with MVN or by importing the PDC file. Refer to the "Assigning Technologies and VREF to I/O Banks" section on page 8-14 for further description. The I/O bank report can also be extracted from Designer by choosing Tools > Report and setting the Report Type to IOBank. This report has the following tables: I/O Function, I/O Technology, I/O Bank Resource Usage, and I/O Voltage Usage. This report is useful if the user wants to do I/O assignments manually. v1.4 8 - 11 I/O Software Control in Low-Power Flash Devices I/O Function Figure 8-9 shows an example of the I/O Function table included in the I/O bank report: Figure 8-9 * I/O Function Table This table lists the number of input I/Os, output I/Os, bidirectional I/Os, and differential input and output I/O pairs that use I/O and DDR registers. Certain rules must be met to implement registered and DDR I/O functions (refer to the I/O Structures section of the handbook for the device you are using and the "DDR" section on page 8-6). I/O Technology The I/O Technology table (shown in Figure 8-10) gives the values of VCCI and VREF (reference voltage) for all the I/O standards used in the design. The user should assign these voltages appropriately. Figure 8-10 * I/O Technology Table 8 -1 2 v1.4 I/O Software Control in Low-Power Flash Devices I/O Bank Resource Usage This is an important portion of the report. The user must meet the requirements stated in this table. Figure 8-11 shows the I/O Bank Resource Usage table included in the I/O bank report: Figure 8-11 * I/O Bank Resource Usage Table The example in Figure 8-11 shows that none of the I/O macros is assigned to the bank because more than one VCCI is detected. I/O Voltage Usage The I/O Voltage Usage table provides the number of VREF (E devices only) and VCCI assignments required in the design. If the user decides to make I/O assignments manually (PDC or MVN), the issues listed in this table must be resolved before proceeding to Layout. As stated earlier, VREF assignments must be made if there are any voltage-referenced I/Os. Figure 8-12 shows the I/O Voltage Usage table included in the I/O bank report. Figure 8-12 * I/O Voltage Usage Table The table in Figure 8-12 indicates that there are two voltage-referenced I/Os used in the design. Even though both of the voltage-referenced I/O technologies have the same VCCI voltage, their VREF voltages are different. As a result, two I/O banks are needed to assign the VCCI and VREF voltages. v1.4 8 - 13 I/O Software Control in Low-Power Flash Devices In addition, there are six single-ended I/Os used that have the same VCCI voltage. Since two banks are already assigned with the same VCCI voltage and there are enough unused bonded I/Os in those banks, the user does not need to assign the same VCCI voltage to another bank. The user needs to assign the other three VCCI voltages to three more banks. Assigning Technologies and VREF to I/O Banks Low-power flash devices offer a wide variety of I/O standards, including voltage-referenced standards. Before proceeding to Layout, each bank must have the required VCCI voltage assigned for the corresponding I/O technologies used for that bank. The voltage-referenced standards require the use of a reference voltage (VREF). This assignment can be done manually or automatically. The following sections describe this in detail. Manually Assigning Technologies to I/O Banks The user can import the PDC at this point and resolve this requirement. The PDC command is set_iobank [bank name] -vcci [vcci value] Another method is to use the I/O Bank Settings dialog box (MVN > Edit > I/O Bank Settings) to set up the VCCI voltage for the bank (Figure 8-13). Figure 8-13 * Setting VCCI for a Bank 8 -1 4 v1.4 I/O Software Control in Low-Power Flash Devices The procedure is as follows: 1. Select the bank to which you want VCCI to be assigned from the Choose Bank list. 2. Select the I/O standards for that bank. If you select any standard, the tool will automatically show all compatible standards that have a common VCCI voltage requirement. 3. Click Apply. 4. Repeat steps 1-3 to assign VCCI voltages to other banks. Refer to Figure 8-12 on page 8-13 to find out how many I/O banks are needed for VCCI bank assignment. Manually Assigning VREF Pins Voltage-referenced inputs require an input reference voltage (VREF). The user must assign VREF pins before running Layout. Before assigning a VREF pin, the user must set a VREF technology for the bank to which the pin belongs. VREF Rules for the Implementation of Voltage-Referenced I/O Standards The VREF rules are as follows: 1. Any I/O (except JTAG I/Os) can be used as a VREF pin. 2. One VREF pin can support up to 15 I/Os. It is recommended, but not required, that eight of them be on one side and seven on the other side (in other words, all 15 can still be on one side of VREF). 3. SSTL3 (I) and (II): Up to 40 I/Os per north or south bank in any position 4. LVPECL / GTL+ 3.3 V / GTL 3.3 V: Up to 48 I/Os per north or south bank in any position 5. SSTL2 (I) and (II) / GTL+ 2.5 V / GTL 2.5 V: Up to 72 I/Os per north or south bank in any position 6. VREF minibanks partition rule: Each I/O bank is physically partitioned into VREF minibanks. The VREF pins within a VREF minibank are interconnected internally, and consequently, only one VREF voltage can be used within each VREF minibank. If a bank does not require a VREF signal, the VREF pins of that bank are available as user I/Os. 7. The first VREF minibank includes all I/Os starting from one end of the bank to the first power triple and eight more I/Os after the power triple. Therefore, the first VREF minibank may contain (0 + 8), (2 + 8), (4 + 8), (6 + 8), or (8 + 8) I/Os. The second VREF minibank is adjacent to the first VREF minibank and contains eight I/Os, a power triple, and eight more I/Os after the triple. An analogous rule applies to all other VREF minibanks but the last. The last VREF minibank is adjacent to the previous one but contains eight I/Os, a power triple, and all I/Os left at the end of the bank. This bank may also contain (8 + 0), (8 + 2), (8 + 4), (8 + 6), or (8 + 8) available I/Os. Example: 4 I/Os Triple 8 I/Os, 8 I/Os Triple 8 I/Os, 8 I/Os Triple 2 I/Os That is, minibank A = (4 + 8) I/Os, minibank B = (8 + 8) I/Os, minibank C = (8 + 2) I/Os. Assigning the VREF Voltage to a Bank When importing the PDC file, the VREF voltage can be assigned to the I/O bank. The PDC command is as follows: set_iobank -vref [value] Another method for assigning VREF is by using MVN > Edit > I/O Bank Settings (Figure 8-14 on page 8-16). v1.4 8 - 15 I/O Software Control in Low-Power Flash Devices VREF for GTL+ 3.3 V Figure 8-14 * Selecting VREF Voltage for the I/O Bank Assigning VREF Pins for a Bank The user can use default pins for VREF. In this case, select the Use default pins for VREFs check box (Figure 8-14). This option guarantees full VREF coverage of the bank. The equivalent PDC command is as follows: set_vref_default [bank name] To be able to choose VREF pins, adequate VREF pins must be created to allow legal placement of the compatible voltage-referenced I/Os. To assign VREF pins manually, the PDC command is as follows: set_vref -bank [bank name] [package pin numbers] For ChipPlanner/PinEditor to show the range of a VREF pin, perform the following steps: 1. Assign VCCI to a bank using MVN > Edit > I/O Bank Settings. 2. Open ChipPlanner. Zoom in on an I/O package pin in that bank. 3. Highlight the pin and then right-click. Choose Use Pin for VREF. 8 -1 6 v1.4 I/O Software Control in Low-Power Flash Devices 4. Right-click and then choose Highlight VREF range. All the pins covered by that VREF pin will be highlighted (Figure 8-15). Figure 8-15 * VREF Range Using PinEditor or ChipPlanner, VREF pins can also be assigned (Figure 8-16). Figure 8-16 * Assigning VREF from PinEditor To unassign a VREF pin: 1. Select the pin to unassign. 2. Right-click and choose Use Pin for VREF. The check mark next to the command disappears. The VREF pin is now a regular pin. Resetting the pin may result in unassigning I/O cores, even if they are locked. In this case, a warning message appears so you can cancel the operation. After you assign the VREF pins, right-click a VREF pin and choose Highlight VREF Range to see how many I/Os are covered by that pin. To unhighlight the range, choose Unhighlight All from the Edit menu. v1.4 8 - 17 I/O Software Control in Low-Power Flash Devices Automatically Assigning Technologies to I/O Banks The I/O Bank Assigner (IOBA) tool runs automatically when you run Layout. You can also use this tool from within the MultiView Navigator (Figure 8-18). The IOBA tool automatically assigns technologies and VREF pins (if required) to every I/O bank that does not currently have any technologies assigned to it. This tool is available when at least one I/O bank is unassigned. To automatically assign technologies to I/O banks, choose I/O Bank Assigner from the Tools menu (or click the I/O Bank Assigner's toolbar button, shown in Figure 8-17). Figure 8-17 * I/O Bank Assigner's Toolbar Button Messages will appear in the Output window informing you when the automatic I/O bank assignment begins and ends. If the assignment is successful, the message "I/O Bank Assigner completed successfully" appears in the Output window, as shown in Figure 8-18. Figure 8-18 * I/O Bank Assigner Displays Messages in Output Window 8 -1 8 v1.4 I/O Software Control in Low-Power Flash Devices If the assignment is not successful, an error message appears in the Output window. To undo the I/O bank assignments, choose Undo from the Edit menu. Undo removes the I/O technologies assigned by the IOBA. It does not remove the I/O technologies previously assigned. To redo the changes undone by the Undo command, choose Redo from the Edit menu. To clear I/O bank assignments made before using the Undo command, manually unassign or reassign I/O technologies to banks. To do so, choose I/O Bank Settings from the Edit menu to display the I/O Bank Settings dialog box. Conclusion Actel Fusion, IGLOO, and ProASIC3 support for multiple I/O standards minimizes board-level components and makes possible a wide variety of applications. The Actel Designer software, integrated with Actel Libero IDE, presents a clear visual display of I/O assignments, allowing users to verify I/O and board-level design requirements before programming the device. The device I/O features and functionalities ensure board designers can produce low-cost and low-power FPGA applications fulfilling the complexities of contemporary design needs. Related Documents Handbook Documents DDR for Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_DDR_HBs.pdf Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices http://www.actel.com/documents/LPD_FlashFreeze_HBs.pdf Global Resources in Actel Low-Power Flash Devices http://www.actel.com/documents/LPD_Global_HBs.pdf I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf I/O Structures in IGLOO PLUS Devices http://www.actel.com/documents/IGLOOPLUS_IO_HBs.pdf I/O Structures in IGLOOe and ProASIC3E Devices http://www.actel.com/documents/IGLOOe_PA3E_IO_HBs.pdf Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions_HBs.pdf Power-Up/-Down Behavior of Low-Power Flash Devices http://www.actel.com/documents/LPD_PowerUp_HBs.pdf ProASIC3/E SSO and Pin Placement and Guidelines http://www.actel.com/documents/PA3_E_SSO_HBs.pdf User's Guides Actel Libero IDE User's Guide http://www.actel.com/documents/libero_ug.pdf IGLOO, Fusion, and ProASIC3 Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf SmartGen Core Reference Guide http://www.actel.com/documents/genguide_ug.pdf v1.4 8 - 19 I/O Software Control in Low-Power Flash Devices Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-026-3 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v1.4) Page IGLOO nano and ProASIC3 nano devices were added to Table 8-1 * Flash-Based FPGAs. 8-2 The notes for Table 8-2 * Designer State (resulting from I/O attribute modification) were revised to indicate that skew control and input delay do not apply to nano devices. 8-3 v1.2 (June 2008) The "Flash FPGAs I/O Support" section was revised to include new families and make the information more concise. 8-2 v1.1 (March 2008) The following changes were Table 8-1 * Flash-Based FPGAs: in 8-2 This document was previously part of the I/O Structures in IGLOO and ProASIC3 Devices document. The content was separated and made into a new document. N/A Table 8-2 * Designer State (resulting from I/O attribute modification) was updated to include note 2 for IGLOO PLUS. 8-3 v1.3 (October 2008) v1.0 (January 2008) 8 -2 0 made to the family descriptions * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. v1.4 9 - DDR for Actel's Low-Power Flash Devices Introduction The I/Os in Fusion, IGLOO,(R) and ProASIC(R)3 devices support Double Data Rate (DDR) mode. In this mode, new data is present on every transition (or clock edge) of the clock signal. This mode doubles the data transfer rate compared with Single Data Rate (SDR) mode, where new data is present on one transition (or clock edge) of the clock signal. Low-power flash devices have DDR circuitry built into the I/O tiles. I/Os are configured to be DDR receivers or transmitters by instantiating the appropriate special macros (examples shown in Figure 9-4 on page 9-6 and Figure 9-5 on page 9-7) and buffers (DDR_OUT or DDR_REG) in the RTL design. This document discusses the options the user can choose to configure the I/Os in this mode and how to instantiate them in the design. Double Data Rate (DDR) Architecture Low-power flash devices support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidths and signal integrity requirements, making them very efficient for implementing very high-speed systems. High-speed DDR interfaces can be implemented using LVDS. In IGLOOe, ProASIC3E, AFS600, and AFS1500 devices, DDR interfaces can also be implemented using the HSTL, SSTL, and LVPECL I/O standards. The DDR feature is primarily implemented in the FPGA core periphery and is not tied to a specific I/O technology or limited to any I/O standard. INBUF_SSTL2_I PAD PAD Y DDR_REG D DataR QR DDR_OUT DR DF Q OUTBUF_SSTL3_I D PAD DataF CLK QF CLR CLR CLR Figure 9-1 * DDR Support in Low-Power Flash Devices v1.4 9-1 DDR for Actel's Low-Power Flash Devices DDR Support in Flash-Based Devices The flash FPGAs listed in Table 9-1 support the DDR feature and the functions described in this document. Table 9-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 9-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 9-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 9 -2 v1.4 DDR for Actel's Low-Power Flash Devices I/O Cell Architecture Low-power flash devices support DDR in the I/O cells in four different modes: Input, Output, Tristate, and Bidirectional pins. For each mode, different I/O standards are supported, with most I/O standards having special sub-options. For the ProASIC3 nano and IGLOO nano devices, DDR is supported only in the 60 k, 125 k, and 250 k logic densities. Refer to Table 9-2 for a sample of the available I/O options. Additional I/O options can be found in the relevant family datasheet. Table 9-2 * DDR I/O Options DDR Register Type Receive Register Transmit Register I/O Type I/O Standard Sub-Options Input Normal None LVCMOS Voltage 1.5 V, 1.8 V, 2.5 V, 5 V (1.5 V default) Pull-Up None (default) Output Comments 3.3 V TTL (default) PCI/PCI-X None GTL/GTL+ Voltage HSTL Class I / II (I default) SSTL2/SSTL3 Class I / II (I default) LVPECL None LVDS None Normal None LVTTL Output Drive Slew Rate 2.5 V, 3.3 V (3.3 V default) 3.3 V TTL (default) 2, 4, 6, 8, 12, 16, 24, 36 mA (8 mA default) Low/high (high default) LVCMOS Voltage PCI/PCI-X None GTL/GTL+ Voltage HSTL Class I / II (I default) SSTL2/SSTL3 Class I / II (I default) LVPECL None LVDS None v1.4 1.5 V, 1.8 V, 2.5 V, 5 V (1.5 V default) 1.8 V, 2.5 V, 3.3 V (3.3 V default) 9-3 DDR for Actel's Low-Power Flash Devices Table 9-2 * DDR I/O Options (continued) DDR Register Type I/O Type I/O Standard Transmit Register (continued) Tristate Buffer Normal LVTTL Sub-Options Comments Enable Polarity Low/high (low default) Output Drive Slew Rate 2, 4, 6, 8, 12,16, 24, 36 mA (8 mA default) Low/high (high default) Enable Polarity Low/high (low default) Pull-Up/-Down None (default) LVCMOS Voltage Output Drive Slew Rate 1.5 V, 1.8 V, 2.5 V, 5 V (1.5 V default) 2, 4, 6, 8, 12, 16, 24, 36 mA (8 mA default) Low/high (high default) Enable Polarity Low/high (low default) Pull-Up/-Down None (default) PCI/PCI-X GTL/GTL+ Enable Polarity Low/high (low default) Voltage 1.8 V, 2.5 V, 3.3 V (3.3 V default) Enable Polarity Low/high (low default) HSTL Class I / II (I default) Enable Polarity Low/high (low default) SSTL2/SSTL3 Class I / II (I default) Enable Polarity Low/high (low default) Bidirectional Buffer Normal LVTTL Enable Polarity Low/high (low default) Output Drive Slew Rate 2, 4, 6, 8, 12, 16, 24, 36 mA (8 mA default) Low/high (high default) Enable Polarity Low/high (low default) Pull-Up/-Down None (default) LVCMOS Voltage 1.5 V, 1.8 V, 2.5 V, 5 V (1.5 V default) Enable Polarity Low/high (low default) Pull-Up PCI/PCI-X None (default) None Enable Polarity Low/high (low default) GTL/GTL+ Voltage 1.8 V, 2.5 V, 3.3 V (3.3 V default) Enable Polarity Low/high (low default) HSTL Class I / II (I default) Enable Polarity Low/high (low default) SSTL2/SSTL3 Class I / II (I default) Enable Polarity Low/high (low default) 9 -4 v1.4 DDR for Actel's Low-Power Flash Devices Input Support for DDR The basic structure to support a DDR input is shown in Figure 9-2. Three input registers are used to capture incoming data, which is presented to the core on each rising edge of the I/O register clock. Each I/O tile supports DDR inputs. INBUF_SSTL2_I DDR_REG Y PAD D QR PAD QR CLK QF QF CLR CLR Figure 9-2 * DDR Input Register Support in Low-Power Flash Devices Output Support for DDR The basic DDR output structure is shown in Figure 9-1 on page 9-1. New data is presented to the output every half clock cycle. Note: DDR macros and I/O registers do not require additional routing. The combiner automatically recognizes the DDR macro and pushes its registers to the I/O register area at the edge of the chip. The routing delay from the I/O registers to the I/O buffers is already taken into account in the DDR macro. DDR_OUT DataR DataF DR DF Q OUTBUF_SSTL3_I D PAD CLK CLR CLR Figure 9-3 * DDR Output Register (SSTL3 Class I) v1.4 9-5 DDR for Actel's Low-Power Flash Devices Instantiating DDR Registers Using SmartGen is the simplest way to generate the appropriate RTL files for use in the design. Figure 9-4 shows an example of using SmartGen to generate a DDR SSTL2 Class I input register. SmartGen provides the capability to generate all of the DDR I/O cells as described. The user, through the graphical user interface, can select from among the many supported I/O standards. The output formats supported are Verilog, VHDL, and EDIF. Figure 9-5 on page 9-7 through Figure 9-8 on page 9-10 show the I/O cell configured for DDR using SSTL2 Class I technology. For each I/O standard, the I/O pad is buffered by a special primitive that indicates the I/O standard type. Figure 9-4 * Example of Using SmartGen to Generate a DDR SSTL2 Class I Input Register 9 -6 v1.4 DDR for Actel's Low-Power Flash Devices DDR Input Register INBUF_SSTL2_I DDR_REG Y PAD D QR PAD QR CLK QF QF CLR CLR Figure 9-5 * DDR Input Register (SSTL2 Class I) The corresponding structural representations, as generated by SmartGen, are shown below: Verilog module DDR_InBuf_SSTL2_I(PAD,CLR,CLK,QR,QF); input output PAD, CLR, CLK; QR, QF; wire Y; INBUF_SSTL2_I INBUF_SSTL2_I_0_inst(.PAD(PAD),.Y(Y)); DDR_REG DDR_REG_0_inst(.D(Y),.CLK(CLK),.CLR(CLR),.QR(QR),.QF(QF)); endmodule VHDL library ieee; use ieee.std_logic_1164.all; --The correct library will be inserted automatically by SmartGen library proasic3; use proasic3.all; --library fusion; use fusion.all; --library igloo; use igloo.all; entity DDR_InBuf_SSTL2_I is port(PAD, CLR, CLK : in std_logic; end DDR_InBuf_SSTL2_I; architecture DEF_ARCH of QR, QF : out std_logic) ; DDR_InBuf_SSTL2_I is component INBUF_SSTL2_I port(PAD : in std_logic := 'U'; Y : out std_logic) ; end component; component DDR_REG port(D, CLK, CLR : in std_logic := 'U'; QR, QF : out std_logic) ; end component; signal Y : std_logic ; begin INBUF_SSTL2_I_0_inst : INBUF_SSTL2_I port map(PAD => PAD, Y => Y); DDR_REG_0_inst : DDR_REG port map(D => Y, CLK => CLK, CLR => CLR, QR => QR, QF => QF); end DEF_ARCH; v1.4 9-7 DDR for Actel's Low-Power Flash Devices DDR Output Register DDR_OUT DataR DataF DR DF Q OUTBUF_SSTL3_I D PAD CLK CLR CLR Figure 9-6 * DDR Output Register (SSTL3 Class I) Verilog module DDR_OutBuf_SSTL3_I(DataR,DataF,CLR,CLK,PAD); input output DataR, DataF, CLR, CLK; PAD; wire Q, VCC; VCC VCC_1_net(.Y(VCC)); DDR_OUT DDR_OUT_0_inst(.DR(DataR),.DF(DataF),.CLK(CLK),.CLR(CLR),.Q(Q)); OUTBUF_SSTL3_I OUTBUF_SSTL3_I_0_inst(.D(Q),.PAD(PAD)); endmodule VHDL library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity DDR_OutBuf_SSTL3_I is port(DataR, DataF, CLR, CLK : in std_logic; end DDR_OutBuf_SSTL3_I; architecture DEF_ARCH of PAD : out std_logic) ; DDR_OutBuf_SSTL3_I is component DDR_OUT port(DR, DF, CLK, CLR : in std_logic := 'U'; Q : out std_logic) ; end component; component OUTBUF_SSTL3_I port(D : in std_logic := 'U'; PAD : out std_logic) ; end component; component VCC port( Y : out std_logic); end component; signal Q, VCC_1_net : std_logic ; begin VCC_2_net : VCC port map(Y => VCC_1_net); DDR_OUT_0_inst : DDR_OUT port map(DR => DataR, DF => DataF, CLK => CLK, CLR => CLR, Q => Q); OUTBUF_SSTL3_I_0_inst : OUTBUF_SSTL3_I port map(D => Q, PAD => PAD); end DEF_ARCH; 9 -8 v1.4 DDR for Actel's Low-Power Flash Devices DDR Tristate Output Register Y TrienAux Trien INV A DDR_OUT DataR DataF DR DF Q D PAD TRIBUFF_F_8U CLK CLR CLR Figure 9-7 * DDR Tristate Output Register, LOW Enable, 8 mA, Pull-Up (LVTTL) Verilog module DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp(DataR, DataF, CLR, CLK, Trien, PAD); input output DataR, DataF, CLR, CLK, Trien; PAD; wire TrienAux, Q; INV Inv_Tri(.A(Trien),.Y(TrienAux)); DDR_OUT DDR_OUT_0_inst(.DR(DataR),.DF(DataF),.CLK(CLK),.CLR(CLR),.Q(Q)); TRIBUFF_F_8U TRIBUFF_F_8U_0_inst(.D(Q),.E(TrienAux),.PAD(PAD)); endmodule VHDL library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp is port(DataR, DataF, CLR, CLK, Trien : in std_logic; PAD : out std_logic) ; end DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp; architecture DEF_ARCH of DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp is component INV port(A : in std_logic := 'U'; Y : out std_logic) ; end component; component DDR_OUT port(DR, DF, CLK, CLR : in std_logic := 'U'; Q : out std_logic) ; end component; component TRIBUFF_F_8U port(D, E : in std_logic := 'U'; PAD : out std_logic) ; end component; signal TrienAux, Q : std_logic ; begin Inv_Tri : INV v1.4 9-9 DDR for Actel's Low-Power Flash Devices port map(A => Trien, Y => TrienAux); DDR_OUT_0_inst : DDR_OUT port map(DR => DataR, DF => DataF, CLK => CLK, CLR => CLR, Q => Q); TRIBUFF_F_8U_0_inst : TRIBUFF_F_8U port map(D => Q, E => TrienAux, PAD => PAD); end DEF_ARCH; DDR Bidirectional Buffer Trien INV A Y E DDR_OUT DataR DataF DR DF Q CLK D PAD BIBUF_HSTL_I CLR CLR QR QF DDR_REG QR D Y QF CLR Figure 9-8 * DDR Bidirectional Buffer, LOW Output Enable (HSTL Class II) Verilog module DDR_BiDir_HSTL_I_LowEnb(DataR,DataF,CLR,CLK,Trien,QR,QF,PAD); input output inout DataR, DataF, CLR, CLK, Trien; QR, QF; PAD; wire TrienAux, D, Q; INV Inv_Tri(.A(Trien), .Y(TrienAux)); DDR_OUT DDR_OUT_0_inst(.DR(DataR),.DF(DataF),.CLK(CLK),.CLR(CLR),.Q(Q)); DDR_REG DDR_REG_0_inst(.D(D),.CLK(CLK),.CLR(CLR),.QR(QR),.QF(QF)); BIBUF_HSTL_I BIBUF_HSTL_I_0_inst(.PAD(PAD),.D(Q),.E(TrienAux),.Y(D)); endmodule 9 -1 0 v1.4 DDR for Actel's Low-Power Flash Devices VHDL library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity DDR_BiDir_HSTL_I_LowEnb is port(DataR, DataF, CLR, CLK, Trien : in std_logic; QR, QF : out std_logic; PAD : inout std_logic) ; end DDR_BiDir_HSTL_I_LowEnb; architecture DEF_ARCH of DDR_BiDir_HSTL_I_LowEnb is component INV port(A : in std_logic := 'U'; Y : out std_logic) ; end component; component DDR_OUT port(DR, DF, CLK, CLR : in std_logic := 'U'; Q : out std_logic) ; end component; component DDR_REG port(D, CLK, CLR : in std_logic := 'U'; QR, QF : out std_logic) ; end component; component BIBUF_HSTL_I port(PAD : inout std_logic := 'U'; D, E : in std_logic := 'U'; Y : out std_logic) ; end component; signal TrienAux, D, Q : std_logic ; begin Inv_Tri : INV port map(A => Trien, Y => TrienAux); DDR_OUT_0_inst : DDR_OUT port map(DR => DataR, DF => DataF, CLK => CLK, CLR => CLR, Q => Q); DDR_REG_0_inst : DDR_REG port map(D => D, CLK => CLK, CLR => CLR, QR => QR, QF => QF); BIBUF_HSTL_I_0_inst : BIBUF_HSTL_I port map(PAD => PAD, D => Q, E => TrienAux, Y => D); end DEF_ARCH; v1.4 9 - 11 DDR for Actel's Low-Power Flash Devices Design Example Figure 9-9 shows a simple example of a design using both DDR input and DDR output registers. The user can copy the HDL code in Actel Libero(R) Integrated Design Environment (IDE) and go through the design flow. Figure 9-10 and Figure 9-11 on page 9-13 show the netlist and ChipPlanner views of the ddr_test design. Diagrams may vary slightly for different families. INBUF_SSTL2_I PAD PAD Y DDR_REG D DataR QR DDR_OUT DR DF Q DataF CLK QF CLR CLR CLR Figure 9-9 * Design Example Figure 9-10 * DDR Test Design as Seen by NetlistViewer for IGLOO/e Devices 9 -1 2 v1.4 OUTBUF_SSTL3_I D PAD DDR for Actel's Low-Power Flash Devices Figure 9-11 * DDR Input/Output Cells as Seen by ChipPlanner for IGLOO/e Devices Verilog module Inbuf_ddr(PAD,CLR,CLK,QR,QF); input PAD, CLR, CLK; output QR, QF; wire Y; DDR_REG DDR_REG_0_inst(.D(Y), .CLK(CLK), .CLR(CLR), .QR(QR), .QF(QF)); INBUF INBUF_0_inst(.PAD(PAD), .Y(Y)); endmodule module Outbuf_ddr(DataR,DataF,CLR,CLK,PAD); input DataR, DataF, CLR, CLK; output PAD; wire Q, VCC; VCC VCC_1_net(.Y(VCC)); DDR_OUT DDR_OUT_0_inst(.DR(DataR), .DF(DataF), .CLK(CLK), .CLR(CLR), .Q(Q)); OUTBUF OUTBUF_0_inst(.D(Q), .PAD(PAD)); endmodule v1.4 9 - 13 DDR for Actel's Low-Power Flash Devices module ddr_test(DIN, CLK, CLR, DOUT); input DIN, CLK, CLR; output DOUT; Inbuf_ddr Inbuf_ddr (.PAD(DIN), .CLR(clr), .CLK(clk), .QR(qr), .QF(qf)); Outbuf_ddr Outbuf_ddr (.DataR(qr),.DataF(qf), .CLR(clr), .CLK(clk),.PAD(DOUT)); INBUF INBUF_CLR (.PAD(CLR), .Y(clr)); INBUF INBUF_CLK (.PAD(CLK), .Y(clk)); endmodule Simulation Consideration Actel DDR simulation models use inertial delay modeling by default (versus transport delay modeling). As such, pulses that are shorter than the actual gate delays should be avoided, as they will not be seen by the simulator and may be an issue in post-routed simulations. The user must be aware of the default delay modeling and must set the correct delay model in the simulator as needed. Conclusion Fusion, IGLOO, and ProASIC3 devices support a wide range of DDR applications with different I/O standards and include built-in DDR macros. The powerful capabilities provided by SmartGen and its GUI can simplify the process of including DDR macros in designs and minimize design errors. Additional considerations should be taken into account by the designer in design floorplanning and placement of I/O flip-flops to minimize datapath skew and to help improve system timing margins. Other system-related issues to consider include PLL and clock partitioning. 9 -1 4 v1.4 DDR for Actel's Low-Power Flash Devices Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-010-4 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.3 (October 2008) Changes in the Current Version (v1.4) Page IGLOO nano and ProASIC3 nano devices were added to Table 9-1 * Flash-Based FPGAs. 9-2 The "I/O Cell Architecture" section was updated with information applicable to nano devices. 9-3 The output buffer (OUTBUF_SSTL3_I) input was changed to D, instead of Q, in 9-1, 9-5, Figure 9-1 * DDR Support in Low-Power Flash Devices, Figure 9-3 * DDR Output 9-8, 9-9 Register (SSTL3 Class I), Figure 9-6 * DDR Output Register (SSTL3 Class I), Figure 9-7 * DDR Tristate Output Register, LOW Enable, 8 mA, Pull-Up (LVTTL), and the output from the DDR_OUT macro was connected to the input of the TRIBUFF macro in Figure 9-7 * DDR Tristate Output Register, LOW Enable, 8 mA, Pull-Up (LVTTL). v1.2 (June 2008) v1.1 (March 2008) The "Double Data Rate (DDR) Architecture" section was updated to include mention of the AFS600 and AFS1500 devices. 9-1 The "DDR Support in Flash-Based Devices" section was revised to include new families and make the information more concise. 9-2 The following changes were made to the family descriptions in Table 9-1 * FlashBased FPGAs: 9-2 * * v1.0 (January 2008) ProASIC3L was updated to include 1.5 V. The number of PLLs for ProASIC3E was changed from five to six. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. v1.4 9-2 9 - 15 Packaging and Pin Descriptions 10 - Pin Descriptions Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V for ProASIC(R)3/E devices, 1.5 V for IGLOO(R)/e V5 devices, and 1.2 V or 1.5 V for IGLOO/e V2 and ProASIC3L devices. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. For IGLOO/e V2 and ProASIC3L devices, VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This allows in-system programming (ISP) when VCC is at 1.5 V and the benefit of low-power operation when VCC is at 1.2 V. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on low-power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V (not supported on ProASIC3/E devices), 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane is decoupled from the simultaneous switching noise originating from the output buffer VCCI domain. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V (ProASIC3L and IGLOO/e devices only), 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V or 1.2 V, depending on the device family. * 1.5 V for IGLOO V5, IGLOOe V5, ProASIC3, and ProASIC3E devices * 1.2 V or 1.5 V for IGLOO V2, IGLOOe V2, ProASIC3L, and ProASIC3EL devices When the PLLs are not used, the Actel Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Actel recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of Clock Conditioning Circuits in IGLOO and ProASIC3 Devices for a complete board solution for the PLL analog power supply and ground. * There is one VCCPLF pin on IGLOO, IGLOO PLUS, ProASIC3L, and ProASIC3 devices. * There are six VCCPLX pins on IGLOOe, ProASIC3EL, and ProASIC3E devices. v1.3 1 0 -1 Pin Descriptions VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the Actel Designer place-androute tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. * There is one VCOMPLF pin on IGLOO, ProASIC3L, and ProASIC3 devices. * There are six VCOMPL pins (PLL ground) on IGLOOe, ProASIC3EL, and ProASIC3E devices. VJTAG JTAG Supply Voltage Low-power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Actel recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage IGLOO, ProASIC3L, and ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in the datasheet. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 F and 0.33 F capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Actel recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User-Defined Supply Pins VREF I/O Voltage Reference Reference voltage for I/O minibanks in IGLOOe, ProASIC3EL, and ProASIC3E devices. VREF pins are configured by the user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated the voltage reference I/O. Only certain I/O standards require a voltage reference--HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support the number of I/Os available in its minibank. 1 0 -2 v1.3 Pin Descriptions User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows: GL * Output buffer is disabled (with tristate value of high impedance) * Input buffer is disabled (with tristate value of high impedance) * Weak pull-up is programmed Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in Clock Conditioning Circuits in IGLOO and ProASIC3 Devices. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the I/O Structure section of the handbook for the device you are using for an explanation of the naming of global pins. FF Flash*Freeze Mode Activation Pin Flash*Freeze is available on IGLOO, ProASIC3L, and RT ProASIC3 devices. It is not supported on ProASIC3/E devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active-low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O. For IGLOOe, ProASIC3EL, and RT ProASIC3 only, the FF pin can be configured as a Schmitt trigger input. When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin should be treated as a sensitive asynchronous signal. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. v1.3 1 0 -3 Pin Descriptions Table 10-1 shows the Flash*Freeze pin location on the available packages for IGLOO and ProASIC3L devices. The Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing migration to larger or smaller IGLOO devices while maintaining the same pin location on the board. Refer to Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices for more information on I/O states during Flash*Freeze mode. Table 10-1 * Flash*Freeze Pin Location in IGLOO and ProASIC3L Family Packages (deviceindependent) IGLOO and ProASIC3L Packages Flash*Freeze Pin CS81/UC81 H2 CS121 J5 CS196 P3 QN48 14 QN68 18 QN132 B12 CS281 W2 CS201 R4 CS289 U1 VQ100 27 VQ128 34 VQ176 47 FG144 L3 FG256 T3 FG484 W6 CG/LG484 (package available only for RT ProASIC3 devices) W6 FG896 AH4 CG/LG896 (package available only for RT ProASIC3 devices) TBD PQ208 (package available only for ProASIC3L devices) 1 0 -4 PQ208-A3P250 56 PQ208-A3P600L 55 PQ2097-A3P1000L 55 PQ208-A3PE3000L 58 v1.3 Pin Descriptions JTAG Pins Low-power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used, Actel recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 10-2 for more information. Table 10-2 * Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance VJTAG at 3.3 V 200 to 1 k VJTAG at 2.5 V 200 to 1 k VJTAG at 1.8 V 500 to 1 k VJTAG at 1.5 V 500 to 1 k Notes: 1. Equivalent parallel resistance if more than one device is on the JTAG chain 2. The TCK pin can be pulled up/down. 3. The TRST pin is pulled down. TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP, and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 10-2 and must satisfy the parallel resistance value requirement. The values in Table 10-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In such cases, Actel recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. v1.3 1 0 -5 Pin Descriptions Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Related Documents Handbook Documents Clock Conditioning Circuits in IGLOO and ProASIC3 Devices http://www.actel.com/documents/LPD_CCC_HBs.pdf I/O Structures in IGLOO PLUS Devices http://www.actel.com/documents/IGLOOPLUS_IO_HBs.pdf I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf I/O Structures in IGLOOe and ProASIC3E Devices http://www.actel.com/documents/IGLOOe_PA3E_IO_HBs.pdf Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices http://www.actel.com/documents/LPD_FlashFreeze_HBs.pdf 1 0 -6 v1.3 Pin Descriptions Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet. To improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage information. No technical changes were made to the content unless explicitly listed. Part Number 51700094-011-3 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.2 (October 2008) Changes in Current Version (v1.3) Page Table 10-1 * Flash*Freeze Pin Location in IGLOO and ProASIC3L Family Packages (device-independent) was updated as follows: 10-4 The QN48, VQ128, and VQ176 packages were added. The note that CS201 and CS289 packages are available only for IGLOO PLUS devices was removed. U1 was designated as the Flash*Freeze pin for the CS289 package. v1.1 (March 2008) v1.0 (January 2008) The "FF Flash*Freeze Mode Activation Pin" section was updated to include RT ProASIC3 devices. 10-3 CG/LG484 and CG/LG896 were added to Table 10-1 * Flash*Freeze Pin Location in IGLOO and ProASIC3L Family Packages (device-independent). 10-4 The "VCCIBx I/O Supply Voltage" section was revised to note that 1.2 V is not supported for ProASIC3/E devices. The "VMVx I/O Supply Voltage (quiet)" section was updated to state that VMVx can also be 1.2 V nominal voltage on ProASIC3L and IGLOO/e devices. 10-1 The "Handbook Documents" section was revised to include the three different I/O Structures chapters for IGLOO and ProASIC3 device families. 10-6 The "VCCPLA/B/C/D/E/F PLL Supply Voltage" section and "VCOMPLA/B/C/D/E/F PLL Ground" section were revised. The "VCCPLF PLL Supply Voltage" section and "VCOMPLF PLL Ground" section were removed. 10-1 to 10-2 The following packages were added to Table 10-1 * Flash*Freeze Pin Location in IGLOO and ProASIC3L Family Packages (device-independent): UC81, QN68, CS201, and CS289. Flash*Freeze pin W2 was specified for the CS281 package. The PG208 package was changed to the correct designation of PQ208. 10-4 v1.3 1 0 -7 11 - Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Actel consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability and performance. Actel IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Actel offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. The following documents provide packaging information and device selection for low-power flash devices. Product Catalog http://www.actel.com/documents/ProdCat_PIB.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.actel.com/documents/PckgMechDrwngs.pdf This document contains the package mechanical drawings for all packages currently or previously supplied by Actel. Use the bookmarks to navigate to the package mechanical drawings. Related Documents Additional packaging materials are available at http://www.actel.com/products/solutions/package/docs.aspx. Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 5170009-012-1 Revised February 2009 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) Changes in Current Version (v1.1) Page This document now references the Product Catalog, which replaced the Product Selector Guide. 1 v1.1 1 1 -1 Programming and Security 12 - Programming Flash Devices Introduction This document provides an overview of the various programming options available for the Actel flash families. The electronic version of this document includes active links to all programming resources, which are available at http://www.actel.com/products/hardware/default.aspx. For Actel antifuse devices, refer to the Programming Antifuse Devices document. Summary of Programming Support FlashPro3 is a high-performance in-system programming (ISP) tool targeted at the latest generation of low-power flash devices offered by Actel: Fusion, IGLOO,(R) and ProASIC(R)3, including ARM(R)-enabled devices. FlashPro3 offers extremely high performance through the use of USB 2.0, is high-speed compliant for full use of the 480 Mbps bandwidth, and can program ProASIC3 devices in under 30 seconds. Powered exclusively via USB, FlashPro3 provides a VPUMP voltage of 3.3 V for programming these devices. Silicon Sculptor 3 is an easy-to-use, single-site programming tool for Actel FPGAs that delivers high data throughput and promotes ease of use while lowering the overall cost of ownership. Silicon Sculptor 3 includes a high-speed USB 2.0 interface that allows a customer to connect as many as 12 programmers to a single PC. Furthermore, Silicon Sculptor 3 is compatible with adapter modules from Silicon Sculptor II, thereby preserving a customer's investment and enabling a seamless upgrade to this latest generation of the tool. For details of programmer support for each device, refer to Table 12-6 on page 12-10. JTAG FlashPro Software FlashPro3 ProASIC3/E PDB File with Security Settings Figure 12-1 * FlashPro Programming Setup v1.3 1 2 -1 Programming Flash Devices Programming Support in Flash Devices The flash FPGAs listed in Table 12-1 support flash in-system programming and the functions described in this document. Table 12-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device ProASIC ProASIC PLUS ProASIC First generation ProASIC devices Second generation ProASIC devices Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 12-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 12-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 1 2 -2 v1.3 Programming Flash Devices General Flash Programming Information Programming Basics When choosing a programming solution, there are a number of options available. This section provides a brief overview of those options. The next sections provide more detail on those options as they apply to Actel FPGAs. Reprogrammable or One-Time-Programmable (OTP) Depending on the technology chosen, devices may be reprogrammable or one-timeprogrammable. As the name implies, a reprogrammable device can be programmed many times. Generally, the contents of such a device will be completely overwritten when it is reprogrammed. All Actel flash devices are reprogrammable. An OTP device is programmable one time only. Once programmed, no more changes can be made to the contents. Actel flash devices provide the option of disabling the reprogrammability for security purposes. This combines the convenience of reprogrammability during design verification with the security of an OTP technology for highly sensitive designs. Device Programmer or In-System Programming There are two fundamental ways to program an FPGA: using a device programmer or, if the technology permits, using in-system programming. A device programmer is a piece of equipment in a lab or on the production floor that is used for programming devices. The devices are placed into a socket mounted in a programming adapter module, and the appropriate electrical interface is applied. The device can then be placed on the board. A typical programmer, used during development, programs a single device at a time and is referred to as a single-site engineering programmer. With ISP, the device is already mounted onto the board when programming occurs, most typically via the JTAG pins. The JTAG pins can be controlled either by an on-board resource, such as a microprocessor, or by an off-board programmer through a header connection. Once mounted, it can be programmed repeatedly. If the application requires it, the system can be designed to reprogram itself using a microprocessor, without the use of any external programmer. For production, high-volume multi-site production programmers handle designs that require device programmers. In addition, Actel can preprogram devices for production, negating the need for further programming. This service is referred to as in-house programming (IHP). Live at Power-Up (LAPU) or Boot PROM Utilizing the technology of the FPGA significantly impacts board-level power-up considerations. Some technologies are nonvolatile and are considered functional, or "live," as soon as power reaches the operational level. All Actel FPGA technologies are live at power-up. By contrast, SRAM technology is volatile, and devices built using SRAM cells lose their contents when power cycling occurs. These devices must be reprogrammed every time power is applied. Such a design must include nonvolatile storage for the contents as well as the means to reprogram. There is a delay before SRAM devices are functional; other parts of the board must come alive first to reprogram these types of FPGAs. Therefore, such devices can never be part of critical boot circuits. Design Security Design security is a growing concern for systems designers. The choice of programming methodology and technology affects system security. Use of Actel programming technology is the most secure option available, providing much better protection than SRAM-based devices and ASICs. Actel provides a number of ways to ensure designs are protected. General information on design security can be found on the Actel website: http://www.actel.com/products/solutions/security/default.aspx v1.3 1 2 -3 Programming Flash Devices Programming Features for Actel Devices Actel provides two types of FPGAs: flash and antifuse (Table 12-2). Some programming methods are common to both and some are exclusive to flash. This document describes only the programming solutions supported for flash devices. Table 12-2 * Programming Features for Actel Devices Feature Flash Antifuse Reprogrammable Yes No In-system programmable Yes No One-time programmable Yes (option) Yes Live at power-up Yes Yes Secure Yes Yes Single-site programmer support Yes Yes Multi-site programmer support Yes Yes In-house programming support Yes Yes Flash Devices The flash devices supplied by Actel are reprogrammable by either a generic device programmer or ISP. Actel supports ISP using JTAG, which is supported by the FlashPro3, FlashPro Lite, FlashPro, Silicon Sculptor 3, and Silicon Sculptor II programmers. Levels of ISP support vary depending on the device chosen: * All Fusion, IGLOO, and ProASIC3 devices support ISP. * IGLOO, IGLOOe, IGLOO nano V5, and IGLOO PLUS devices can be programmed in-system when the device is using a 1.5 V supply voltage to the FPGA core. * All IGLOO V2 and ProASIC3L devices can be operated at any voltage between 1.2 V and 1.5 V; the Designer software allows 50 mV increments in the voltage. Although the device can operate at 1.2 V core voltage, the device can only be reprogrammed when the core voltage is 1.5 V. Voltage switching is required in-system to switch from a 1.2 V supply (VCC, VCCI, and VJTAG) to 1.5 V for programming. Since flash devices are nonvolatile, they are live at power-up. This is different from an SRAM-based device, which loads its programming information when it is powered up. SRAM devices require a time on the order of hundreds of milliseconds before the system is active. There are multiple levels of security available in flash devices. Use of a security key will lock the device. The device can then only be reprogrammed by first unlocking the device with the appropriate security key. It can also be locked permanently, which means there is no key that can access the device. The command to secure the device is embedded within the programming file, optionally enabled by the programming software. This is also referred to as the OTP version of flash, allowing for only a single programming instance. This is discussed in more detail in the Implementation of Security in Actel's ProASIC and ProASICPLUS Flash-Based FPGAs application note, and in the Security in Low-Power Flash Devices handbook section. Flash devices can also be programmed using single-site or multi-site programmers as well as volume programming services from Actel or other vendors. 1 2 -4 v1.3 Programming Flash Devices Types of Programming for Flash Devices The number of devices to be programmed will influence the optimal programming methodology. Those available are listed below: * * * In-system programming - Using a programmer - Using a microprocessor or microcontroller Device programmers - Single-site programmers - Multi-site programmers, batch programmers, or gang programmers - Automated production (robotic) programmers Volume programming services - Actel in-house programming - Programming centers In-System Programming Device Type Supported: Flash ISP refers to programming the FPGA after it has been mounted on the system board. The FPGA may be preprogrammed and later reprogrammed using ISP. The advantage of using ISP is the ability to update the FPGA design many times without any changes to the board. This eliminates the requirement of using a socket for the FPGA, saving cost and improving reliability. It also reduces programming hardware expenses, as the ISP methodology is die-/package-independent. There are two methods of in-system programming: external and internal. * Programmer ISP--Refer to In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 for more information. Using an external programmer and a cable, the device can be programmed through a header on the system board. In Actel documentation, this is referred to as external ISP. Actel provides FlashPro3, FlashPro Lite, FlashPro, or Silicon Sculptor 3 to perform external ISP. Note that Silicon Sculptor II and Silicon Sculptor 3 can only provide ISP for ProASIC and ProASICPLUS(R) families, not for Fusion, IGLOO, or ProASIC3. * - Advantages: Allows local control of programming and data files for maximum security. The programming algorithms and hardware are available from Actel. The only hardware required on the board is a programming header. - Limitations: A negligible board space requirement for the programming header and JTAG signal routing Microprocessor ISP--Refer to Microprocessor Programming of Actel's Low-Power Flash Devices for more information. Using a microprocessor and an external or internal memory, you can store the program in memory and use the microprocessor to perform the programming. In Actel documentation, this is referred to as internal ISP. Both the code for the programming algorithm and the FPGA programming file must be stored in memory on the board. Programming voltages must also be generated on the board. - Advantages: The programming code is stored in the system memory. An external programmer is not required during programming. - Limitations: This is the approach that requires the most design work, since some way of getting and/or storing the data is needed; a system interface to the device must be designed; and the low-level API to the programming firmware must be written and linked into the code provided by Actel. While there are benefits to this methodology, serious thought and planning should go into the decision. v1.3 1 2 -5 Programming Flash Devices Device Programmers Device Type Supported: Flash and Antifuse Device programmers are used to program a device before it is mounted on the system board. The advantage of using device programmers is that no programming hardware is required on the system board. Therefore, no additional components or board space are required. If devices are to be reprogrammed multiple times, or if the quantity of devices to be programmed is relatively low, a single-site device programmer is the simplest solution. For applications in which design security is paramount (often the case in military or space designs), the use of on-site programming maintains design security at all times. Adapter modules are purchased with the programmers to support the FPGA packages used. The FPGA is placed in the adapter module and the programming software is run from a PC. Actel supplies the programming software for all of the Actel programmers. The software allows for the selection of the correct die/package and programming files. It will then program and verify the device. * Single-site programmers A single-site programmer programs one device at a time. Actel offers Silicon Sculptor 3 as a single-site programmer. * - Advantages: Lower cost than multi-site programmers. No additional overhead for programming on the system board. Allows local control of programming and data files for maximum security. Allows on-demand programming on-site. - Limitations: Only programs one device at a time. Multi-site programmers Often referred to as batch or gang programmers, multi-site programmers can program multiple devices at the same time using the same programming file. This is often used for large volume programming and by programming houses. The sites often have independent processors and memory enabling the sites to operate concurrently, meaning each site may start programming the same file independently. This enables the operator to change one device while the other sites continue programming, which increases throughput. Multiple adapter modules for the same package are required when using a multi-site programmer. Silicon Sculptor I, II, and 3 programmers can be cascaded to program multiple devices in a chain. Multi-site programmers can also be purchased from BP Microsystems. * - Advantages: Provides the capability of programming multiple devices at the same time. No additional overhead for programming on the system board. Allows local control of programming and data files for maximum security. - Limitations: More expensive than a single-site programmer Automated production (robotic) programmers Automated production programmers are based on multi-site programmers. They consist of a large input tray holding multiple parts and a robotic arm to select and place parts into appropriate programming sockets automatically. When the programming of the parts is complete, the parts are removed and placed in a finished tray. The automated programmers are often used in volume programming houses to program parts for which the programming time is small. 1 2 -6 v1.3 Programming Flash Devices Volume Programming Services Device Type Supported: Flash and Antifuse Once the design is stable for applications with large production volumes, preprogrammed devices can be purchased. Table 12-3 describes the volume programming services. Table 12-3 * Volume Programming Services Programmer Vendor In-House Programming Distributor Programming Centers Independent Programming Centers Availability Actel Contact Actel Sales Memec Unique Contact Distribution Various Contact Vendor Advantages: As programming is outsourced, this solution is easier to implement than creating a substantial in-house programming capability. As programming houses specialize in large-volume programming, this is often the most cost-effective solution. Limitations: There are some logistical issues with the use of a programming service provider, such as the transfer of programming files and the approval of First Articles. By definition, the programming file must be released to a third-party programming house. Nondisclosure agreements (NDAs) can be signed to help ensure data protection; however, for extremely securityconscious designs, this may not be an option. * Actel In-House Programming When purchasing Actel devices in volume, IHP can be requested as part of the purchase. If this option is chosen, there is a small cost adder for each device programmed. Each device is marked with a special mark to distinguish it from blank parts. Programming files for the design will be sent to Actel. Sample parts with the design programmed, First Articles, will be returned for customer approval. Once approval of First Articles has been received, Actel will proceed with programming the remainder of the order. To request Actel IHP, contact your local Actel representative. * Distributor Programming Centers If purchases are made through a distributor, many distributors will provide programming for their customers. Consult with your preferred distributor about this option. * Independent Programming Centers There are many programming centers that specialize only in programming but are not directly affiliated with Actel or our distributors. These programming centers must follow the guidelines for programming Actel devices and use certified programmers to program Actel devices. Actel does not have recommendations for external programming centers. v1.3 1 2 -7 Programming Flash Devices Programming Solutions Details for the available programmers can be found in the programmer user's guides listed in the "Related Documents" section on page 12-15. Refer to Table 12-6 on page 12-10 for more information concerning programming solutions. All of the programmers except FlashPro3, FlashPro Lite, and FlashPro require adapter modules, which are designed to support device packages. The modules are all listed on the Actel website at http://www.actel.com/products/hardware/program_debug/ss/modules.aspx. They are not listed in this document, since this list is updated frequently with new package options and any upgrades required to improve programming yield or support new families. Table 12-4 * Programming Solutions Programmer Vendor FlashPro3 ISP Actel FlashPro Lite Only Actel Only Single Device Multi-Device Availability Yes 1 Yes Available Yes Yes1 Available Available Actel Only Yes Yes1 Actel Yes 2 Yes Cascade option (up to two) Available Silicon Sculptor II Actel Yes 2 Yes Cascade option (up to two) Available Silicon Sculptor Actel Yes Yes Cascade option (up to four) Discontinued Sculptor 6X Actel No Yes Yes Discontinued BP Microsystems No Yes Yes Contact BP Microsystems at www.bpmicro.com FlashPro Silicon Sculptor 3 BP MicroProgrammers Notes: 1. Multiple devices can be connected in the same JTAG chain for programming. 2. Silicon Sculptor II and Silicon Sculptor 3 can only provide ISP for ProASIC and ProASICPLUS families, not for Fusion, IGLOO, or ProASIC3 devices. Programmer Ordering Codes The products shown in Table 12-5 can be ordered through Actel sales and will be shipped directly from Actel. Products can also be ordered from Actel distributors, but will still be shipped directly from Actel. Table 12-5 includes ordering codes for the full kit, as well as codes for replacement items and any related hardware. Some additional products can be purchased from external suppliers for use with the programmers. Ordering codes for adapter modules used with Silicon Sculptor are available on the Actel website at http://www.actel.com/products/hardware/program_debug/ss/modules.aspx. Table 12-5 * Programming Ordering Codes Description Vendor Ordering Code FlashPro3 ISP programmer Actel FLASHPRO 3 Comment FlashPro Lite ISP programmer Actel FLASHPRO LITE Supports small programming header or large header through header converter (not included) FlashPro ISP programmer Actel FLASH PRO Supports small programming header or large header through header converter (not included) Silicon Sculptor 3 Actel SILICON-SCULPTOR 3 USB 2.0 high-speed production programmer Silicon Sculptor II Actel SILICON-SCULPTOR II Requires add-on adapter modules to support devices Silicon Sculptor ISP module Actel SMPA-ISP-ACTEL-3-KIT Uses a 2x5, RA male header connector Ships with both large and small header support * A maximum of two Silicon Sculptor II programmers can be chained together using a standard IEEE 1284 parallel port cable. 1 2 -8 v1.3 Programming Flash Devices Table 12-5 * Programming Ordering Codes (continued) Vendor Ordering Code Comment Concurrent programming cable Description Actel SS-EXPANDER Used to cascade Silicon Sculptor I programmers together* Software for Silicon Sculptor Actel ISP cable for small header Actel ISP-CABLE-S Supplied with SMPA-ISP-ACTEL-3-KIT ISP cable for large header Actel PA-ISP-CABLE Supplied with SMPA-ISP-ACTEL-3-KIT Header converter Actel Header-Converter Converts from small to large header FTSH-113-01-L-D-K Supported by FlashPro, FlashPro Lite, and Silicon Sculptor Small programming Samtec header SCULPTOR-SOFTWARE-CD http://www.actel.com/download/program_debug/ss/ In migrating to ProASIC3/E devices, an FP3-26PINADAPTER is required. 10-pin 0.1" pitch cable header (rightangle PCB mount angle) AMP 103310-1 Supported by FlashPro3 10-pin 0.1" pitch cable header (straight PCB mount angle) 3M 2510-6002UB Supported by FlashPro3 Compact Samtec programming header (10-pin 0.05" pitch, 2 rows of 5 pins) FTSH-105-01-L-D-K Supported by FlashPro3, FP3-10PIN-ADAPTER-KIT required. Used for boards where space is at a premium. Actel FP3-10PIN-ADAPTER-KIT Compact header and migration kit. Comes with Samtec FFSD-05-D-06.00-01-N (6-inch cable for connecting to compact 10-pin headers). Large programming header, 0.062" board thickness 3M 3429-6502 Supported by Silicon Sculptor by default, FlashPro and FlashPro Lite with header converter Large programming header, 0.094" to 0.125" board thickness 3M 3429-6503 Supported by Silicon Sculptor by default, FlashPro and FlashPro Lite with header converter Plug-in header, small Actel SMPA-ISP-HEADER-S Required for small header for ProASIC only; not used for ProASICPLUS Plug-in header Actel SMPA-ISP-HEADER Required for large header for ProASIC only; not used for ProASICPLUS Vacuum pens for PQ, TQ, VQ; <208 pins Actel PENVAC Vacuum pens for PQ, TQ, VQ; 208 pins Actel PENVAC-HD Migration and compact header adapter Heavy-duty, provides stronger vacuum * A maximum of two Silicon Sculptor II programmers can be chained together using a standard IEEE 1284 parallel port cable. v1.3 1 2 -9 Programming Flash Devices Programmer Device Support Refer to Table 12-6 to determine which general-purpose flash devices have programmer device support. To learn more about the different Actel families, refer to the Actel website: http://www.actel.com/products/devices.aspx. Data in Table 12-6 also applies to ARM-enabled M7 device versions of Fusion, IGLOO, and ProASIC3 devices. Refer to the appropriate family datasheets for information on die/package combinations available as ARM-enabled versions. Table 12-6 * Programmer Device Support Actel Family Fusion Device Silicon Silicon Silicon ARM- Silicon Sculptor Sculptor Sculptor FlashPro Enabled Sculptor 6X II 3 FlashPro Lite FlashPro3 AFS090 No No IGLOO AFS1500 AGL015 Yes. No No Yes. ISP support No No Yes. ISP support. No No Yes. ISP support No No Yes. ISP support No No Yes. No ISP No ISP support. support. AFS250 AFS600 Yes. No No Yes. Yes. No ISP No ISP support. support. AGL030 AGL060 AGL125 IGLOOe AGL250 AGL400 AGL600 AGL1000 AGLE600 AGLE3000 IGLOO PLUS AGLP030 No No Yes. No ISP No ISP support support. No No Yes. Yes. No ISP No ISP support support. AGLP060 AGLP125 IGLOO nano Yes. AGLN010 No No Yes. Yes. No ISP No ISP support. support. AGLN015 AGLN020 ISP support AGLN060 AGLN125 AGLN250 ProASIC3 nano A3PN010 No No Yes. Yes. No No No ISP No ISP support. support. A3PN015 A3PN020 Yes. ISP support. A3PN060 A3PN125 A3PN250 ProASIC3L A3P250L A3P600L A3P1000L A3PE3000L No No Yes. Yes. No ISP No ISP support. support. No No Yes. ISP support. * Refer to the "Certified Programming Solutions" section on page 12-12 for more information on programmer support. 1 2 -1 0 v1.3 Programming Flash Devices Table 12-6 * Programmer Device Support (continued) Actel Family ProASIC3 Device Silicon Silicon Silicon ARM- Silicon Sculptor Sculptor Sculptor FlashPro Enabled Sculptor 6X II 3 FlashPro Lite FlashPro3 A3P015 No No Yes. Yes. No No Yes. ISP support. No No Yes. ISP support. No ISP No ISP support. support. A3P030 A3P060 A3P125 ProASIC3E A3P250 A3P400 A3P600 A3P1000 A3PE600 A3PE1500 A3PE3000 ProASICPLUS APA075 APA150 APA300 No No Yes. Yes. No ISP No ISP support. support. Yes. Yes. Yes. Yes. Yes. Yes. ISP ISP ISP ISP ISP ISP support. support. support. support. support. support. No APA450 APA600 APA750 APA1000 ProASIC A500K50 Yes Yes Yes Yes Yes No No A500K130 A500K180 A500K270 * Refer to the "Certified Programming Solutions" section on page 12-12 for more information on programmer support. v1.3 1 2 - 11 Programming Flash Devices Certified Programming Solutions The Actel-certified programmers for flash devices are FlashPro3, FlashPro Lite, FlashPro, Silicon Sculptor I and II, and any programmer that is built by BP Microsystems. All other programmers are considered noncertified programmers. * FlashPro3, FlashPro Lite, FlashPro The Actel family of FlashPro device programmers provides in-system programming in an easy-to-use, compact system that supports all flash families. Whether programming a board containing a single device or multiple devices connected in a chain, the Actel line of FlashPro programmers enables fast programming and reprogramming. Programming with the FlashPro series of programmers saves board space and money as it eliminates the need for sockets on the board. There are no built-in algorithms, so there is no delay between product release and programming support. * Silicon Sculptor II Silicon Sculptor II is a robust, compact, single-device programmer with standalone software for the PC. It is designed to enable concurrent programming of multiple units from the same PC with speeds equivalent to or faster than previous Actel programmers. It replaces Silicon Sculptor I as the Actel programmer of choice. * Silicon Sculptor I and Silicon Sculptor 6X Actel no longer offers Silicon Sculptor I or Silicon Sculptor 6X for sale. Both items have been discontinued. Actel does support Silicon Sculptor I and Silicon Sculptor 6X by continuing to release new software that enables improved programming of previously covered Actel devices; new Actel devices are only supported on Silicon Sculptor II. All software support for Silicon Sculptor I and Silicon Sculptor 6X programmers will be disconnected by the end of 2005; no support for these older programmers will be offered in 2006. Actel recommends that all customers upgrade to Silicon Sculptor II or a BP multi-site programmer. * Noncertified Programmers Actel does not test programming solutions from other vendors, and CANNOT guarantee programming yield. Also, Actel will not perform any failure analysis on devices programmed by hardware from other vendors. * Programming Centers Actel programming hardware policy also applies to programming centers. Actel expects all programming centers to use certified programmers to program Actel devices. If a programming center uses noncertified programmers to program Actel devices, the "Noncertified Programmers" policy applies. Flash Programming Guidelines Preprogramming Setup Before programming, several steps are required to ensure an optimal programming yield. Use Proper Handling and Electrostatic Discharge (ESD) Precautions Actel FPGAs are sensitive electronic devices that are susceptible to damage from ESD and other types of mishandling. For more information about ESD, refer to the Actel Quality and Reliability Guide, beginning with page 41. Use the Latest Version of the Designer Software to Generate Your Programming File (recommended) The files used to program Actel flash devices (*.bit, *.stp) contain important information about the switches that will be programmed in the FPGA. Find the latest version and corresponding release notes at http://www.actel.com/download/software/designer/. Also, programming files must always be zipped during file transfer to avoid the possibility of file corruption. 1 2 -1 2 v1.3 Programming Flash Devices Use the Latest Version of the Programming Software The programming software is frequently updated to accommodate yield enhancements in FPGA manufacturing. These updates ensure maximum programming yield and minimum programming times. Before programming, always check the version of software being used to ensure it is the most recent. Depending on the programming software, refer to one of the following: * FlashPro: http://www.actel.com/download/program_debug/flashpro/ * Silicon Sculptor: http://www.actel.com/download/program_debug/ss/ Use the Most Recent Adapter Module with Silicon Sculptor Occasionally, Actel makes modifications to the adapter modules to improve programming yields and programming times. To identify the latest version of each module before programming, visit http://www.actel.com/products/hardware/program_debug/ss/modules.aspx. Perform Routine Hardware Self-Diagnostic Test * FlashPro The self-test is only applicable when programming with FlashPro and FlashPro3 programmers. It is not supported with FlashPro Lite. To run the self-diagnostic test, follow the instructions given in the "Performing a Self-Test" section of http://www.actel.com/documents/FlashPro_UG.pdf. * Silicon Sculptor The self-diagnostic test verifies correct operation of the pin drivers, power supply, CPU, memory, and adapter module. This test should be performed before every programming session. At minimum, the test must be executed every week. To perform self-diagnostic testing using the Silicon Sculptor software, perform the following steps, depending on the operating system: - DOS: From anywhere in the software, type ALT + D. - Windows: Click Device > choose Actel Diagnostic > select the Test tab > click OK. Programming Flash FPGAs Programming a flash device is a one-step process, whether programming is conducted with a socket adapter module or via ISP. The Execute function will automatically erase the device, program the flash cells, and verify that it is programmed correctly. Actel recommends confirming the security status is correct before programming. The following steps are required to program Actel flash FPGAs. Programming with FlashPro Setup Properly connect the FlashPro ribbon cable with the programming header and turn on the switch. Actel recommends running the self-test before programming any devices; see the "Perform Routine Hardware Self-Diagnostic Test" section on page 12-13. In the programming software, from the File menu, choose Connect. In the FlashPro Connect to Programmer dialog box that appears, select the port to which the FlashPro programmer is connected, and select the device family. Disable voltages from the programmer if they are available on the board. Click Connect. A successful connect or any errors appear in the Log window. Analyze Chain and Device Selection From the File menu, choose Analyze Chain. Chain details appear in the Log window. If any failures appear, refer to the error and troubleshooting section of the FlashPro User's Guide. Select the device to be programmed from the Device list. If only one device is present in the chain, performing Analyze Chain selects that device automatically from the Device list. v1.3 1 2 - 13 Programming Flash Devices Loading the STAPL file FlashPro3, FlashPro Lite, and FlashPro programmers use a STAPL (*.stp) file to program the device. To load the STAPL file, from the File menu, choose Open STAPL file, or click the Open File button on the toolbar. Selecting an Action After loading the STAPL file, select an action from the Action list. See the "Programming File Actions" section in the FlashPro User's Guide for a definition of each action. Programming the Device To program the device, in the Action list, select Program. Make the required selections and click Execute to start programming. The progress of the programming action displays in the Log window. The message "Exit 0" indicates that the device has successfully been programmed. Note: Do not interrupt the programming sequence; it may damage the device or programmer. Verify Correct Programming To verify the device is programmed with the correct STAPL file, load the STAPL file and in the Action list, click Verify. Click Execute to start the verification process. A successful verification results in "Exit 0." Note: Verification is also performed in the previous "Programming the Device" step; clicking Verify is an additional standalone option. Programming Failure Allowances Flash FPGAs are reprogrammable, so Actel tests the programmability for 100% of the devices shipped. Return Material Authorization (RMA) Policies Actel consistently strives to exceed customer expectations by continuing to improve the quality of our products and our quality management system. Actel has RMA procedures in place to address programming fallout. Customers should be mindful of the following RMA policies. All devices submitted for an RMA must be within the Actel warranty period of one year from date of shipment. Actel will reject RMAs for devices that are no longer under warranty. RMAs will only be authorized for current Actel devices. Devices that have been discontinued will not receive RMAs. All functional failure analysis requests must be initiated by opening a case with Actel Technical Support. Devices returned for failure analysis against an RMA should be in their original packaging and must have an RMA number issued by Actel. Contacting the Customer Support Group Highly skilled engineers staff the Customer Applications Center from 7:00 A.M. to 6:00 P.M., Pacific time, Monday through Friday. You can contact the center by one of the following methods: Electronic Mail You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. Actel monitors the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and contact information for efficient processing of your request. The technical support email address is tech@actel.com. Telephone Our Technical Support Hotline answers all calls. The center retrieves information, such as your name, company name, telephone number, and question. Once this is done, a case number is assigned. Then the center forwards the information to a queue where the first available applications engineer receives the data and returns your call. The phone hours are from 7:00 A.M. to 6:00 P.M., Pacific time, Monday through Friday. The Customer Applications Center number is (800) 262-1060. European customers can call +44 (0) 1256 305 600. 1 2 -1 4 v1.3 Programming Flash Devices Related Documents Below is a list of related documents, their location on the Actel website, and a brief summary of each document. Application Notes Programming Antifuse Devices http://www.actel.com/documents/AntifuseProgram_AN.pdf Implementation of Security in Actel's ProASIC and ProASICPLUS Flash-Based FPGAs http://www.actel.com/documents/Flash_Security_AN.pdf Handbook Documents Security in Low-Power Flash Devices http://www.actel.com/documents/LPD_Security_HBs.pdf In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 http://www.actel.com/documents/LPD_ISP_HBs.pdf Microprocessor Programming of Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_Microprocessor_HBs.pdf User's Guides FlashPro Programmers FlashPro3, FlashPro Lite, and FlashPro http://www.actel.com/products/hardware/program_debug/flashpro/default.aspx FlashPro User's Guide http://www.actel.com/documents/FlashPro_UG.pdf The FlashPro User's Guide includes hardware and software setup, self-test instructions, use instructions, and a troubleshooting / error message guide. Silicon Sculptor 3 and Silicon Sculptor II http://www.actel.com/products/hardware/program_debug/ss/default.aspx Other Documents http://www.actel.com/products/solutions/security/default.aspx#flashlock The security resource center describes security in Actel Flash FPGAs. Actel Quality and Reliability Guide http://www.actel.com/documents/RelGuide.pdf Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-013-3 Revised December 2008 v1.3 1 2 - 15 Programming Flash Devices List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.2 (October 2008) v1.1 (March 2008) v1.0 (January 2008) 1 2 -1 6 Changes in Current Version (v1.3) Page The "Programming Support in Flash Devices" section was updated to include IGLOO nano and ProASIC3 nano devices. 12-2 The "Flash Devices" section was updated to include information for IGLOO nano devices. The following sentence was added: IGLOO PLUS devices can also be operated at any voltage between 1.2 V and 1.5 V; the Designer software allows 50 mV increments in the voltage. 12-4 Table 12-5 * Programming Ordering Codes was updated to replace FP3-26PINADAPTER with FP3-10PIN-ADAPTER-KIT. 12-8 Table 12-6 * Programmer Device Support was updated to add IGLOO nano and ProASIC3 nano devices. AGL400 was added to the IGLOO portion of the table. 12-10 The "Programming Support in Flash Devices" section was revised to include new families and make the information more concise. 12-2 Figure 12-1 * FlashPro Programming Setup and the "Programming Support in Flash Devices" section are new. 12-1, 12-2 Table 12-6 * Programmer Device Support was updated to include A3PE600L with the other ProASIC3L devices, and the RT ProASIC3 family was added. 12-10 The "Flash Devices" section was updated to include the IGLOO PLUS family. The text, "Voltage switching is required in-system to switch from a 1.2 V core to 1.5 V core for programming," was revised to state, "Although the device can operate at 1.2 V core voltage, the device can only be reprogrammed when the core voltage is 1.5 V. Voltage switching is required in-system to switch from a 1.2 V supply (VCC, VCCI, and VJTAG) to 1.5 V for programming." 12-4 The ProASIC3L family was added to Table 12-6 * Programmer Device Support as a separate set of rows rather than combined with ProASIC3 and ProASIC3E devices. The IGLOO PLUS family was included, and AGL015 and A3P015 were added. 12-10 v1.3 13 - Security in Low-Power Flash Devices Security in Programmable Logic The need for security on FPGA programmable logic devices (PLDs) has never been greater than today. If the contents of the FPGA can be read by an external source, the intellectual property (IP) of the system is vulnerable to unauthorized copying. Actel Fusion,(R) IGLOO,(R) and ProASIC(R)3 devices contain state-of-the-art circuitry to make the flash-based devices secure during and after programming. Low-power flash devices have a built-in 128-bit Advanced Encryption Standard (AES) decryption core (except for 30 k gate devices and smaller). The decryption core facilitates secure insystem programming (ISP) of the FPGA core array fabric, the FlashROM, and the Flash Memory Blocks (FBs) in Fusion devices. The FlashROM, Flash Blocks, and FPGA core fabric can be programmed independently of each other, allowing the FlashROM or Flash Blocks to be updated without the need for change to the FPGA core fabric. Actel has incorporated the AES decryption core into the low-power flash devices and has also included the Actel flash-based lock technology, FlashLock.(R) Together, they provide leading-edge security in a programmable logic device. Configuration data loaded into a device can be decrypted prior to being written to the FPGA core using the AES 128-bit block cipher standard. The AES encryption key is stored in on-chip, nonvolatile flash memory. This document outlines the security features offered in low-power flash devices, some applications and uses, as well as the different software settings for each application. Figure 13-1 * Overview on Security v1.5 1 3 -1 Security in Low-Power Flash Devices Security Support in Flash-Based Devices The flash FPGAs listed in Table 13-1 support the security feature and the functions described in this document. Table 13-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 13-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 13-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 1 3 -2 v1.5 Security in Low-Power Flash Devices Security Architecture Fusion, IGLOO, and ProASIC3 devices have been designed with the most comprehensive programming logic design security in the industry. In the architecture of these devices, security has been designed into the very fabric. The flash cells are located beneath seven metal layers, and the use of many device design and layout techniques makes invasive attacks difficult. Since device layers cannot be removed without disturbing the charge on the programmed (or erased) flash gates, devices cannot be easily deconstructed to decode the design. Low-power flash devices are unique in being reprogrammable and having inherent resistance to both invasive and noninvasive attacks on valuable IP. Secure, remote ISP is now possible with AES encryption capability for the programming file during electronic transfer. Figure 13-2 shows a view of the AES decryption core inside an IGLOO device; Figure 13-3 on page 13-4 shows the AES decryption core inside a Fusion device. The AES core is used to decrypt the encrypted programming file when programming. Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 2 Note: *ISP AES Decryption is not supported by 30 k gate devices and smaller. For details of other architecture features by device, refer to the appropriate family datasheet. Figure 13-2 * Block Representation of the AES Decryption Core in IGLOO and ProASIC3 Devices v1.5 1 3 -3 Security in Low-Power Flash Devices Bank 0 Bank 1 CCC SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block OSC I/Os CCC/PLL Bank 2 Bank 4 VersaTile ISP AES Decryption User Nonvolatile FlashROM Flash Memory Blocks Analog Quad Analog Quad Analog Quad Analog Quad ADC Analog Quad Analog Quad Charge Pumps SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Flash Memory Blocks Analog Quad Analog Quad Analog Quad Analog Quad CCC Bank 3 Figure 13-3 * Block Representation of the AES Decryption Core in a Fusion AFS600 FPGA Security Features IGLOO and ProASIC3 devices have two entities inside: FlashROM and the FPGA core fabric. Fusion devices contain three entities: FlashROM, FBs, and the FPGA core fabric. The parts can be programmed or updated independently with a STAPL programming file. The programming files can be AES-encrypted or plaintext. This allows maximum flexibility in providing security to the entire device. Refer to FlashROM in Actel's Low-Power Flash Devices for information on the FlashROM structure. Unlike SRAM-based FPGA devices, which require a separate boot PROM to store programming data, low-power flash devices are nonvolatile, and the secured configuration data is stored in onchip flash cells that are part of the FPGA fabric. Once programmed, this data is an inherent part of the FPGA array and does not need to be loaded at system power-up. SRAM-based FPGAs load the configuration bitstream upon power-up; therefore, the configuration is exposed and can be read easily. The built-in FPGA core, FBs, and FlashROM support programming files encrypted with the 128-bit AES (FIPS-192) block ciphers. The AES key is stored in dedicated, on-chip flash memory and can be programmed before the device is shipped to other parties (allowing secure remote field updates). Security in ARM-Enabled Low-Power Flash Devices There are slight differences between the regular flash devices and the ARM(R)-enabled flash devices, which have the M1 and M7 prefix. The AES key is used by Actel and preprogrammed into the device to protect the ARM IP. As a result, the design is encrypted along with the ARM IP, according to the details below. 1 3 -4 v1.5 Security in Low-Power Flash Devices Cortex-M1 Device Security Cortex-M1-enabled devices are shipped with the following security features: * FPGA array enabled for AES-encrypted programming and verification * FlashROM enabled for AES-encrypted Write and Verify * Fusion Embedded Flash Memory enabled for AES-encrypted Write AES Encryption of Programming Files Low-power flash devices employ AES as part of the security mechanism that prevents invasive and noninvasive attacks. The mechanism entails encrypting the programming file with AES encryption and then passing the programming file through the AES decryption core, which is embedded in the device. The file is decrypted there, and the device is successfully programmed. The AES master key is stored in on-chip nonvolatile memory (flash). The AES master key can be preloaded into parts in a secure programming environment (such as the Actel In-House Programming center), and then "blank" parts can be shipped to an untrusted programming or manufacturing center for final personalization with an AES-encrypted bitstream. Late-stage product changes or personalization can be implemented easily and securely by simply sending a STAPL file with AES-encrypted data. Secure remote field updates over public networks (such as the Internet) are possible by sending and programming a STAPL file with AES-encrypted data. The AES key protects the programming data for file transfer into the device with 128-bit AES encryption. If AES encryption is used, the AES key is stored or preprogrammed into the device. To program, you must use an AES-encrypted file, and the encryption used on the file must match the encryption key already in the device. The AES key is protected by a FlashLock security Pass Key that is also implemented in each device. The AES key is always protected by the FlashLock Key, and the AES-encrypted file does NOT contain the FlashLock Key. This FlashLock Pass Key technology is exclusive to the Actel flash-based device families. FlashLock Pass Key technology can also be implemented without the AES encryption option, providing a choice of different security levels. In essence, security features can be categorized into the following three options: * AES encryption with FlashLock Pass Key protection * FlashLock protection only (no AES encryption) * No protection Each of the above options is explained in more detail in the following sections with application examples and software implementation options. Advanced Encryption Standard The 128-bit AES standard (FIPS-192) block cipher is the NIST (National Institute of Standards and Technology) replacement for DES (Data Encryption Standard FIPS46-2). AES has been designed to protect sensitive government information well into the 21st century. It replaces the aging DES, which NIST adopted in 1977 as a Federal Information Processing Standard used by federal agencies to protect sensitive, unclassified information. The 128-bit AES standard has 3.4 x 1038 possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit AES cipher text using exhaustive techniques. Keys are stored (securely) in low-power flash devices in nonvolatile flash memory. All programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. All programming verification is performed on-chip, ensuring that the contents of low-power flash devices remain secure. Actel has implemented the 128-bit AES (Rijndael) algorithm in low-power flash devices. With this key size, there are approximately 3.4 x 1038 possible 128-bit keys. DES has a 56-bit key size, which provides approximately 7.2 x 1016 possible keys. In their AES fact sheet, the National Institute of Standards and Technology uses the following hypothetical example to illustrate the theoretical security provided by AES. If one were to assume that a computing system existed that could recover a DES key in a second, it would take that same machine approximately 149 trillion years to crack a 128-bit AES key. NIST continues to make their point by stating the universe is believed to be less than 20 billion years old.1 v1.5 1 3 -5 Security in Low-Power Flash Devices The AES key is securely stored on-chip in dedicated low-power flash device flash memory and cannot be read out. In the first step, the AES key is generated and programmed into the device (for example, at a secure or trusted programming site). The Actel Designer software tool provides AES key generation capability. After the key has been programmed into the device, the device will only correctly decrypt programming files that have been encrypted with the same key. If the individual programming file content is incorrect, a Message Authentication Control (MAC) mechanism inside the device will fail in authenticating the programming file. In other words, when an encrypted programming file is being loaded into a device that has a different programmed AES key, the MAC will prevent this incorrect data from being loaded, preventing possible device damage. See Figure 13-3 on page 13-4 and Figure 13-4 on page 13-7 for graphical representations of this process. It is important to note that the user decides what level of protection will be implemented for the device. When AES protection is desired, the FlashLock Pass Key must be set. The AES key is a content protection mechanism, whereas the FlashLock Pass Key is a device protection mechanism. When the AES key is programmed into the device, the device still needs the Pass Key to protect the FPGA and FlashROM contents and the security settings, including the AES key. Using the FlashLock Pass Key prevents modification of the design contents by means of simply programming the device with a different AES key. AES Decryption and MAC Authentication Low-power flash devices have a built-in 128-bit AES decryption core, which decrypts the encrypted programming file and performs a MAC check that authenticates the file prior to programming. MAC authenticates the entire programming data stream. After AES decryption, the MAC checks the data to make sure it is valid programming data for the device. This can be done while the device is still operating. If the MAC validates the file, the device will be erased and programmed. If the MAC fails to validate, then the device will continue to operate uninterrupted. This will ensure the following: 1. 1 3 -6 * Correct decryption of the encrypted programming file * Prevention of erroneous or corrupted data being programmed during the programming file transfer * Correct bitstream passed to the device for decryption National Institute of Standards and Technology, "ADVANCED ENCRYPTION STANDARD (AES) Questions and Answers," 28 January 2002 (10 January 2005). See http://csrc.nist.gov/archive/aes/index1.html for more information. v1.5 Security in Low-Power Flash Devices IGLOO and ProASIC3 MAC Validation Actel Designer Software Decrypted Bitstream Programming File Generation with AES Encryption AES Key AES Decryption Core FlashROM FPGA Core Transmit Medium / Public Network Encrypted Bitstream Figure 13-4 * Example Application Scenario Using AES in IGLOO and ProASIC3 Devices Fusion MAC Validation Actel Designer Software Programming File Generation with AES Encryption Decrypted Bitstream AES Key AES Decryption Core FlashROM FPGA Core FBs Transmit Medium / Public Network Encrypted Bitstream Figure 13-5 * Example Application Scenario Using AES in Fusion Devices FlashLock Additional Options for IGLOO and ProASIC3 Devices The user also has the option of prohibiting Write operations to the FPGA array but allowing Verify operations on the FPGA array and/or Read operations on the FlashROM without the use of the FlashLock Pass Key. This option provides the user the freedom of verifying the FPGA array and/or reading the FlashROM contents after the device is programmed, without having to provide the FlashLock Pass Key. The user can incorporate AES encryption on the programming files to better enhance the level of security used. v1.5 1 3 -7 Security in Low-Power Flash Devices Permanent Security Setting Options In applications where a permanent lock is not desired, yet the security settings should not be modifiable, IGLOO and ProASIC3 devices can accommodate this requirement. This application is particularly useful in cases where a device is located at a remote location and must be reprogrammed with a design or data update. Refer to the "Application 3: Nontrusted Environment--Field Updates/Upgrades" section on page 13-10 for further discussion and examples of how this can be achieved. The user must be careful when considering the Permanent FlashLock or Permanent Security Settings option. Once the design is programmed with the permanent settings, it is not possible to reconfigure the security settings already employed on the device. Therefore, exercise careful consideration before programming permanent settings. Permanent FlashLock The purpose of the permanent lock feature is to provide the benefits of the highest level of security to IGLOO and ProASIC3 devices. If selected, the permanent FlashLock feature will create a permanent barrier, preventing any access to the contents of the device. This is achieved by permanently disabling Write and Verify access to the array, and Write and Read access to the FlashROM. After permanently locking the device, it has been effectively rendered one-timeprogrammable. This feature is useful if the intended applications do not require design or system updates to the device. Security in Action This section illustrates some applications of the security advantages of Actel's devices (Figure 13-6). Plaintext Source File AES Encryption Cipher Text Source File Application 3 Application 2 Application 1 Public Domain AES Decryption Core FlashROM FPGA Core Flash Device Note: Flash blocks are only used in Fusion devices. Figure 13-6 * Security Options 1 3 -8 v1.5 Flash Blocks Security in Low-Power Flash Devices Application 1: Trusted Environment As illustrated in Figure 13-7 on page 13-10, this application allows the programming of devices at design locations where research and development take place. Therefore, encryption is not necessary and is optional to the user. This is often a secure way to protect the design, since the design program files are not sent elsewhere. In situations where production programming is not available at the design location, programming centers (such as Actel In-House Programming) provide a way of programming designs at an alternative, secure, and trusted location. In this scenario, the user generates a STAPL programming file from the Designer software in plaintext format, containing information on the entire design or the portion of the design to be programmed. The user can choose to employ the FlashLock Pass Key feature with the design. Once the design is programmed to unprogrammed devices, the design is protected by this FlashLock Pass Key. If no future programming is needed, the user can consider permanently securing the IGLOO and ProASIC3 device, as discussed in the "Permanent FlashLock" section on page 13-8. Application 2: Nontrusted Environment--Unsecured Location Often, programming of devices is not performed in the same location as actual design implementation, to reduce manufacturing cost. Overseas programming centers and contract manufacturers are examples of this scenario. To achieve security in this case, the AES key and the FlashLock Pass Key can be initially programmed in-house (trusted environment). This is done by generating a programming file with only the security settings and no design contents. The design FPGA core, FlashROM, and (for Fusion) FB contents are generated in a separate programming file. This programming file must be set with the same AES key that was used to program to the device previously so the device will correctly decrypt this encrypted programming file. As a result, the encrypted design content programming file can v1.5 1 3 -9 Security in Low-Power Flash Devices be safely sent off-site to nontrusted programming locations for design programming. Figure 13-7 shows a more detailed flow for this application. OEM Trusted Environment Generates and Programs Security Settings Only (programming of the security keys) Generates Design Contents Encrypted with AES Flash Device Security Settings* Security Settings FPGA/FlashROM/FBs FPGA/FlashROM/FBs Flash Device AES and/or Pass Key Protected Programming File Sends File(s) to Manufacturer Ships Devices to Manufacturer Returns Programmed Devices to Vendor Ships Programmed Devices to End Customer Security Settings Programs Design Contents to Devices FPGA/FlashROM/FBs Contents Flash Device OEM Customers Nontrusted Manufacturing Environment Notes: 1. Programmed portion indicated with dark gray. 2. Programming of FBs applies to Fusion only. Figure 13-7 * Application 2: Device Programming in a Nontrusted Environment Application 3: Nontrusted Environment--Field Updates/Upgrades Programming or reprogramming of devices may occur at remote locations. Reconfiguration of devices in consumer products/equipment through public networks is one example. Typically, the remote system is already programmed with particular design contents. When design update (FPGA array contents update) and/or data upgrade (FlashROM and/or FB contents upgrade) is necessary, an updated programming file with AES encryption can be generated, sent across public networks, and transmitted to the remote system. Reprogramming can then be done using this AES-encrypted programming file, providing easy and secure field upgrades. Low-power flash devices support this secure ISP using AES. The detailed flow for this application is shown in Figure 13-8 on page 13-11. Refer to Microprocessor Programming of Actel's Low-Power Flash Devices for more information. To prepare devices for this scenario, the user can initially generate a programming file with the available security setting options. This programming file is programmed into the devices before shipment. During the programming file generation step, the user has the option of making the security settings permanent or not. In situations where no changes to the security settings are necessary, the user can select this feature in the software to generate the programming file with permanent security settings. Actel recommends that the programming file use encryption with an AES key, especially when ISP is done via public domain. For example, if the designer wants to use an AES key for the FPGA array and the FlashROM, Permanent needs to be chosen for this setting. At first, the user chooses the options to use an AES key for the FPGA array and the FlashROM, and then chooses Permanently lock the security settings. A unique AES key is chosen. Once this programming file is generated and programmed to 1 3 -1 0 v1.5 Security in Low-Power Flash Devices the devices, the AES key is permanently stored in the on-chip memory, where it is secured safely. The devices are sent to distant locations for the intended application. When an update is needed, a new programming file must be generated. The programming file must use the same AES key for encryption; otherwise, the authentication will fail and the file will not be programmed in the device. Trusted Environment OEM Generates Updated Design Contents Encrypted with AES AES Encrypted Programming File Transmits to Remote System Update/Upgrade Flash Device Original Design Contents AES Encrypted and FlashLock Pass Key Protected Remote Environment / System Figure 13-8 * Application 3: Nontrusted Environment--Field Updates/Upgrades FlashROM Security Use Models Each of the subsequent sections describes in detail the available selections in Actel Designer as an aid to understanding security applications and generating appropriate programming files for those applications. Before proceeding, it is helpful to review Figure 13-7 on page 13-10, which gives a general overview of the programming file generation flow within the Designer software as well as what occurs during the device programming stage. Specific settings are discussed in the following sections. In Figure 13-7 on page 13-10, the flow consists of two sub-flows. Sub-flow 1 describes programming security settings to the device only, and sub-flow 2 describes programming the design contents only. In Application 1, described in the "Application 1: Trusted Environment" section on page 13-9, the user does not need to generate separate files but can generate one programming file containing both security settings and design contents. Then programming of the security settings and design contents is done in one step. Both sub-flow 1 and sub-flow 2 are used. In Application 2, described in the "Application 2: Nontrusted Environment--Unsecured Location" section on page 13-9, the trusted site should follow sub-flows 1 and 2 separately to generate two separate programming files. The programming file from sub-flow 1 will be used at the trusted site to program the device(s) first. The programming file from sub-flow 2 will be sent off-site for production programming. v1.5 1 3 - 11 Security in Low-Power Flash Devices In Application 3, described in the "Application 3: Nontrusted Environment--Field Updates/Upgrades" section on page 13-10, typically only sub-flow 2 will be used, because only updates to the design content portion are needed and no security settings need to be changed. In the event that update of the security settings is necessary, see the "Reprogramming Devices" section on page 13-21 for details. For more information on programming low-power flash devices, refer to In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3. User 1 Designer Software Program Security Settings Programming Software User Assigns Desired Security Settings To FPGA/FlashROM/FB/All: - AES Key and FlashLock Pass Key - FlashLock Pass Key Only Software Generates Programming File with Desired Security Settings: - Encrypted with AES and Protected with FlashLock Pass Key - Protected with FlashLock Pass Key Only Device Previously Programmed? No Software Programs Selected Security Settings into Device Yes Yes Software Performs Comparison of FlashLock Pass Key between Programming File and Device Does FlashLock Pass Key Match? No Returns Error 2 Program Design Contents Programming Previously Secured Device(s)? No Software Generates Programming File with Desired Design Contents (FPGA Array, FlashROM, FB, or All) Yes AES Key Used Previously? No User Must Reassign Exact FlashLock Pass Key Previously Programmed into the Device Design Content Programmed into Device Yes Software Performs Comparison of FlashLock Pass Key between Programming File and Device Does FlashLock Pass Key Match? No Yes Returns Error User Must Reassign Exact AES Key Previously Programmed into the Device Software Generates Programming File with FlashLock Pass Key and Design Contents No Encrypted Design Content Passes through MAC for Authentication Correct? Yes Software Generates Programming File with Encrypted Design Contents Design Content Decrypted and Programmed into Device Note: If programming the Security Header only, just perform sub-flow 1. If programming design content only, just perform sub-flow 2. Figure 13-9 * Security Programming Flows 1 3 -1 2 v1.5 Security in Low-Power Flash Devices Generating Programming Files Generation of the Programming File in a Trusted Environment-- Application 1 As discussed in the "Application 1: Trusted Environment" section on page 13-9, in a trusted environment, the user can choose to program the device with plaintext bitstream content. It is possible to use plaintext for programming even when the FlashLock Pass Key option has been selected. In this application, it is not necessary to employ AES encryption protection. For AES encryption settings, refer to the next sections. The generated programming file will include the security setting (if selected) and the plaintext programming file content for the FPGA array, FlashROM, and/or FBs. These options are indicated in Table 13-2 and Table 13-3. Table 13-2 * IGLOO and ProASIC3 Plaintext Security Options, No AES FlashROM Only FPGA Core Only Both FlashROM and FPGA No AES / no FlashLock FlashLock only AES and FlashLock - - - Security Protection Table 13-3 * Fusion Plaintext Security Options Security Protection FlashROM Only FPGA Core Only FB Core Only All No AES / no FlashLock FlashLock AES and FlashLock - - - - Note: For all instructions, the programming of Flash Blocks refers to Fusion only. For this scenario, generate the programming file as follows: 1. Select the Silicon features to be programmed (Security Settings, FPGA Array, FlashROM, Flash Memory Blocks), as shown in Figure 13-10 on page 13-14 and Figure 13-11 on page 13-14. Click Next. If Security Settings is selected (i.e., the FlashLock security Pass Key feature), an additional dialog will be displayed to prompt you to select the security level setting. If no security setting is selected, you will be directed to Step 3. v1.5 1 3 - 13 Security in Low-Power Flash Devices Figure 13-10 * All Silicon Features Selected for IGLOO and ProASIC3 Devices Figure 13-11 * All Silicon Features Selected for Fusion 1 3 -1 4 v1.5 Security in Low-Power Flash Devices 2. Choose the appropriate security level setting and enter a FlashLock Pass Key. The default is the Medium security level (Figure 13-12). Click Next. If you want to select different options for the FPGA and/or FlashROM, this can be set by clicking Custom Level. Refer to the "Advanced Options" section on page 13-22 for different custom security level options and descriptions of each. Figure 13-12 * Medium Security Level Selected for Low-Power Flash Devices v1.5 1 3 - 15 Security in Low-Power Flash Devices 3. Choose the desired settings for the FlashROM configurations to be programmed (Figure 13-13). Click Finish to generate the STAPL programming file for the design. Figure 13-13 * FlashROM Configuration Settings for Low-Power Flash Devices Generation of Security Header Programming File Only-- Application 2 As mentioned in the "Application 2: Nontrusted Environment--Unsecured Location" section on page 13-9, the designer may employ FlashLock Pass Key protection or FlashLock Pass Key with AES encryption on the device before sending it to a nontrusted or unsecured location for device programming. To achieve this, the user needs to generate a programming file containing only the security settings desired (Security Header programming file). Note: If AES encryption is configured, FlashLock Pass Key protection must also be configured. The available security options are indicated in Table 13-4 and Table 13-5 on page 13-17. Table 13-4 * FlashLock Security Options for IGLOO and ProASIC3 FlashROM Only FPGA Core Only Both FlashROM and FPGA No AES / no FlashLock - - - FlashLock only AES and FlashLock Security Option 1 3 -1 6 v1.5 Security in Low-Power Flash Devices Table 13-5 * FlashLock Security Options for Fusion Security Option FlashROM Only FPGA Core Only FB Core Only All No AES / no FlashLock - - - - FlashLock AES and FlashLock For this scenario, generate the programming file as follows: 1. Select only the Security settings option, as indicated in Figure 13-14 and Figure 13-15 on page 13-18. Click Next. Figure 13-14 * Programming IGLOO and ProASIC3 Security Settings Only v1.5 1 3 - 17 Security in Low-Power Flash Devices Figure 13-15 * Programming Fusion Security Settings Only 2. Choose the desired security level setting and enter the key(s). - The High security level employs FlashLock Pass Key with AES Key protection. - The Medium security level employs FlashLock Pass Key protection only. Figure 13-16 * High Security Level to Implement FlashLock Pass Key and AES Key Protection 1 3 -1 8 v1.5 Security in Low-Power Flash Devices Table 13-6 and Table 13-7 show all available options. If you want to implement custom levels, refer to the "Advanced Options" section on page 13-22 for information on each option and how to set it. 3. When done, click Finish to generate the Security Header programming file. Table 13-6 * All IGLOO and ProASIC3 Header File Security Options FlashROM Only FPGA Core Only Both FlashROM and FPGA No AES / no FlashLock FlashLock only AES and FlashLock Security Option Note: = options that may be used Table 13-7 * All Fusion Header File Security Options Security Option FlashROM Only FPGA Core Only FB Core Only All No AES / No FlashLock FlashLock AES and FlashLock Generation of Programming Files with AES Encryption-- Application 3 This section discusses how to generate design content programming files needed specifically at unsecured or remote locations to program devices with a Security Header (FlashLock Pass Key and AES key) already programmed ("Application 2: Nontrusted Environment--Unsecured Location" section on page 13-9 and "Application 3: Nontrusted Environment--Field Updates/Upgrades" section on page 13-10). In this case, the encrypted programming file must correspond to the AES key already programmed into the device. If AES encryption was previously selected to encrypt the FlashROM, FBs, and FPGA array, AES encryption must be set when generating the programming file for them. AES encryption can be applied to the FlashROM only, the FBs only, the FPGA array only, or all. The user must ensure both the FlashLock Pass Key and the AES key match those already programmed to the device(s), and all security settings must match what was previously programmed. Otherwise, the encryption and/or device unlocking will not be recognized when attempting to program the device with the programming file. The generated programming file will be AES-encrypted. In this scenario, generate the programming file as follows: 1. Deselect Security settings and select the portion of the device to be programmed (Figure 13-17 on page 13-20). Select Programming previously secured device(s). Click Next. v1.5 1 3 - 19 Security in Low-Power Flash Devices Note: The settings in this figure are used to show the generation of an AES-encrypted programming file for the FPGA array, FlashROM, and FB contents. One or all locations may be selected for encryption. Figure 13-17 * Settings to Program a Device Secured with FlashLock and using AES Encryption Choose the High security level to reprogram devices using both the FlashLock Pass Key and AES key protection (Figure 13-18 on page 13-21). Enter the AES key and click Next. A device that has already been secured with FlashLock and has an AES key loaded must recognize the AES key to program the device and generate a valid bitstream in authentication. The FlashLock Key is only required to unlock the device and change the security settings. This is what makes it possible to program in an untrusted environment. The AES key is protected inside the device by the FlashLock Key, so you can only program if you have the correct AES key. In fact, the AES key is not in the programming file either. It is the key used to encrypt the data in the file. The same key previously programmed with the FlashLock Key matches to decrypt the file. An AES-encrypted file programmed to a device without FlashLock would not be secure, since without FlashLock to protect the AES key, someone could simply reprogram the AES key first, then program with any AES key desired or no AES key at all. This option is therefore not available in the software. 1 3 -2 0 v1.5 Security in Low-Power Flash Devices Figure 13-18 * Security Level Set High to Reprogram Device with AES Key Programming with this file is intended for an unsecured environment. The AES key encrypts the programming file with the same AES key already used in the device and utilizes it to program the device. Reprogramming Devices Previously programmed devices can be reprogrammed using the steps in the "Generation of the Programming File in a Trusted Environment--Application 1" section on page 13-13 and "Generation of Security Header Programming File Only--Application 2" section on page 13-16. In the case where a FlashLock Pass Key has been programmed previously, the user must generate the new programming file with a FlashLock Pass Key that matches the one previously programmed into the device. The software will check the FlashLock Pass Key in the programming file against the FlashLock Pass Key in the device. The keys must match before the device can be unlocked to perform further programming with the new programming file. Figure 13-10 on page 13-14 and Figure 13-11 on page 13-14 show the option Programming previously secured device(s), which the user should select before proceeding. Upon going to the next step, the user will be notified that the same FlashLock Pass Key needs to be entered, as shown in Figure 13-19 on page 13-22. v1.5 1 3 - 21 Security in Low-Power Flash Devices Figure 13-19 * FlashLock Pass Key, Previously Programmed Devices It is important to note that when the security settings need to be updated, the user also needs to select the Security settings check box in Step 1, as shown in Figure 13-10 on page 13-14 and Figure 13-11 on page 13-14, to modify the security settings. The user must consider the following: * If only a new AES key is necessary, the user must re-enter the same Pass Key previously programmed into the device in Designer and then generate a programming file with the same Pass Key and a different AES key. This ensures the programming file can be used to access and program the device and the new AES key. * If a new Pass Key is necessary, the user can generate a new programming file with a new Pass Key (with the same or a new AES key if desired). However, for programming, the user must first load the original programming file with the Pass Key that was previously used to unlock the device. Then the new programming file can be used to program the new security settings. Advanced Options As mentioned, there may be applications where more complicated security settings are required. The "Custom Security Levels" section in the FlashPro User's Guide describes different advanced options available to aid the user in obtaining the best available security settings. 1 3 -2 2 v1.5 Security in Low-Power Flash Devices Programming File Header Definition In each STAPL programming file generated, there will be information about how the AES key and FlashLock Pass Key are configured. Table 13-8 shows the header definitions in STAPL programming files for different security levels. Table 13-8 * STAPL Programming File Header Definitions by Security Level Security Level STAPL File Header Definition No security (no FlashLock Pass Key or AES key) NOTE "SECURITY" "Disable"; FlashLock Pass Key with no AES key NOTE "SECURITY" "KEYED "; FlashLock Pass Key with AES key NOTE "SECURITY" "KEYED ENCRYPT "; Permanent Security Settings option enabled NOTE "SECURITY" "PERMLOCK ENCRYPT "; AES-encrypted FPGA array (for programming updates) NOTE "SECURITY" "ENCRYPT CORE "; AES-encrypted FlashROM (for programming updates) NOTE "SECURITY" "ENCRYPT FROM "; AES-encrypted FPGA array and FlashROM (for programming NOTE "SECURITY" "ENCRYPT FROM CORE "; updates) Example File Headers STAPL Files Generated with FlashLock Key and AES Key Containing Key Information * FlashLock Key / AES key indicated in STAPL file header definition * Intended ONLY for secured/trusted environment programming applications ============================================= NOTE "CREATOR" "Designer Version: 6.1.1.108"; NOTE "DEVICE" "A3PE600"; NOTE "PACKAGE" "208 PQFP"; NOTE "DATE" "2005/04/08"; NOTE "STAPL_VERSION" "JESD71"; NOTE "IDCODE" "$123261CF"; NOTE "DESIGN" "counter32"; NOTE "CHECKSUM" "$EDB9"; NOTE "SAVE_DATA" "FRomStream"; NOTE "SECURITY" "KEYED ENCRYPT "; NOTE "ALG_VERSION" "1"; NOTE "MAX_FREQ" "20000000"; NOTE "SILSIG" "$00000000"; NOTE "PASS_KEY" "$00123456789012345678901234567890"; NOTE "AES_KEY" "$ABCDEFABCDEFABCDEFABCDEFABCDEFAB"; ============================================== v1.5 1 3 - 23 Security in Low-Power Flash Devices STAPL File with AES Encryption * Does not contain AES key / FlashLock Key information * Intended for transmission through web or service to unsecured locations for programming ============================================= NOTE "CREATOR" "Designer Version: 6.1.1.108"; NOTE "DEVICE" "A3PE600"; NOTE "PACKAGE" "208 PQFP"; NOTE "DATE" "2005/04/08"; NOTE "STAPL_VERSION" "JESD71"; NOTE "IDCODE" "$123261CF"; NOTE "DESIGN" "counter32"; NOTE "CHECKSUM" "$EF57"; NOTE "SAVE_DATA" "FRomStream"; NOTE "SECURITY" "ENCRYPT FROM CORE "; NOTE "ALG_VERSION" "1"; NOTE "MAX_FREQ" "20000000"; NOTE "SILSIG" "$00000000"; Conclusion The new and enhanced security features offered in Actel Fusion, IGLOO, and ProASIC3 devices provide state-of-the-art security to designs programmed into these flash-based devices. Actel lowpower flash devices employ the encryption standard used by NIST and the U.S. government--AES using the 128-bit Rijndael algorithm. The combination of an on-chip AES decryption engine and Actel FlashLock technology provides the highest level of security against invasive attacks and design theft, implementing the most robust and secure ISP solution. These security features protect IP within the FPGA and protect the system from cloning, wholesale "black box" copying of a design, invasive attacks, and explicit IP or data theft. Glossary Term Security Header programming file Explanation Programming file used to program the FlashLock Pass Key and/or AES key into the device to secure the FPGA, FlashROM, and/or FBs. AES (encryption) key 128-bit key defined by the user when the AES encryption option is set in the Actel Designer software when generating the programming file. FlashLock Pass Key 128-bit key defined by the user when the FlashLock option is set in the Actel Designer software when generating the programming file. The FlashLock Key protects the security settings programmed to the device. Once a device is programmed with FlashLock, whatever settings were chosen at that time are secure. FlashLock 1 3 -2 4 The combined security features that protect the device content from attacks. These features are the following: * Flash technology that does not require an external bitstream to program the device * FlashLock Pass Key that secures device content by locking the security settings and preventing access to the device as defined by the user * AES key that allows secure, encrypted device reprogrammability v1.5 Security in Low-Power Flash Devices References National Institute of Standards and Technology. "ADVANCED ENCRYPTION STANDARD (AES) Questions and Answers." 28 January 2002 (10 January 2005). See http://csrc.nist.gov/archive/aes/index1.html for more information. Related Documents Handbook Documents FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Programming ProASIC3/E Using a Microprocessor http://www.actel.com/documents/LPD_Microprocessor_HBs.pdf In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 http://www.actel.com/documents/LPD_ISP_HBs.pdf Fusion Embedded Flash Memory Blocks http://www.actel.com/documents/Fusion_Flash_HBs.pdf User's Guides FlashPro User's Guide http://www.actel.com/documents/flashpro_ug.pdf v1.5 1 3 - 25 Security in Low-Power Flash Devices Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-014-5 Revised August 2009 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.5) Page The "CoreMP7 Device Security" section was removed from "Security in ARMEnabled Low-Power Flash Devices", since M7-enabled devices are no longer supported. 13-4 (December 2008) v1.3 (October 2008) IGLOO nano and ProASIC3 nano devices were added to Table 13-1 * Flash-Based FPGAs. 13-2 v1.2 (June 2008) The "Security Support in Flash-Based Devices" section was revised to include new families and make the information more concise. 13-2 v1.1 (March 2008) The following changes were Table 13-1 * Flash-Based FPGAs: in 13-2 The chapter was updated to include the IGLOO PLUS family and information regarding 15 k gate devices. N/A The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 13-2 v1.4 v1.0 (January 2008) 1 3 -2 6 made to the family descriptions * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. v1.5 14 - In-System Programming (ISP) of Actel's LowPower Flash Devices Using FlashPro3 Introduction Actel's low-power flash devices are all in-system programmable. This document describes the general requirements for programming a device and specific requirements for the FlashPro3 programmer. Fusion, IGLOO,(R) and ProASIC(R)3 devices offer a low-power, single-chip, live-at-power-up solution with the ASIC advantages of security and low unit cost through nonvolatile flash technology. Each device contains 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications such as Internet Protocol (IP) addressing, user system preference storage, device serialization, or subscription-based business models. Fusion, IGLOO, and ProASIC3 devices offer the best in-system programming (ISP) solution, FlashLock(R) security features, and AESdecryption-based ISP. ISP Architecture Low-power flash devices support ISP via JTAG and require a single VPUMP voltage of 3.3 V during programming. In addition, programming via a microcontroller in a target system is also supported. Refer to Microprocessor Programming of Actel's Low-Power Flash Devices. Family-specific support: * Fusion, ProASIC3, and ProASIC3E devices support ISP. * ProASIC3L devices operate using a 1.2 V core voltage and support ISP at 1.5 V only. Voltage switching is required in-system to switch from a 1.2 V core to 1.5 V core for programming. * IGLOO and IGLOOe V5 devices can be programmed in-system when the device is using a 1.5 V supply voltage to the FPGA core. * All IGLOO V2 and ProASIC3L devices can be operated at any voltage between 1.2 V and1.5 V. Designer software allows 50 mV increments in the voltage. Although devices can operate at 1.2 V core voltage, a device can only be reprogrammed when the core voltage is 1.5 V. Voltage switching is required in-system to switch from a 1.2 V supply (VCC,VCCI, and VJTAG) to 1.5 V for programming. IGLOO devices cannot be programmed in-system when the device is in Flash*Freeze mode. The device should exit Flash*Freeze mode and be in normal operation for programming to start. Programming operations in IGLOO devices can be achieved when the device is in normal operating mode and a 1.5 V core voltage is used. JTAG 1532 Fusion, IGLOO, and ProASIC3 devices support the JTAG-based IEEE 1532 standard for ISP. To start JTAG operations, the IGLOO device should exit Flash*Freeze mode and be in normal operation before starting to send JTAG commands to the device. As part of this support, when a device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by keeping the global IO_EN signal deactivated, which also has the effect of disabling the input buffers. The SAMPLE/PRELOAD instruction captures the status of pads in parallel and shifts them out as new data is shifted in for loading into the Boundary Scan Register (BSR). When the device is in an unprogrammed state, the SAMPLE/PRELOAD instruction has no effect on I/O status; however, it will continue to shift in new data to be loaded into the BSR. Therefore, when SAMPLE/PRELOAD is used on an unprogrammed device, the BSR will be loaded with undefined data. For JTAG timing information on setup, hold, and fall times, refer to the FlashPro User's Guide. v1.5 1 4 -1 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 ISP Support in Flash-Based Devices The flash FPGAs listed in Table 14-1 support the ISP feature and the functions described in this document. Table 14-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 14-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 14-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 1 4 -2 v1.5 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 Programming Voltage (VPUMP) and VJTAG Low-power flash devices support on-chip charge pumps, and therefore require only a single 3.3 V programming voltage for the VPUMP pin during programming. When the device is not being programmed, the VPUMP pin can be left floating or can be tied (pulled up) to any voltage between 0 V and 3.6 V. During programming, the target board or the FlashPro3 programmer can provide VPUMP. FlashPro3 is capable of supplying VPUMP to a single device. If more than one device is to be programmed using FlashPro3 on a given board, FlashPro3 should not be relied on to supply the VPUMP voltage. Low-power flash device I/Os support a bank-based, voltage-supply architecture that simultaneously supports multiple I/O voltage standards (Table 14-2 on page 14-3). By isolating the JTAG power supply in a separate bank from the user I/Os, low-power flash devices provide greater flexibility with supply selection and simplify power supply and printed circuit board (PCB) design. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Actel recommends that TCK be tied to GND or VJTAG when not used. This prevents a possible totempole current on the input buffer stage. For TDI, TMS, and TRST pins, the devices provide an internal nominal 10 k pull-up resistor. During programming, all I/O pins, except for JTAG interface pins, are tristated and weakly pulled up to VCCI. This isolates the part and prevents the signals from floating. The JTAG interface pins are driven by the FlashPro3 during programming, including the TRST pin, which is driven HIGH. Table 14-2 * Power Supplies Programming Mode Current during Programming VCC 1.5 V < 70 mA VCCI 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-selectable) I/Os are weakly pulled up. VJTAG 1.5 V / 1.8 V / 2.5 V / 3.3 V < 20 mA VPUMP 3.0 V to 3.6 V < 80 mA Power Supply Note: All supply voltages should be at 1.5 V or higher, regardless of the setting during normal operation. IEEE 1532 (JTAG) Interface The supported industry-standard IEEE 1532 programming interface builds on the IEEE 1149.1 (JTAG) standard. IEEE 1532 defines the standardized process and methodology for ISP. Both silicon and software issues are addressed in IEEE 1532 to create a simplified ISP environment. Any IEEE 1532-compliant programmer can be used to program low-power flash devices. However, only limited security and FlashROM features are supported when using the IEEE 1532 standard. The Actel FlashPro3 programmer was developed exclusively for these devices and will support all the security and device serialization features. Refer to the standard for detailed information about IEEE 1532. Security Unlike SRAM-based FPGAs that require loading at power-up from an external source such as a microcontroller or boot PROM, Actel nonvolatile devices are live at power-up, and there is no bitstream required to load the device when power is applied. The unique flash-based architecture prevents reverse engineering of the programmed code on the device, because the programmed data is stored in nonvolatile memory cells. Each nonvolatile memory cell is made up of small capacitors and any physical deconstruction of the device will disrupt stored electrical charges. Each low-power flash device has a built-in 128-bit Advanced Encryption Standard (AES) decryption core, except for the 30 k gate devices and smaller. Any FPGA core or FlashROM content loaded into the device can optionally be sent as encrypted bitstream and decrypted as it is loaded. This is v1.5 1 4 -3 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 particularly suitable for applications where device updates must be transmitted over an unsecured network such as the Internet. The embedded AES decryption core can prevent sensitive data from being intercepted (Figure 14-1 on page 14-4). A single 128-bit AES Key (32 hex characters) is used to encrypt FPGA core programming data and/or FlashROM programming data in the Actel tools. The low-power flash devices also decrypt with a single 128-bit AES Key. In addition, low-power flash devices support a Message Authentication Code (MAC) for authentication of the encrypted bitstream on-chip. This allows the encrypted bitstream to be authenticated and prevents erroneous data from being programmed into the device. The FPGA core, FlashROM, and Flash Memory Blocks (FBs), in Fusion only, can be updated independently using a programming file that is AES-encrypted (cipher text) or uses plain text. Security in ARM-Enabled Low-Power Flash Devices There are slight differences between the regular flash device and the ARM(R)-enabled flash devices, which have the M1 and M7 prefix. The AES key is used by Actel and preprogrammed into the device to protect the ARM IP. As a result, the design will be encrypted along with the ARM IP, according to the details below. Cortex-M1 Device Security Cortex-M1-enabled devices are shipped with the following security features: * FPGA array enabled for AES-encrypted programming and verification * FlashROM enabled for AES-encrypted write and verify * Fusion Embedded Flash Memory enabled for AES encrypted write Flash Device Actel Designer Software MAC Validation User Encryption AES Key Decrypted Bitstream Programming File Generation with AES Encryption AES Decryption Transmit Medium / Public Network Encrypted Bistream Figure 14-1 * AES-128 Security Features 1 4 -4 v1.5 FPGA Core, FlashROM, FBs In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 Figure 14-2 shows different applications for ISP programming. 1. In a trusted programming environment, you can program the device using the unencrypted (plaintext) programming file. 2. You can program the AES Key in a trusted programming environment and finish the final programming in an untrusted environment using the AES-encrypted (cipher text) programming file. 3. For the remote ISP updating/reprogramming, the AES Key stored in the device enables the encrypted programming bitstream to be transmitted through the untrusted network connection. Actel low-power flash devices also provide the unique Actel FlashLock feature, which protects the Pass Key and AES Key. Unless the original FlashLock Pass Key is used to unlock the device, security settings cannot be modified. Low-power flash devices do not support read-back of FPGA coreprogrammed data; however, the FlashROM contents can selectively be read back (or disabled) via the JTAG port based on the security settings established by the Actel Designer software. Refer to Security in Low-Power Flash Devices for more information. Source Plain Text AES Encryption Source Encrypted Bitstream FlashROM Option 3 Option 2 Option 1 TCP/IP AES Decryption FPGA Core IGLOO or ProASIC3 Device Figure 14-2 * Different ISP Use Models v1.5 1 4 -5 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 FlashROM and Programming Files Each low-power flash device has 1 kbit of on-chip, nonvolatile flash memory that can be accessed from the FPGA core. This nonvolatile FlashROM is arranged in eight pages of 128 bits (Figure 14-3). Each page can be programmed independently, with or without the 128-bit AES encryption. The FlashROM can only be programmed via the IEEE 1532 JTAG port and cannot be programmed from the FPGA core. In addition, during programming of the FlashROM, the FPGA core is powered down automatically by the on-chip programming control logic. Page Number 15 14 13 12 Byte Number in Page 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 14-3 * FlashROM Architecture Using FlashROM combined with AES, many subscription-based applications or device serialization applications are possible. SmartGen supports easy management of the FlashROM contents even over large numbers of devices. SmartGen can support FlashROM contents that contain the following: * Static values * Random numbers * Values read from a file * Independent updates of each page In addition, auto-incrementing of fields is possible. In applications where the FlashROM content is different for each device, you have the option to generate a single STAPL file for all the devices or individual serialization files for each device. For more information on how to generate the FlashROM content for device serialization, refer to FlashROM in Actel's Low-Power Flash Devices. Actel Libero(R) Integrated Designed Environment (IDE) includes a unique tool to support the generation and management of FlashROM and FPGA programming files. This tool is called FlashPoint. Depending on the applications, designers can use the FlashPoint software to generate a STAPL file with different contents. In each case, optional AES encryption and/or different security settings can be set. In Designer, when you click the Programming File icon, FlashPoint launches, and you can generate STAPL file(s) with four different cases (Figure 14-4 on page 14-7). When the serialization feature is used during the configuration of FlashROM in SmartGen, you can generate a single STAPL file that will program all the devices or an individual STAPL file for each device. The following cases present the FPGA core and FlashROM programming file combinations that can be used for different applications. In each case, you can set the optional security settings (FlashLock Pass Key and/or AES Key) depending on the application. 1. A single STAPL file or multiple STAPL files with multiple FlashROM contents and the FPGA core content. A single STAPL file will be generated if the device serialization feature is not used. You can program the whole FlashROM or selectively program individual pages. 2. A single STAPL file for the FPGA core content 1 4 -6 v1.5 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 3. A single STAPL file or multiple STAPL files with multiple FlashROM contents. A single STAPL file will be generated if the device serialization feature is not used. You can program the whole FlashROM or selectively program individual pages. 4. A single STAPL file to configure the security settings for the device, such as the AES Key and/or Pass Key. SmartGen Actel's Designer Software Suite Netlist Programming File (FlashPoint) 1 2 FlashROM Configuration File (*.ufc) 3 Security Settings Security Settings Security Settings Single/Multiple FlashROM Content(s) FPGA Core Content Single/Multiple FlashROM Content(s) 4 Security Settings FPGA Core Content Figure 14-4 * Flexible Programming File Generation for Different Applications Programming Solution For device programming, any IEEE 1532-compliant programmer can be used; however, the FlashPro3 programmer must be used to control the low-power flash device's rich security features and FlashROM programming options. The FlashPro3 programmer is a low-cost portable programmer for the Actel flash families. It can also be used with a powered USB hub for parallel programming. General specifications for the FlashPro3 programmer are as follows: * Programming clock - TCK is used with a maximum frequency of 20 MHz, and the default frequency is 4 MHz. * Programming file - STAPL * Daisy chain - Supported. You can use the ChainBuilder software to build the programming file for the chain. * Parallel programming - Supported. Multiple FlashPro3 programmers can be connected together using a powered USB hub or through the multiple USB ports on the PC. * Power supply - The target board must provide VCC, VCCI, VPUMP, and VJTAG during programming. However, if there is only one device on the target board, the FlashPro3 programmer can generate the required VPUMP voltage from the USB port. v1.5 1 4 -7 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 ISP Programming Header Information The FlashPro3 programming cable connector can be connected with a 10-pin, 0.1"-pitch programming header. The recommended programming headers are manufactured by AMP (103310-1) and 3M (2510-6002UB). If you have limited board space, you can use a compact programming header manufactured by Samtec (FTSH-105-01-L-D-K). Using this compact programming header, you are required to order an additional header adapter manufactured by Actel (FP3-26PIN-ADAPTER). Existing ProASICPLUS family customers who are using the Samtec Small Programming Header (FTSH113-01-L-D-K) and are planning to migrate to IGLOO or ProASIC3 devices can order a separate adapter kit from Actel (FP3-10PIN-ADAPTER-KIT), which contains a compact 10-pin adapter kit as well as 26-pin migration capability. Table 14-3 * Programming Header Ordering Codes Manufacturer AMP 3M Samtec Part Number Description 103310-1 10-pin, 0.1"-pitch cable header (right-angle PCB mount angle) 2510-6002UB 10-pin, 0.1"-pitch cable header (straight PCB mount angle) FTSH-113-01-L-D-K Small programming header supported by FlashPro and Silicon Sculptor Samtec FTSH-105-01-L-D-K Samtec FFSD-05-D-06.00-01-N Actel Compact programming header 10-pin cable with 50 mil pitch sockets; included in FP310PIN-ADAPTER-KIT. FP3-10PIN-ADAPTER-KIT Compact header and migration kit TCK TDO TMS VPUMP TDI 1 3 5 7 9 2 4 6 8 10 GND NC VJTAG TRST GND Figure 14-5 * Programming Header (top view) Table 14-4 * Programming Header Pin Numbers and Description Pin Signal 1 TCK Source Programmer 1 Description JTAG Clock 2 GND - 3 TDO Target Board 4 NC - 5 TMS Programmer Test Mode Select 6 VJTAG Target Board JTAG Supply Voltage 2 Signal Reference Test Data Output No Connect Programmer/Target Board Programming Supply Voltage 7 VPUMP 8 nTRST Programmer JTAG Test Reset (Hi-Z with 10 k pull-down, HIGH, LOW, or toggling) 9 TDI Programmer Test Data Input 10 1 GND - Signal Reference Notes: 1. Both GND pins must be connected. 2. FlashPro3 can provide VPUMP if there is only one device on the target board. 1 4 -8 v1.5 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 Board-Level Considerations A bypass capacitor is required from VPUMP to GND for all low-power flash devices during programming. This bypass capacitor protects the devices from voltage spikes that may occur on the VPUMP supplies during the erase and programming cycles. Refer to Pin Descriptions for specific recommendations. For proper programming, 0.01 F and 0.33 F capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. The bypass capacitor must be placed within 2.5 cm of the device pins. VJTAG from the target board VCCI from the target board VCC from the target board VCC VCCI Polarizing Notch VJTAG Low-Power Flash Device GND TCK TDO TMS VPUMP 1 TCK 3 TDO 5 TMS 7 VPUMP 9 TDI TDI TRST 2 GND 4 NC 6 VJTAG 8 TRST 10 GND C1 C2 Figure 14-6 * Board Layout and Programming Header Top View Troubleshooting Signal Integrity Symptoms of a Signal Integrity Problem A signal integrity problem can manifest itself in many ways. The problem may show up as extra or dropped bits during serial communication, changing the meaning of the communication. There is a normal variation of threshold voltage and frequency response between parts even from the same lot. Because of this, the effects of signal integrity may not always affect different devices on the same board in the same way. Sometimes, replacing a device appears to make signal integrity problems go away, but this is just masking the problem. Different parts on identical boards will exhibit the same problem sooner or later. It is important to fix signal integrity problems early. Unless the signal integrity problems are severe enough to completely block all communication between the device and the programmer, they may show up as subtle problems. Some of the FlashPro3 exit codes that are caused by signal integrity problems are listed below. Signal integrity problems are not the only possible cause of these errors, but this list is intended to show where problems can occur. FlashPro3 allows TCK to be lowered from 24 MHz down to 1 MHz to allow you to address some signal integrity problems that may occur with impedance mismatching at higher frequencies. Chain Integrity Test Error or Analyze Chain Failure Normally, the FlashPro3 Analyze Chain command expects to see 0x2 on the TDO pin. If the command reports reading 0x0 or 0x3, it is seeing the TDO pin stuck at 0 or 1. The only time the TDO v1.5 1 4 -9 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 pin comes out of tristate is when the JTAG TAP state machine is in the Shift-IR or Shift-DR state. If noise or reflections on the TCK or TMS lines have disrupted the correct state transitions, the device's TAP state controller might not be in one of these two states when the programmer tries to read the device. When this happens, the output is floating when it is read and does not match the expected data value. This can also be caused by a broken TDO net. Only a small amount of data is read from the device during the Analyze Chain command, so marginal problems may not always show up during this command. Exit 11 This error occurs during the verify stage of programming a device. After programming the design into the device, the device is verified to ensure it is programmed correctly. The verification is done by shifting the programming data into the device. An internal comparison is performed within the device to verify that all switches are programmed correctly. Noise induced by poor signal integrity can disrupt the writes and reads or the verification process and produce a verification error. While technically a verification error, the root cause is often related to signal integrity. Refer to the FlashPro User's Guide for other error messages and solutions. For the most up-to-date known issues and solutions, refer to http://www.actel.com/support. Conclusion Fusion, IGLOO, and ProASIC3 devices offer a low-cost, single-chip solution that is live at power-up through nonvolatile flash technology. The FlashLock Pass Key and 128-bit AES Key security features enable secure ISP in an untrusted environment. On-chip FlashROM enables a host of new applications, including device serialization, subscription-based applications, and IP addressing. Additionally, as the FlashROM is nonvolatile, all of these services can be provided without battery backup. Related Documents Handbook Documents Microprocessor Programming of Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_Microprocessor_HBs.pdf Security in Low-Power Flash Devices http://www.actel.com/LPD_Security_HBs.pdf FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions_HBs.pdf User's Guides FlashPro User's Guide http://www.actel.com/documents/flashpro_ug.pdf 1 4 -1 0 v1.5 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-015-5 Revised August 2009 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.5) Page v1.4 (December 2008) The "CoreMP7 Device Security" section was removed from "Security in ARMEnabled Low-Power Flash Devices", since M7-enabled devices are no longer supported. 14-4 v1.3 (October 2008) The "ISP Architecture" section was revised to include information about core voltage for IGLOO V2 and ProASIC3L devices, as well as 50 mV increments allowable in Designer software. 14-1 IGLOO nano and ProASIC3 nano devices were added to Table 14-1 * Flash-Based FPGAs. 14-2 A second capacitor was added to Figure 14-6 * Board Layout and Programming Header Top View. 14-9 v1.2 (June 2008) The "ISP Support in Flash-Based Devices" section was revised to include new families and make the information more concise. 14-2 v1.1 (March 2008) The following changes were Table 14-1 * Flash-Based FPGAs: in 14-2 The "ISP Architecture" section was updated to included the IGLOO PLUS family in the discussion of family-specific support. The text, "When 1.2 V is used, the device can be reprogrammed in-system at 1.5 V only," was revised to state, "Although the device can operate at 1.2 V core voltage, the device can only be reprogrammed when all supplies (VCC, VCCI, and VJTAG) are at 1.5 V." 14-1 The "ISP Support in Flash-Based Devices" section and Table 14-1 * Flash-Based FPGAs were updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 14-2 The "Security" section was updated to mention that 15 k gate devices do not have a built-in 128-bit decryption core. 14-3 Table 14-2 * Power Supplies was revised to remove the Normal Operation column and add a table note stating, "All supply voltages should be at 1.5 V or higher, regardless of the setting during normal operation." 14-3 The "ISP Programming Header Information" section was revised to change FP3-26PIN-ADAPTER to FP3-10PIN-ADAPTER-KIT. Table 14-3 * Programming Header Ordering Codes was updated with the same change, as well as adding the part number FFSD-05-D-06.00-01-N, a 10-pin cable with 50-mil-pitch sockets. 14-8 The "Board-Level Considerations" section was updated to describe connecting two capacitors in parallel across VPUMP and GND for proper programming. 14-9 v1.0 (January 2008) made to the family descriptions * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. v1.5 1 4 - 11 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 Previous Version Changes in Current Version (v1.5) Page 51900055-2/7.06 Information was added to the "Programming Voltage (VPUMP) and VJTAG" section about the JTAG interface pin. 14-3 51900055-1/1.05 ACTgen was changed to SmartGen. N/A In Figure 14-6 * Board Layout and Programming Header Top View, the order of the text was changed to: 14-9 VJTAG from the target board VCCI from the target board VCC from the target board 1 4 -1 2 v1.5 15 - Core Voltage Switching Circuit for IGLOO and ProASIC3L In-System Programming Introduction The IGLOO(R) and ProASIC(R)3L families offer devices that can be powered by either 1.5 V or, in the case of V2 devices, a core supply voltage anywhere in the range of 1.2 V to 1.5 V, in 50 mV increments. Since IGLOO and ProASIC3L devices are flash-based, they can be programmed and reprogrammed multiple times in-system using Actel FlashPro3. Actel FlashPro3 uses the JTAG standard interface (IEEE 1149.1) and STAPL file (defined in JESD 71 to support programming of programmable devices using IEEE 1149.1) for in-system configuration/programming (IEEE 1532) of a device. Programming can also be executed by other methods, such as an embedded microcontroller that follows the same standards above. All IGLOO and ProASIC3L devices must be programmed with the VCC core voltage at 1.5 V. Therefore, applications using IGLOO or ProASIC3L devices powered by a 1.2 V supply must switch the core supply to 1.5 V for in-system programming. The purpose of this document is to describe an easy-to-use and cost-effective solution for switching the core supply voltage from 1.2 V to 1.5 V during in-system programming for IGLOO and ProASIC3L devices. v1.2 1 5 -1 Core Voltage Switching Circuit for IGLOO and ProASIC3L In-System Programming Actel's Flash Families Support Voltage Switching Circuit The flash FPGAs listed in Table 15-1 support the voltage switching circuit feature and the functions described in this document. Table 15-1 * Flash-Based FPGAs Supporting Voltage Switching Circuit Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 15-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 15-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 1 5 -2 v1.2 Core Voltage Switching Circuit for IGLOO and ProASIC3L In-System Programming Circuit Description All IGLOO devices as well as the ProASIC3L product family are available in two versions: V5 devices, which are powered by a 1.5 V supply and V2 devices, which are powered by a supply anywhere in the range of 1.2 V to 1.5 V in 50 mV increments. Applications that use IGLOO or ProASIC3L devices powered by a 1.2 V core supply must have a mechanism that switches the core voltage from 1.2 V (or other voltage below 1.5 V) to 1.5 V during in-system programming (ISP). There are several possible techniques to meet this requirement. Actel recommends utilizing a linear voltage regulator, a resistor voltage divider, and an N-Channel Digital FET to set the appropriate VCC voltage, as shown in Figure 15-1. Where 1.2 V is mentioned in the following text, the meaning applies to any voltage below the 1.5 V range. Resistor values in the figures have been calculated for 1.2 V, so refer to power regulator datasheets if a different core voltage is required. The main component of Actel's recommended circuit is the LTC3025 linear voltage regulator from LinearTech. The output voltage of the LTC3025 on the OUT pin is set by the ratio of two external resistors, R37 and R38, in a voltage divider. The linear voltage regulator adjusts the voltage on the OUT pin to maintain the ADJ pin voltage at 0.4 V (referenced to ground). By using an R38 value of 40.2 k and an R37 value of 80.6 k, the output voltage on the OUT pin is 1.2 V. To achieve 1.5 V on the OUT pin, R44 can be used in parallel with R38. The OUT pin can now be used as a switchable source for the VCC supply. Refer to the LTC3025 Linear Voltage Regulator datasheet for more information. In Figure 15-1, the N-Channel Digital FET is used to enable and disable R44. This FET is controlled by the JTAG TRST signal driven by the FlashPro3 programmer. During programming of the device, the TRST signal is driven HIGH by the FlashPro3, and turns the N-Channel Digital FET ON. When the FET is ON, R44 becomes enabled as a parallel resistance to R38, which forces the regulator to set OUT to 1.5 V. When the FlashPro3 is connected and not in programming mode or when it is not connected, the pull-down resistor, R10, will pull the TRST signal LOW. When this signal is LOW, the N-Channel Digital FET is "open" and R44 is not part of the resistance seen by the LTC3025. The new resistance momentarily changes the voltage value on the ADJ pin, which in turn causes the output of the LTC3025 to compensate by setting OUT to 1.2 V. Now the device will run in regular active mode at the regular 1.2 V core voltage. Figure 15-1 * Circuit Diagram v1.2 1 5 -3 Core Voltage Switching Circuit for IGLOO and ProASIC3L In-System Programming Circuit Verification The power switching circuit recommended above is implemented on Actel's Icicle board (Figure 15-2). On the Icicle board, VJTAGENB is used to control the N-Channel Digital FET; however, this circuit was modified to use TRST instead of VJTAGENB in this application. There are three important aspects of this circuit that were verified: 1. The rise on VCC from 1.2 V to 1.5 V when TRST is HIGH 2. VCC rises to 1.5 V before programming begins. 3. VCC switches from 1.5 V to 1.2 V when TRST is LOW. Verification Steps 1. The rise on VCC from 1.2 V to 1.5 V when TRST is HIGH. VCC Signal TRST Signal Figure 15-2 * Core Voltage on the IGLOO AGL125-QNG132 Device In the oscilloscope plots (Figure 15-2), the TRST from FlashPro3 and the VCC core voltage of the IGLOO device are labeled. This plot shows the rise characteristic of the TRST signal from FlashPro3. Once the TRST signal is asserted HIGH, the LTC3025 shown in Figure 15-1 on page 15-3 senses the increase in voltage and changes the output from 1.2 V to 1.5 V. It takes the circuit approximately 100 s to respond to TRST and change the voltage to 1.5 V on the VCC core. 1 5 -4 v1.2 Core Voltage Switching Circuit for IGLOO and ProASIC3L In-System Programming 2. VCC rises to 1.5 V before programming begins. TMS Signal Green Floating Signal TDI/TMS VCC Core Voltage TRST Signal (purple) TDI Signal (yellow) Figure 15-3 * Programming Algorithm The oscilloscope plot in Figure 15-3 shows a wider time interval for the programming algorithm and includes the TDI and TMS signals from the FlashPro3. These signals carry the programming information that is programmed into the device and should only start toggling after the VCC core voltage reaches 1.5 V. Again, TRST from FlashPro3 and the VCC core voltage of the IGLOO device are labeled. As shown in Figure 15-3, TDI and TMS are floating initially, and the core voltage is 1.2 V. When a programming command on the FlashPro3 is executed, TRST is driven HIGH and TDI is momentarily driven to ground. In response to the HIGH TRST signal, the circuit responds and pulls the core voltage to 1.5 V. After 100 ms, TRST is briefly driven LOW by the FlashPro software. This is expected behavior that ensures the device JTAG state machine is in Reset prior to programming. TRST remains HIGH for the duration of the programming. It can be seen in Figure 15-3 that the VCC core voltage signal remains at 1.5 V for approximately 50 ms before information starts passing through on TDI and TMS. This confirms that the voltage switching circuit drives the VCC core supply voltage to 1.5 V prior to programming. v1.2 1 5 -5 Core Voltage Switching Circuit for IGLOO and ProASIC3L In-System Programming 3. VCC switches from 1.5 V to 1.2 V when TRST is LOW. TRST Signal VCC Core Signal Figure 15-4 * TRST Toggled LOW In Figure 15-4, the TRST signal and the VCC core voltage signal are labeled. As TRST is pulled to ground, the core voltage is observed to switch from 1.5 V to 1.2 V. The observed fall time is approximately 2 ms. DirectC The above analysis is based on FlashPro3, but there are other solutions to ISP, such as DirectC. DirectC is a microprocessor program that can be run in-system to program Actel flash devices. For FlashPro3, TRST is the most convenient control signal to use for the recommended circuit. However, for DirectC, users may use any signal to control the FET. For example, the DirectC code can be edited so that a separate non-JTAG signal can be asserted from the microcontroller that signals the board that it is about to start programming the device. After asserting the N-Channel Digital FET control signal, the programming algorithm must allow sufficient time for the supply to rise to 1.5 V before initiating DirectC programming. As seen in Figure 15-3 on page 15-5, 50 ms is adequate time. Depending on the size of the PCB and the capacitance on the VCC supply, results may vary from system to system. Actel recommends using a conservative value for the wait time to make sure that the VCC core voltage is at the right level. Conclusion For applications using Actel's IGLOO and ProASIC3L low-power FPGAs and taking advantage of the low core voltage power supplies with less than 1.5 V operation, there must be a way for the core voltage to switch from 1.2 V (or other voltage) to 1.5 V, which is required during in-system programming. The circuit explained in this document illustrates one simple, cost-effective way of handling this requirement. A JTAG signal from the FlashPro3 programmer allows the circuit to sense when programming is in progress, enabling it to switch to the correct core voltage. 1 5 -6 v1.2 Core Voltage Switching Circuit for IGLOO and ProASIC3L In-System Programming Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-028-2 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.1 (October 2008) v1.0 (August 2008) Changes in Current Version (v1.2) Page The "Introduction" was revised to include information about the core supply voltage range of operation in V2 devices. 15-1 IGLOO nano device support was added to Table 15-1 * Flash-Based FPGAs Supporting Voltage Switching Circuit. 15-2 The "Circuit Description" section was updated to include IGLOO PLUS core operation from 1.2 V to 1.5 V in 50 mV increments. 15-3 The "Actel's Flash Families Support Voltage Switching Circuit" section was revised to include new families and make the information more concise. 15-2 v1.2 1 5 -7 16 - Microprocessor Programming of Actel's LowPower Flash Devices Introduction The Fusion, IGLOO,(R) and ProASIC(R)3 families of flash FPGAs support in-system programming (ISP) with the use of a microprocessor. Flash-based FPGAs store their configuration information in the actual cells within the FPGA fabric. SRAM-based devices need an external configuration memory, and hybrid nonvolatile devices store the configuration in a flash memory inside the same package as the SRAM FPGA. Since the programming of a true flash FPGA is simpler, requiring only one stage, it makes sense that programming with a microprocessor in-system should be simpler than with other SRAM FPGAs. This reduces bill-of-materials costs and printed circuit board (PCB) area, and increases system reliability. Nonvolatile flash technology also gives the low-power flash devices the advantage of a secure, lowpower, live-at-power-up, and single-chip solution. Low-power flash devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These features enable engineers to create high-density systems using existing ASIC or FPGA design flows and tools. This document is an introduction to microprocessor programming only. To explain the difference between the options available, user's guides for DirectC and STAPL provide more detail on implementing each style. Microprocessor Internal/External Memory Running DirectC Internal RAM On Board Memory Device .dat file I/O Functions JTAG Bus Flash Device Figure 16-1 * ISP Using Microprocessor v1.4 1 6 -1 Microprocessor Programming of Actel's Low-Power Flash Devices Microprocessor Programming Support in Flash Devices The flash-based FPGAs listed in Table 16-1 support programming with a microprocessor and the functions described in this document. Table 16-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 16-1. Where the information applies to only one device or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 16-1. Where the information applies to only one device or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 1 6 -2 v1.4 Microprocessor Programming of Actel's Low-Power Flash Devices Programming Algorithm JTAG Interface The low-power flash families are fully compliant with the IEEE 1149.1 (JTAG) standard. They support all the mandatory boundary scan instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS) as well as six optional public instructions (USERCODE, IDCODE, HIGHZ, and CLAMP). IEEE 1532 The low-power flash families are also fully compliant with the IEEE 1532 programming standard. The IEEE 1532 standard adds programming instructions and associated data registers to devices that comply with the IEEE 1149.1 standard (JTAG). These instructions and registers extend the capabilities of the IEEE 1149.1 standard such that the Test Access Port (TAP) can be used for configuration activities. The IEEE 1532 standard greatly simplifies the programming algorithm, reducing the amount of time needed to implement microprocessor ISP. Implementation Overview To implement device programming with a microprocessor, the user should first download the Cbased STAPL player or DirectC code from the Actel website. (See the Actel website for future updates regarding the STAPL player and DirectC code). Using the easy-to-follow Actel user's guide, create the low-level application programming interface (API) to provide the necessary basic functions. These API functions act as the interface between the programming software and the actual hardware (Figure 16-2). Programming algorithm and data STAPL File STAPL Player or DirectC Programming software I/O and memory functions API Figure 16-2 * Device Programming Code Relationship The API is then linked with the STAPL player or DirectC and compiled using the microprocessor's compiler. Once the entire code is compiled, the user must download the resulting binary into the MCU system's program memory (such as ROM, EEPROM, or flash). The system is now ready for programming. To program a design into the FPGA, the user creates a bitstream or STAPL file using the Actel Designer software, downloads it into the MCU system's volatile memory, and activates the stored programming binary file (Figure 16-3 on page 16-4). Once the programming is completed, the bitstream or STAPL file can be removed from the system, as the configuration profile is stored in the flash FPGA fabric and does not need to be reloaded at every system power-on. v1.4 1 6 -3 Microprocessor Programming of Actel's Low-Power Flash Devices Programming Software Source Code Programming File Microprocessor Compiler BIN File Download to System Program Device Figure 16-3 * MCU FPGA Programming Model FlashROM Actel low-power flash devices have 1 kbit of user-accessible, nonvolatile, FlashROM on-chip. This nonvolatile FlashROM can be programmed along with the core or on its own using the standard IEEE 1532 JTAG programming interface. The FlashROM is architected as eight pages of 128 bits. Each page can be individually programmed (erased and written). Additionally, on-chip AES security decryption can be used selectively to load data securely into the FlashROM (e.g., over public or private networks, such as the Internet). Refer to FlashROM in Actel's Low-Power Flash Devices. 1 6 -4 v1.4 Microprocessor Programming of Actel's Low-Power Flash Devices STAPL vs. DirectC Programming the low-power flash devices is performed using DirectC or the STAPL player. Both tools use the STAPL file as an input. DirectC is a compiled language, whereas STAPL is an interpreted language. Microprocessors will be able to load the FPGA using DirectC much more quickly than STAPL. This speed advantage becomes more apparent when lower clock speeds of 8or 16-bit microprocessors are used. DirectC also requires less memory than STAPL, since the programming algorithm is directly implemented. STAPL does have one advantage over DirectC-- the ability to upgrade. When a new programming algorithm is required, the STAPL user simply needs to regenerate a STAPL file using the latest version of the Designer software and download it to the system. The DirectC user must download the latest version of DirectC from Actel, compile everything, and download the result into the system (Figure 16-4). STAPL Flow DirectC Flow Generate the New STAPL File DirectC Source Code Download to System Microprocessor Compiler Program Device BIN File Input STAPL File Download to System Program Device Figure 16-4 * STAPL vs. DirectC v1.4 1 6 -5 Microprocessor Programming of Actel's Low-Power Flash Devices Remote Upgrade via TCP/IP Transmission Control Protocol (TCP) provides a reliable bitstream transfer service between two endpoints on a network. TCP depends on Internet Protocol (IP) to move packets around the network on its behalf. TCP protects against data loss, data corruption, packet reordering, and data duplication by adding checksums and sequence numbers to transmitted data and, on the receiving side, sending back packets and acknowledging the receipt of data. The system containing the low-power flash device can be assigned an IP address when deployed in the field. When the device requires an update (core or FlashROM), the programming instructions along with the new programming data (AES-encrypted cipher text) can be sent over the Internet to the target system via the TCP/IP protocol. Once the MCU receives the instruction and data, it can proceed with the FPGA update. Low-power flash devices support Message Authentication Code (MAC), which can be used to validate data for the target device. More details are given in the "Message Authentication Code (MAC) Validation/Authentication" section on page 16-6. Hardware Requirement To facilitate the programming of the low-power flash families, the system must have a microprocessor (with access to the device JTAG pins) to process the programming algorithm, memory to store the programming algorithm, programming data, and the necessary programming voltage. Refer to the relevant datasheet for programming voltages. Security Read-Back Prevention The low-power flash devices are designed with security in mind. Even without any security measures (such as FlashLock with AES), it is not possible to read back the programming data from a programmed device. Upon programming completion, the programming algorithm will reload the programming data into the device. The device will then use built-in circuitry to determine if it was programmed correctly. As an additional security measure, the devices are equipped with AES decryption. AES works in two steps. The first step is to program a key into the devices in a secure or trusted programming center (such as Actel In-House Programming (IHP) center). The second step is to encrypt any programming files with the same encryption key. The encrypted programming file will only work with the devices that have the same key. The AES used in the low-power flash families is the 128-bit AES decryption engine (Rijndael algorithm). Message Authentication Code (MAC) Validation/Authentication As part of the AES decryption flow, the devices are equipped with a MAC validation/authentication system. MAC is an authentication tag, also called a checksum, derived by applying an on-chip authentication scheme to a STAPL file as it is loaded into the FPGA. MACs are computed and verified with the same key so they can only be verified by the intended recipient. When the MCU system receives the AES-encrypted programming data (cipher text), it can validate the data by loading it into the FPGA and performing a MAC verification prior to loading the data, via a second programming pass, into the FPGA core cells. This prevents erroneous or corrupt data from getting into the FPGA. Low-power flash devices with AES and MAC are superior to devices with only DES or 3DES encryption. Because the MAC verifies the correctness of the data, the FPGA is protected from erroneous loading of invalid programming data that could damage a device (Figure 16-5 on page 16-7). The AES with MAC enables field updates over public networks without fear of having the design stolen. An encrypted programming file can only work on devices with the correct key, rendering 1 6 -6 v1.4 Microprocessor Programming of Actel's Low-Power Flash Devices any stolen files useless to the thief. To learn more about the low-power flash devices' security features, refer to Security in Low-Power Flash Devices. ProASIC3 MAC Validation Designer Software AES KEY AES Encryption Decrypted Stream AES Decryption Programming Control TCP/IP Public Network Encrypted Stream Encrypted Stream Figure 16-5 * ProASIC3 Device Encryption Flow Conclusion The Actel Fusion, IGLOO, and ProASIC3 FPGAs are ideal for applications that require field upgrades. The single-chip devices save board space by eliminating the need for EEPROM. The built-in AES with MAC enables transmission of programming data over any network without fear of design theft. Fusion, IGLOO, and ProASIC3 FPGAs are IEEE 1532-compliant and support STAPL, making the target programming software easy to implement. v1.4 1 6 -7 Microprocessor Programming of Actel's Low-Power Flash Devices Related Documents Handbook Documents FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Security in Low-Power Flash Devices http://www.actel.com/documents/LPD_Security_HBs.pdf Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-016-4 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in the Current Version (v1.4) Page v1.3 (October 2008) IGLOO nano and ProASIC3 nano devices were added to Table 16-1 * FlashBased FPGAs. 16-2 v1.2 (June 2008) The "Microprocessor Programming Support in Flash Devices" section was revised to include new families and make the information more concise. 16-2 v1.1 (March 2008) The following changes were made to the family descriptions in Table 16-1 * Flash-Based FPGAs: 16-2 v1.0 (January 2008) 1 6 -8 * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. The "Microprocessor Programming Support in Flash Devices" section was updated to include information on the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. v1.4 16-2 Boundary Scan and UJTAG 17 - Boundary Scan in Low-Power Flash Devices Boundary Scan Low-power flash devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture and the set of mechanisms for boundary scan testing. JTAG operations are used during boundary scan testing. The basic boundary scan logic circuit is composed of the TAP controller, test data registers, and instruction register (Figure 17-2 on page 17-4). Low-power flash devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (LSB, ID number, part number, and version). The boundary scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary scan register cells, each with serial-in, serial-out, parallel-in, and parallel-out pins. TAP Controller State Machine The TAP controller is a 4-bit state machine (16 states) that operates as shown in Figure 17-1. The 1s and 0s represent the values that must be present on TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the TestLogic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain HIGH for five TCK cycles. The TRST pin can also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. 1 TEST_LOGIC_RESET 0 0 1 1 RUN_TEST_IDLE 1 SELECT_DR SELECT_IR 0 0 CAPTURE_DR 1 1 CAPTURE_IR 0 0 0 SHIFT_DR 0 SHIFT_IR 1 1 1 1 EXIT1_DR EXIT1_IR 0 0 0 PAUSE_DR 1 1 EXIT2_DR 0 0 EXIT2_IR 1 1 UPDATE_DR 1 0 PAUSE_IR 0 UPDATE_IR 1 0 Figure 17-1 * TAP Controller State Machine v1.4 1 7 -1 Boundary Scan in Low-Power Flash Devices Actel's Flash Devices Support the JTAG Feature The flash-based FPGAs listed in Table 17-1 support the JTAG feature and the functions described in this document. Table 17-1 * Flash-Based FPGAs Family* Series IGLOO (R) ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC(R)3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 17-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 17-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 1 7 -2 v1.4 Boundary Scan in Low-Power Flash Devices Boundary Scan Support in Low-Power Devices The information in this document applies to all Fusion, IGLOO, and ProASIC3 devices. For IGLOO, IGLOO PLUS, and ProASIC3L devices, the Flash*Freeze pin must be deasserted for successful boundary scan operations. Devices cannot enter JTAG mode directly from Flash*Freeze mode. Boundary Scan Opcodes Low-power flash devices support all mandatory IEEE 1149.1 instructions SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 17-2). (EXTEST, Table 17-2 * Boundary Scan Opcodes Hex Opcode EXTEST 00 HIGHZ 07 USERCODE 0E SAMPLE/PRELOAD 01 IDCODE 0F CLAMP 05 BYPASS FF Boundary Scan Chain The serial pins are used to serially connect all the boundary scan register cells in a device into a boundary scan register chain (Figure 17-2 on page 17-4), which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic I/O tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS, TDI, and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins" description in Pin Descriptions for pull-up/-down recommendations for TDO and TCK pins. v1.4 1 7 -3 Boundary Scan in Low-Power Flash Devices I/O I/O I/O I/O I/O TDI Test Data Registers Instruction Register TAP Controller Device Logic TDO I/O TRST I/O TMS I/O TCK I/O Bypass Register I/O I/O I/O I/O I/O Figure 17-2 * Boundary Scan Chain Board-Level Recommendations Table 17-3 gives pull-down recommendations for the TRST and TCK pins. Table 17-3 * TRST and TCK Pull-Down Recommendations VJTAG Tie-Off Resistance* VJTAG at 3.3 V 200 to 1 k VJTAG at 2.5 V 200 to 1 k VJTAG at 1.8 V 500 to 1 k VJTAG at 1.5 V 500 to 1 k * Equivalent parallel resistance if more than one device is on JTAG chain (Figure 17-3) 1 7 -4 v1.4 Boundary Scan in Low-Power Flash Devices 1.5 V VJTAG JTAG Header TRST GND TCK 2 k TDO TDI Actel FPGA 1 TDO TDI Actel FPGA 2 1.5 k 2 k 1.5 k 2 k TDO TDI Actel FPGA 3 TDO TDI Actel FPGA 4 1.5 k 2 k 1.5 k Note: TCK is correctly wired with an equivalent tie-off resistance of 500 , which satisfies the table for VJTAG of 1.5 V. The resistor values for TRST are not appropriate in this case, as the tie-off resistance of 375 is below the recommended minimum for VJTAG = 1.5 V, but would be appropriate for a VJTAG setting of 2.5 V or 3.3 V. Figure 17-3 * Parallel Resistance on JTAG Chain of Devices Related Documents Handbook Documents Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions_HBs.pdf v1.4 1 7 -5 Boundary Scan in Low-Power Flash Devices Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet. To improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage information. No technical changes were made to the content unless explicitly listed. Part Number 51700094-019-3 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.4) Page v1.3 (October 2008) IGLOO nano and ProASIC3 nano devices were added to Table 17-1 * Flash-Based FPGAs. 17-2 v1.2 (June 2008) The "Boundary Scan Support in Low-Power Devices" section was revised to include new families and make the information more concise. 17-3 v1.1 (March 2008) The following changes were Table 17-1 * Flash-Based FPGAs: in 17-2 The chapter was updated to include the IGLOO PLUS family and information regarding 15 k gate devices. N/A The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 17-2 v1.0 (January 2008) 1 7 -6 made to the family descriptions * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. v1.4 18 - UJTAG Applications in Actel's Low-Power Flash Devices Introduction In Fusion, IGLOO,(R) and ProASIC(R)3 devices, there is bidirectional access from the JTAG port to the core VersaTiles during normal operation of the device (Figure 18-1). User JTAG (UJTAG) is the ability for the design to use the JTAG ports for access to the device for updates, etc. While regular JTAG is used, the UJTAG tiles, located at the southeast area of the die, are directly connected to the JTAG Test Access Port (TAP) Controller in normal operating mode. As a result, all the functional blocks of the device, such as Clock Conditioning Circuits (CCCs) with PLLs, SRAM blocks, embedded FlashROM, flash memory blocks, and I/O tiles, can be reached via the JTAG ports. The UJTAG functionality is available by instantiating the UJTAG macro directly in the source code of a design. Access to the FPGA core VersaTiles from the JTAG ports enables users to implement different applications using the TAP Controller (JTAG port). This document introduces the UJTAG tile functionality and discusses a few application examples. However, the possible applications are not limited to what is presented in this document. UJTAG can serve different purposes in many designs as an elementary or auxiliary part of the design. For detailed usage information, refer to Boundary Scan in Low-Power Flash Devices. UJTAG Address Generation and Data Serlialization UIREG[7:0] Enable FROM RESET TDO TDI TMS TCK TRST URSTB UDRUPD Control UDRCK CLK UDRCAP SDI UDRSH Addr[6:0] Addr [6:0] Data[7:0] Data[7:0] SDO UTDI UTDO Figure 18-1 * Block Diagram of Using UJTAG to Read FlashROM Contents v1.4 1 8 -1 UJTAG Applications in Actel's Low-Power Flash Devices UJTAG Support in Flash-Based Devices The flash-based FPGAs listed in Table 18-1 support the UJTAG feature and the functions described in this document. Table 18-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Fusion Fusion Mixed-signal FPGA integrating ProASIC3 FPGA fabric, programmable analog block, support for ARM(R) CortexTM-M1 soft processors, and flash memory into a monolithic device Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 18-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 18-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 1 8 -2 v1.4 UJTAG Applications in Actel's Low-Power Flash Devices UJTAG Macro The UJTAG tiles can be instantiated in a design using the UJTAG macro from the Fusion, IGLOO, or ProASIC3 macro library. Note that "UJTAG" is a reserved name and cannot be used for any other user-defined blocks. A block symbol of the UJTAG tile macro is presented in Figure 18-2. In this figure, the ports on the left side of the block are connected to the JTAG TAP Controller, and the right-side ports are accessible by the FPGA core VersaTiles. The TDI, TMS, TDO, TCK, and TRST ports of UJTAG are only provided for design simulation purposes and should be treated as external signals in the design netlist. However, these ports must NOT be connected to any I/O buffer in the netlist. Figure 18-3 on page 18-4 illustrates the correct connection of the UJTAG macro to the user design netlist. Actel Designer software will automatically connect these ports to the TAP during place-and-route. Table 18-2 gives the port descriptions for the rest of the UJTAG ports: Table 18-2 * UJTAG Port Descriptions Port Description UIREG [7:0] This 8-bit bus carries the contents of the JTAG Instruction Register of each device. Instruction Register values 16 to 127 are not reserved and can be employed as user-defined instructions. URSTB URSTB is an active-low signal and will be asserted when the TAP Controller is in Test-Logic-Reset mode. URSTB is asserted at power-up, and a power-on reset signal resets the TAP Controller. URSTB will stay asserted until an external TAP access changes the TAP Controller state. UTDI This port is directly connected to the TAP's TDI signal. UTDO This port is the user TDO output. Inputs to the UTDO port are sent to the TAP TDO output MUX when the IR address is in user range. UDRSH Active-high signal enabled in the ShiftDR TAP state UDRCAP Active-high signal enabled in the CaptureDR TAP state UDRCK This port is directly connected to the TAP's TCK signal. UDRUPD Active-high signal enabled in the UpdateDR TAP state TDO TDI TMS UIREG0 UIREG1 UIREG2 UIREG3 UIREG4 UIREG5 UIREG6 UIREG7 URSTB UDRUPD TCK TRST UDRCK UDRCAP UDRSH UTDI UTDO Figure 18-2 * UJTAG Tile Block Symbol v1.4 1 8 -3 UJTAG Applications in Actel's Low-Power Flash Devices a) CORRECT Instantiation UIREG[7:0] TDO URSTB TDI INPUTS UDRUPD UDRCK TMS UDRCAP TCK FPGA VersaTiles UDRSH TRST UTDI UTDO OUTPUTS b) INCORRECT Instantiation UIREG[7:0] TDO URSTB TDI INPUTS UDRUPD UDRCK TMS UDRCAP TCK FPGA VersaTiles UDRSH TRST UTDI UTDO OUTPUTS Note: Do not connect JTAG pins (TDO, TDI, TMS, TCK, or TRST) to I/Os in the design. Figure 18-3 * Connectivity Method of UJTAG Macro UJTAG Operation There are a few basic functions of the UJTAG macro that users must understand before designing with it. The most important fundamental concept of the UJTAG design is its connection with the TAP Controller state machine. TAP Controller State Machine The 16 states of the TAP Controller state machine are shown in Figure 18-4 on page 18-5. The 1s and 0s, shown adjacent to the state transitions, represent the TMS values that must be present at the time of a rising TCK edge for a state transition to occur. In the states that include the letters "IR," the instruction register operates; in the states that contain the letters "DR," the test data register operates. The TAP Controller receives two control inputs, TMS and TCK, and generates control and clock signals for the rest of the test logic. On power-up (or the assertion of TRST), the TAP Controller enters the Test-Logic-Reset state. To reset the controller from any other state, TMS must be held HIGH for at least five TCK cycles. After reset, the TAP state changes at the rising edge of TCK, based on the value of TMS. 1 8 -4 v1.4 UJTAG Applications in Actel's Low-Power Flash Devices 1 Test_Logic_Reset 0 0 Run_Test/ Idle 1 1 Select_ DR_Scan 0 1 1 Capture_DR Capture_IR 0 0 0 Shift_DR 1 Exit1_DR 1 1 Exit1_IR 0 0 Pause_DR 0 Pause_IR 1 0 1 Exit2_DR 0 Exit2_IR 1 1 Update_DR 1 0 Shift_IR 1 0 1 Select_ IR_Scan 0 0 Update_IR 1 0 Figure 18-4 * TAP Controller State Diagram UJTAG Port Usage UIREG[7:0] hold the contents of the JTAG instruction register. The UIREG vector value is updated when the TAP Controller state machine enters the Update_IR state. Instructions 16 to 127 are userdefined and can be employed to encode multiple applications and commands within an application. Loading new instructions into the UIREG vector requires users to send appropriate logic to TMS to put the TAP Controller in a full IR cycle starting from the Select IR_Scan state and ending with the Update_IR state. UTDI, UTDO, and UDRCK are directly connected to the JTAG TDI, TDO, and TCK ports, respectively. The TDI input can be used to provide either data (TAP Controller in the Shift_DR state) or the new contents of the instruction register (TAP Controller in the Shift_IR state). UDRSH, UDRUPD, and UDRCAP are HIGH when the TAP Controller state machine is in the Shift_DR, Update_DR, and Capture_DR states, respectively. Therefore, they act as flags to indicate the stages of the data shift process. These flags are useful for applications in which blocks of data are shifted into the design from JTAG pins. For example, an active UDRSH can indicate that UTDI contains the data bitstream, and UDRUPD is a candidate for the end-of-data-stream flag. As mentioned earlier, users should not connect the TDI, TDO, TCK, TMS, and TRST ports of the UJTAG macro to any port or net of the design netlist. The Designer software will automatically handle the port connection. v1.4 1 8 -5 UJTAG Applications in Actel's Low-Power Flash Devices Typical UJTAG Applications Bidirectional access to the JTAG port from VersaTiles--without putting the device into test mode-- creates flexibility to implement many different applications. This section describes a few of these. All are based on importing/exporting data through the UJTAG tiles. Clock Conditioning Circuitry--Dynamic Reconfiguration In low-power flash devices, CCCs, which include PLLs, can be configured dynamically through either an 81-bit embedded shift register or static flash programming switches. These 81 bits control all the characteristics of the CCC: routing MUX architectures, delay values, divider values, etc. Table 18-3 lists the 81 configuration bits in the CCC. Table 18-3 * Configuration Bits of Fusion, IGLOO, and ProASIC3 CCC Blocks Bit Number(s) Control Function 80 RESET ENABLE 79 DYNCSEL 78 DYNBSEL 77 DYNASEL <76:74> VCOSEL [2:0] 73 STATCSEL 72 STATBSEL 71 STATASEL <70:66> DLYC [4:0] <65:61> DLYB {4:0] <60:56> DLYGLC [4:0] <55:51> DLYGLB [4:0] <50:46> DLYGLA [4:0] 45 XDLYSEL <44:40> FBDLY [4:0] <39:38> FBSEL <37:35> OCMUX [2:0] <34:32> OBMUX [2:0] <31:29> OAMUX [2:0] <28:24> OCDIV [4:0] <23:19> OBDIV [4:0] <18:14> OADIV [4:0] <13:7> FBDIV [6:0] <6:0> FINDIV [6:0] The embedded 81-bit shift register (for the dynamic configuration of the CCC) is accessible to the VersaTiles, which, in turn, have access to the UJTAG tiles. Therefore, the CCC configuration shift register can receive and load the new configuration data stream from JTAG. Dynamic reconfiguration eliminates the need to reprogram the device when reconfiguration of the CCC functional blocks is needed. The CCC configuration can be modified while the device continues to operate. Employing the UJTAG core requires the user to design a module to provide the configuration data and control the CCC configuration shift register. In essence, this is a userdesigned TAP Controller requiring chip resources. 1 8 -6 v1.4 UJTAG Applications in Actel's Low-Power Flash Devices Similar reconfiguration capability exists in the Actel ProASICPLUS(R) family. The only difference is the number of shift register bits controlling the CCC (27 in ProASICPLUS and 81 in IGLOO, ProASIC3, and Fusion). Fine Tuning In some applications, design constants or parameters need to be modified after programming the original design. The tuning process can be done using the UJTAG tile without reprogramming the device with new values. If the parameters or constants of a design are stored in distributed registers or embedded SRAM blocks, the new values can be shifted onto the JTAG TAP Controller pins, replacing the old values. The UJTAG tile is used as the "bridge" for data transfer between the JTAG pins and the FPGA VersaTiles or SRAM logic. Figure 18-5 shows a flow chart example for finetuning application steps using the UJTAG tile. In Figure 18-5, the TMS signal sets the TAP Controller state machine to the appropriate states. The flow mainly consists of two steps: a) shifting the defined instruction and b) shifting the new data. If the target parameter is constantly used in the design, the new data can be shifted into a temporary shift register from UTDI. The UDRSH output of UJTAG can be used as a shift-enable signal, and UDRCK is the shift clock to the shift register. Once the shift process is completed and the TAP Controller state is moved to the Update_DR state, the UDRUPD output of the UJTAG can latch the new parameter value from the temporary register into a permanent location. This avoids any interruption or malfunctioning during the serial shift of the new value. TAP Controller in Test_Logic_Reset State Set TAP state to SHIFT_DR Set TAP state to SHIFT_IR Shift data into TDI and record UTDI in a shift register Shift the user-defined instruction of tuning application Set TAP state in Update_DR Set TAP state to Update_IR UIREG Equal to the user-defined instruction Yes Latch the recorded data onto the location of stored parameter No Figure 18-5 * Flow Chart Example of Fine-Tuning an Application Using UJTAG v1.4 1 8 -7 UJTAG Applications in Actel's Low-Power Flash Devices Silicon Testing and Debugging In many applications, the design needs to be tested, debugged, and verified on real silicon or in the final embedded application. To debug and test the functionality of designs, users may need to monitor some internal logic (or nets) during device operation. The approach of adding design test pins to monitor the critical internal signals has many disadvantages, such as limiting the number of user I/Os. Furthermore, adding external I/Os for test purposes may require additional or dedicated board area for testing and debugging. The UJTAG tiles of low-power flash devices offer a flexible and cost-effective solution for silicon test and debug applications. In this solution, the signals under test are shifted out to the TDO pin of the TAP Controller. The main advantage is that all the test signals are monitored from the TDO pin; no pins or additional board-level resources are required. Figure 18-6 illustrates this technique. Multiple test nets are brought into an internal MUX architecture. The selection of the MUX is done using the contents of the TAP Controller instruction register, where individual instructions (values from 16 to 127) correspond to different signals under test. The selected test signal can be synchronized with the rising or falling edge of TCK (optional) and sent out to UTDO to drive the TDO output of JTAG. The test and debug procedure is not limited to the example in Figure 18-5 on page 18-7. Users can customize the debug and test interface to make it appropriate for their applications. For example, multiple test signals can be registered and then sent out through UTDO, each at a different edge of TCK. In other words, n signals are sampled with an FTCK / n sampling rate. The bandwidth of the information sent out to TDO is always proportional to the frequency of TCK. Internal Test Nets Instruction Decode UIREG[7:0] To Scope Channel TDO TDI URSTB UDRUPD UDRCK TMS TCK TRST D Q UDRCAP CLK UDRSH UTDI UTDO Figure 18-6 * UJTAG Usage Example in Test and Debug Applications SRAM Initialization Users can also initialize embedded SRAMs of the low-power flash devices. The initialization of the embedded SRAM blocks of the design can be done using UJTAG tiles, where the initialization data is imported using the TAP Controller. Similar functionality is available in ProASICPLUS devices using JTAG. The guidelines for implementation and design examples are given in the RAM Initialization and ROM Emulation in ProASICPLUS Devices application note. SRAMs are volatile by nature; data is lost in the absence of power. Therefore, the initialization process should be done at each power-up if necessary. 1 8 -8 v1.4 UJTAG Applications in Actel's Low-Power Flash Devices FlashROM Read-Back Using JTAG The low-power flash architecture contains a dedicated nonvolatile FlashROM block, which is formatted into eight 128-bit pages. For more information on FlashROM, refer to FlashROM in Actel's Low-Power Flash Devices. The contents of FlashROM are available to the VersaTiles during normal operation through a read operation. As a result, the UJTAG macro can be used to provide the FlashROM contents to the JTAG port during normal operation. Figure 18-7 illustrates a simple block diagram of using UJTAG to read the contents of FlashROM during normal operation. The FlashROM read address can be provided from outside the FPGA through the TDI input or can be generated internally using the core logic. In either case, data serialization logic is required (Figure 18-7) and should be designed using the VersaTile core logic. FlashROM contents are read asynchronously in parallel from the flash memory and shifted out in a synchronous serial format to TDO. Shifting the serial data out of the serialization block should be performed while the TAP is in UDRSH mode. The coordination between TCK and the data shift procedure can be done using the TAP state machine by monitoring UDRSH, UDRCAP, and UDRUPD. UJTAG Address Generation and Data Serlialization UIREG[7:0] Enable FROM RESET TDO TDI TMS TCK TRST URSTB UDRUPD Control UDRCK CLK UDRCAP SDI UDRSH Addr[6:0] Addr [6:0] Data[7:0] Data[7:0] SDO UTDI UTDO Figure 18-7 * Block Diagram of Using UJTAG to Read FlashROM Contents Conclusion Actel low-power flash FPGAs offer many unique advantages, such as security, nonvolatility, reprogrammablity, and low power--all in a single chip. In addition, Fusion, IGLOO, and ProASIC3 devices provide access to the JTAG port from core VersaTiles while the device is in normal operating mode. A wide range of available user-defined JTAG opcodes allows users to implement various types of applications, exploiting this feature of these devices. The connection between the JTAG port and core tiles is implemented through an embedded and hardwired UJTAG tile. A UJTAG tile can be instantiated in designs using the UJTAG library cell. This document presents multiple examples of UJTAG applications, such as dynamic reconfiguration, silicon test and debug, finetuning of the design, and RAM initialization. Each of these applications offers many useful advantages. v1.4 1 8 -9 UJTAG Applications in Actel's Low-Power Flash Devices Related Documents Application Notes RAM Initialization and ROM Emulation in ProASICPLUS Devices http://www.actel.com/documents/APA_RAM_Initd_AN.pdf Handbook Documents Boundary Scan in Low-Power Flash Devices http://www.actel.com/documents/LPD_BoundaryScan_HBs.pdf FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information Part Number 51700094-020-4 Revised December 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.4) Page v1.3 (October 2008) IGLOO nano and ProASIC3 nano devices were added to Table 18-1 * Flash-Based FPGAs. 18-2 v1.2 (June 2008) The "UJTAG Support in Flash-Based Devices" section was revised to include new families and make the information more concise. 18-2 The title of Table 18-3 * Configuration Bits of Fusion, IGLOO, and ProASIC3 CCC Blocks was revised to include Fusion. 18-6 The following changes were Table 18-1 * Flash-Based FPGAs: in 18-2 The chapter was updated to include the IGLOO PLUS family and information regarding 15 k gate devices. N/A The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 18-2 v1.1 (March 2008) v1.0 (January 2008) 1 8 -1 0 made to the family descriptions * ProASIC3L was updated to include 1.5 V. * The number of PLLs for ProASIC3E was changed from five to six. v1.4 Board-Level Requirements 19 - Power-Up/-Down Behavior of Low-Power Flash Devices Introduction Actel's low-power flash devices are flash-based FPGAs manufactured on a 0.13 m process node. These devices offer a single-chip, reprogrammable solution and support Level 0 live at power-up (LAPU) due to their nonvolatile architecture. Actel's low-power flash FPGA families are optimized for logic area, I/O features, and performance. IGLOO(R) devices are optimized for power, making them the industry's lowest power programmable solution. IGLOO PLUS FPGAs offer enhanced I/O features beyond those of the IGLOO ultra-lowpower solution for I/O-intensive low-power applications. IGLOO nano devices are the industry's lowest-power cost-effective solution. ProASIC3(R)L FPGAs balance low power with high performance. The ProASIC3 family is Actel's high-performance flash FPGA solution. ProASIC3 nano devices offer the lowest-cost solution with enhanced I/O capabilities. Actel's low-power flash devices exhibit very low transient current on each power supply during power-up. The peak value of the transient current depends on the device size, temperature, voltage levels, and power-up sequence. The following devices can have inputs driven in while the device is not powered: * IGLOO (AGL015 and AGL030) * IGLOO nano (all devices) * IGLOO PLUS (AGLP030, AGLP060, AGLP125) * IGLOOe (AGLE600, AGLE3000) * ProASIC3L (A3PE3000L) * ProASIC3 (A3P015, A3P030) * ProASIC3 nano (all devices) * ProASIC3E (A3PE600, A3PE1500, A3PE3000) * Military ProASIC3EL (A3PE600L, A3PE3000L, but not A3P1000) * RT ProASIC3 (RT3PE600L, RT3PE3000L) The driven I/Os do not pull up power planes, and the current draw is limited to very small leakage current, making them suitable for applications that require cold-sparing. These devices are hotswappable, meaning they can be inserted in a live power system.1 1. For more details on the levels of hot-swap compatibility in Actel's low-power flash devices, refer to the "Hot-Swap Support" section in the I/O Structures chapter of the handbook for the device you are using. v1.2 1 9 -1 Power-Up/-Down Behavior of Low-Power Flash Devices Actel's Flash Devices Support Power-Up Behavior The flash FPGAs listed in Table 19-1 support power-up behavior and the functions described in this document. Table 19-1 * Flash-Based FPGAs Family* Series IGLOO ProASIC3 Description IGLOO Ultra-low-power 1.2 V to 1.5 V FPGAs with Flash*Freeze technology IGLOOe Higher density IGLOO FPGAs with six PLLs and additional I/O standards IGLOO nano The industry's lowest-power, smallest-size solution IGLOO PLUS IGLOO FPGAs with enhanced I/O capabilities ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E Higher density ProASIC3 FPGAs with six PLLs and additional I/O standards ProASIC3 nano Lowest-cost solution with enhanced I/O capabilities ProASIC3L ProASIC3 FPGAs supporting 1.2 V to 1.5 V with Flash*Freeze technology RT ProASIC3 Radiation-tolerant RT3PE600L and RT3PE3000L Military ProASIC3/EL Military temperature A3PE600L, A3P1000, and A3PE3000L Automotive ProASIC3 ProASIC3 FPGAs qualified for automotive applications Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information. IGLOO Terminology In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 19-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 19-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated. To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio. 1 9 -2 v1.2 Power-Up/-Down Behavior of ProASIC3/E Devices Power-Up/-Down Sequence and Transient Current Actel's low-power flash devices use the following main voltage pins during normal operation:2 * VCCPLX * VJTAG * VCC: Voltage supply to the FPGA core - VCC is 1.5 V 0.075 V for IGLOO, IGLOO nano, IGLOO PLUS, and ProASIC3 devices operating at 1.5 V. - VCC is 1.2 V 0.06 V for IGLOO, IGLOO nano, IGLOO PLUS, and ProASIC3L devices operating at 1.2 V. - V5 devices will require a 1.5 V VCC supply, whereas V2 devices can utilize either a 1.2 V or 1.5 V VCC. * VCCIBx: Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. * VMVx: Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. (Note: IGLOO nano, IGLOO PLUS, and ProASIC3 nano devices do not have VMVx supply pins.) The I/O bank VMV pin must be tied to the VCCI pin within the same bank. Therefore, the supplies that need to be powered up/down during normal operation are VCC and VCCI. These power supplies can be powered up/down in any sequence during normal operation of IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, ProASIC3, and ProASIC3 nano FPGAs. During power-up, I/Os in each bank will remain tristated until the last supply (either VCCIBx or VCC) reaches its functional activation voltage. Similarly, during power-down, I/Os of each bank are tristated once the first supply reaches its brownout deactivation voltage. Although Actel's low-power flash devices have no power-up or power-down sequencing requirements, Actel identifies the following power conditions that will result in higher than normal transient current. Use this information to help maximize power savings: Actel recommends tying VCCPLX to VCC and using proper filtering circuits to decouple VCC noise from the PLL. a. If VCCPLX is powered up before VCC, a static current of up to 5 mA (typical) per PLL may be measured on VCCPLX. i. The current vanishes as soon as VCC reaches the VCCPLX voltage level. ii. The same current is observed at power-down (VCC before VCCPLX). b. If VCCPLX is powered up simultaneously or after VCC: i. Actel's low-power flash devices exhibit very low transient current on VCC. For ProASIC3 devices, the maximum transient current on VCC does not exceed the maximum standby current specified in the device datasheet. The source of transient current, also known as inrush current, varies depending on the FPGA technology. Due to their volatile technology, the internal registers in SRAM FPGAs must be initialized before configuration can start. This initialization is the source of significant inrush current in SRAM FPGAs during power-up. Due to the nonvolatile nature of flash technology, lowpower flash devices do not require any initialization at power-up, and there is very little or no crossbar current through PMOS and NMOS devices. Therefore, the transient current at power-up is significantly less than for SRAM FPGAs. Figure 19-1 on page 19-4 illustrates the types of power consumption by SRAM FPGAs compared to Actel's antifuse and flash FPGAs. 2. For more information on Actel FPGA voltage supplies, refer to the appropriate datasheet located at http://www.actel.com/techdocs/ds. v1.2 1 9 -3 Power-Up/-Down Behavior of Low-Power Flash Devices Current Power-On Inrush SRAM FPGAs SRAM Actel FPGAs Active Frequency Dependent System Supply Voltage Configuration SRAM FPGAs Static Time (or frequency) Figure 19-1 * Types of Power Consumption in SRAM FPGAs and Actel Nonvolatile FPGAs Transient Current on VCC The characterization of the transient current on VCC is performed on nearly all devices within the IGLOO, ProASIC3L, and ProASIC3 families. A sample size of five units is used from each device family member. All the device I/Os are internally pulled down while the transient current measurements are performed. For ProASIC3 devices, the measurements at typical conditions show that the maximum transient current on VCC, when the power supply is powered at ramp-rates ranging from 15 V/ms to 0.15 V/ms, does not exceed the maximum standby current specified in the device datasheets. Refer to ProASIC3 DC and Switching Characteristics and ProASIC3E DC and Switching Characteristics for more information. Similarly, IGLOO, IGLOO nano, IGLOO PLUS, and ProASIC3L devices exhibit very low transient current on VCC. The transient current does not exceed the typical operating current of the device while in active mode. For example, the characterization of AGL600-FG256 V2 and V5 devices has shown that the transient current on VCC is typically in the range of 1-5 mA. Transient Current on VCCI The characterization of the transient current on VCCI is performed on devices within the IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3, ProASIC3 nano, and ProASIC3L groups of devices, similarly to VCC transient current measurements. For ProASIC3 devices, the measurements at typical conditions show that the maximum transient current on VCCI, when the power supply is powered at ramprates ranging from 33 V/ms to 0.33 V/ms, does not exceed the maximum standby current specified in the device datasheet. Refer to ProASIC3 DC and Switching Characteristics and ProASIC3E DC and Switching Characteristics for more information. Similarly, IGLOO, IGLOO PLUS, and ProASIC3L devices exhibit very low transient current on VCCI. The transient current does not exceed the typical operating current of the device while in active mode. For example, the characterization of AGL600-FG256 V2 and V5 devices has shown that the transient current on VCCI is typically in the range of 1-2 mA. 1 9 -4 v1.2 Power-Up/-Down Behavior of ProASIC3/E Devices I/O Behavior at Power-Up/-Down This section discusses the behavior of device I/Os, used and unused, during power-up/-down of VCC and VCCI. As mentioned earlier, VMVx and VCCIBx are tied together, and therefore, inputs and outputs are powered up/down at the same time. I/O State during Power-Up/-Down This section discusses the characteristics of I/O behavior during device power-up and power-down. Before the start of power-up, all I/Os are in tristate mode. The I/Os will remain tristated during power-up until the last voltage supply (VCC or VCCI) is powered to its functional level (power supply functional levels are discussed in the "Power-Up to Functional Time" section on page 19-6). After the last supply reaches the functional level, the outputs will exit the tristate mode and drive the logic at the input of the output buffer. Similarly, the input buffers will pass the external logic into the FPGA fabric once the last supply reaches the functional level. The behavior of user I/Os is independent of the VCC and VCCI sequence or the state of other voltage supplies of the FPGA (VPUMP and VJTAG). Figure 19-2 shows the output buffer driving HIGH and its behavior during power-up with 10 k external pull-down. In Figure 19-2, VCC is powered first, and VCCI is powered 5 ms after VCC. Figure 19-3 on page 19-6 shows the state of the I/O when VCCI is powered about 5 ms before VCC. In the circuitry shown in Figure 19-3 on page 19-6, the output is externally pulled down. During power-down, device I/Os become tristated once the first power supply (VCC or VCCI) drops below its brownout voltage level. The I/O behavior during power-down is also independent of voltage supply sequencing. Figure 19-2 * I/O State when VCC Is Powered before VCCI v1.2 1 9 -5 Power-Up/-Down Behavior of Low-Power Flash Devices Figure 19-3 * I/O State when VCCI Is Powered before VCC Power-Up to Functional Time At power-up, device I/Os exit the tristate mode and become functional once the last voltage supply in the power-up sequence (VCCI or VCC) reaches its functional activation level. The power-up-to- functional time is the time it takes for the last supply to power up from zero to its functional level. Note that the functional level of the power supply during power-up may vary slightly within the specification at different ramp-rates. Refer to Table 19-2 for the functional level of the voltage supplies at power-up. Typical I/O behavior during power-up-to-functional time is illustrated in Figure 19-2 on page 19-5 and Figure 19-3. Table 19-2 * Power-Up Functional Activation Levels for VCC and VCCI VCC Functional Activation Level (V) VCCI Functional Activation Level (V) ProASIC3, ProASIC3 nano, IGLOO, IGLOO nano, IGLOO PLUS, and ProASIC3L devices running at VCC = 1.5 V* 0.85 V 0.25 V 0.9 V 0.3 V IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L devices running at VCC = 1.2 V* 0.85 V 0.2 V 0.9 V 0.15 V Device and Note: *V5 devices will require a 1.5 V VCC supply, whereas V2 devices can utilize either a 1.2 V or 1.5 V VCC. Actel's low-power flash devices meet Level 0 LAPU; that is, they can be functional prior to VCC reaching the regulated voltage required. This important advantage distinguishes low-power flash devices from their SRAM-based counterparts. SRAM-based FPGAs, due to their volatile technology, require hundreds of milliseconds after power-up to configure the design bitstream before they become functional. Refer to Figure 19-4 on page 19-7 and Figure 19-5 on page 19-8 for more information. 1 9 -6 v1.2 Power-Up/-Down Behavior of ProASIC3/E Devices VCC = VCCI + VT Where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specifcation. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH /VOL , etc. VCC = 1.425 V Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCCI Figure 19-4 * I/O State as a Function of VCCI and VCC Voltage Levels for IGLOO V5, IGLOO nano V5, IGLOO PLUS V5, ProASIC3L, and ProASIC3 Devices Running at VCC = 1.5 V 0.075 V v1.2 1 9 -7 Power-Up/-Down Behavior of Low-Power Flash Devices VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.2 V Deactivation trip point: Vd = 0.75 V 0.2 V Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.15 V Deactivation trip point: Vd = 0.8 V 0.15 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V Figure 19-5 * I/O State as a Function of VCCI and VCC Voltage Levels for IGLOO V2, IGLOO nano V2, IGLOO PLUS V2, and ProASIC3L Devices Running at VCC = 1.2 V 0.06 V 1 9 -8 v1.2 VCCI Power-Up/-Down Behavior of ProASIC3/E Devices Brownout Voltage Brownout is a condition in which the voltage supplies are lower than normal, causing the device to malfunction as a result of insufficient power. In general, Actel does not guarantee the functionality of the design inside the flash FPGA if voltage supplies are below their minimum recommended operating condition. Actel has performed measurements to characterize the brownout levels of FPGA power supplies. Refer to Table 19-3 for device-specific brownout deactivation levels. For the purpose of characterization, a direct path from the device input to output is monitored while voltage supplies are lowered gradually. The brownout point is defined as the voltage level at which the output stops following the input. Characterization tests performed on several IGLOO, ProASIC3L, and ProASIC3 devices in typical operating conditions showed the brownout voltage levels to be within the specification. During device power-down, the device I/Os become tristated once the first supply in the powerdown sequence drops below its brownout deactivation voltage. Table 19-3 * Brownout Deactivation Levels for VCC and VCCI VCC Brownout VCCI Brownout Deactivation Level (V) Deactivation Level (V) Devices ProASIC3, ProASIC3 nano, IGLOO, IGLOO nano, IGLOO PLUS and ProASIC3L devices running at VCC = 1.5 V 0.75 V 0.25 V 0.8 V 0.3 V IGLOO, IGLOO nano, IGLOO PLUS, and ProASIC3L devices running at VCC = 1.2 V 0.75 V 0.2 V 0.8 V 0.15 V PLL Behavior at Brownout Condition When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels mentioned above for 1.5 V and 1.2 V devices, the PLL output lock signal goes LOW and/or the output clock is lost. The following sections explain PLL behavior during and after the brownout condition. VCCPLL and VCC Tied Together In this condition, both VCC and VCCPLL drop below the 0.75 V ( 0.25 V or 0.2 V) brownout level. During the brownout recovery, once VCCPLL and VCC reach the activation point (0.85 0.25 V or 0.2 V) again, the PLL output lock signal may still remain LOW with the PLL output clock signal toggling. If this condition occurs, there are two ways to recover the PLL output lock signal: 1. Cycle the power supplies of the PLL (power off and on) by using the PLL POWERDOWN signal. 2. Turn off the input reference clock to the PLL and then turn it back on. Only VCCPLL Is at Brownout In this case, only VCCPLL drops below the 0.75 V ( 0.25 V or 0.2 V) brownout level and the VCC supply remains at nominal recommended operating voltage (1.5 V 0.075 V for 1.5 V devices and 1.2 V 0.06 V for 1.2 V devices). In this condition, the PLL behavior after brownout recovery is similar to initial power-up condition, and the PLL will regain lock automatically after VCCPLL is ramped up above the activation level (0.85 0.25 V or 0.2 V). No intervention is necessary in this case. Only VCC Is at Brownout In this condition, VCC drops below the 0.75 V ( 0.25 V or 0.2 V) brownout level and VCCPLL remains at nominal recommended operating voltage (1.5 V 0.075 V for 1.5 V devices and 1.2 V 0.06 V for 1.2 V devices). During the brownout recovery, once VCC reaches the activation point again (0.85 0.25 V or 0.2 V), the PLL output lock signal may still remain LOW with the PLL output clock signal toggling. If this condition occurs, there are two ways to recover the PLL output lock signal: 1. Cycle the power supplies of the PLL (power off and on) by using the PLL POWERDOWN signal. 2. Turn off the input reference clock to the PLL and then turn it back on. v1.2 1 9 -9 Power-Up/-Down Behavior of Low-Power Flash Devices It is important to note that Actel recommends using a monotonic power supply or voltage regulator to ensure proper power-up behavior. Internal Pull-Up and Pull-Down Low-power flash device I/Os are equipped with internal weak pull-up/-down resistors that can be used by designers. If used, these internal pull-up/-down resistors will be activated during power-up, once both VCC and VCCI are above their functional activation level. Similarly, during power-down, these internal pull-up/-down resistors will turn off once the first supply voltage falls below its brownout deactivation level. Cold-Sparing In cold-sparing applications, voltage can be applied to device I/Os before and during power-up. Cold-sparing applications rely on three important characteristics of the device: 1. I/Os must be tristated before and during power-up. 2. Voltage applied to the I/Os must not power up any part of the device. 3. VCCI should not exceed 3.6 V, per datasheet specifications. As described in the "Power-Up to Functional Time" section on page 19-6, Actel's low-power flash I/Os are tristated before and during power-up until the last voltage supply (VCC or VCCI) is powered up past its functional level. Furthermore, applying voltage to the FPGA I/Os does not pull up VCC or VCCI and, therefore, does not partially power up the device. Table 19-4 includes the cold-sparing test results on A3PE600-PQ208 devices. In this test, leakage current on the device I/O and residual voltage on the power supply rails were measured while voltage was applied to the I/O before power-up. Table 19-4 * Cold-Sparing Test Results for A3PE600 Devices Residual Voltage (V) Device I/O VCC VCCI Leakage Current Input 0 0.003 <1 A Output 0 0.003 <1 A VCCI must not exceed 3.6 V, as stated in the datasheet specification. Therefore, ProASIC3E devices meet all three requirements stated earlier in this section and are suitable for cold-sparing applications. The following devices and families support cold-sparing: 1 9 -1 0 * IGLOO: AGL015 and AGL030 * All IGLOO nano * All IGLOO PLUS * All IGLOOe * ProASIC3L: A3PE3000L * ProASIC3: A3P015 and A3P030 * All ProASIC3 nano * All ProASIC3E * Military ProASIC3EL: A3PE600L and A3PE3000L * RT ProASIC3: RT3PE600L and RT3PE3000L v1.2 Power-Up/-Down Behavior of ProASIC3/E Devices The following devices and families do not support cold-sparing: * IGLOO: AGL060, AGL125, AGL250, AGL600, AGL1000 * ProASIC3: A3P060, A3P125, A3P250, A3P400, A3P600, A3P1000 * ProASIC3L: A3P250L, A3P600L, A3P1000L * Military ProASIC3: A3P1000 Hot-Swapping Hot-swapping is the operation of hot insertion or hot removal of a card in a powered-up system. The I/Os need to be configured in hot-insertion mode if hot-swapping compliance is required. For more details on the levels of hot-swap compatibility in low-power flash devices, refer to the "HotSwap Support" section in the I/O Structures chapter of the handbook for the device you are using. The following devices and families support hot-swapping: * IGLOO: AGL015 and AGL030 * All IGLOO nano * All IGLOO PLUS * All IGLOOe * ProASIC3L: A3PE3000L * ProASIC3: A3P015 and A3P030 * All ProASIC3 nano * All ProASIC3E * Military ProASIC3EL: A3PE600L and A3PE3000L * RT ProASIC3: RT3PE600L and RT3PE3000L The following devices and families do not support hot-swapping: * IGLOO: AGL060, AGL125, AGL250, AGL400, AGL600, AGL1000 * ProASIC3: A3P060, A3P125, A3P250, A3P400, A3P600, A3P1000 * ProASIC3L: A3P250L, A3P600L, A3P1000L * Military ProASIC3: A3P1000 Conclusion Actel's low-power flash FPGAs provide an excellent programmable logic solution for a broad range of applications. In addition to high performance, low cost, security, nonvolatility, and single chip, they are live at power-up (meet Level 0 of the LAPU classification) and offer clear and easy-to-use power-up/-down characteristics. Unlike SRAM FPGAs, low-power flash devices do not require any specific power-up/-down sequencing and have extremely low power-up inrush current in any power-up sequence. Actel low-power flash FPGAs also support both cold-sparing and hotswapping for applications requiring these capabilities. v1.2 1 9 - 11 Power-Up/-Down Behavior of Low-Power Flash Devices Related Documents Datasheets ProASIC3 DC and Switching Characteristics http://www.actel.com/documents/PA3GenSpecs_DS.pdf ProASIC3E DC and Switching Characteristics http://www.actel.com/documents/PA3EGenSpecs_DS.pdf Handbook Documents I/O Structures in IGLOO PLUS Devices http://www.actel.com/documents/IGLOOPLUS_IO_HBs.pdf I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf I/O Structures in IGLOOe and ProASIC3E Devices http://www.actel.com/documents/IGLOOe_PA3E_IO_HBs.pdf Part Number and Revision Date This document was a previously published handbook chapter that only discussed ProASIC3/E (Power-Up Behavior of ProASIC3/E Devices, part number 51700094-021), and has now been updated to include data for IGLOO and ProASIC3L families. Part Number 51700094-027-2 Revised December 2008 1 9 -1 2 v1.2 Power-Up/-Down Behavior of ProASIC3/E Devices List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.2) Page v1.1 (October 2008) IGLOO nano and ProASIC3 nano devices were added to the document as supported device types. N/A v1.0 (August 2008) The "Introduction" section was updated to add Military ProASIC3EL and RT ProASIC3 devices to the list of devices that can have inputs driven in while the device is not powered. 19-1 The "Actel's Flash Devices Support Power-Up Behavior" section was revised to include new families and make the information more concise. 19-2 The "Cold-Sparing" section was revised to add Military ProASIC3/EL and RT ProASIC3 devices to the lists of devices with and without cold-sparing support. 19-10 The "Hot-Swapping" section was revised to add Military ProASIC3/EL and RT ProASIC3 devices to the lists of devices with and without hot-swap support. AGL400 was added to the list of devices that do not support hot-swapping. 19-11 v1.3 (March 2008) This document was revised, renamed, and assigned a new part number. It now includes data for the IGLOO and ProASIC3L families. N/A v1.2 (January 2008) 51700094-021-2 The "Handbook Documents" section was updated to include the three different I/O Structure handbook chapters. 19-12 v1.1 (January 2008) The first sentence of the "PLL Behavior at Brownout Condition" section was updated to read, "When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost." 19-9 The "PLL Behavior at Brownout Condition" section was added. 19-9 51700094-021-1 v1.0 (January 2008) 51700094-021-0 v1.2 1 9 - 13 Actel, IGLOO, Actel Fusion, ProASIC, Libero, Pigeon Point and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation Actel Europe Ltd. Actel Japan Actel Hong Kong 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn 51700096-004-13/11.09