Order this document by MC74VHC1G53/D SEMICONDUCTOR TECHNICAL DATA The MC74VHC1G53 is an advanced high speed CMOS multiplexer - demultiplexer analog switch fabricated with silicon gate CMOS technology. It achieves high speed propagation delays and low ON resistances while maintaining CMOS low power dissipation. This multiplexer - demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The MC74VHC1G53 is compatible in function to a single gate of the High Speed CMOS MC74VHC4053 and the metal-gate CMOS MC14053. The device has been designed so that the ON resistances (RON) are much lower and more linear over input voltage than RON of the metal-gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pull-up resistors, it is compatible with LSTTL outputs. PLANNED PACKAGE 8-LEAD MICRO 8 PACKAGE Tamb = -55C to 125C * * * * High Speed: tPD = 4 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C Diode Protection Provided on Inputs and Outputs Improved Linearity and Lower ON Resistance over Input Voltage than the MC14053B or the HC4053 * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300 mA * ESD Performance: HBM > 2000 V; MM > 200 V, CDM > 1500 V OUT/IN X 1 FUNCTION TABLE Enable Select ON Channel L L H L L X X0 X1 NONE 8 VCC ENABLE 2 7 IN/OUT X0 N/C 3 6 IN/OUT X1 GND 4 5 CHANNEL SELECT VT ddd PIN ASSIGNMENT ENABLE 2X0 U CHANNEL SELECT 2X1 U U OUT/IN X MARKING DIAGRAM d = date code IN/OUT X0 IN/OUT X1 LOGIC SYMBOL DEVICE ORDERING INFORMATION Device Nomenclature D i O Device Order d Number N b MC74VHC1G53DMT1 Motorola Circuit Indicator Temp Range Identifier Technology Device Function Package Suffix Tape and Reel Suffix Package P k Type T Tape and dR Reell Size MC 74 VHC1G 53 DM R2 Micro 8 13-Inch/4000 Unit This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 10/98 Motorola, Inc. 1998 1 REV 0 MC74VHC1G53 ABSOLUTE MAXIMUM RATINGS Maximum ratings are those values beyond which damage to the device may occur. Exposureto these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. Symbol Value Unit DC Supply Voltage Characteristics VCC -0.5 to +7.0 V Digital Input Voltage VIN -0.5 to VCC +0.5 V Analog Input Voltage VIS -0.5 to VCC + 0.5 V Digital Input Diode Current IIK -20 mA DC Supply Current, VCC and GND ICC 25 mA Power dissipation in still air, Micro-8 PD 300 mW Lead temperature, 1 mm from case for 10 s TL 260 C -65 to +150 C Storage temperature Tstg Power Dissipation Derating: Micro-8 Package: - 4.4 mW/_C from 65_C to 125_C RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply Voltage Characteristics VCC 2.0 5.5 V Digital Input Voltage VIN GND VCC V Analog Input Voltage VIS GND VCC V Static or Dynamic Voltage Across Switch VIO* -- 100 mV Operating Temperature Range TA -55 +125 Input Rise and Fall Time, SELECT & ENABLE tr, tf C ns/V VCC = 3.3 V 0.3 V 0 100 VCC = 5.0 V 0.5 V 0 20 * For voltage drops across the switch greater than 100 mV (switch on), excessive VCC current may be drawn; i.e. the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. MOTOROLA 2 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHC1G53 DC ELECTRICAL CHARACTERISTICS VCC Symbol (V) Min Minimum High-Level Input Voltage ON/OFF Control Input RON = Per Spec 2.0 3.0 4.5 5.5 1.5 2.1 3.15 3.85 VIL Maximum Low-Level Input Voltage ON/OFF Control Input RON = Per Spec 2.0 3.0 4.5 5.5 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 V IIN Maximum Input Leakage Current ON/OFF Control Input VIN = VCC or GND 0 to 5.5 0.1 1.0 1.0 A ICC Maximum Quiescent Supply Current VIN = VCC or GND VIO = 0 V 5.5 2.0 20 40 A RON Maximum "ON" Resistance VIN = VIH VIS = VCC to GND IIS 20 mA (Figure 1) 2.0 3.0 4.5 25 12 5 50 20 10 70 30 15 100 45 25 Endpoints VIN = VIH VIS = VCC to GND IIS 20 mA (Figure 1) 2.0 3.0 4.5 25 12 5 50 20 10 65 26 13 90 40 22 Maximum Off-Channel Leakage Current, Any One Channel VIN = VIL VIO = VCC to GND Switch Off (Figure 2) 5.5 0.1 0.5 1.0 A Maximum Off-Channel Leakage Current, Common Channel VIN = VIL VIO = VCC to GND Switch Off (Figure 3) 5.5 0.1 1.0 2.0 A Maximum On-Channel Leakage Current VIN = VIH VIS = VCC to GND (Figure 4) 5.5 0.1 0.5 1.0 A ION Test Conditions Typ Max Min Max TA 125C VIH IOFF Parameter TA 85C TA = 25C 1.5 2.1 3.15 3.85 Min Max 1.5 2.1 3.15 3.85 Unit V W W IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII III IIIIIII IIIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII III III III III III III III III II IIIIIII IIIII IIIII IIII IIIIIII IIIIIII III III III III III III III III II IIII IIIIIII IIIIIII III III III III III III III IIIII IIII IIIIIII IIIIIII III III III III III III III III II II IIII IIIIIII IIIIIII III III III III III III III III IIII IIIIIII IIIIIII III III III III III III III III II IIII IIIIIII IIIIIII III III III III III III III III II II IIII IIIIIII IIIIIII III III III III III III III III W IIII IIIIIII IIIIIII III III III III III III III IIIII IIII IIIIIII IIIIIII III III III III III III III III II II IIII IIIIIII IIIIIII III III III III III III III III IIII IIIIIII IIIIIII III III III III III III III III II IIII IIIIIII IIIIIII III III III III III III III III II IIII IIIIIII IIIIIII III III III III III III III IIIII AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr/tf = 3.0 ns) S b l Symbol tPLH, tPHL tPLH, tPHL P Parameter Maximum Propagation Delay, Input X to X0 or X1 Maximum Propagation Delay, SELECT to Analog Output T Test C Conditions di i Figure 5 Figure 6 VCC (V) TA 85C TA = 25C Min TA 125C Max U i Unit 6 3 1 1 7 4 2 1 ns 35 15 10 7 46 20 13 9 57 25 17 11 ns 15 8 6 4 35 15 10 7 46 20 13 9 57 25 17 11 ns pF Typ Max 2.0 3.0 4.5 5.5 1 0 0 0 5 2 1 1 2.0 3.0 4.5 5.5 15 8 6 4 2.0 3.0 4.5 5.5 Min Max Min tPZL, tPZH tPLZ, tPHZ Maximum Propagation Delay, ENABLE to Analog Output RL = 1000 CIN Maximum Input Capacitance ON/OFF Control Input 0.0 3 10 10 10 Analog I/O (Control Input = GND) Feedthrough 5.0 4 10 10 10 4 10 10 10 Figure 7 Typical @ 25C, VCC = 5.0 V CPD P Power Dissipation Di i i Capacitance C i ((per S Switch) i h) (N (Note 1) Figure Fi 8 pF F 18 (1) CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. VHC Data - Advanced CMOS Logic DL203 -- Rev 1 3 MOTOROLA MC74VHC1G53 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III W IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III W IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III W IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III W IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III W IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III W IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III IIII IIIIIIIIII IIIIIIIIIIIIII III IIII III ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted) Symbol Parameter Test Conditions VCC Limit { 25C Unit BW Maximum On-Channel Bandwidth or Minimum Frequency Response Figure 9 fin = 1 MHz Sine Wave Adjust fin voltage to obtain 0 dBm at VOS Increase fin = frequency until dB meter reads -3 dB RL = 50 , CL = 10 pF 3.0 4.5 5.5 150 175 200 MHz ISOoff Off-Channel Feedthrough Isolation Figure 10 fin = Sine Wave Adjust fin voltage to obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF 3.0 4.5 5.5 -50 -50 -50 dB 3.0 4.5 5.5 -40 -40 -40 3.0 4.5 5.5 45 60 100 3.0 4.5 5.5 25 30 60 fin = 1.0 MHz, RL = 50 NOISEfeed Feedthrough Noise Channel Select to Switch Figure 11 Vin 1 MHz Square Wave (tr = tf = 2 ns) Adjust RL at setup so that Is = 0 A RL = 600 , CL = 50 pF RL = 50 THD Total Harmonic Distortion Figure 12 , CL = 10 pF , CL = 10 pF fin = 1 kHz, RL = 10 k , CL = 50 pF THD = THDMeasured - THDSource VIS = 3.0 VPP sine wave VIS = 4.0 VPP sine wave VIS = 5.0 VPP sine wave mVPP % 3.3 4.5 5.5 0.20 0.10 0.06 Guaranteed limits not tested. Determined by design and verified by qualification. MOTOROLA 4 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHC1G53 PLOTTER VCC DC PARAMETER ANALYZER POWER SUPPLY COMPUTER + VCC VIH - VCC 1 8 2 7 3 6 4 5 1 8 2 7 3 6 4 5 A VIH Figure 1. On Resistance Test Set-Up VCC VCC 1 VIH 2 1 VCC VCC A VCC Figure 2. Maximum Off-Channel Leakage Current Test Set-Up, Any One Channel 2 1 8 1 8 2 7 2 7 3 6 3 6 4 5 4 5 N/C Figure 3. Maximum Off-Channel Leakage Current Test Set-Up, Common Channel TEST POINT A VCC Figure 4. Maximum On-Channel Leakage Current Test Set-Up TEST POINT VCC VCC VCC CL 1 8 2 7 3 6 CL 1 8 2 7 3 6 4 5 VCC 4 5 Figure 5. Propagation Delay Test Set-Up, Analog I/O to Analog I/O VHC Data - Advanced CMOS Logic DL203 -- Rev 1 Figure 6. Propagation Delay Test Set-Up, Channel Select to Analog I/O 5 MOTOROLA MC74VHC1G53 Switch SW1 to Position 1 when testing tPLZ and tPZL Switch SW1 to Position 2 when testing tPHZ and tPZH Testing should be repeated with Switch SW2 in Position 2 to test both channels VCC RL TEST POINT VCC A VCC CL* 1 8 2 7 1 N/C 2 1 8 2 7 3 6 4 5 SW1 3 1 6 4 2 5 N/C VCC 1 2 SW2 *Includes all probe and jig capacitance. Figure 7. Propagation Delay Output Enable/ Disable to Analog Output Test Set-Up Figure 8. Power Dissipation Capacitance Test Set-Up fin VOS CL* dB Meter VCC 1 8 2 7 3 4 VOS fin 0.1 mF 1 8 2 7 6 3 6 5 4 5 dB Meter RL CL* VCC 8 RL 2 7 RL 3 6 4 5 V tr RL v 1 MHz + tf + 2 ns IN VCC GND *Includes all probe and jig capacitance. RL VCC CL* fin VCC 1 8 2 7 3 6 4 5 0.1 mF *Includes all probe and jig capacitance. Figure 11. Feedthrough Noise, Channel Select to Analog Out, Test Set-Up MOTOROLA 0.1 mF Figure 10. Off-Channel Feedthrough Isolation Test Set-Up TO DISTORTION VOS METER 1 VIS *Includes all probe and jig capacitance. Figure 9. Maximum On-Channel Bandwidth Test Set-Up VOS CL* VCC *Includes all probe and jig capacitance. TEST POINT VCC VIS VCC Figure 12. Total Harmonic Distortion Test Set-Up 6 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHC1G53 OUTLINE DIMENSIONS PLANNED PACKAGE 8-Lead Micro 8 Tamb = -55C to 125C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. -A- -B- K PIN 1 ID G D 8 PL 0.08 (0.003) -T- M T B S A S SEATING PLANE C 0.038 (0.0015) H VHC Data - Advanced CMOS Logic DL203 -- Rev 1 DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 --- 1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 --- 0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028 L J 7 MOTOROLA MC74VHC1G53 INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 0.041 1.04 0.208 5.28 0.126 3.20 0.015 0.38 0.0256 0.65 inches mm Micro8 POWER DISSIPATION the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 300 mW. The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows: PD = PD = 100C - 25C 250C/W = 300 mW The 250C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 300 mW using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. MOTOROLA 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. 8 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHC1G53 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. *TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX. R MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS "R" WITHOUT DAMAGE EMBOSSED CARRIER BENDING RADIUS 10 100 mm (3.937") MAXIMUM COMPONENT ROTATION EMBOSSMENT 1 mm MAX TYPICAL COMPONENT CAVITY CENTER LINE TAPE 1 mm (0.039") MAX TYPICAL COMPONENT CENTER LINE 250 mm (9.843") CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm Figure 13. Carrier Tape Specifications VHC Data - Advanced CMOS Logic DL203 -- Rev 1 9 MOTOROLA MC74VHC1G53 t MAX 13.0 mm 0.2 mm (0.512" 0.008") 1.5 mm MIN (0.06") A 20.2 mm MIN (0.795") 50 mm MIN (1.969") FULL RADIUS G Figure 14. Reel Dimensions REEL DIMIENSIONS Tape Size 12 mm A Max G t Max 330 mm (12.992") 12.4 mm, +2.0 mm, -0.0 (0.49", +0.079", -0.00) 18.4 mm (0.72") DIRECTION OF FEED BARCODE LABEL POCKET HOLE Figure 15. Reel Winding Direction MOTOROLA 10 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHC1G53 CAVITY TAPE TOP TAPE TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN COMPONENTS TAPE LEADER NO COMPONENTS 400 mm MIN DIRECTION OF FEED Figure 16. Tape Ends for Finished Goods VHC Data - Advanced CMOS Logic DL203 -- Rev 1 11 MOTOROLA MC74VHC1G53 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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