MC74VHC1G53DMT1 - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA Order this document

by MC74VHC1G53/D

1REV 0

 Motorola, Inc. 1998

10/98

   

  

The MC74VHC1G53 is an advanced high speed CMOS multiplexer –

demultiplexer analog switch fabricated with silicon gate CMOS

technology. It achieves high speed propagation delays and low ON

resistances while maintaining CMOS low power dissipation. This

multiplexer – demultiplexer controls analog and digital voltages that may

vary across the full power–supply range (from VCC to GND).

The MC74VHC1G53 is compatible in function to a single gate of the

High Speed CMOS MC74VHC4053 and the metal–gate CMOS

MC14053. The device has been designed so that the ON resistances

(RON) are much lower and more linear over input voltage than RON of

the metal–gate CMOS analog switches.

The ON/OFF control inputs are compatible with standard CMOS

outputs; with pull–up resistors, it is compatible with LSTTL outputs.

•High Speed: tPD = 4 ns (Typ) at VCC = 5 V

•Low Power Dissipation: ICC = 2

m

A (Max) at TA = 25°C

•Diode Protection Provided on Inputs and Outputs

•Improved Linearity and Lower ON Resistance over Input Voltage

than the MC14053B or the HC4053

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance: HBM > 2000 V; MM > 200 V, CDM > 1500 V

VCC

OUT/IN X

CHANNEL SELECT

GND

PIN ASSIGNMENT

8

1

2

54

3

7

6

IN/OUT X0

IN/OUT X1

N/C

ENABLE

U U

OUT/IN X

LOGIC SYMBOL

CHANNEL SELECT 2 X 0

2 X 1 IN/OUT X0

U

IN/OUT X1

ENABLE

DEVICE ORDERING INFORMATION

Di OdN b

Device Nomenclature

Pk

TdRl

Device Order Number

Motorola

Circuit

Indicator

Temp

Range

Identifier Technology Device

Function Package

Suffix Tape and

Reel Suffix Package

Type Tape and Reel

Size

MC74VHC1G53DMT1 MC 74 VHC1G 53 DM R2 Micro 8 13–Inch/4000 Unit

This document contains information on a product under development. Motorola reserves the right to change or

discontinue this product without notice.



PLANNED PACKAGE

8–LEAD MICRO 8 PACKAGE

Tamb = –55°C to 125°C

L

H

FUNCTION TABLE

Enable

L

X

Select

X0

X1

NONE

ON Channel

MARKING DIAGRAM

d = date code

VT

ddd

MC74VHC1G53

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

2

ABSOLUTE MAXIMUM RATINGS

Maximum ratings are those values beyond which damage to the device may occur. Exposureto these conditions or condi-

tions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated

conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions.

Characteristics Symbol Value Unit

DC Supply Voltage VCC –0.5 to +7.0 V

Digital Input Voltage VIN –0.5 to VCC +0.5 V

Analog Input Voltage VIS –0.5 to VCC + 0.5 V

Digital Input Diode Current IIK –20 mA

DC Supply Current, VCC and GND ICC ±25 mA

Power dissipation in still air, Micro–8 †PD300 mW

Lead temperature, 1 mm from case for 10 s TL260 °C

Storage temperature Tstg –65 to +150 °C

†Power Dissipation Derating: Micro–8 Package: – 4.4 mW/

_

C from 65

_

C to 125

_

C

RECOMMENDED OPERATING CONDITIONS

Characteristics Symbol Min Max Unit

DC Supply Voltage VCC 2.0 5.5 V

Digital Input Voltage VIN GND VCC V

Analog Input Voltage VIS GND VCC V

Static or Dynamic Voltage Across Switch VIO* — 100 mV

Operating Temperature Range TA–55 +125 °C

Input Rise and Fall T ime,

SELECT & ENABLE VCC = 3.3 V ± 0.3 V

VCC = 5.0 V ± 0.5 V

tr, tf0

0100

20

ns/V

* For voltage drops across the switch greater than 100 mV (switch on), excessive VCC current may be drawn; i.e. the current out of the switch may

contain both VCC and switch input components. The reliability of the device will be unaf fected unless the Maximum Ratings are exceeded.

MC74VHC1G53

VHC Data – Advanced CMOS Logic

DL203 — Rev 1 3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS

VCC TA = 25°C TA ≤ 85°C TA ≤ 125°C

Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit

VIH Minimum High–Level

Input Voltage

ON/OFF Control Input

RON = Per Spec 2.0

3.0

4.5

5.5

1.5

2.1

3.15

3.85

1.5

2.1

3.15

3.85

1.5

2.1

3.15

3.85

V

VIL Maximum Low–Level

Input Voltage

ON/OFF Control Input

RON = Per Spec 2.0

3.0

4.5

5.5

0.5

0.9

1.35

1.65

0.5

0.9

1.35

1.65

0.5

0.9

1.35

1.65

V

IIN Maximum Input

Leakage Current

ON/OFF Control Input

VIN = VCC or GND 0 to

5.5 ±0.1 ±1.0 ±1.0 µA

ICC Maximum Quiescent

Supply Current VIN = VCC or GND

VIO = 0 V 5.5 2.0 20 40 µA

RON Maximum “ON”

Resistance VIN = VIH

VIS = VCC to GND

IIS ≤ 20 mA (Figure 1)

2.0

3.0

4.5

25

12

5

50

20

10

70

30

15

100

45

25

W

Endpoints

VIN = VIH

VIS = VCC to GND

IIS ≤ 20 mA (Figure 1)

2.0

3.0

4.5

25

12

5

50

20

10

65

26

13

90

40

22

W

IOFF Maximum Off–Channel

Leakage Current,

Any One Channel

VIN = VIL

VIO = VCC to GND

Switch Off (Figure 2)

5.5 0.1 0.5 1.0 µA

Maximum Off–Channel

Leakage Current,

Common Channel

VIN = VIL

VIO = VCC to GND

Switch Off (Figure 3)

5.5 0.1 1.0 2.0 µA

ION Maximum On–Channel

Leakage Current VIN = VIH

VIS = VCC to GND

(Figure 4)

5.5 0.1 0.5 1.0 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr/tf = 3.0 ns)

ÎÎÎÎ

Sbl

ÎÎÎÎÎÎÎ

P

ÎÎÎÎÎÎÎ

T C di i

ÎÎÎ

V

CC

ÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎ

TA ≤ 85°C

ÎÎÎÎÎ

TA ≤ 125°C

ÎÎ

Ui

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

(V)

ÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎ

Unit

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Maximum Propagation

Delay ,

Input X to X0 or X1

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Figure 5

ÎÎÎ

Î

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

1

0

ÎÎÎ

Î

ÎÎÎ

5

2

1

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

6

3

1

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

7

4

2

1

ÎÎ

ns

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Maximum Propagation

Delay ,

SELECT to Analog

Output

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Figure 6

ÎÎÎ

Î

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

15

8

6

4

ÎÎÎ

Î

ÎÎÎ

35

15

10

7

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

46

20

13

9

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

57

25

17

11

ÎÎ

ns

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

tPZL,

tPZH

tPLZ,

tPHZ

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Maximum Propagation

Delay ,

ENABLE to Analog

Output

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

RL = 1000

W

Figure 7

ÎÎÎ

Î

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

15

8

6

4

ÎÎÎ

Î

ÎÎÎ

35

15

10

7

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

46

20

13

9

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

57

25

17

11

ÎÎ

ns

ÎÎÎÎ

CIN

ÎÎÎÎÎÎÎ

Maximum Input

Capacitance

ÎÎÎÎÎÎÎ

ON/OFF Control Input

ÎÎÎ

0.0

ÎÎÎ

3

ÎÎÎ

10

ÎÎÎ

10

ÎÎÎ

10

ÎÎ

pF

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

Capacitance

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

ÎÎÎÎÎ

Î

Analog I/O

(Control Input = GND)

Feedthrough

ÎÎÎ

Î

5.0

ÎÎÎ

Î

ÎÎÎ

Î

4

ÎÎÎ

Î

10

ÎÎÎ

Î

ÎÎÎ

Î

10

ÎÎÎ

Î

ÎÎÎ

Î

10

ÎÎ

C

P Di i i C i ( S i h) (N 1) Fi 8

Typical @ 25°C, VCC = 5.0 V

F

CPD Power Dissipation Capacitance (per Switch) (Note 1) Figure 8 18 pF

(1) CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD



VCC



fin + ICC. CPD is used to determine the no–load dynamic

power consumption; PD = CPD



VCC2



fin + ICC



VCC.

MC74VHC1G53

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ADDITIONAL APPLICATION CHARACTERISTICS (V oltages Referenced to GND Unless Noted)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

Î

ÎÎÎ

VCC

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Limit

{

25°C

ÎÎÎ

Î

ÎÎÎ

Unit

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

BW

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Maximum On–Channel Bandwidth

or Minimum Frequency Response

Figure 9

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 MHz Sine Wave

Adjust fin voltage to obtain 0 dBm at VOS

Increase fin = frequency until dB meter reads –3 dB

RL = 50

W

, CL = 10 pF

ÎÎÎ

Î

ÎÎÎ

3.0

4.5

5.5

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

150

175

200

ÎÎÎ

Î

ÎÎÎ

MHz

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

ISOoff

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Off–Channel Feedthrough Isolation

Figure 10

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = Sine Wave

Adjust fin voltage to obtain 0 dBm at VIS

fin = 10 kHz, RL = 600

W

, CL = 50 pF

ÎÎÎ

Î

ÎÎÎ

3.0

4.5

5.5

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

–50

ÎÎÎ

Î

ÎÎÎ

dB

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1.0 MHz, RL = 50

W

, CL = 10 pF

ÎÎÎ

Î

ÎÎÎ

3.0

4.5

5.5

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

–40

ÎÎÎ

Î

ÎÎÎ

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

NOISEfeed

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Feedthrough Noise Channel Select

to Switch

Figure 11

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin ≤ 1 MHz Square Wave (tr = tf = 2 ns)

Adjust RL at setup so that Is = 0 A

RL = 600

W

, CL = 50 pF

ÎÎÎ

Î

ÎÎÎ

3.0

4.5

5.5

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

45

60

100

ÎÎÎ

Î

ÎÎÎ

mVPP

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

RL = 50

W

, CL = 10 pF

ÎÎÎ

Î

ÎÎÎ

3.0

4.5

5.5

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

25

30

60

ÎÎÎ

Î

ÎÎÎ

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

THD

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Total Harmonic Distortion

Figure 12

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 kHz, RL = 10 k

W

, CL = 50 pF

THD = THDMeasured – THDSource

VIS = 3.0 VPP sine wave

VIS = 4.0 VPP sine wave

VIS = 5.0 VPP sine wave

ÎÎÎ

Î

ÎÎÎ

3.3

4.5

5.5

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

0.20

0.10

0.06

ÎÎÎ

Î

ÎÎÎ

%

†Guaranteed limits not tested. Determined by design and verified by qualification.

MC74VHC1G53

VHC Data – Advanced CMOS Logic

DL203 — Rev 1 5 MOTOROLA

Figure 1. On Resistance Test Set–Up Figure 2. Maximum Off–Channel Leakage Current

Test Set–Up, Any One Channel

8

1

2

54

Figure 3. Maximum Off–Channel Leakage Current

Test Set–Up, Common Channel Figure 4. Maximum On–Channel Leakage

Current Test Set–Up

Figure 5. Propagation Delay Test Set–Up,

Analog I/O to Analog I/O Figure 6. Propagation Delay Test Set–Up,

Channel Select to Analog I/O

POWER

SUPPLY

COMPUTER

DC PARAMETER

ANALYZER

VCC +–

PLOTTER

VCC

VIH

A

3

7

6

8

1

2

54

3

7

6

VIH

VCC

8

1

2

54

3

7

6

VIH

VCC

A

VCC

A

8

1

2

54

3

7

6

VCC

N/C

VCC

8

1

2

54

3

7

6

VCC VCC

VCC

CL

8

1

2

54

3

7

6

VCC

CL

2

1

2

1

TEST

POINT TEST

POINT

MC74VHC1G53

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

6

Figure 7. Propagation Delay Output Enable/

Disable to Analog Output Test Set–Up Figure 8. Power Dissipation Capacitance

Test Set–Up

Figure 9. Maximum On–Channel Bandwidth

Test Set–Up Figure 10. Off–Channel Feedthrough Isolation

Test Set–Up

dB

Meter

Figure 11. Feedthrough Noise, Channel Select

to Analog Out, Test Set–Up Figure 12. Total Harmonic Distortion Test Set–Up

GND

VCC

VIN

v

1MHz

t

r

+

t

f

+

2ns

8

1

2

54

3

7

6

V

CC VCC

VCC

CL*

SW2

2

1

2

1

2

SW1

TEST

POINT

RL

8

1

2

54

3

7

6

VCC

CL*

VOS

*Includes all probe and jig capacitance.

0.1

m

Ffin

8

1

2

54

3

7

6

VCC

A

N/C

dB

Meter

8

1

2

54

3

7

6

VCC

CL*

VOS

*Includes all probe and jig capacitance.

0.1

m

F

fin VIS

RL

8

1

2

54

3

7

6

VCC

CL*

VOS

*Includes all probe and jig capacitance.

0.1

m

F

fin

VIS

RL

TO

DISTORTION

METER

8

1

2

54

3

7

6

VCC

CL*

VOS

*Includes all probe and jig capacitance.

RL

TEST

POINT

RL

Switch SW1 to Position 1 when testing tPLZ and tPZL

Switch SW1 to Position 2 when testing tPHZ and tPZH

Testing should be repeated with Switch SW2 in Position 2 to test both channels

MC74VHC1G53

VHC Data – Advanced CMOS Logic

DL203 — Rev 1 7 MOTOROLA

OUTLINE DIMENSIONS

PLANNED PACKAGE

8–Lead Micro 8

Tamb = –55°C to 125°C

S

B

M

0.08 (0.003) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C––– 1.10 ––– 0.043

D0.25 0.40 0.010 0.016

G0.65 BSC 0.026 BSC

H0.05 0.15 0.002 0.006

J0.13 0.23 0.005 0.009

K4.75 5.05 0.187 0.199

L0.40 0.70 0.016 0.028

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

–B–

–A–

D

K

G

PIN 1 ID

8 PL

0.038 (0.0015)

–T–

SEATING

PLANE

C

HJL

MC74VHC1G53

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

8

INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the semiconductor packages must be

the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad

geometry, the packages will self–align when subjected to a

solder reflow process.

mm

inches

0.041

1.04

0.208

5.28

0.015

0.38 0.0256

0.65

0.126

3.20

Micro8 POWER DISSIPATION

The power dissipation of the Micro8 is a function of the input

pad size. This can vary from the minimum pad size for

soldering to the pad size given for maximum power

dissipation. Power dissipation for a surface mount device is

determined by TJ(max), the maximum rated junction

temperature of the die, RθJA, the thermal resistance from the

device junction to ambient; and the operating temperature, TA.

Using the values provided on the data sheet for the Micro8

package, PD can be calculated as follows:

PD = TJ(max) – TA

RθJA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values into

the equation for an ambient temperature T A of 25°C, one can

calculate the power dissipation of the device which in this case

is 300 mW.

PD = 100°C – 25°C

250°C/W = 300 mW

The 250°C/W for the Micro8 package assumes the

recommended footprint on a glass epoxy printed circuit board

to achieve a power dissipation of 300 mW using the footprint

shown. Another alternative would be to use a ceramic

substrate or an aluminum core board such as Thermal Clad.

Using board material such as Thermal Clad, the power

dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within a

short time could result in device failure. Therefore, the

following items should always be observed in order to

minimize the thermal stress to which the devices are

subjected.

•Always preheat the device.

•The delta temperature between the preheat and soldering

should be 100°C or less.*

•When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering method,

the difference shall be a maximum of 10°C.

•The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

•When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

•After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and result

in latent failure due to mechanical stress.

•Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive

thermal shock and stress which can result in damage to the

device.

MC74VHC1G53

VHC Data – Advanced CMOS Logic

DL203 — Rev 1 9 MOTOROLA

Figure 13. Carrier Tape Specifications

R MIN.

TAPE AND COMPONENTS

SHALL PASS AROUND RADIUS “R”

WITHOUT DAMAGE

BENDING RADIUS

*TOP COVER

TAPE THICKNESS (t1)

0.10 mm

(0.004”) MAX.

EMBOSSED

CARRIER EMBOSSMENT

TYPICAL

COMPONENT CAVITY

CENTER LINE

TYPICAL

COMPONENT

CENTER LINE

MAXIMUM COMPONENT ROTA TION

10

°

CAMBER (TOP VIEW)

ALLOW ABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm

100 mm

(3.937”)

1 mm

(0.039”) MAX 250 mm

(9.843”)

1 mm MAX

TAPE

FEED DIRECTION SECTION A–A

NOTES:

1. CONFORMS TO EIA–481–1.

2. CONTROLLING DIMENSION: MILLIMETER.

NUMBER 1

12.30

4.10 (.161)

11.70

(.484)

(.461)

1.85 (.072)

3.90 (.154)

2.05 (.080)

1.95 (.077)

BBA

A

8.10 (.318)

7.90 (.312)

5.55 (.218)

5.45 (.215)

1.65 (.065)

1.60 (.063)

1.50 (.059)

1.60 (.063)

1.50 (.059)

TYP.

0.35 (.013)

0.25 (.010)

3.50 (.137)

3.30 (.130)

1.50 (.059)

1.30 (.052)

SECTION B–B

5.40 (.212)

5.20 (.205)

MC74VHC1G53

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

10

Figure 14. Reel Dimensions

13.0 mm

±

0.2 mm

(0.512”

±

0.008”)

1.5 mm MIN

(0.06”)

50 mm MIN

(1.969”)

20.2 mm MIN

(0.795”)

FULL RADIUS

t MAX

G

A

REEL DIMIENSIONS

Tape

Size A Max G t Max

12 mm 330 mm

(12.992”) 12.4 mm, +2.0 mm, –0.0

(0.49”, +0.079”, –0.00) 18.4 mm

(0.72”)

Figure 15. Reel Winding Direction

DIRECTION OF FEED

BARCODE LABEL

HOLEPOCKET

MC74VHC1G53

VHC Data – Advanced CMOS Logic

DL203 — Rev 1 11 MOTOROLA

TAPE TRAILER

(Connected to Reel Hub)

NO COMPONENTS

160 mm MIN

TAPE LEADER

NO COMPONENTS

400 mm MIN

COMPONENTS

DIRECTION OF FEED

CAVITY

TAPE TOP TAPE

Figure 16. Tape Ends for Finished Goods

MC74VHC1G53

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

12

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specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

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MC74VHC1G53/D

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