MC33FS6500CAER2 - NXP SEMICONDUCTORS

FS6500, FS4500

Safety power system basis chip with CAN FD and LIN

transceivers

Rev. 7.0 — 11 November 2020 Product short data sheet

1 General description

The FS6500/FS4500 SMARTMOS devices are a multi-output, power supply, integrated

circuit, including CAN Flexible Data (FD) and/or LIN transceivers, dedicated to the

automotive market.

Multiple switching and linear voltage regulators, including low-power mode (32 μA) are

available with various wake-up capabilities. An advanced power management scheme is

implemented to maintain high efficiency over a wide range of input voltages (down to 2.7

V) and output current ranges (up to 2.2 A).

The FS6500/FS4500 includes configurable fail-safe/fail silent safety behavior and

features, with two fail-safe outputs, becoming a full part of a safety oriented system

partitioning, to reach a high integrity safety level (up to ASIL D).

The built-in CAN FD interface fulfills the ISO 11898-2(13) and -5(14) standards. The LIN

interface fulfills LIN protocol specifications 2.0, 2.1(23), 2.2(24), and SAE J2602-2(25).

High temperature capability up to TA = 125 °C and TJ = 150 °C, compliant with AEC-

Q100 Grade 1 automotive qualification.

2 Features and benefits

•Battery voltage sensing and MUX output pin

•Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost

and standard buck

•Family of devices to supply MCU core from 1.0 V to 5.0 V, with SMPS (0.8 A, 1.5 A or

2.2 A) or LDO (0.5 A)

•Linear voltage regulator dedicated to auxiliary functions, or to sensor supply (VCCA

tracker or independent), 5.0 V, or 3.3 V

•Linear voltage regulator dedicated to MCU Analog/Digital (A/D) reference voltage or

I/Os supply (VCCA), 5.0 V, or 3.3 V

•3.3 V keep alive memory supply available in low-power mode

•Long duration timer, counting up to 6 months with 1.0 s resolution

•Multiple wake-up sources in low-power mode: CAN, LIN, IOs, LDT

•Five configurable I/Os

3 Applications

•Drive Train Electrification (BMS, Hybrid EV and HEV, Inverter, DC-DC, Alterno Starter)

•Drive Train - Chassis and Safety (Active Suspension, Steering, Safety Domain

Gateway)

•Power Train (EMS, TCU, Gear Box)

•ADAS (LDW, Radar, Sensor Fusion Safety area)

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

2 / 25

4 Simplified application diagrams

aaa-037730

FB_CORE

COMP_CORE

FCRBM

VCCA_E

VCCA_B

VDDIO

VCCA

MUX_OUT

IO_5/VKAM

MOSI

MISO

SCLK

NCS

INTB

RSTB

TXD

RXD

IO_3

IO_2

VSUP3

VSENSE

VAUX_E

VAUX_B

VAUX

SELECT

CAN-5V

DEBUG

IO_0

IO_4

CANH

CANL

VPU-FS

+battery

(KL30)

DEBUG

mode

ignition key

(KL15)

to switch

CAN BUS

fail-safe

delay

fail-safe

drive

VAUX

VPRE

VDDIO

VPRE VCORE VDD

AD ref.

voltage

ADC Input

Vstandby

SPI

NMI

Reset

CAN

MCU

VCCA

VDDIO

VCORE

VCCA

FS1B

FS0B

GNDA DGNDGND_COM

FS6500C

FCCU

Figure 1. FS6500C simplified application diagram - buck boost configuration - FS1B

aaa-037731

FB_CORE

COMP_CORE

FCRBM

VCCA_E

VCCA_B

VDDIO

VCCA

MUX_OUT

IO_5/VKAM

MOSI

MISO

SCLK

NCS

INTB

RSTB

TXD

RXD

IO_3

IO_2

VSUP3

VSENSE

VAUX_E

VAUX_B

VAUX

SELECT

CAN-5V

DEBUG

IO_0

IO_4

CANH

CANL

+battery

(KL30)

DEBUG

mode

ignition key

(KL15)

to switch

CAN BUS

fail-safe

drive

VAUX

VPRE

VDDIO

VSUP3

LIN BUS

VPRE VCORE VDD

AD ref.

voltage

ADC Input

Vstandby

SPI

NMI

Reset

CAN

MCU

VCCA

VPRE

VDDIO

VCORE

VCCA

FS0B

GNDA DGNDGND_COM

LIN

FS6500L

TXDL

RXDL LIN

FCCU

Figure 2. FS6500L simplified application diagram - buck configuration - LIN - VCCA = 100

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

3 / 25

aaa- 037732

FB_CORE

COMP_CORE

FCRBM

VCCA _E

VCCA _B

VDDIO

VCCA

MUX_OUT

IO_5/VKAM

MOSI

MISO

SCLK

NCS

INTB

RSTB

TXD

RXD

IO_3

IO_2

VSUP3

VSENSE

VAUX_E

VAUX_B

VAUX

SELECT

CAN-5V

DEBUG

IO_0

IO_4

CANH

CANL

VPU-FS

+battery

(KL30)

DEBUG

mode

ignition key

(KL15)

to switch

CAN BUS

fail-safe

delay

fail-safe

drive

VAUX

VPRE

VDDIO

VPRE VCORE VDD

AD ref.

voltage

ADC Input

Vstandby

SPI

NMI

Reset

CAN

MCU

VCCA

VDDIO

VCORE

VCCA

FS1B

FS0B

GNDA DGNDGND_COM

FS4500C

VDDIO

FCCU

Figure 3. FS4500C simplified application diagram - buck boost configuration - FS1B

5 Ordering information

5.1 Part number definition

MC33FS c 5 x y z AE/R2

Table 1. Part number breakdown

Code Option Variable Description

4 series Linearc

6 series

VCORE type

DC-DC

0 0.5 A or 0.8 A

1 1.5 A

VCORE current

2.2 A

0 None

1 FS1B

2 LDT

3 FS1B, LDT

Functions

LDT, VKAM ON by default

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

4 / 25

Code Option Variable Description

N None

C CAN FD

Physical interface

CAN FD and LIN

5.2 Part numbers list

Table 2. Orderable part variations

Part Number Temperature

(TA)

Package FS1B LDT VCORE VCORE

type

VKAM

CAN

LIN Notes

MC33FS4500CAE 0 0 0.5 A Linear by SPI 1 0

MC33FS4500LAE 0 0 0.5 A Linear by SPI 1 1

MC33FS4500NAE 0 0 0.5 A Linear by SPI 0 0

MC33FS4501CAE 1 0 0.5 A Linear by SPI 1 0

MC33FS4501NAE 1 0 0.5 A Linear by SPI 0 0

MC33FS4502CAE 0 1 0.5 A Linear by SPI 1 0

MC33FS4502LAE 0 1 0.5 A Linear by SPI 1 1

MC33FS4502NAE 0 1 0.5 A Linear by SPI 0 0

MC33FS4503CAE 1 1 0.5 A Linear by SPI 1 0

MC33FS4503NAE 1 1 0.5 A Linear by SPI 0 0

MC33FS6500CAE 0 0 0.8 A DC-DC by SPI 1 0

MC33FS6500LAE 0 0 0.8 A DC-DC by SPI 1 1

MC33FS6500NAE 0 0 0.8 A DC-DC by SPI 0 0

MC33FS6501CAE 1 0 0.8 A DC-DC by SPI 1 0

MC33FS6501NAE 1 0 0.8 A DC-DC by SPI 0 0

MC33FS6502CAE 0 1 0.8 A DC-DC by SPI 1 0

MC33FS6502LAE 0 1 0.8 A DC-DC by SPI 1 1

MC33FS6502NAE 0 1 0.8 A DC-DC by SPI 0 0

MC33FS6503CAE 1 1 0.8 A DC-DC by SPI 1 0

MC33FS6503NAE 1 1 0.8 A DC-DC by SPI 0 0

MC33FS6504LAE 0 1 0.8 A DC-DC by default 1 1

MC33FS6510CAE 0 0 1.5 A DC-DC by SPI 1 0

MC33FS6510LAE 0 0 1.5 A DC-DC by SPI 1 1

MC33FS6510NAE 0 0 1.5 A DC-DC by SPI 0 0

MC33FS6511CAE 1 0 1.5 A DC-DC by SPI 1 0

MC33FS6511NAE 1 0 1.5 A DC-DC by SPI 0 0

MC33FS6512CAE 0 1 1.5 A DC-DC by SPI 1 0

MC33FS6512LAE 0 1 1.5 A DC-DC by SPI 1 1

MC33FS6512NAE 0 1 1.5 A DC-DC by SPI 0 0

MC33FS6513CAE 1 1 1.5 A DC-DC by SPI 1 0

MC33FS6513NAE 1 1 1.5 A DC-DC by SPI 0 0

MC33FS6514LAE 0 1 1.5 A DC-DC by default 1 1

MC33FS6520CAE

–40 °C

125 °C

48-pin LQFP

exposed pad

0 0 2.2 A DC-DC by SPI 1 0

[1] [2]

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

5 / 25

Part Number Temperature

(TA)

Package FS1B LDT VCORE VCORE

type

VKAM

CAN

LIN Notes

MC33FS6520LAE 0 0 2.2 A DC-DC by SPI 1 1

MC33FS6520NAE 0 0 2.2 A DC-DC by SPI 0 0

MC33FS6521CAE 1 0 2.2 A DC-DC by SPI 1 0

MC33FS6521NAE 1 0 2.2 A DC-DC by SPI 0 0

MC33FS6522CAE 0 1 2.2 A DC-DC by SPI 1 0

MC33FS6522LAE 0 1 2.2 A DC-DC by SPI 1 1

MC33FS6522NAE 0 1 2.2 A DC-DC by SPI 0 0

MC33FS6523CAE 1 1 2.2 A DC-DC by SPI 1 0

MC33FS6523NAE 1 1 2.2 A DC-DC by SPI 0 0

[1] To order parts in tape and reel, add the R2 suffix to the part number.

[2] LIN and FS1B functions are exclusive. The differentiation is made by part numbers. When LIN is available, FS1B is not, and vice versa. VKAM on by

default is available on certain part numbers only.

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

6 / 25

6 Block diagram

aaa-037733

VSUP3

VpreVpre

Vpre

select

select debug

debug

MIFO FS

Vsup3

(1)

Vsup3

Vsup3Vpre

Vpre

Vsup3

Vsup_mon

Vsense_mon

CAN/LIN diag

Vpre Vsense

Vref

(2.5 V)

VCCA_E

VCCA_B

VCCA

GNDA

MUX_OUT

DEBUG

INTB

NCS

SCLK

MOSI

MISO

VDDIO

VSENSE

RXD

TXD

RSTB

FS0B

FS1B

VPU_FS

VAUX_E

VAUX_B

VAUX

CAN-5V

SELECT

IO_0

IO_2

IO_3

IO_4

IO_5/VKAM

VKAM

FCRBM

CANH

CANL

LIN

Vpre SMPS

TSD

Vaux LINEAR REGULATOR

TSD

TDS

Vcore SMPS

Vcca LINEAR REGULATOR

ANALOG

REFERENCE #1

POWER

MANAGEMENT

STATE

MACHINE

LONG

DURATION

TIMER

TSD

CHARGE

PUMP

V2p5d

MAIN

V2p5d

OSC

MAIN

VKAM

SPI

MAIN

MUX

INTERFACE

Vcan

LINEAR REGULATOR

CAN-5 V

FB_core

Vaux Vcca

Die

Temp

I/Os

INTERFACE

(1)

SPI

OSC

ANALOG REFERENCE #2

CAN FLEXIBLE DATA INTERFACE(1)

fail safe logic and supply part number dependent(1)

VOLTAGE

REGULATOR

SUPERVISOR

(OVER AND

UNDERVOLTAGE) FAIL SAFE

MACHINE

FS1B DELAY

AND DRIVER

RXDL

TXDL

LIN INTERFACE(1)

GND_COM

Figure 4. FS6500/FS4500 with CAN and LIN simplified internal block diagram

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

7 / 25

7 Pinning information

7.1 Pinning information

VSUP1 BOOT_CORE

VSUP2 SW_CORE

VSENSE VCORE_SNS

VSUP3 COMP_CORE

FS1B FB_CORE

GND_COM SELECT

CAN_5V VDDIO

CANH INTB

CANL NCS

IO_4 SCLK

IO_5/VKAM MOSI

IO_0 MISO

FCRBM

FS0B

BUG

AGND

MUX_OUT

IO_2

IO_3

TXD

RXD

U_FS VA

n.c.

RSTB

aaa-037734

724

Figure 5. FS6500 pinout with CAN and FS1B

VSUP1 BOOT_CORE

VSUP2 SW_CORE

VSENSE VCORE_SNS

VSUP3 COMP_CORE

LIN FB_CORE

GND_COM SELECT

CAN_5V VDDIO

CANH INTB

CANL NCS

IO_4 SCLK

IO_5/VKAM MOSI

IO_0 MISO

FCRBM

FS0B

BUG

AGND

MUX_OUT

IO_2

IO_3

TXD

RXD

TXDL VA

RXDL

RSTB

aaa-037735

724

Figure 6. FS6500 pinout with CAN and LIN

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

8 / 25

VSUP1 BOOT_CORE

VSUP2 SW_CORE

VSENSE VCORE_SNS

VSUP3 COMP_CORE

n.c. FB_CORE

GND_COM SELECT

CAN_5V VDDIO

n.c INTB

n.c NCS

IO_4 SCLK

IO_5/VKAM MOSI

IO_0 MISO

FCRBM

FS0B

BUG

AGND

MUX_OUT

IO_2

IO_3

n.c

n.c. VA

n.c.

RSTB

aaa-037736

724

Figure 7. FS6500 pinout without CAN, without LIN

VSUP1 n.c.

VSUP2 VCORE

VSENSE VCORE_SNS

VSUP3 n.c.

FS1B FB_CORE

GND_COM SELECT

CAN_5V VDDIO

CANH INTB

CANL NCS

IO_4 SCLK

IO_5/VKAM MOSI

IO_0 MISO

FCRBM

FS0B

DEBUG

AGND

MUX_OUT

IO_2

IO_3

TXD

RXD

VPU_FS VA

n.c

RSTB

aaa-037737

724

Figure 8. FS4500 pinout with CAN and FS1B

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

9 / 25

7.2 Pin description

A functional description of each pin can be found in the full data sheet.

Table 3. FS6500/FS4500 pin definition

number

Pin name Type Definition

1 VSUP1 A_IN Power supply of the device. An external reverse battery protection diode in series is

mandatory

2 VSUP2 A_IN Second power supply. Protected by the external reverse battery protection diode

used for VSUP1. VSUP1 and VSUP2 must be connected together externally.

3 VSENSE A_IN Sensing of the battery voltage. Must be connected prior to the reverse battery

protection diode.

4 VSUP3 A_IN Third power supply dedicated to the device supply. Protected by the external

reverse battery protection diode used for VSUP1. Must be connected between the

reverse protection diode and the input PI filter.

LIN A_IN/OUT LIN single-wire bus transmitter and receiver.

or FS1B D_OUT Second output of the safety block (active low). The pin is asserted low at start-up

and when a fault condition is detected, with a configurable delay or duration versus

FS0B output terminal. Open drain structure.

LIN and FS1B functions are exclusive. The differentiation is made by part numbers. When LIN is available, FS1B

is not, and vice versa. If neither LIN, nor FS1B functions are used, this pin must be left open.

6 GND_COM GROUND Dedicated ground for physical layers

7 CAN_5V A_OUT Output voltage for the embedded CAN FD interface

8 CANH A_IN/OUT CAN output high. If CAN function is not used, this pin must be left open.

9 CANL A_IN/OUT CAN output low. If CAN function is not used, this pin must be left open.

10 IO_4 D_IN

A_OUT

Can be used as digital input (load dump proof) with wake-up capability or as an

output gate driver

Digital input: Pin status can be read through the SPI. Can be used to monitor error

signals from another IC for safety purposes (when used with IO_5).

Wake-up capability: Can be selectable to wake-up on edges or levels.

Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by

the SPI.

IO_5/VKAM A_IN

D_IN

A_OUT

Can be used as digital input with wake-up capability or as an analog output

providing keep alive memory supply in low-power mode.

Analog input: Pin status can be read through the MUX output terminal

Digital input: Pin status can be read through the SPI. Can be used to monitor error

signals from another IC for safety purposes (when used with IO_4).

Wake-up capability: Can be selectable to wake-up on edges or levels.

Supply output: Provide keep alive memory supply in low-power mode

VKAM can be enabled or disabled by default at power up. The differentiation is made by part numbers.

12 IO_0 A_IN

D_IN

Can be used as analog or digital input (load dump proof) with wake-up capability

(selectable)

Analog input: Pin status can be read through the MUX output terminal

Digital input: Pin status can be read through the SPI.

Wake-up capability: Can be selectable to wake-up on edges or levels.

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

10 / 25

number

Pin name Type Definition

13 FCRBM A_IN Feedback core resistor bridge monitoring: For safety purposes, this pin is used to

monitor the middle point of a redundant resistor bridge connected on VCORE (in

parallel to the one used to set the VCORE voltage). If not used, this pin must be

connected directly to FB_CORE.

14 FS0B D_OUT First output of the safety block (active low). The pin is asserted low at start-up and

when a fault condition is detected. Open drain structure.

15 DEBUG D_IN Debug mode entry input

16 AGND GROUND Analog ground connection

17 MUX_OUT A_OUT Multiplexed output to be connected to a MCU ADC. Selection of the analog

parameter is available at MUX-OUT through the SPI.

IO_2:3 D_IN Digital input pin with wake-up capability (logic level compatible)

Digital input: Pin status can be read through the SPI. Can be used to monitor

FCCU error signals from MCU for safety purposes.

Wake-up capability: Can be selectable to wake-up on edges or levels.

20 TXD D_IN Transceiver input from the MCU which controls the state of the CAN-bus. Internal

pull-up to VDDIO.

If CAN function is not used, this pin must be left open.

21 RXD D_OUT Receiver output which reports the state of the CAN-bus to the MCU

If CAN function is not used, this pin must be left open.

TXDL D_IN Transceiver input from the MCU controlling the state of the LIN bus. Internal pull-up

to VDDIO.

or VPU_FS A_OUT Pull-up output for FS1B function.

LIN and FS1B functions are exclusive. The differentiation is made by part numbers. When LIN is available, FS1B

is not, and vice versa.

If neither LIN, nor FS1B functions are used, this pin must be left open.

23 RXDL D_OUT Receiver output reporting the state of the LIN bus to the MCU.

If LIN function is not used, this pin must be left open.

24 RSTB D_OUT This output is asserted low when the safety block reports a failure. The main

function is to reset the MCU. Reset input voltage is also monitored in order to detect

external reset and fault condition. Open drain structure.

25 MISO D_OUT SPI bus. Master input slave output

26 MOSI D_IN SPI bus. Master output slave input

27 SCLK D_IN SPI Bus. Serial clock

28 NCS D_IN Not chip select (active low)

29 INTB D_OUT This output pin generates a low pulse when an Interrupt condition occurs. Pulse

duration is configurable. Internal pull-up to VDDIO.

30 VDDIO A_IN Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os.

31 SELECT D_IN Hardware selection pin for VAUX and VCCA output voltages

32 FB_CORE A_IN VCORE voltage feedback. Input of the error amplifier.

33 COMP_

CORE

A_OUT Compensation network. Output of the error amplifier.

For FS4500 series, this pin must be left open (NC).

34 VCORE_

SNS

A_IN VCORE input voltage sense

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

11 / 25

number

Pin name Type Definition

SW_CORE A_OUT VCORE output switching point for FS6500 series35

or VCORE A_OUT VCORE output voltage for FS4500 series

36 BOOT_

CORE

A_IN/OUT Bootstrap capacitor for VCORE internal NMOS gate drive

For FS4500 series, this pin must be left open (NC).

37 VPRE A_IN VPRE input voltage sense

38 VAUX A_OUT VAUX output voltage. External PNP ballast transistor. Collector connection

39 VAUX_B A_OUT VAUX voltage regulator. External PNP ballast transistor. Base connection

40 VAUX_E A_OUT VAUX voltage regulator. External PNP ballast transistor. Emitter connection

41 VCCA_E A_OUT VCCA voltage regulator. External PNP ballast transistor. Emitter connection

42 VCCA_B A_OUT VCCA voltage regulator. External PNP ballast transistor. Base connection

43 VCCA A_OUT VCCA output voltage. External PNP ballast transistor. Collector connection

44 GATE_LS A_OUT Low-side MOSFET gate drive for non-inverting buck-boost configuration

45 DGND GROUND Digital ground connection

46 BOOT_PRE A_IN/OUT Bootstrap capacitor for the VPRE internal NMOS gate drive

47 SW_PRE2 A_OUT Second pre-regulator output switching point

48 SW_PRE1 A_OUT First pre-regulator output switching point

8 Maximum ratings

Table 4. Maximum ratings

All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Symbol Ratings Value Unit Notes

Electrical ratings

VSUP1/2/3 DC voltage at power supply pins –1.0 to 40 V [1]

VSENSE DC voltage at battery sense pin (with ext R in series mandatory) –14 to 40 V

VSW1,2 DC voltage at SW_PRE1 and SW_PRE2 Pins –1.0 to 40 V

VPRE DC voltage at VPRE Pin –0.3 to 8 V

VGATE_LS DC voltage at Gate_LS pin –0.3 to 8 V

VBOOT_PRE DC voltage at BOOT_PRE pin –1.0 to 50 V

VSW_CORE DC voltage at SW_CORE pin –1.0 to 8 V

VCORE_SNS DC voltage at VCORE_SNS pin 0.0 to 8 V

VBOOT_CORE DC voltage at BOOT_CORE pin 0.0 to 15 V

VFB_CORE DC voltage at FB_CORE pin –0.3 to 2.5 V

VCOMP_CORE DC voltage at COMP_CORE pin –0.3 to 2.5 V

VFCRBM DC voltage at FCRBM pin –0.3 to 8 V

VAUX_B,E DC voltage at VAUX_B, VAUX_E pins –0.3 to 40 V

VAUX DC voltage at VAUX pin –2.0 to 40 V

VCCA_B,E DC voltage at VCCA_B, VCCA_E pins –0.3 to 8 V

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

12 / 25

Symbol Ratings Value Unit Notes

VCCA DC voltage at VCCA pin –0.3 to 8 V

VDDIO DC voltage at VDDIO pin –0.3 to 8 V

VCAN_5V DC voltage on CAN_5V pin –0.3 to 8 V

VPU_FS DC voltage at VPU_FS pin –0.3 to 8 V

VFSxB DC voltage at FS0B, FS1B pins (with ext R in series mandatory) –0.3 to 40 V

VDEBUG DC voltage at DEBUG pin –0.3 to 40 V

VIO_0,4 DC voltage at IO_0, IO_4 pins (with ext R in series mandatory) –0.3 to 40 V

VIO_5 DC voltage at IO_5 pin –0.3 to 20 V

VKAM DC voltage at VKAM pin –0.3 to 8 V

VDIG DC voltage at INTB, RSTB, MISO, MOSI, NCS, SCLK, MUX_OUT, RXD, TXD, RXDL,

TXDL, IO_2, IO_3 pins

–0.3 to 8 V

VSELECT DC voltage at SELECT pin –0.3 to 8 V

VBUS_CAN DC voltage on CANL, CANH pins –27 to 40 V

VBUS_LIN DC voltage on LIN pin –18 to 40 V

I_Isense VSENSE maximum current capability –5.0 to 5.0 mA

I_IO0, 4, 5 IOs maximum current capability (IO_0, IO_4, IO_5) –5.0 to 5.0 mA

ESD voltage

Human body model (JESD22/A114)(20) – 100 pF, 1.5 kΩ

VESD-HBM1 •All pins ±2.0 kV [2]

VESD-HBM2 •VSUP1, 2, 3, VSENSE, VAUX, IO_0,4, FS0B, FS1B, DEBUG ±4.0 kV

VESD-HBM3 •CANH, CANL ±6.0 kV

VESD-HBM4 •LIN ±8.0 kV

Charge device model (JESD22/C101)(21):

VESD-CDM1 •All pins ±500 V

VESD-CDM2 •Corner pins ±750 V

System level ESD (gun test)

•VSUP1, 2, 3, VSENSE, VAUX, IO_0, 4, 5, FS0B, FS1B

VESD-GUN1 330 Ω/150 pF unpowered according to IEC 61000-4-2:(17) ±8.0 kV

VESD-GUN2 330 Ω/150 pF unpowered according to OEM LIN, CAN, FlexRay Conformance ±8.0 kV

VESD-GUN3 2.0 kΩ/150 pF unpowered according to ISO 10605(16) ±8.0 kV

VESD-GUN4 2.0 kΩ/330 pF powered according to ISO 10605(16) ±8.0 kV

•CANH, CANL

VESD-GUN5 330 Ω/150 pF unpowered according to IEC 61000-4-2:(17) ±15.0 kV

VESD-GUN6 330 Ω/150 pF unpowered according to OEM LIN, CAN, FlexRay Conformance ±12.0 kV

VESD-GUN7 2.0 kΩ/150 pF unpowered according to ISO 10605(16) ±15.0 kV

VESD-GUN8 2.0 kΩ/330 pF powered according to ISO 10605(16) ±12.0 kV

•LIN

VESD-GUN9 330 Ω/150 pF unpowered according to IEC 61000-4-2:(17) ±12.0 kV

VESD-GUN10 330 Ω/150 pF unpowered according to OEM LIN, CAN, FlexRay conformance ±12.0 kV

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Symbol Ratings Value Unit Notes

VESD-GUN11 2.0 kΩ/150 pF unpowered according to ISO 10605(16) ±12.0 kV

VESD-GUN12 2.0 kΩ/330 pF powered according to ISO 10605(16) ±12.0 kV

Thermal ratings

TAAmbient temperature –40 to 125 °C

TJJunction temperature –40 to 150 °C

TSTG Storage temperature –55 to 150 °C

Thermal resistance

RθJA Thermal resistance junction to ambient 30 °C/W [3]

RθJCTOP Thermal resistance junction to case top 23.8 °C/W [4]

RθJCBOTTOM Thermal resistance junction to case bottom 0.9 °C/W [5]

[1] All VSUPS (VSUP1/2/3) must be connected to the same supply (Figure 1).

[2] Compared to AGND.

[3] Per JEDEC JESD51-6(18) with the board (JESD51-7)(19) horizontal.

[4] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1)(22).

[5] Thermal resistance between the die and the solder pad on the bottom of the packaged based on simulation without any interface resistance.

9 Packaging

9.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current

package outline drawing, go to www.nxp.com and perform a keyword search for the

drawing’s document number.

Table 5. Package mechanical dimensions

Package Suffix Package outline drawing number

7.0 × 7.0, 48–Pin LQFP exposed pad,

with 0.5 mm pitch, and a 4.5 × 4.5

exposed pad

AE 98ASA00173D

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9.2 Package outline

Figure 9. SOT1571-1 Rev F

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Figure 10. SOT1571-1 Rev. F Detail View

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

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Figure 11. SOT1571-1 Rev F Notes

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

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10 Soldering

Figure 12. SOT1571-1 Rev. F - PCB design guidelines - solder mask opening pattern

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

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Figure 13. SOT1571-1 Rev. F - PCB design guidelines - I/O pads and solderable area

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

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Figure 14. SOT1571-1 Rev. F - PCB design guidelines - solder paste stencil

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Product short data sheet Rev. 7.0 — 11 November 2020

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11 References

Obtain additional information on related NXP products and application solutions through

the documents and URLs listed below.

(1) AN5238 - FS6500 and FS4500 Safe System Basis Chip Hardware Design and Product Guidelines - Application Note

https://www.nxp.com/AN5238-DOWNLOAD

(2) AN4388 - Quad Flat Package (QFP)

https://www.nxp.com/files/analog/doc/app_note/AN4388.pdf

(3) FS6500-FS4500PDTCALC - Power dissipation tool (Excel File)

https://www.nxp.com/files/analog/software_tools/FS6500-FS4500-power-dissipation-calculator.xlsx

(4) VCORE compensation network simulation tool (CNC)[1]

(5) FMEDA - FS6500/FS4500 FMEDA[1]

(6) FS6500-FS4500SMUG - FS6500/FS4500 Safety manual – user guide

https://www.docstore.nxp.com/products/product-hierarchy?query=Sm5509

(7) KITFS6522LAEEVM - FS6522, System Basis Chip, DC-DC 2.2 A Vcore LDT, CAN, LIN

http://www.nxp.com/KITFS6522LAEEVM

(8) KITFS6523CAEEVM - FS6523, System Basis Chip, DC-DC 2.2A Vcore FS1B LDT CAN

https://www.nxp.com/KITFS6523CAEEVM

(9) KITFS4503CAEEVM - FS4503, System Basis Chip, Linear 0.5 A Vcore, FS1b, LDT, CAN

https://www.nxp.com/KITFS4503CAEEVM

(10) FS6500 product summary page -

https://www.nxp.com/FS6500

(11) FS4500 product summary page -

https://www.nxp.com/FS4500

(12) Analog power management homepage -

https://www.nxp.com/products/power-management

(13) ISO 11898-2:2003 - Road vehicles — Controller area network (CAN) — Part 2: High-speed medium access unit

https://www.iso.org/standard/33423.html

(14) ISO 11898-5:2007 - Road vehicles — Controller area network (CAN) — Part 5: High-speed medium access unit with

low-power mode

https://www.iso.org/contents/data/standard/04/12/41284.html

(15) ISO 7637-2:2011 - Road vehicles — Electrical disturbances from conduction and coupling — Part 2: Electrical

transient conduction along supply lines only

https://www.iso.org/standard/50925.html

(16) ISO 10605:2008 - Road vehicles — Test methods for electrical disturbances from electrostatic discharge

https://www.iso.org/standard/41937.html

(17) IEC 61000-4-2:2008 - Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques -

Electrostatic discharge immunity test

https://webstore.iec.ch/publication/4189

(18) JESD51- 6 - INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED

CONVECTION (MOVING AIR)

(19) JESD51-7 - HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT

PACKAGES

(20) JESD22-A114F - ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING HUMAN BODY MODEL (HBM)

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(21) JESD22-C101F - FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC

DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS

(22) MIL-STD-883-1, Method 1012.1 - TEST METHOD STANDARD MICROCIRCUITS

(23) LIN Specification Package Revision 2.1:2006

https://www.lin-cia.org/fileadmin/microsites/lin-cia.org/resources/documents/LIN-Spec_Pac2_1.pdf

(24) LIN Specification Package Revision 2.2A:2010

https://www.lin-cia.org/fileadmin/microsites/lin-cia.org/resources/documents/LIN_2.2A.pdf

(25) SAE J2602-2:201211 - LIN Network for Vehicle Applications Conformance Test

https://www.sae.org/standards/content/j2602/2_201211/

[1] Available upon request.

12 Revision history

Table 6. Revision history

Document ID Release date Data sheet status Change notice Supersedes

FS6500-FS4500SDS v.7.0 20201111 Product data sheet — FS6500-

FS4500SDS v.1.0

Modifications •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors, N.V. Legal texts have been adapted to the new

company name where appropriate.

•Updated short data sheet revision number from v.1.0 to v.7.0 to align with the

revision number of the full data sheet.

•Changed product status from "Advance information" to "Product short data sheet".

•Global: Performed minor grammar, punctuation, and typographical changes

throughout the document.

•Revised all images in Figures 1 through 7.

•Section 1, added new paragraph beginning with "High temperature capability.…"

•Section 2, removed the feature "36 V maximum input operating voltage".

•Section 9.2, updated the package outline images and created separate figures for

each drawing in Figure 9, Figure 10, and Figure 11

•Section 10, added new Soldering section and Figure 12, Figure 13, and Figure 14.

•Section 11, Updated reference to FS6500-FS4500SMUG - FS6500/FS4500 Safety

Manual – user guide and added industry standard documents referenced in the

narrative.

FS6500-FS4500SDS v.1.0 20171214 Data sheet: advance

information

— —

Modifications •Initial release

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13 Legal information

13.1 Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product

development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

13.2 Definitions

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

13.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

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Product short data sheet Rev. 7.0 — 11 November 2020

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Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Security — Customer understands that all NXP products may be subject

to unidentified or documented vulnerabilities. Customer is responsible

for the design and operation of its applications and products throughout

their lifecycles to reduce the effect of these vulnerabilities on customer’s

applications and products. Customer’s responsibility also extends to other

open and/or proprietary technologies supported by NXP products for use

in customer’s applications. NXP accepts no liability for any vulnerability.

Customer should regularly check security updates from NXP and follow up

appropriately. Customer shall select products with security features that best

meet rules, regulations, and standards of the intended application and make

the ultimate design decisions regarding its products and is solely responsible

for compliance with all legal, regulatory, and security related requirements

concerning its products, regardless of any information or support that may

be provided by NXP. NXP has a Product Security Incident Response Team

(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,

reporting, and solution release to security vulnerabilities of NXP products.

Suitability for use in automotive applications — This NXP product has

been qualified for use in automotive applications. It has been developed in

accordance with ISO 26262, and has been ASIL-classified accordingly. If

this product is used by customer in the development of, or for incorporation

into, products or services (a) used in safety critical applications or (b) in

which failure could lead to death, personal injury, or severe physical or

environmental damage (such products and services hereinafter referred

to as “Critical Applications”), then customer makes the ultimate design

decisions regarding its products and is solely responsible for compliance with

all legal, regulatory, safety, and security related requirements concerning

its products, regardless of any information or support that may be provided

by NXP. As such, customer assumes all risk related to use of any products

in Critical Applications and NXP and its suppliers shall not be liable for

any such use by customer. Accordingly, customer will indemnify and hold

NXP harmless from any claims, liabilities, damages and associated costs

and expenses (including attorneys’ fees) that NXP may incur related to

customer’s incorporation of any product in a Critical Application.

13.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

NXP — wordmark and logo are trademarks of NXP B.V.

SafeAssure — is a trademark of NXP B.V.

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Product short data sheet Rev. 7.0 — 11 November 2020

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Tables

Tab. 1. Part number breakdown ....................................3

Tab. 2. Orderable part variations ...................................4

Tab. 3. FS6500/FS4500 pin definition ........................... 9

Tab. 4. Maximum ratings .............................................11

Tab. 5. Package mechanical dimensions .................... 13

Tab. 6. Revision history ...............................................21

Figures

Fig. 1. FS6500C simplified application diagram -

buck boost configuration - FS1B ....................... 2

Fig. 2. FS6500L simplified application diagram -

buck configuration - LIN - VCCA = 100 mA ....... 2

Fig. 3. FS4500C simplified application diagram -

buck boost configuration - FS1B ....................... 3

Fig. 4. FS6500/FS4500 with CAN and LIN

simplified internal block diagram ....................... 6

Fig. 5. FS6500 pinout with CAN and FS1B ..................7

Fig. 6. FS6500 pinout with CAN and LIN ..................... 7

Fig. 7. FS6500 pinout without CAN, without LIN .......... 8

Fig. 8. FS4500 pinout with CAN and FS1B ..................8

Fig. 9. SOT1571-1 Rev F ...........................................14

Fig. 10. SOT1571-1 Rev. F Detail View ....................... 15

Fig. 11. SOT1571-1 Rev F Notes ................................ 16

Fig. 12. SOT1571-1 Rev. F - PCB design guidelines

- solder mask opening pattern ........................ 17

Fig. 13. SOT1571-1 Rev. F - PCB design guidelines

- I/O pads and solderable area ....................... 18

Fig. 14. SOT1571-1 Rev. F - PCB design guidelines

- solder paste stencil .......................................19

NXP Semiconductors FS6500, FS4500

Safety power system basis chip with CAN FD and LIN transceivers

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 11 November 2020

Document identifier: FS6500-FS4500SDS

Contents

1 General description ............................................ 1

2 Features and benefits .........................................1

3 Applications .........................................................1

4 Simplified application diagrams ........................ 2

5 Ordering information .......................................... 3

5.1 Part number definition ....................................... 3

5.2 Part numbers list ............................................... 4

6 Block diagram ..................................................... 6

7 Pinning information ............................................ 7

7.1 Pinning information ............................................ 7

7.2 Pin description ................................................... 9

8 Maximum ratings ...............................................11

9 Packaging .......................................................... 13

9.1 Package mechanical dimensions .................... 13

9.2 Package outline ............................................... 14

10 Soldering ............................................................17

11 References ......................................................... 20

12 Revision history ................................................ 21

13 Legal information .............................................. 22