24 GHz to 44 GHz, Wideband, Microwave Downconverter ADMV1014 Data Sheet GND LO_N LO_P GND VCC_QUAD BG_RBIAS I_P x4 RST I_N IF_I VCC_BG 90 0 VCC_LNA_1P5 IF_Q GND Q_N RF_IN GND VCC_LNA_3P3 VCC_VVA VCTRL GND VCC_VGA VDET VCC_IF_BB DET Figure 1. GENERAL DESCRIPTION The ADMV1014 is a silicon germanium (SiGe), wideband, microwave downconverter optimized for point to point microwave radio designs operating in the 24 GHz to 44 GHz frequency range. The downconverter offers two modes of frequency translation. The device is capable of direct quadrature demodulation to baseband inphase (I)/quadrature (Q) output signals, as well as image rejection downconversion to a complex intermediate frequency (IF) output carrier frequency. The baseband outputs can be dc-coupled, or, more typically, the I/Q outputs are ac-coupled with a sufficiently low high-pass corner frequency to ensure adequate demodulation accuracy. The serial port interface (SPI) allows fine adjustment of the quadrature phase to allow the user to optimize I/Q demodulation performance. Alternatively, the baseband I/Q outputs can be disabled, and the I/Q signals can be passed through an on-chip active balun to Rev. A provide two single-ended complex IF outputs anywhere between 800 MHz and 6000 MHz. When used as an image rejecting downconverter, the unwanted image term is typically suppressed to better than 30 dBc below the wanted sideband. The ADMV1014 offers a flexible local oscillator (LO) system, including a frequency quadruple option allowing up to a 41 GHz range of LO input frequencies to cover a radio frequency (RF) input range as wide as 24 GHz to 44 GHz. A square law power detector is provided to allow monitoring of the power levels at the mixer inputs. The detector output provides closed-loop control of the RF input variable attenuator through an external op amp error integrator circuit option. The ADMV1014 downconverter comes in a compact, thermally enhanced, 5 mm x 5 mm LGA package. The ADMV1014 operates over the -40C to +85C case temperature range. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018-2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 17172-001 GND SDO Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE) VCC_MIXER ADMV1014 SEN Q_P APPLICATIONS DVDD SCLK FUNCTIONAL BLOCK DIAGRAM Wideband RF input frequency range: 24 GHz to 44 GHz 2 downconversion modes Direct conversion from RF to baseband I/Q Image rejecting downconversion to complex IF LO input frequency range: 5.4 GHz to 10.25 GHz LO quadrupler for up to 41 GHz Matched 50 , single-ended RF input, and complex IF outputs Option between matched 100 balanced or 50 singleended LO inputs 100 balanced baseband I/Q output impedance with adjustable output common-mode voltage level Image rejection optimization Square law power detector for setting mixer input power Variable attenuator for receiver power control Programmable via a 4-wire SPI interface 32-terminal, 5 mm x 5 mm LGA package SDI FEATURES ADMV1014 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Image Rejection Downconversion ........................................... 29 Applications ....................................................................................... 1 Detector ....................................................................................... 29 Functional Block Diagram .............................................................. 1 LO Input Path ............................................................................. 29 General Description ......................................................................... 1 Power-Down ............................................................................... 29 Revision History ............................................................................... 2 Serial Port Interface (SPI) ......................................................... 30 Specifications..................................................................................... 3 Applications Information .............................................................. 31 Serial Port Register Timing ......................................................... 5 Error Vector Magnitude (EVM) Performance ....................... 31 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 Baseband Quadrature Demodulation to Very Low Frequencies ................................................................................. 32 ESD Caution .................................................................................. 6 Performance at Different Quad Filter Settings ....................... 32 Pin Configuration and Function Descriptions ............................. 7 VVA Temperature Compensation............................................ 33 Typical Performance Characteristics ............................................. 9 Performance Between Differential vs. Single-Ended LO Input ....................................................................................................... 33 I/Q Mode ....................................................................................... 9 IF Mode........................................................................................ 17 Performance across RF Frequency at Fixed IF and Baseband Frequencies ................................................................................. 34 Output Detector Performance .................................................. 24 Recommended Land Pattern .................................................... 35 Return Loss and Isolations ........................................................ 25 Evaluation Board Information ................................................. 35 M x N Spurious Performance ................................................... 27 Register Summary .......................................................................... 36 Theory of Operation ...................................................................... 28 Register Details ............................................................................... 37 Start-Up Sequence ...................................................................... 28 Outline Dimensions ....................................................................... 42 Baseband Quadrature Demodulation (I/Q Mode) ................ 28 Ordering Guide .......................................................................... 42 REVISION HISTORY 4/2019--Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Table 3 and Thermal Resistance Section................... 6 Changes to Figure 3 and Table 5 ..................................................... 7 Changes to Figure 14 ...................................................................... 10 Changes to Figure 19 Caption....................................................... 11 Changes to Figure 27 ...................................................................... 12 Changes to Figure 51 Caption and Figure 52 Caption .............. 17 Changes to Figure 63 Caption and Figure 64 Caption .............. 19 Changes to Figure 69 Caption and Figure 70 Caption .............. 20 Changes to Figure 75 ...................................................................... 21 Changes to Figure 79 ...................................................................... 22 Changes to Return Loss and Isolations Section, Figure 95, and Figure 97 .......................................................................................... 25 Changes to Figure 99 and Figure 101 .......................................... 26 Changes to Start-Up Sequence Section and Baseband Quadrature Demodulation (I/Q Mode) Section ....................... 28 Changes to Image Rejection Downconversion Section and LO Input Path Section ............................................................ 29 Change to Serial Port Interface (SPI) Section............................. 30 Changes to Figure 111 ................................................................... 32 Changes to Table 18 and Table 19 ................................................ 41 10/2018--Revision 0: Initial Version Rev. A | Page 2 of 42 Data Sheet ADMV1014 SPECIFICATIONS RF amplitude = -30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B set to 0x727C, Register 0x03, Bits[12:13] set to 11, and ambient temperature (TA) = 25C, unless otherwise noted. Measurements are in IF mode, performed with a 90 hybrid, Register 0x03, Bit 11 = 0, and Register 0x03, Bit 8 = 1, unless otherwise noted. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, common-mode voltage (VCM) = 1.15 V, Register 0x03, Bit 11 = 1, and Register 0x03, Bit 8 = 0, unless otherwise noted. Table 1. Parameter FREQUENCY RANGES RF Input LO Input LO Quadrupler IF Output Baseband (BB) I/Q Output LO AMPLITUDE RANGE I/Q DEMODULATOR PERFORMANCE Conversion Gain 24 GHz to 42 GHz 42 GHz to 44 GHz Voltage Variable Attenuator (VVA) Control Range Single Sideband (SSB) Noise Figure 24 GHz to 42 GHz 42 GHz to 44 GHz Input Third-Order Intercept (IP3) 24 GHz to 42 GHz 42 GHz to 44 GHz Input Second-Order Intercept (IP2) Input 1 dB Compression Point (P1dB) 24 GHz to 42 GHz 42 GHz to 44 GHz Amplitude Balance Phase Balance Image Rejection Uncalibrated Calibrated IF DOWNCONVERTER PERFORMANCE Conversion Gain 24 GHz to 42 GHz 42 GHz to 44 GHz VVA Control Range SSB Noise Figure 24 GHz to 42 GHz 42 GHz to 44 GHz Input IP3 24 GHz to 42 GHz 42 GHz to 44 GHz Test Conditions/Comments Min 24 5.4 21.6 0.8 DC -6 Typ Max Unit 0 44 10.25 41 6.0 6.0 +6 GHz GHz GHz GHz GHz dBm At maximum gain 12.5 12.5 17 17 19 dB dB dB At maximum gain 5.5 6 8 8.5 dB dB At maximum gain 24 GHz to 44 GHz, at maximum gain At maximum gain -14 -15 DC < baseband frequency (fBB) < 2 GHz 2 GHz < fBB < 4 GHz 4 GHz < fBB < 6 GHz 24 GHz to 44 GHz, at maximum gain 0 -1 45 dBm dBm dBm -10 -11 0.5 1 2 4 dBm dBm dB Degrees Degrees Degrees 45 52 dBc dBc 17 16 19 dB dB dB At maximum gain 12.5 11.5 At maximum gain 5.5 6 8 8.5 dB dB At maximum gain 0 0.5 Rev. A | Page 3 of 42 dBm dBm ADMV1014 Parameter Input P1dB 24 GHz to 42 GHz 42 GHz to 44 GHz Amplitude Balance Phase Balance Image Rejection Uncalibrated Calibrated RECEIVER (Rx) POWER DETECTOR PERFORMANCE Input Level Minimum Maximum 1 dB Dynamic Range Output Voltage Maximum DC Output RETURN LOSS RF Input LO Input IF Output BB Output BB I/Q Output Impedance LEAKAGE Fundamental LO to RF 4 x LO to RF Fundamental LO to IF Fundamental LO to I/Q LOGIC INPUTS Input Voltage Range High, VINH Low, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output Voltage Range High, VOH Low, VOL Output High Current, IOH POWER INTERFACE VCC_IF_BB, VCC_VGA, VCC_LNA_3P3, VCC_MIXER, VCC_BG, VCC_QUAD 3.3 V Supply Current DVDD, VCC_VVA 1.8 V Supply Current VCC_LNA_1P5 1.5 V Supply Current Total Power Consumption Power-Down Data Sheet Test Conditions/Comments At maximum gain Min Typ -14 -15 -9 -10 -0.5 0.5 1 2.5 dBm dBm dB Degrees Degrees Degrees 30 35 dBc dBc -35 -14 20 dBm dBm dB 3.3 V -13 -10 -12 -15 100 dB dB dB dB -70 -70 -60 -60 dBm dBm dBm dBm 800 MHz < IF frequency (fIF) < 2 GHz 2 GHz < fIF < 4 GHz 4 GHz < fIF < 6 GHz Max Unit 1 dB dynamic range 50 single-ended 100 differential 50 single-ended 100 differential At maximum gain DVDD - 0.4 0 1.8 0.4 V V A pF 1.8 0.4 500 V V A 3.45 V 100 3 DVDD - 0.4 0 3.15 1.7 1.43 Rev. A | Page 4 of 42 3.3 437 1.8 4.2 1.5 33 1.5 96 1.9 1.57 125 mA V mA V mA W mW Data Sheet ADMV1014 SERIAL PORT REGISTER TIMING Table 2. Parameter tSDI, SETUP tSDI, HOLD tSCLK, HIGH tSCLK, LOW tSCLK, SEN_SETUP escription Data to clock setup time Data to clock hold time Clock high duration Clock low duration Clock to SEN setup time tSCLK, DOT tSCLK, DOV tSCLK, SEN_INACTIVE Clock to data out transition time Clock to data out valid time Clock to SEN inactive tSEN_INACTIVE Inactive SEN (between two operations) Min 10 10 40 to 60 40 to 60 30 Typ Max Unit ns ns % % ns 10 10 20 ns ns ns 80 ns Timing Diagram tSCLK, HIGH tSCLK, LOW SCLK tSCLK, SEN_SETU P tSEN_INACTIVE SEN tSCLK, DOT tSCLK, SEN_INACTIVE tSCLK, DOV tSDI, SETUP tSDI, HOLD SDI Figure 2. Serial Port Register Timing Diagram Rev. A | Page 5 of 42 17172-106 SDO ADMV1014 Data Sheet ABSOLUTE MAXIMUM RATINGS TJ = (P x JT) + TTOP Table 3. Parameter Supply Voltage VCC_IF_BB, VCC_VGA, VCC_LNA_3P3, VCC_MIXER, VCC_BG, VCC_QUAD, DVDD VCC_VVA, VCC_LNA_1P5 RF Input Power LO Input Power Maximum Junction Temperature Maximum Power Dissipation1 Lifetime at Maximum Junction Temperature (TJ) Operating Case Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Moisture Sensitivity Level (MSL) Rating2 Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) Field Induced Charged Device Model (FICDM) Rating 4.3 V 2.3 V 0 dBm 9 dBm 125C 2.17 W 1 x106 hours -40C to +85C -55C to +125C 260C MSL3 3000 V 750 V (1) where: TTOP is package top temperature (C). TTOP is measured at the top center of the package. JT is the junction to top thermal characterization number. P is the total power dissipation in the chip (W). TJ = (P x JB) + TBOARD (2) where: TBOARD is the board temperature measured on the midpoint of the longest side of the package no more than 1 mm from the edge of the package body (C). JB is the junction to board thermal characterization number. P is the total power dissipation in the chip (W). As stated in JEDEC51-12, only use Equation 1 and Equation 2 when no heat sink or heat spreader is present. When a heat sink or heat spreader is added, use JC_TOP to estimate or calculate the junction temperature. Table 4. Thermal Resistance 1 The maximum power dissipation is a theoretical number calculated by (TJ - 85C)/JC_TOP. 2 Based on IPC/JEDEC J-STD-20 MSL classifications. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Package Type1 CC-32-6 1 JA2 33.6 JC_TOP3 18.4 JB4 13.3 JT5 4.9 JB6 12.6 Unit C/W The thermal resistance values specified in Table 4 are simulated based on JEDEC specifications, unless specified otherwise, and must be used in compliance with JESD51-12. 2 JA is the junction to ambient thermal resistance in a natural convection, JEDEC environment. 3 JC_TOP is the junction to case (top) JEDEC thermal resistance. 4 JB is the junction to board JEDEC thermal resistance. 5 JT is the junction to top JEDEC thermal characterization parameter. 6 JB is the junction to board JEDEC thermal characterization parameter ESD CAUTION Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Only use JA and JC to compare the thermal performance of different packages when all test conditions listed are similar to JEDEC specifications. Otherwise, use JT and JB to calculate the device junction temperature using the following equations: Rev. A | Page 6 of 42 Data Sheet ADMV1014 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADMV1014 GND LO_N LO_P GND VCC_MIXER DVDD SCLK SDI TOP VIEW (Not to Scale) 32 31 30 29 28 27 26 25 SEN 1 24 VCC_QUAD I_P 2 23 BG_RBIAS I_N 3 22 RST IF_I 4 21 VCC_BG GND 5 20 VCC_LNA_1P5 IF_Q 6 19 GND Q_N 7 18 RF_IN Q_P 8 17 GND NOTES 1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE GROUND PLANE. 17172-002 VCC_LNA_3P3 VCC_VVA VCTRL GND VCC_VGA VDET SDO 10 11 12 13 14 15 16 VCC_IF_BB 9 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2, 3 Mnemonic SEN 4, 6 IF_I, IF_Q 5, 13, 17, 19, 25, 28 7, 8 GND Q_N, Q_P 9 10 SDO VCC_IF_BB 11 12 14 VDET VCC_VGA VCTRL 15 VCC_VVA 16 18 VCC_LNA_3P3 RF_IN 20 VCC_LNA_1P5 21 VCC_BG 22 23 RST BG_RBIAS 24 VCC_QUAD I_P, I_N Description SPI Serial Enable. SEN is a high impedance pin with a logic of 1.8 V. Negative (I_N) and Positive (I_P) Differential BB I Outputs. These pins are dc-coupled. IF I and IF Q Single-Ended Complex Quadrature Outputs. These pins are dc-coupled to GND, and each pin is matched to 50 . Ground. Positive (Q_P) and Negative (Q_N) Differential Baseband Q Outputs. These pins are dc-coupled. SPI Serial Data Output. 3.3 V Power Supply for BB and IF Section. Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. Square Law Detector Output Voltage. 3.3 V Power Supply for RF Amplifier. Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. RF VVA Control Voltage. The voltage on this pin ranges from 1.8 V (minimum gain) to 0 V (maximum gain). Refer to the ADMV1014-EVALZ user guide for the external component requirements. 1.8 V Power Supply for VVA Control Circuit. Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. 3.3 V Power Supply for LNA. Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. RF Input. This pin is dc-coupled internally with a choke to GND, and matched to 50 , singleended. A dc input above 0 V requires external ac coupling. 1.5 V Power Supply for Low Noise Amplifier (LNA). Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. 3.3 V Power Supply for Band Gap Circuit. Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. SPI Reset. Connect this pin to logic high for normal operation. Bang Gap Circuit External High Precision Resistor. Place a 1.1 k, high precision resistor shunt to ground close to this pin. 3.3 V Power Supply for Quadruple. Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. Rev. A | Page 7 of 42 ADMV1014 Data Sheet Pin No. 26, 27 Mnemonic LO_N, LO_P 29 30 31 32 VCC_MIXER DVDD SCLK SDI EPAD Description Negative (LO_N) and Positive (LO_P) Differential Local Oscillator Input. These pins are dc-coupled internally with a choke to GND and matched to 100 differential or 50 single-ended. A dc input above 0 V requires external ac coupling. When using the LO input as single-ended, terminate the unused LO port with a 50 impedance to ground. 3.3 V Power Supply for the Mixer. Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. 1.8 V SPI Digital Supply. Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. SPI Clock Digital Input. SCLK is a high impedance pin. SPI Serial Data Input. SDI is a high impedance pin. Exposed Pad. Solder the exposed pad to a low impedance ground plane. Rev. A | Page 8 of 42 Data Sheet ADMV1014 TYPICAL PERFORMANCE CHARACTERISTICS I/Q MODE RF amplitude = -30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, and TA = 25C, unless otherwise noted. Register 0x0B is set to 0x727C, Register 0x03, Bits[13:12] are set to 11, VCM = 1.15 V, Register 0x03, Bit 11 = 1, Register 0x03, Bit 8 = 0, and measurements are a composite of the I and Q channels. VATT is the attenuation voltage at the VCTRL pin. VATT = 0 V, unless otherwise specified. 25 25 20 CONVERSION GAIN (dB) 5 0 -5 -15 -20 -25 -30 23 +85C AT 1.8V +25C AT 1.8V -40C AT 1.8V +85C AT 0.8V +25C AT 0.8V -40C AT 0.8V +85C AT 0V +25C AT 0V -40C AT 0V 25 27 29 15 10 5 0 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VATT (V) Figure 4. Conversion Gain vs. RF Frequency at Three Different Gain Settings for Various Temperatures, fBB = 100 MHz (Upper Sideband) 17172-006 -10 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz 20 10 17172-003 CONVERSION GAIN (dB) 15 Figure 7. Conversion Gain vs. VATT for Various RF Frequencies (fRF), fBB = 100 MHz at fRF = 28 GHz and 39 GHz 25 25 20 CONVERSION GAIN (dB) CONVERSION GAIN (dB) 20 15 10 5 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 0 15 10 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 5 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 17172-004 -10 23 Figure 5. Conversion Gain vs. RF Frequency for Various Supply Voltages, fBB = 100 MHz 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) 17172-007 -5 Figure 8. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Upper Sideband) 25 25 20 CONVERSION GAIN (dB) CONVERSION GAIN (dB) 20 15 10 5 0 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND 15 10 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 5 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 0 17172-005 -10 23 Figure 6. Conversion Gain vs. RF Frequency for Various LO Inputs, fBB = 100 MHz 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) 17172-008 -5 Figure 9. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Lower Sideband) Rev. A | Page 9 of 42 ADMV1014 Data Sheet 10.0 10 8 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND 6 INPUT IP3 (dBm) 4 INPUT IP3 (dBm) 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 7.5 2 0 -2 -4 -6 5.0 2.5 0 -2.5 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -5.0 17172-009 -10 23 Figure 10. Input IP3 vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VATT (V) 17172-012 -8 Figure 13. Input IP3 vs. VATT for Various RF Frequencies (fRF), RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) at fRF = 28 GHz and 39 GHz 10.0 10 8 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 6 7.5 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 5.0 INPUT IP3 (dBm) INPUT IP3 (dBm) 4 2 0 -2 2.5 0 -2.5 -4 -5.0 -6 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -10.0 17172-010 Figure 11. Input IP3 vs. RF Frequency at Maximum Gain for Various Supply Voltages, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) 0 BASEBAND FREQUENCY (GHz) Figure 14. Input IP3 vs. Baseband Frequency at Maximum Gain, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and 39 GHz, Upper Sideband and Lower Sideband 10 5 8 4 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND 6 INPUT IP3 (dBm) 2 2 0 -2 1 0 -1 -4 -2 -6 -3 -8 -4 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 -5 -30 17172-011 INPUT IP3 (dBm) 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 3 4 -10 23 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Figure 12. Input IP3 vs. RF Frequency at Maximum Gain for Various LO Inputs, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) -29 -28 -27 -26 -25 -24 -23 INPUT POWER (dBm) -22 -21 -20 17172-014 -10 23 17172-013 -7.5 -8 Figure 15. Input IP3 vs. Input Power for Various RF Frequencies (fRF) at 20 MHz Spacing, fBB = 100 MHz, fRF = 28 GHz and 39 GHz Rev. A | Page 10 of 42 Data Sheet ADMV1014 25 12 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND 8 6 4 10 29 31 33 35 37 39 41 43 45 0 Figure 16. Noise Figure vs. RF Frequency at Maximum Gain for Various Temperatures, fBB = 100 MHz 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VATT (V) 17172-018 27 17172-015 25 RF FREQUENCY (GHz) Figure 19. Noise Figure vs. VATT for Various RF Frequencies and Temperatures, fBB = 100 MHz at fRF = 28 GHz and 39 GHz 12 9 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 8 7 NOISE FIGURE (dB) 10 NOISE FIGURE (dB) 15 5 2 0 23 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz 20 NOISE FIGURE (dB) NOISE FIGURE (dB) 10 8 6 4 6 5 4 3 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 2 2 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 17172-016 0 23 Figure 17. Noise Figure vs. RF Frequency for Various Supply Voltages, fBB = 100 MHz 0 BASEBAND FREQUENCY (GHz) Figure 20. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Upper Sideband) 12 9 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND 8 7 NOISE FIGURE (dB) 10 NOISE FIGURE (dB) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 17172-019 1 8 6 4 6 5 4 3 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 2 2 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 0 17172-017 0 23 Figure 18. Noise Figure vs. RF Frequency for Various LO Inputs, fBB = 100 MHz 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) 17172-020 1 Figure 21. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Lower Sideband) Rev. A | Page 11 of 42 ADMV1014 Data Sheet 80 80 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND 70 60 IMAGE REJECTION (dBc) 50 40 30 20 29 31 33 35 37 39 41 43 45 Figure 22. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Temperatures, fBB = 100 MHz, Uncalibrated 25 27 29 31 33 35 37 39 41 43 45 Figure 25. Image Rejection vs. RF Input Frequency for Various LO Inputs, fBB = 100 MHz 80 70 IMAGE REJECTION (dBc) 60 50 40 30 20 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 60 50 40 30 20 27 29 31 33 35 37 39 41 43 45 RF INPUT FREQUENCY (GHz) 0 17172-022 25 0 70 70 60 60 IMAGE REJECTION (dBc) 80 30 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 20 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Figure 26. Image Rejection vs. VATT for Various RF Frequencies (fRF), fBB = 100 MHz at fRF = 28 GHz and 39 GHz 80 40 0.4 VATT (V) Figure 23. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Temperatures, fBB = 100 MHz, Calibrated 50 0.2 17172-025 10 10 10 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 50 40 30 20 10 25 27 29 31 33 35 37 39 RF INPUT FREQUENCY (GHz) 41 43 45 0 17172-023 0 23 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND 20 RF INPUT FREQUENCY (GHz) +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND 70 IMAGE REJECTION (dBc) 30 0 23 80 IMAGE REJECTION (dBc) 40 17172-024 27 17172-021 25 RF INPUT FREQUENCY (GHz) 0 23 50 10 10 0 23 60 Figure 24. Image Rejection vs. RF Input Frequency for Various Supply Voltages, fBB = 100 MHz 0 1 2 3 4 5 BASEBAND FREQUENCY (GHz) 6 7 17172-026 IMAGE REJECTION (dBc) 70 Figure 27. Image Rejection vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) Rev. A | Page 12 of 42 ADMV1014 60 60 50 50 40 40 INPUT IP2 (dBm) 30 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND 20 10 20 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 10 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 17172-027 0 23 30 Figure 28. Input IP2 vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VATT (V) 17172-030 INPUT IP2 (dBm) Data Sheet Figure 31. Input IP2 vs. VATT for Various RF Frequencies (fRF), RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) at fRF = 28 GHz and 39 GHz 60 55 50 50 45 INPUT IP2 (dBm) INPUT IP2 (dBm) 40 40 30 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 20 35 30 25 20 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 15 10 10 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 17172-028 25 Figure 29. Input IP2 vs. RF Frequency (fRF) at Maximum Gain for Various Supply Voltages, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) 17172-031 5 0 23 Figure 32. Input IP2 vs. Baseband Frequency at Maximum Gain, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and 39 GHz, Upper Sideband 55 60 50 50 45 INPUT IP2 (dBm) INPUT IP2 (dBm) 40 40 30 20 30 25 20 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 15 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND 10 35 10 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 0 17172-029 25 Figure 30. Input IP2 vs. RF Frequency at Maximum Gain for Various LO Inputs, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) 17172-032 5 0 23 Figure 33. Input IP2 vs. Baseband Frequency for Various RF Frequencies (fRF) at 20 MHz Spacing, fBB = 100 MHz, fRF = 28 GHz and 39 GHz Rev. A | Page 13 of 42 ADMV1014 Data Sheet 0 0 -2 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND -2 -4 -8 -10 -12 -14 -6 -8 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz -10 -16 -12 -18 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -14 17172-033 0 1.0 1.2 1.4 1.6 1.8 -2 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND -4 INPUT P1dB (dBm) -6 -8 -10 -12 -14 -6 -8 -10 -12 -16 -16 -18 -18 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -20 17172-034 25 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND -14 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) Figure 35. Input P1dB vs. RF Frequency for Various Supply Voltages, fBB = 100 MHz 17172-037 -4 INPUT P1dB (dBm) 0.8 0 -2 Figure 38. Input P1dB vs. Baseband Output Frequency at fRF = 28 GHz and 39 GHz (Upper Sideband) 0 0 -2 -2 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND -4 -4 INPUT P1dB (dBm) -6 -8 -10 -12 -14 -6 -8 -10 -12 -16 -18 -18 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 Figure 36. Input P1dB vs. RF Frequency for Various LO Inputs, fBB = 100 MHz Rev. A | Page 14 of 42 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND -14 -16 17172-035 INPUT P1dB (dBm) 0.6 Figure 37. Input P1dB vs. VATT for Various RF Frequencies (fRF), fBB = 100 MHz at fRF = 28 GHz and 39 GHz 0 -20 23 0.4 VATT (V) Figure 34. Input P1dB vs. RF Frequency at Maximum Gain for Various Temperatures, fBB = 100 MHz -20 23 0.2 -20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) Figure 39. Input P1dB vs. Baseband Output Frequency at fRF = 28 GHz and 39 GHz (Lower Sideband) 17172-038 -20 23 17172-036 -6 INPUT P1dB (dBm) INPUT P1dB (dBm) -4 ADMV1014 1.0 1.0 0.8 0.8 0.6 0.6 MAGNITUDE ERROR (dB) 0.4 0.2 0 -0.2 -0.4 0 -0.2 -0.4 -0.6 BB Q_N +85C BB Q_N +25C BB Q_N -40C BB Q_P +85C BB Q_P +25C BB Q_P -40C -1.0 0 1 2 3 4 5 6 7 BASEBAND OUTPUT FREQUENCY (GHz) Figure 40. Magnitude Error vs. Baseband Output Frequency, Referenced to I_P Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain 0 4 4 PHASE ERROR (Degrees) 6 -2 -4 BB Q_P +85C BB Q_P +25C BB Q_P -40C -8 0 1 2 3 4 5 BASEBAND OUTPUT FREQUENCY (GHz) 6 7 Figure 41. Phase Error vs. Baseband Output Frequency, Referenced to I_P Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain 2 3 4 5 6 7 2 0 -2 -4 BB I_N +85C BB I_N +25C BB I_N -40C -6 BB Q_N +85C BB Q_N +25C BB Q_N -40C BB Q_P +85C BB Q_P +25C BB Q_P -40C -8 17172-046 -6 BB Q_N +85C BB Q_N +25C BB Q_N -40C 1 Figure 42. Magnitude Error vs. Baseband Output Frequency, Referenced to I_P Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain 6 0 BB Q_P +85C BB Q_P +25C BB Q_P -40C BASEBAND OUTPUT FREQUENCY (GHz) 8 2 BB Q_N +85C BB Q_N +25C BB Q_N -40C -1.0 8 BB I_N +85C BB I_N +25C BB I_N -40C BB I_N +85C BB I_N +25C BB I_N -40C -0.8 17172-045 BB I_N +85C BB I_N +25C BB I_N -40C -0.8 PHASE ERROR (Degrees) 0.2 17172-047 -0.6 0.4 0 1 2 3 4 5 BASEBAND OUTPUT FREQUENCY (GHz) 6 7 17172-048 MAGNITUDE ERROR (dB) Data Sheet Figure 43. Phase Error vs. Baseband Output Frequency, Referenced to I_P Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain Rev. A | Page 15 of 42 ADMV1014 Data Sheet 25 12 10 10 0 1 2 3 5 0 23 25 27 29 31 33 35 37 39 41 43 45 Figure 44. Conversion Gain vs. RF Frequency at Four Different BB_AMP_GAIN_CTRL (Register 0x0A, Bits[2:1]) Settings, fBB = 100 MHz (Upper Sideband) INPUT IP3 (dBm) 2 1 0 -1 0 1 2 3 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 17172-043 -4 27 25 27 29 31 33 35 37 39 41 43 45 Figure 46. Noise Figure vs. RF Frequency Four Different BB_AMP_GAIN_CTRL (Register 0x0A, Bits[2:1]) Settings, fBB = 100 MHz (Upper Sideband) 3 25 0 1 2 3 RF FREQUENCY (GHz) 4 -5 23 4 0 23 5 -3 6 2 RF FREQUENCY (GHz) -2 8 17172-044 NOISE FIGURE (dB) 15 17172-042 CONVERSION GAIN (dB) 20 Figure 45. Input IP3 vs. RF Frequency at Four Different BB_AMP_GAIN_CTRL (Register A, Bits[2:1]) Settings, fBB = 100 MHz (Upper Sideband) Rev. A | Page 16 of 42 Data Sheet ADMV1014 IF MODE RF amplitude = -30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25C unless otherwise specified. Register 0x0B set to 0x727C, Register 0x03, Bits[12:13] set to 11, measurements performed with a 90 hybrid, Register 0x03, Bit 11 = 0, and Register 0x03, Bit 8 = 1. 25 25 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 20 CONVERSION GAIN (dB) 20 10 5 0 -5 -10 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND -20 -25 25 27 29 31 33 35 10 5 37 39 41 43 45 RF FREQUENCY (GHz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 IF FREQUENCY Figure 47. Conversion Gain vs. RF Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) Figure 50. Conversion Gain vs. IF Frequency (fIF) at Maximum Gain, fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) 25 25 20 +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz 20 CONVERSION GAIN (dB) 10 5 0 -5 -10 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND -20 -25 -30 23 25 27 29 31 33 15 10 5 0 -5 -10 35 37 39 41 43 45 RF FREQUENCY (GHz) -15 Figure 48. Conversion Gain vs. RF Frequency at Maximum Gain for Various Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.8 25 +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz 20 20 15 CONVERSION GAIN (dB) 10 5 0 -5 -10 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND -15 -20 -25 25 27 29 31 33 35 15 10 5 0 -5 -10 37 RF FREQUENCY (GHz) 39 41 43 45 -15 17172-051 CONVERSION GAIN (dB) 1.6 Figure 51. Conversion Gain vs. VATT at Various Temperatures, fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Upper Sideband) 25 -30 23 1.4 VATT (V) 17172-053 -15 17172-050 CONVERSION GAIN (dB) 15 Figure 49. Conversion Gain vs. RF Frequency at Maximum Gain for Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 0 0.2 0.4 0.6 0.8 1.0 VATT (V) 1.2 1.4 1.6 1.8 17172-054 -30 23 15 17172-052 -15 17172-049 CONVERSION GAIN (dB) 15 Figure 52. Conversion Gain vs. VATT at Various Temperatures, fIF = 3.5 GHz , fRF = 28 GHz and 39 GHz (Lower Sideband) Rev. A | Page 17 of 42 ADMV1014 Data Sheet 10 12 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND 10 8 6 4 INPUT IP3 (dBm) INPUT IP3 (dBm) 6 8 2 0 -2 -4 -6 4 2 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 0 -2 -8 -4 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -6 17172-055 -12 23 Figure 53. Input IP3 vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VATT (V) 17172-058 -10 Figure 56. Input IP3 vs. VATT for Various RF Frequencies (fRF), RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz at fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) 12 10 10 8 8 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 6 4 INPUT IP3 (dBm) 4 2 0 -2 -4 -10 -12 23 25 27 29 31 33 0 -2 -6 -8 35 37 39 41 43 45 RF FREQUENCY (GHz) -10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Figure 54. Input IP3 vs. RF Frequency at Maximum Gain for Various Supply Voltages, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) IF FREQUENCY (GHz) 17172-059 -8 2 -4 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND -6 17172-056 INPUT IP3 (dBm) 6 Figure 57. Input IP3 vs. IF Frequency at Maximum Gain, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) 12 5 10 4 8 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 3 6 INPUT IP3 (dBm) 2 0 -2 -4 -10 -12 23 25 27 29 31 33 35 0 -1 -3 -4 37 RF FREQUENCY (GHz) 39 41 43 45 -5 -30 Figure 55. Input IP3 vs. RF Frequency at Maximum gain for Various LO Inputs, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) -29 -28 -27 -26 -25 -24 -23 INPUT POWER (dBm) -22 -21 -20 17172-060 -8 1 -2 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND -6 17172-057 INPUT IP3 (dBm) 2 4 Figure 58. Input IP3 vs. Input Power for Various RF Frequencies (fRF), at 20 MHz Spacing, fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) Rev. A | Page 18 of 42 Data Sheet ADMV1014 9 12 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND 8 7 NOISE FIGURE (dB) NOISE FIGURE (dB) 10 8 6 4 6 5 4 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 3 2 2 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 17172-061 Figure 59. Noise Figure vs. RF Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) IF FREQUENCY (GHz) Figure 62. Noise Figure vs. IF Frequency at Maximum Gain, fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) 22 12 +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz 20 10 18 NOISE FIGURE (dB) 6 4 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND 2 0 23 25 27 29 31 33 35 14 12 10 8 6 4 2 37 39 41 43 45 RF FREQUENCY (GHz) 0 17172-062 NOISE FIGURE (dB) 16 8 Figure 60. Noise Figure vs. RF Frequency at Maximum Gain for Various Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VATT (V) 17172-065 0 23 17172-064 1 Figure 63. Noise Figure vs. VATT at Various Temperatures, fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Upper Sideband) 22 12 +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz 20 18 NOISE FIGURE (dB) 16 8 6 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND 12 10 8 4 2 0 0 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 Figure 61. Noise Figure vs. RF Frequency at Maximum Gain for Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 0.2 0.4 0.6 0.8 1.0 VATT (V) 1.2 1.4 1.6 1.8 17172-066 2 0 23 14 6 4 17172-063 NOISE FIGURE (dB) 10 Figure 64. Noise Figure vs. VATT at Various Temperatures, fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Lower Sideband) Rev. A | Page 19 of 42 ADMV1014 Data Sheet 1 0 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND -2 -3 -6 INPUT P1dB (dBm) INPUT P1dB (dBm) -4 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND -1 -8 -10 -12 -14 -5 -7 -9 -11 -16 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 17172-067 IF FREQUENCY (GHz) Figure 65. Input P1dB vs. RF Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) Figure 68. Input P1dB vs. IF Frequency at Maximum Gain, fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) 0 2 -2 0 -2 INPUT P1dB (dBm) -6 -8 -10 -12 -14 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND -16 -18 -20 23 25 27 29 31 33 -4 -6 -8 -10 +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz -12 -14 35 37 39 41 43 45 RF FREQUENCY (GHz) -16 17172-068 INPUT P1dB (dBm) -4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VATT (V) 17172-071 -20 23 17172-070 -13 -18 Figure 69. Input P1dB vs. VATT at Various Temperatures, fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Upper Sideband) Figure 66. Input P1dB vs. RF Frequency at Maximum Gain for Various Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 2 0 0 -2 -2 -8 -10 -12 -14 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND -16 -18 -20 24 26 28 30 32 34 -4 -6 -8 -10 +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz -12 -14 -16 36 38 RF FREQUENCY (GHz) 40 42 44 Figure 67. Input P1dB vs. RF Frequency at Maximum Gain for Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) Rev. A | Page 20 of 42 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VATT (V) Figure 70. Input P1dB vs. VATT at Various Temperatures, fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Lower Sideband) 17172-072 INPUT P1dB (dBm) -6 17172-069 INPUT P1dB (dBm) -4 Data Sheet ADMV1014 60 60 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND 40 30 20 29 31 33 35 37 39 41 43 45 Figure 71. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband), Uncalibrated 27 29 31 33 35 37 39 41 43 45 RF INPUT FREQUENCY (GHz) Figure 74. Image Rejection vs. RF Input Frequency at Maximum Gain for Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND 40 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 50 IMAGE REJECTION (dBc) 30 20 40 30 20 27 29 31 33 35 37 39 41 43 45 RF INPUT FREQUENCY (GHz) 0 17172-074 25 Figure 72. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband), Calibrated 0 1 2 3 4 5 6 7 IF INPUT FREQUENCY (GHz) 17172-077 10 10 Figure 75. Image Rejection vs. IF Input Frequency at Maximum Gain, fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) 60 60 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND 40 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 50 IMAGE REJECTION (dBc) 50 30 20 10 40 30 20 25 27 29 31 33 35 37 39 RF INPUT FREQUENCY (GHz) 41 43 45 17172-075 10 Figure 73. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 0 0 0.2 0.4 0.6 0.8 1.0 VATT (V) 1.2 1.4 1.6 1.8 17172-078 IMAGE REJECTION (dBc) 25 60 50 IMAGE REJECTION (dBc) 20 0 23 60 0 23 30 17172-076 27 17172-073 25 RF INPUT FREQUENCY (GHz) 0 23 40 10 10 0 23 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND 50 IMAGE REJECTION (dBc) IMAGE REJECTION (dBc) 50 Figure 76. Image Rejection vs. VATT at Various RF Frequencies (fRF), fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) Rev. A | Page 21 of 42 Data Sheet 20 18 18 16 16 CONVERSION GAIN (dB) 20 14 12 10 8 6 0 1 3 7 15 2 10 8 27 29 31 33 35 37 39 41 43 45 Figure 77. Conversion Gain vs. RF Frequency at Different IF_AMP_COARSE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[11:8] and Register 0x09, Bits[15:12] Are the Same 0 23 4 3 3 2 2 INPUT IP3 (dBm) 4 0 -1 0 1 3 7 15 29 31 33 35 37 39 41 43 45 1 0 -1 4 5 6 7 0 1 2 3 -2 -3 -4 12 13 14 15 8 9 10 11 -4 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -5 23 17172-080 -5 23 27 Figure 80. Conversion Gain vs. RF Frequency at Different IF_AMP_ FINE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Register 0x08, Bits[7:4] and Bits[3:0] Are the Same 5 1 25 RF FREQUENCY (GHz) 5 -3 12 13 14 15 8 9 10 11 2 25 -2 4 5 6 7 0 1 2 3 6 4 RF FREQUENCY (GHz) INPUT IP3 (dBm) 12 Figure 78. Input IP3 vs. RF Frequency at Different IF_AMP_COARSE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[11:8] and Register 0x09, Bits[15:12] Are the Same 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 17172-083 0 23 14 17172-082 4 17172-079 CONVERSION GAIN (dB) ADMV1014 Figure 81. Input IP3 vs. RF Frequency at Different IF_AMP_FINE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[7:4] and Bits[3:0] Are the Same 10 10 9 9 8 NOISE FIGURE (dB) 6 5 4 3 0 1 3 7 15 1 0 23 25 7 6 5 4 0 1 2 3 3 2 4 5 6 7 8 9 10 11 12 13 14 15 1 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 0 23 25 27 29 31 33 35 37 RF FREQUENCY (GHz) Figure 79. Noise Figure vs. RF Frequency at Different IF_AMP_COARSE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[11:8] and Register 0x09, Bits[15:12] Are the Same 39 41 43 45 17172-084 2 17172-081 NOISE FIGURE (dB) 8 7 Figure 82. Noise Figure vs. RF Frequency at Different IF_AMP_FINE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[7:4] and Bits[3:0] Are the Same Rev. A | Page 22 of 42 Data Sheet ADMV1014 1.0 1.0 +85C +25C -40C 0.6 0.8 I/Q MAGNITUDE ERROR (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 0.2 0 -0.2 -0.4 -0.6 -0.8 0 1 2 3 4 5 6 7 IF OUTPUT FREQUENCY (GHz) -1.0 17172-085 -1.0 Figure 83. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain 0 5 4 4 3 3 1 0 -1 -2 +85C +25C -40C -3 2 3 4 5 6 7 Figure 85. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain 5 2 1 IF OUTPUT FREQUENCY (GHz) I/Q PHASE ERROR (dB) I/Q PHASE ERROR (dB) 0.4 17172-087 -0.8 +85C +25C -40C 0.6 2 1 0 -1 -2 +85C +25C -40C -3 -4 -4 0 1 2 3 4 5 IF OUTPUT FREQUENCY (GHz) 6 7 -5 17172-086 -5 Figure 84. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain 0 1 2 3 4 5 IF OUTPUT FREQUENCY (GHz) 6 7 17172-088 I/Q MAGNITUDE ERROR (dB) 0.8 Figure 86. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain Rev. A | Page 23 of 42 ADMV1014 Data Sheet OUTPUT DETECTOR PERFORMANCE RF amplitude = -30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set to 0x727C, Register 0x03, Bit 6 = 0, Register 0x03, Bits[13:12] set to 11, and TA = 25C, unless otherwise noted. 3.5 3.0 -22 -27 -32 3.0 2.5 VDET (V) VDET (V) 2.5 2.0 1.5 2.0 1.5 1.0 1.0 -35 -30 +25C = 64 +25C = 8 +25C = 0 -25 -40C = 64 -40C = 8 -40C = 0 -20 -15 -10 RF INPUT POWER (dBm) 0.5 23 25 27 29 31 33 35 37 39 41 43 45 RF INPUT FREQUENCY (GHz) Figure 87. VDET vs. RF Input Power, fRF = 28 GHz for Various Temperatures and DET_PROG Settings 17172-089 0 -40 +85C = 64 +85C = 8 +85C = 0 17172-090 0.5 Figure 89. VDET vs. RF Input Frequency at Various Input Power Levels, DET_PROG = 8 3.5 5 4 VDET LINEARITY ERROR (dB) 3.0 2.0 1.5 1.0 -35 -30 +25C = 64 +25C = 8 +25C = 0 -25 -40C = 64 -40C = 8 -40C = 0 -20 RF INPUT POWER (dBm) -15 2 1 0 -1 -2 -3 +85C = 64 +85C = 8 +85C = 0 +25C = 64 +25C = 8 +25C = 0 -40C = 64 -40C = 8 -40C = 0 -4 -10 -5 -40 Figure 88. VDET vs. RF Input Power, fRF = 39 GHz for Various Temperatures and DET_PROG Settings -35 -30 -25 -20 -15 -10 RF INPUT POWER (dBm) 17172-093 0 -40 +85C = 64 +85C = 8 +85C = 0 17172-091 0.5 3 Figure 90. VDET Linearity Error vs. RF Input Power, fRF = 28 GHz for Various Temperatures and DET_PROG Settings 5 VDET LINEARITY ERROR (dB) 4 3 2 1 0 -1 -2 -3 +85C = 64 +85C = 8 +85C = 0 +25C = 64 +25C = 8 +25C = 0 -40C = 64 -40C = 8 -40C = 0 -4 -5 -40 -35 -30 -25 -20 RF INPUT POWER (dBm) -15 -10 17172-094 VDET (V) 2.5 Figure 91. VDET Linearity Error vs. RF Input Power, fRF = 39 GHz for Various Temperatures and DET_PROG Settings Rev. A | Page 24 of 42 Data Sheet ADMV1014 RETURN LOSS AND ISOLATIONS RF amplitude = -30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set to 0x727C, Register 0x03, Bits[13:12] are set to 11, and TA = 25C, unless otherwise noted. Measurements in IF mode performed with a 90 hybrid, Register 0x03, Bit 11 = 0, Register 0x03, Bit 8 = 1, unless otherwise noted. Measurements in I/Q mode are measured as a composite of the I and Q channel performed, VCM = 1.15 V, Register 0x03, Bit 11 = 1, and Register 0x03, Bit 8 = 0, unless otherwise noted. I/Q DIFFERENTIAL RETURN LOSS (dB) 0 -10 -15 -20 -25 -35 23 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -20 -25 -30 2 3 4 5 6 7 I/Q FREQUENCY (GHz) 0 0 -5 -5 -10 -10 -15 -20 LON LOP LODIFF -25 1 0 IF RETURN LOSS (dB) -30 -15 -20 IF_I IF_Q -25 -30 4 5 6 7 8 9 10 11 12 LO FREQUENCY (GHz) -35 17172-096 -35 0 Figure 93. LO Return Loss vs. LO Frequency -50 4 5 6 7 LOx1 = 1.8 LOx1 = 0.9 LOx1 = 0 LOx4 = 1.8 LOx4 = 0.9 LOx4 = 0 -55 -60 LO TO IF LEAKAGE (dBm) -65 3 Figure 96. IF Return Loss vs. IF Frequency (Taken Without Hybrid) LOx1 = +85C LOx1 = +25C LOx1 = -40C LOx4 = +85C LOx4 = +25C LOx4 = -40C -60 2 IF FREQUENCY (GHz) -50 -55 1 17172-099 LO RETURN LOSS (dB) -15 Figure 95. I/Q Differential Return Loss vs. I/Q Frequency (Taken Without Hybrids or Baluns) Figure 92. RF Input Return Loss vs. RF Frequency LO TO RF LEAKAGE (dBm) -10 -35 17172-095 -30 -5 -70 -75 -80 -85 -90 -65 -70 -75 -80 -85 -90 -95 -100 4 5 6 7 8 9 10 LO INPUT FREQUENCY (GHz) 11 12 17172-097 -95 -100 Figure 94. LO to RF Leakage vs. LO Input Frequency for Various Temperatures at Different Gain Settings 4 5 6 7 8 9 10 LO INPUT FREQUENCY (GHz) 11 12 17172-100 RF RETURN LOSS (dB) -5 I Q 17172-098 0 Figure 97. LO to IF Leakage vs. LO Input Frequency at Different VCTRL Settings Rev. A | Page 25 of 42 ADMV1014 Data Sheet -30 I = +85C I = +25C I = -40C Q = +85C Q = +25C Q = -40C -45 -40 -50 -55 -60 -65 6 7 8 9 10 11 12 LO INPUT FREQUENCY (GHz) Figure 98. LO to IF Leakage vs. LO Input Frequency at Various Temperatures -65 -80 4 5 6 7 8 9 10 11 12 LO INPUT FREQUENCY (GHz) Figure 100. LO to IF Leakage, vs. LO Input Frequency at Different IF Amplifier Gain Settings (Taken Without Hybrid) -40 -50 -55 -60 -65 -70 -75 -80 -85 -90 4 6 Q_P = +85C Q_P = +25C Q_P = -40C Q_N = +85C Q_N = +25C Q_N = -40C 8 10 LO INPUT FREQUENCY (GHz) 12 Figure 99. LO to I/Q Leakage vs. LO Input Frequency at Various Temperatures (Taken Without Hybrid) -50 -55 -60 -65 -70 -75 I_P = 0 I_P = 3 I_N = 0 I_N = 3 -80 -85 Q_P = 0 Q_P = 3 Q_N = 0 Q_N = 3 -90 17172-102 I_P = +85C I_P = +25C I_P = -40C I_N = +85C I_N = +25C I_N = -40C -45 4 5 6 7 8 9 10 LO INPUT FREQUENCY (GHz) 11 12 17172-104 FUNDAMENTAL LO TO I/Q LEAKAGE (dBm) -40 -45 LO TO I/Q LEAKAGE (dBm) -60 -75 5 =0 =1 =3 =7 = 15 -55 -75 4 Q Q Q Q Q -50 -70 -80 =0 =1 =3 =7 = 15 -45 -70 17172-101 LO TO IF LEAKAGE (dBm) -40 I I I I I -35 LO TO IF LEAKAGE (dBm) -35 17172-103 -30 Figure 101. Fundamental LO to I/Q Leakage vs. LO Input Frequency at Different Baseband Amplifier Gain Settings Rev. A | Page 26 of 42 Data Sheet ADMV1014 M x N SPURIOUS PERFORMANCE IF Mode Mixer spurious products are measured in dBc from the IF output power level. Spurious values are measured using the following equation: Measurements are made on the IF_I port. Data is taken without any 90 hybrid. IF frequency (fIF) = 3.5 GHz, LO= 6.125 GHz at 0 dBm, and fRF = 28 GHz at -30 dBm. |(M x RF)+ (N x LO)| N/A means not applicable. Blank cells in the spurious performance tables indicate that the frequency is above 50 GHz and is not measured. The LO frequencies are referred from the frequencies applied to the LO_x pin of the ADMV1014. RF amplitude = -30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_ IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set to 0x727C, Register 0x03, Bits[13:12] are set to 11, and TA = 25C, unless otherwise noted. 0 M x RF M x RF I/Q Mode Measurements are made on the I_P port. Data is taken without any hybrids or baluns. 0 M x RF -2 -1 0 +1 61 N/A 61 1 85 90 43 91 2 87 54 55 80 3 87 46 65 82 7 96 106 81 8 59 82 M x RF -2 -1 0 +1 0 1 2 63 N/A 42 92 42 48 56 48 M x RF 5 87 51 85 6 92 61 7 87 85 5 93 44 71 6 99 46 64 7 96 92 80 8 78 58 1 2 62 N/A 62 93 47 89 81 68 N x LO 4 84 71 0 75 50 3 5 92 39 75 6 91 91 7 93 92 8 59 89 -2 -1 0 +1 70 N/A 70 1 90 93 47 90 2 86 70 62 88 3 83 41 66 N x LO 4 95 0 49 5 94 65 74 6 83 90 86 7 89 89 8 58 83 fIF = 3.5 GHz, LO= 10.5 GHz at 0 dBm, and fRF =39 GHz at -30 dBm fBB = 100 MHz, LO= 9.725 GHz at 0 dBm, and fRF = 39 GHz at -30 dBm. N x LO 3 4 85 88 47 0 67 51 -2 -1 0 +1 0 0 M x RF 6 103 52 78 2 93 89 43 84 fIF = 3.5 GHz, LO= 7.875 GHz at 0 dBm, and fRF = 28 GHz at -30 dBm. BB frequency (fBB) =100 MHz, LO= 6.975 GHz at 0 dBm, and fRF = 28 GHz at -30 dBm. N x LO 4 5 82 86 0 45 48 76 66 N/A 66 1 81 94 45 84 fIF = 3.5 GHz, LO= 8.875 GHz at 0 dBm, and fRF = 39 GHz at -30 dBm. Measurements in IF mode performed with Register 0x03, Bit 11 = 0 and Register 0x03, Bit 8 = 1, unless otherwise noted. The measurements in I/Q mode are as follows: VCM = 1.15 V, Register 0x03, Bit 11 = 1, and Register 0x03, Bit 8 = 0, unless otherwise noted. -2 -1 0 +1 N x LO 3 4 85 93 63 0 65 54 81 8 60 84 Rev. A | Page 27 of 42 -2 -1 0 +1 0 1 2 61 N/A 61 91 39 89 81 51 3 85 35 62 N x LO 4 5 87 94 0 87 53 6 94 84 7 90 84 8 58 82 ADMV1014 Data Sheet THEORY OF OPERATION The ADMV1014 is a wideband microwave downconverter optimized for microwave radio designs operating in the 24 GHz to 44 GHz frequency range. See Figure 1 for a functional block diagram of the device. The ADMV1014 digital settings are controlled via the SPI. The ADMV1014 has two modes of operation: Baseband quadrature demodulation (I/Q mode) Image reject I/Q downconversion (IF mode) START-UP SEQUENCE The ADMV1014 SPI settings require its default settings to be changed during startup for optimum performance. To use the SPI, toggle the RST pin to logic low and then logic high to perform a hard reset before starting up the device. Set Register 0x0B to 0x727C after every power-up or reset. Set Register 0x03, Bits[13:12] to 11 after every power-up or reset. BASEBAND QUADRATURE DEMODULATION (I/Q MODE) In I/Q mode, the output impedance of the baseband I/Q ports is 100 differential. These outputs are designed to be loaded to a dc-coupled, differential, 100 load. I_P and I_N are the differential baseband I outputs. Q_P and Q_N are the differential baseband Q outputs. To set the ADMV1014 in I/Q mode, set BB_AMP_PD (Register 0x03, Bit 8) to 0 and set IF_AMP_PD (Register 0x03, Bit 11) to 1. The baseband I/Q ports are designed to operate from dc to 6.0 GHz at each I and Q channel. The BB output VCM can be changed from 1.05 V to 1.85 V. To change the VCM, set BB_SWITCH_HIGH_LOW_COMMMON (Register 0x0A, Bit 0) to be the opposite of Register 0x0A, Bit 6. Also, set the MIXER_VGATE bit field (Register 0x07, Bits[15:9]) and the BB_AMP_REF_GEN bit field (Register 0x0A, Bits[6:3]) based on Table 6. Table 6 provides the correct setting for these bit fields vs. the required common-mode voltage. The VCM can be further adjusted on each I or Q channel by 15 mV by setting the BB_AMP_OFFSET_I bit field (Register 0x09, Bits[4:0]) and the BB_AMP_OFFSET_Q bit field (Register 0x09, Bits[9:5]) for each VCM setting shown in Table 6. The most significant bit (MSB) for each bit field is the sign bit. When the MSB is 1, the values of the four lower bits are positive. When the MSB is 0, the values of the four lower bits are negative. These bits also offer input IP2 and common-mode rejection optimization. The BB I/Q section of the ADMV1014 also features a baseband amplifier with a digital attenuator that is controlled by setting the BB_AMP_GAIN_CTRL bit field (Register 0x0A, Bits[2:1]). Figure 44, Figure 45, and Figure 46 show the performance of the baseband digital attenuator. The Baseband Quadrature Demodulation to Very Low Frequencies section shows the baseband performance to very low demodulation frequencies. Table 6. Common-Mode Voltage Settings VCM (V) 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 MIXER_VGATE (Register 0x07, Bits[15:9]) 1101010 1101011 1101100 1101110 1101111 1110000 1110001 1110010 1110101 1110110 1110111 1111000 1111010 1111011 0101100 0101101 BB_AMP_REF_GEN (Register 0x0A, Bits[6:3]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Rev. A | Page 28 of 42 BB_SWITCH_HIGH_LOW_COMMON_MODE (Register 0x0A, Bit 0) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Data Sheet ADMV1014 IMAGE REJECTION DOWNCONVERSION The ADMV1014 features the ability to downconvert to a real IF output anywhere from 800 MHz to 6000 MHz, while suppressing the unwanted image sideband by typically better than 30 dBc. The IF outputs are quadrature to each other, 50 single-ended, and are internally ac coupled. IF_I and IF_Q are the quadrature IF outputs. An external 90 hybrid is required to select the appropriate sideband. path can switch from differential to single-ended operation by setting the QUAD_SE_MODE bits (Register 0x04, Bits[9:6]). See the Performance Between Differential vs. Single-Ended LO Input section for more information. Figure 102 shows a block diagram of the LO path. To configure the ADMV1014 in IF mode, set BB_AMP_PD (Register 0x03, Bit 8) to 1 and set IF_AMP_PD (Register 0x03, Bit 11) to 0 DETECTOR The ADMV1014 features a square law detector that produces a voltage linearly, according to the square of the RF voltage output from the low noise amplifier. The detector can be enabled by setting the DET_EN bit (Register 0x03, Bit 6) to 0. The detector can be turned off by setting this bit to 1. The detector linear range can be adjusted by setting the DET_PROG bit field (Register 0x07, Bits[6:0]). These ranges are specified based on the input power into the detector coming from the output of the low noise amplifier. Each DET_PROG setting offers an approximate 20 dB of 1 dB dynamic range based on a twopoint linear regression from an ideal line for one temperature at each DET_PROG setting. See Figure 89 to Figure 91 for more performance information of the detector. LO INPUT PATH The LO input path operates from 5.4 GHz to 10.25 GHz with an LO amplitude range of -6 dBm to +6 dBm. The LO has an internal quadrupler (x4) and a programmable band-pass filter. The LO band-pass filter is programmable using QUAD_FILTERS (Register 0x04 Bits[3:0]). See the Performance at Different Quad Filter Settings section for more information on the QUAD_FILTERS settings. The LO path can operate either differentially or single-ended (SE). LOIP and LOIN are the inputs to the LO path. The LO AMP LO_P x4 4 x LO_N 4 x LO_P 17172-105 Each IF output features an amplifier with a digital attenuator. The digital attenuator can be adjusted using fine or coarse steps. The coarse steps for the IF_I can be adjusted using the IF_AMP_ COARSE_GAIN_I bit field (Register 0x08, Bits[11:8]). The coarse steps for the IF_Q can be adjusted using the IF_AMP_COARSE_ GAIN_Q bit field (Register 0x09, Bits[15:12]). Each course gain bit field has five settings. The fine steps for IF_I can be adjusted using the IF_AMP_FINE_GAIN_I bit field (Register 0x08, Bits[3:0]). The fine steps for the IF_Q can be adjusted using the IF_AMP_FINE_GAIN_Q bit field (Register 0x08, Bits[7:4]). Figure 77 to Figure 82 show the performance of these four bit fields. LO_N Figure 102. LO Path Block Diagram Enable the quadrupler by setting the QUAD_IBIAS_PD bit (Register 0x03, Bit 7) to 0 and the QUAD_BG_PD bit (Register 0x03, Bit 9) to 0. To power down the quadrupler, set both of these bits to 1. An unwanted image can be downconverted from the quadrature error in generating the quadrature LO signals. Deviation from ideal quadrature (that is, total image rejection and no image tone is downconverted) on these signals limits the amount of achievable image rejection. The ADMV1014 offers about 25 of quadrature phase adjustment in the LO path quadrature signals. Make these adjustments through the LOAMP_PH_ADJ_I_FINE bits (Register 0x05, Bits[15:9]) and the LOAMP_PH_ADJ_Q_FINE (Register 0x05, Bits[8:2]) bits. These bits reject the unwanted sideband signal. In IF mode amplitude adjustments can be made to the complex outputs via IF_AMP_FINE_GAIN_Q (Register 0x08, Bits[7:4]) and IF_AMP_FINE_GAIN_I (Register 0x08, Bits[3:0]) to further reduce the unwanted sideband. POWER-DOWN The SPI of the ADMV1014 allows the user to power down device circuits and reduce power consumption. There are two power-down modes: band gap power-down mode (BG_PD) and individual power-down circuits mode. The BG_PD bit (Register 0x03, Bit 5) and the QUAD_BG_PD bit (Register 0x03, Bit 9) power down the band gap circuit. The QUAD_IBIAS_PD bit (Register 0x03, Bit 7) and the IBIAS_PD bit (Register 0x03, Bit 14) power down the specific circuits. Table 7 shows the circuits that are controlled by their related power-down bit, the typical power savings, and the latency requirement to power the circuits back up. Rev. A | Page 29 of 42 ADMV1014 Data Sheet Table 7. Power-Down Power and Latency Requirements Bit Name IBIAS_PD QUAD_IBIAS_PD BG_PD and QUAD_BG_PD IBIAS_PD, IF_AMP_PD, QUAD_BG_PD, BB_AMP_PD, QUAD_IBIAS_PD, BG_PD Typical Power Savings (mW) 1172 238 1423 1435 Circuit Receiver bias current (IBIAS) LO path Band gap Entire chip Power-Up Latency (s) 5 4 4.5 5 Power-Down Latency (s) <1 <1 <1 <1 SEN 1 2 3 4 5 6 7 8 9 D15 D14 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDI R/W A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 17172-107 SCLK Figure 103. Write Serial Port Timing Diagram SEN 1 2 3 4 5 6 7 8 9 D15 D14 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK R/W A5 A4 A3 A2 A1 SDO A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 17172-108 SDI Figure 104. Read Serial Port Timing Diagram Sideband. The ADMV1014 input logic level for the write cycle supports an 1.8 V interface. SERIAL PORT INTERFACE (SPI) The SPI of the ADMV1014 allows the user to configure the device for specific functions or operations via a 4-pin SPI port. This interface provides users with added flexibility and customization. The SPI consists of four control lines: SCLK, SDIN, SDO, and SEN. The ADMV1014 protocol consists of a write/read bit followed by six register address bits, 16 data bits, and a parity bit. Both the address and data fields are organized most significant bit (MSB) first and end with the least significant bit. For a write, set the first bit to 0. For a read, set the first bit to 1. The write cycle sampling must be performed on the rising edge. The 16 bits of the serial write data are shifted in, MSB to Lower For a read cycle, up to 16 bits of serial read data are shifted out, MSB first. After the 16 bits of data shift out, the parity bit shifts out. The output logic level for a read cycle is 1.8 V. The parity bit always follows the direction of the data. If parity is not used, the transmitting end transmits zero instead of parity. The parity is odd, which means that the total number of ones transmitted during a command, including the read/write bit, the address bit, the data bit, and the parity bit, must be odd. Figure 103 and Figure 104 show the SPI write and read protocol, respectively. Rev. A | Page 30 of 42 Data Sheet ADMV1014 APPLICATIONS INFORMATION ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE 1.8 Figure 105 shows the EVM vs. input power performance of the ADMV1014 in IF mode at maximum gain, upper sideband, 25C and 0 dBm LO input power. The EVM measurement was performed using four 100 MHz, 5G-NR, 256QAM waveforms. The EVM shown is the average of the four channels. The EVM of the test equipment was not de-embedded. 1.4 1.6 Figure 106 shows the constellation diagram and EVM statistics of each of the four channels at -30 dBm input power. 1.0 0.8 0.6 0.4 0.2 0 -45 -40 -35 -30 -25 -20 -15 PIN (dBm) 17172-110 Figure 105. EVM vs. Input Power at 28 GHz, VCTRL = 0 V, TA = 25C, LO = 0 dBm, Upper Sideband (Low-Side LO), IF = 3.5 GHz Figure 106. Constellation Diagram and EVM Statistics per Channel Rev. A | Page 31 of 42 17172-109 EVM (%) 1.2 ADMV1014 Data Sheet 50 Figure 107 to Figure 111 show the I/Q mode performance at low baseband frequencies. The measurements were performed at 28 GHz, -25 dBm input power, VCM = 1.15 V, Register 0x03, Bit 11 = 1, Register 0x03, Bit 8 = 0, 6 dBm LO input power, and TA = 25C. 40 350 IMAGE REJECTION (dBc) 45 30 25 20 15 IMAGE REJECT 5 0 1 10 100 200 1k 10k 100k 1M 10M 100M BASEBAND FREQUENCY (Hz) Figure 110. Image Rejection vs. Baseband Frequency Q DIFFERENTIAL I DIFFERENTIAL 150 17172-114 250 350 100 0 10 100 1k 10k 100k 1M 10M 100M BASEBAND FREQUENCY (Hz) Figure 107. I and Q Differential Peak-to-Peak Voltage vs. Baseband Frequency 20 18 DC OFFSET ERROR (mV) 300 50 1 250 200 Q DIFFERENTIAL I DIFFERENTIAL 150 100 14 0 1 12 10 100 1k 10k 100k 1M 10M 100M BASEBAND FREQUENCY (Hz) 10 17172-111 50 16 CONVERSION GAIN (dB) 35 10 300 17172-111 I AND Q DIFFERENTIAL PEAK-TO-PEAK VOLTAGE BASEBAND QUADRATURE DEMODULATION TO VERY LOW FREQUENCIES Figure 111. DC Offset Error vs. Baseband Frequency 8 Q GAIN I GAIN PERFORMANCE AT DIFFERENT QUAD FILTER SETTINGS 7 6 0 1 10 100 1k 10k 100k 1M 10M 100M BASEBAND FREQUENCY (Hz) 17172-112 5 Figure 108. Conversion Gain vs. Baseband Frequency Figure 112 shows the conversion gain vs. RF frequency in IF mode at 25C and LO input power = 6 dBm, for different QUAD_FILTERS settings. Figure 113 shows the LO to IF_I and LO to IF_Q leakage vs. LO frequency at different quad filter settings. 25 5 4 15 CONVERSION GAIN (dB) AMPLITUDE IMBALANCE (dB)/ PHASE IMBALANCE (Degrees) 20 AMPLITUDE IMBALANCE PHASE IMBALANCE 3 2 10 5 0 -5 -10 QUAD_FILTERS = 0 QUAD_FILTERS = 5 QUAD_FILTERS = 10 QUAD_FILTERS = 15 -15 -20 1 1 10 100 1k 10k 100k 1M BASEBAND FREQUENCY (Hz) 10M 100M Figure 109. Amplitude Imbalance and Phase Imbalance vs. Baseband Frequency Rev. A | Page 32 of 42 -30 23 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) Figure 112. Conversion Gain vs. RF Frequency for Four Different QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband) 17172-116 0 17172-113 -25 Data Sheet ADMV1014 -40 IF IF IF IF PERFORMANCE BETWEEN DIFFERENTIAL vs. SINGLE-ENDED LO INPUT I: QUAD_FILTERS = 0 I: QUAD_FILTERS = 5 I: QUAD_FILTERS = 10 I: QUAD_FILTERS = 15 Figure 115 to Figure 117 show the conversion gain, input IP3 and image rejection performance for operating the ADMV1014 LO input as differential vs. SE. The measurements were performed with 0 dBm LO input power, IF mode, with an IF frequency of 3.5 GHz, upper sideband, and TA = 25C. -50 -55 -60 -65 25 -70 Q: QUAD_FILTERS = 0 Q: QUAD_FILTERS = 5 Q: QUAD_FILTERS = 10 Q: QUAD_FILTERS = 15 20 4 5 6 7 8 9 10 11 12 LO FREQUENCY (GHz) Figure 113. LO To IF Leakage vs. RF Frequency for Four Different QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband) VVA TEMPERATURE COMPENSATION Figure 114 shows the conversion gain vs. RF frequency at two different Register 0x0B settings and three different temperatures for IF mode. The recommended value suggested in the Start-Up Sequence section provides the highest conversion gain. If the priority is to decrease the conversion gain variation across temperature, Register 0x0B can be set to 0x726C. However, at this value, the conversion gain is lower at each temperature. 15 10 LO DIFF LO SE P SIDE LO SE N SIDE 5 0 23 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 17172-119 -80 CONVERSION GAIN (dB) IF IF IF IF -75 17172-117 LO TO IF LEAKAGE (dBm) -45 Figure 115. Conversion Gain vs. RF Frequency for Three Different LO Mode Settings, fIF = 3.5 GHz (Upper Sideband) 10 25 8 6 20 INPUT IP3 (dBm) 10 5 -10 23 0 -2 -8 -10 23 25 27 29 31 33 35 LO DIFF LO SE P SIDE LO SE N SIDE -6 37 RF FREQUENCY (GHz) 39 41 43 45 Figure 114. Conversion Gain vs. RF Frequency at Maximum Gain for Various Register 0x0B Settings and Various Temperatures 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 17172-120 -5 2 -4 +85C AT REG 0x0B = 0x727C +25C AT REG 0x0B = 0x727C -40C AT REG 0x0B = 0x727C +85C AT REG 0x0B = 0x726C +25C AT REG 0x0B = 0x726C -40C AT REG 0x0B = 0x726C 0 17172-118 CONVERSION GAIN (dB) 4 15 Figure 116. Input IP3 vs. RF Frequency for Three Different LO Mode Settings, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband) Rev. A | Page 33 of 42 ADMV1014 Data Sheet 40 30 20 35 15 10 LO DIFF LO SE P SIDE LO SE N SIDE 5 0 24 -20 -30 -40 -50 -60 26 28 30 32 34 36 38 40 42 44 RF INPUT FREQUENCY (GHz) Figure 117. Image Rejection vs. RF Input Frequency for Three Different LO Mode Settings, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband) -70 23 Figure 118 and Figure 119 show the conversion gain vs. RF frequency in IF mode for fixed IF frequencies (TA = 25C, LO = 6 dBm) for upper sideband and lower sideband, respectively. Figure 120 and Figure 121 show the conversion gain vs. RF frequency in IQ mode for fixed BB frequencies (TA = 25C, LO = 6 dBm) for upper sideband and lower sideband, respectively. 25 25 27 29 31 33 35 37 39 41 43 45 Figure 119. Conversion Gain vs. RF Frequency at Multiple IF Frequency Settings (Lower Sideband) 25 20 15 CONVERSION GAIN (dB) The ADMV1014 quadrupler operates from 21.6 GHz to 41 GHz. When using high-side LO injection, the conversion gain starts rolling off gradually after the quadrupler frequency reaches 41 GHz. When using low-side LO, the conversion gain starts rolling off when the quadrupler frequency is 21.6 GHz. 0.8GHz LOWER SIDEBAND 1.0GHz LOWER SIDEBAND 2.0GHz LOWER SIDEBAND 3.0GHz LOWER SIDEBAND 4.0GHz LOWER SIDEBAND 5.0GHz LOWER SIDEBAND 6.0GHz LOWER SIDEBAND RF FREQUENCY (GHz) PERFORMANCE ACROSS RF FREQUENCY AT FIXED IF AND BASEBAND FREQUENCIES 10 5 0 -5 -10 0.8GHz UPPER SIDEBAND 1.0GHz UPPER SIDEBAND 2.0GHz UPPER SIDEBAND 3.0GHz UPPER SIDEBAND 4.0GHz UPPER SIDEBAND 5.0GHz UPPER SIDEBAND 6.0GHz UPPER SIDEBAND -15 -20 -25 -30 23 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) Figure 120. Conversion Gain vs. RF Frequency at Multiple I/Q Frequency Settings (Upper Sideband) 20 30 15 20 10 10 0 -5 0.8GHz UPPER SIDEBAND 1.0GHz UPPER SIDEBAND 2.0GHz UPPER SIDEBAND 3.0GHz UPPER SIDEBAND 4.0GHz UPPER SIDEBAND 5.0GHz UPPER SIDEBAND 6.0GHz UPPER SIDEBAND -10 -15 -20 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 -20 -30 -50 17172-122 25 -10 -40 -25 -30 23 0 Figure 118. Conversion Gain vs. RF Frequency for Multiple IF Frequency Settings (Upper Sideband) -60 23 0.8GHz LOWER SIDEBAND 1.0GHz LOWER SIDEBAND 2.0GHz LOWER SIDEBAND 3.0GHz LOWER SIDEBAND 4.0GHz LOWER SIDEBAND 5.0GHz LOWER SIDEBAND 6.0GHz LOWER SIDEBAND 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 17172-125 5 CONVERSION GAIN (dB) CONVERSION GAIN (dB) -10 17172-124 20 0 17172-123 CONVERSION GAIN (dB) 25 17172-121 IMAGE REJECTION (dBc) 10 30 Figure 121. Conversion Gain vs. RF Frequency at Multiple IQ Frequency Settings (Lower Sideband) Rev. A | Page 34 of 42 Data Sheet ADMV1014 EVALUATION BOARD INFORMATION Solder the exposed pad on the underside of the ADMV1014 to a low thermal and electrical impedance ground plane. This pad is typically soldered to an exposed opening in the solder mask on the evaluation board. Connect these ground vias to all other ground layers on the evaluation board to maximize heat dissipation from the device package. For more information about the ADMV1014 evaluation board, refer to the ADMV1014-EVALZ user guide. 17172-126 RECOMMENDED LAND PATTERN Figure 122. Evaluation Board Layout for the LGA package Rev. A | Page 35 of 42 ADMV1014 Data Sheet REGISTER SUMMARY Table 8. Register Summary Reg. 0x00 Name SPI_CONTROL Bits [15:8] 0x01 ALARM [7:0] [15:8] 0x02 [7:0] ALARM_MASKS [15:8] 0x03 ENABLE [7:0] [15:8] [7:0] 0x04 QUAD 0x05 LO_AMP_ PHASE_ ADJUST1 0x07 MIXER 0x08 IF_AMP 0x09 IF_AMP_BB_ AMP 0x0A BB_AMP__AGC 0x0B VVA_TEMP_ COMP [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 15 Bit 7 PARITY_EN PARITY_ ERROR PARITY_ ERROR_MASK RESERVED QUAD_IBIAS_ PD Bit 14 Bit 13 Bit 12 Bit 11 Bit 6 Bit 5 Bit 4 Bit 3 RESERVED SPI_SOFT_ RESET CHIP_ID[3:0] TOO_FEW_ TOO_MANY_ ADDRESS ERRORS ERRORS _RANGE_ ERROR RESERVED TOO_ TOO_MANY_ ADDRESS FEW_ ERRORS_ _RANGE_ ERRORS_ MASK ERROR_ MASK MASK RESERVED IBIAS_PD P1DB_COMPENSATION IF_AMP_ PD DET_EN BG_PD Bit 10 Bit 2 REVISION RESERVED 0x0000 R RESERVED 0xFFFF R/W BB_AMP_ PD 0x0157 R/W QUAD_SE_MODE[3:2] QUAD_FILTERS LOAMP_ PH_ADJ_ Q_FINE[6] RESERVED RESERVED 0x5700 R/W 0x4101 R/W 0xD808 R/W 0x0000 R/W 0x0000 R/W 0x2390 R/W 0x4A5C R/W QUAD_ BG_PD DET_PROG RESERVED IF_AMP_FINE_GAIN_Q IF_AMP_COARSE_GAIN_Q BB_AMP_OFFSET_Q[2:0] RESERVED R/W R/W RESERVED LOAMP_PH_ADJ_Q_FINE[5:0] MIXER_VGATE RESERVED Bit 8 Bit 0 Reset 0x0093 RESERVED RESERVED RESERVED LOAMP_PH_ADJ_I_FINE QUAD_SE_MODE[1:0] Bit 9 Bit 1 CHIP_ID[7:4] IF_AMP_COARSE_GAIN_I IF_AMP_FINE_GAIN_I RESERVED BB_AMP_OFFSET_Q[4:3] BB_AMP_OFFSET_I RESERVED BB_AMP_REF_GEN BB_AMP_GAIN_CTRL [15:8] VVA_TEMPERATURE_COMPENSATION[15:8] [7:0] VVA_TEMPERATURE_COMPENSATION[7:0] Rev. A | Page 36 of 42 BB_ SWITCH_ HIGH_ LOW_ COMMON_ MODE Data Sheet ADMV1014 REGISTER DETAILS Address: 0x00, Reset: 0x0093, Name: SPI_CONTROL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 [15] PARITY_EN (R/W) Enable the Parity for Write Execution [3:0] REVISION (R) Revis ion ID [14] SPI_SOFT_RESET (R/W) SPI Soft Reset [11:4] CHIP_ID (R) Chip ID [13:12] RESERVED Table 9. Bit Descriptions for SPI_CONTROL Bits 15 14 [13:12] [11:4] [3:0] Bit Name PARITY_EN SPI_SOFT_RESET RESERVED CHIP_ID REVISION Settings Description Enable the Parity for Write Execution SPI Soft Reset Reserved Chip ID Revision ID Reset 0x0 0x0 0x0 0x9 0x3 Access R/W R/W R R R Address: 0x01, Reset: 0x0000, Name: ALARM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15] PARITY_ERROR (R) Parity Error [11:0] RESERVED [12] ADDRESS_RANGE_ERROR (R) Address Range Error [14] TOO_FEW_ERRORS (R) Too Few Errors [13] TOO_MANY_ERRORS (R) Too_Many_Errors Table 10. Bit Descriptions for ALARM Bits 15 14 13 12 [11:0] Bit Name PARITY_ERROR TOO_FEW_ERRORS TOO_MANY_ERRORS ADDRESS_RANGE_ERROR RESERVED Settings Description Parity Error Too Few Errors Too Many Errors Address Range Error Reserved Reset 0x0 0x0 0x0 0x0 0x0 Access R R R R R Reset 0x1 0x1 0x1 0x1 0xFFF Access R/W R/W R/W R/W R Address: 0x02, Reset: 0xFFFF, Name: ALARM_MASKS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 [15] PARITY_ERROR_MASK (R/W) Parity Error Mas k [11:0] RESERVED [12] ADDRESS_RANGE_ERROR_MASK (R/W) Address Range Error Mask [14] TOO_FEW_ERRORS_MASK (R/W) Too Few Errors Mask [13] TOO_MANY_ERRORS_MASK (R/W) Too Many Errors Mas k Table 11. Bit Descriptions for ALARM_MASKS Bits 15 14 13 12 [11:0] Bit Name PARITY_ERROR_MASK TOO_FEW_ERRORS_MASK TOO_MANY_ERRORS_MASK ADDRESS_RANGE_ERROR_MASK RESERVED Settings Description Parity Error Mask Too Few Errors Mask Too Many Errors Mask Address Range Error Mask Reserved Rev. A | Page 37 of 42 ADMV1014 Data Sheet Address: 0x03, Reset: 0x0157, Name: ENABLE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 [15] RESERVED [4:0] RESERVED [14] IBIAS_PD (R/W) Power Down the RX Ibias [5] BG_PD (R/W) Power Down the RX BG [13:12] P1DB_COMPENSATION (R/W) Turn on bits to optim ize P1dB [6] DET_EN (R/W) Digital RX Detector Enable [11] IF_AMP_PD (R/W) Power Down the IF Am p [7] QUAD_IBIAS_PD (R/W) Power Down the Quadrupler Bias Current. [10] RESERVED [8] BB_AMP_PD (R/W) Power Down the Base-Band Am p [9] QUAD_BG_PD (R/W) Power Down the Quadrupler BandGap Table 12. Bit Descriptions for ENABLE Bits 15 14 [13:12] 11 10 9 8 7 6 5 [4:0] Bit Name RESERVED IBIAS_PD P1DB_COMPENSATION IF_AMP_PD RESERVED QUAD_BG_PD BB_AMP_PD QUAD_IBIAS_PD DET_EN BG_PD RESERVED Settings Description Reserved Power Down the Rx IBIAS Turn on bits to optimize P1dB Power Down the IF Amp Reserved Power Down the Quadrupler Band Gap Power Down the Baseband Amp Power Down the Quadrupler Bias Current Digital Rx Detector Enable Power Down the Rx BG Reserved Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x0 0x1 Access R R/W R/W R/W R R/W R/W R/W R/W R/W R Address: 0x04, Reset: 0x5700, Name: QUAD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 [15:10] RESERVED [3:0] QUAD_FILTERS (R/W) LO Filters BW Selection 0000: LO Frequency BW: 8.625 to 10.25GHz. 0101: LO Frequency BW: 6.6 to 9.2GHz. 1010: LO Frequency BW: 5.4 to 8GHz. 1111: LO Frequency BW: 5.4 to 7GHz. [9:6] QUAD_SE_MODE (R/W) Switch Differential/SE Modes 0110: SE_Mode_N_Side. 1001: SE_Mode_P_Side. 1100: Differential Mode. [5:4] RESERVED Table 13. Bit Descriptions for QUAD Bits [15:10] [9:6] Bit Name RESERVED QUAD_SE_MODE Settings 0110 1001 1100 [5:4] [3:0] RESERVED QUAD_FILTERS 0000 0101 1010 1111 Description Reserved Switch Differential/SE Modes SE Mode N Side SE Mode P Side Differential Mode Reserved. LO Filters BW Selection LO Frequency BW: 8.625 GHz to 10.25 GHz LO Frequency BW: 6.6 GHz to 9.2 GHz LO Frequency BW: 5.4 GHz to 8 GHz LO Frequency BW: 5.4 GHz to 7 GHz Rev. A | Page 38 of 42 Reset 0x15 0xC Access R R/W 0x0 0x0 R R/W Data Sheet ADMV1014 Address: 0x05, Reset: 0x4101, Name: LO_AMP_PHASE_ADJUST1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 [15:9] LOAMP_PH_ADJ_I_FINE (R/W) Mixer Im age Rejection Calibration 0x00:Maximum Phase, 0x7F: Minim um Phase [1:0] RESERVED [8:2] LOAMP_PH_ADJ_Q_FINE (R/W) Mixer Im age Rejection Calibration 0x00:Maximum Phase, 0x7F: Minim um Phase Table 14. Bit Descriptions for LO_AMP_PHASE_ADJUST1 Bits [15:9] Bit Name LOAMP_PH_ADJ_I_FINE [8:2] LOAMP_PH_ADJ_Q_FINE [1:0] RESERVED Settings Description Mixer Image Rejection Calibration 0x00: Maximum Phase, 0x7F: Minimum Phase Mixer Image Rejection Calibration 0x0: Maximum Phase, 0x7F: Minimum Phase Reserved. Reset 0x20 Access R/W 0x40 R/W 0x1 R Reset 0x6C Access R/W 0x0 0x8 R R/W Address: 0x07, Reset: 0xD808, Name: MIXER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 [15:9] MIXER_VGATE (R/W) Control BB Comm on Mode Voltage (Please see the application section for more Inform ation) [6:0] DET_PROG (R/W) Digital RX Detector Program 0: From -12 to +4dBm . 1: From -13 to +3dBm . 10: From -14 to +2dBm . 100: From -15 to +1dBm . 1000: From -15.5 to +0.5dBm. 10000: From -16.25 to -0.25dBm . 100000: From -17 to -1dBm . 1000000: From -18 to -2dBm . [8:7] RESERVED Table 15. Bit Descriptions for MIXER Bits [15:9] Bit Name MIXER_VGATE [8:7] [6:0] RESERVED DET_PROG Settings 0 1 10 100 1000 10000 100000 1000000 Description Control BB Common Mode Voltage. See the Applications Information section for more information) Reserved. Digital Rx Detector Program. From -12 dBm to +4 dBm. From -13 dBm to +3 dBm. From -14 dBm to +2 dBm. From -15 dBm to +1 dBm. From -15.5 dBm to +0.5 dBm. From -16.25 dBm to -0.25 dBm. From -17 dBm to -1 dBm. From -18 dBm to -2 dBm. Rev. A | Page 39 of 42 ADMV1014 Data Sheet Address: 0x08, Reset: 0x0000, Name: IF_AMP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:12] RESERVED [3:0] IF_AMP_FINE_GAIN_I (R/W) IF Amp I, 10 Fine Steps from 0x0 to 0xA (Total attenuation ~1dB). Refer to Figure 80 to Figure 82. [11:8] IF_AMP_COARSE_GAIN_I (R/W) Digital IF Am p 1dB Step Gain_I 0: Refer to Figure 77 to Figure 79. 1: Refer to Figure 77 to Figure 79. 11: Refer to Figure 77 to Figure 79. 111: Refer to Figure 77 to Figure 79. 1111: Refer to Figure 77 to Figure 79. [7:4] IF_AMP_FINE_GAIN_Q (R/W) IF Amp Q, 10 Fine Steps from 0x0 to 0xA (Total attenuation ~1dB). Refer to Figure 80 to Figure 82. Table 16. Bit Descriptions for IF_AMP Bits [15:12] [11:8] Bit Name RESERVED IF_AMP_COARSE_GAIN_I Settings 0 1 11 111 1111 [7:4] [3:0] IF_AMP_FINE_GAIN_Q IF_AMP_FINE_GAIN_I Description Reserved. Digital IF Amp Step Gain I. Refer to Figure 77 to Figure 79. Refer to Figure 77 to Figure 79. Refer to Figure 77 to Figure 79. Refer to Figure 77 to Figure 79. Refer to Figure 77 to Figure 79. IF Amp Q, 10 Fine Steps from 0x0 to 0xA. Refer to Figure 80 to Figure 82. IF Amp I, 10 Fine Steps from 0x0 to 0xA. Refer to Figure 80 to Figure 82. Reset 0x0 0x0 Access R R/W 0x0 0x0 R/W R/W Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 R/W Address: 0x9, Reset: 0x0000, Name: IF_AMP__BB_AMP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:12] IF_AMP_COARSE_GAIN_Q (R/W) Digital IF Am p 1dB Step Gain_Q 0: Refer to Figure 77 to Figure 79. 1: Refer to Figure 77 to Figure 79. 11: Refer to Figure 77 to Figure 79. 111: Refer to Figure 77 to Figure 79. 1111: Refer to Figure 77 to Figure 79. [4:0] BB_AMP_OFFSET_I (R/W) BB Am p I. Bit 4: Use as Sign Bit, b'1 is for positive values and b'0 is for negative values; Bits [3:0] Minim um Offset, 0xF: Maxim um Offset. [9:5] BB_AMP_OFFSET_Q (R/W) BB Am p Q. Bit 9: Use as Sign Bit, b'1is for positive values and b'0 is for negative values; Bit [8:5] Minim um Offset, 0xF: Maxim um Offset. [11:10] RESERVED Table 17. Bit Descriptions for IF_AMP__BB_AMP Bits [15:12] Bit Name IF_AMP_COARSE_GAIN_Q Settings 0 1 11 111 1111 [11:10] [9:5] RESERVED BB_AMP_OFFSET_Q [4:0] BB_AMP_OFFSET_I Description Digital IF Amp 1 dB Step Gain Q Refer to Figure 77 to Figure 79 Refer to Figure 77 to Figure 79 Refer to Figure 77 to Figure 79 Refer to Figure 77 to Figure 79 Refer to Figure 77 to Figure 79 Reserved. BB Amp Q (Bit 9: Use as Sign Bit, 1 is for positive values and 0 is for negative values; Bits[8:5]: Minimum Offset, 0xF: Maximum Offset) BB Amp I (Bit 4: Use as Sign Bit, 1 is for positive values and 0 is for negative values; Bits[3:0]: Minimum Offset, 0xF: Maximum Offset) Rev. A | Page 40 of 42 Data Sheet ADMV1014 Address: 0x0A, Reset: 0x2390, Name: BB_AMP_AGC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 [15:7] RESERVED [0] BB_SWITCH_HIGH_LOW_COMMON_MODE (R/W) Setting between High and Low Output Com mon Mode Voltage; Should Be Set to Oppos ite from RegA<bit6> [6:3] BB_AMP_REF_GEN (R/W) Control BB Com m on Mode Voltage See the Baseband Quadrature Dem odulation (I/Q Mode) s ection for m ore inform ation. [2:1] BB_AMP_GAIN_CTRL (R/W) See Figure 44 to Figure 46. Table 18. Bit Descriptions for BB_AMP_AGC Bits [15:7] [6:3] Bit Name RESERVED BB_AMP_REF_GEN Settings [2:1] 0 BB_AMP_GAIN_CTRL BB_SWITCH_HIGH_LOW_COMMON_MODE Description Reserved. Control BB Common-Mode Voltage. See the Baseband Quadrature Demodulation (I/Q Mode) section for more information. See Figure 44 to Figure 46. Setting between High and Low Output CommonMode Voltage. This bit must be set to opposite from Register 0x0A, Bit 6. See the Baseband Quadrature Demodulation (I/Q Mode) section for more information. Reset 0x4 0x2 Access R R/W 0x0 0x0 R/W R/W Address: 0x0B, Reset: 0x4A5C, Name: VVA_TEMP_COMP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 0 [15:0] VVA_TEMPPERATURE_COMPENSATION (R/W) VVA Temperature Compensation Table 19. Bit Descriptions for VVA_TEMP_COMP Bits [15:0] Bit Name VVA_TEMPERATURE_COMPENSATION Settings Description VVA Temperature Compensation. Set to 0x727C. See the Start-Up Sequence section and the VVA Temperature Compensation section for more information. Disable PARITY_EN when updating the VVA temperature compensation. Rev. A | Page 41 of 42 Reset 0x4A5C Access R/W ADMV1014 Data Sheet OUTLINE DIMENSIONS PIN 1 CORNER AREA 5.10 5.00 4.90 0.32 0.27 0.22 0.40 0.35 0.30 0.81 BSC SQ PIN 1 INDICATOR 32 25 24 1 3.50 REF SQ 3.57 BSC SQ 0.50 BSC 8 17 PKG-005727 0.75 MAX 0.67 NOM SIDE VIEW 0.52 0.45 0.38 0.75 BSC 0.275 REF 0.25 0.22 0.19 SEATING PLANE 16 9 BOTTOM VIEW 3.77 BSC 0.165 BSC FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-12-2018-A TOP VIEW Figure 123. 32-Terminal Land Grid Array [LGA] (CC-32-6) Dimensions shown in millimeters ORDERING GUIDE Model1 ADMV1014ACCZ ADMV1014ACCZ-R7 ADMV1014-EVALZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 32-Terminal Land Grid Array Package [LGA] 32-Terminal Land Grid Array Package [LGA] Evaluation Board Z = RoHS-Compliant Part. (c)2018-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D17172-0-4/19(A) Rev. A | Page 42 of 42 Package Option CC-32-6 CC-32-6