24 GHz to 44 GHz,
Wideband, Microwave Downconverter
Data Sheet ADMV1014
Rev. A Document Feedback
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FEATURES
Wideband RF input frequency range: 24 GHz to 44 GHz
2 downconversion modes
Direct conversion from RF to baseband I/Q
Image rejecting downconversion to complex IF
LO input frequency range: 5.4 GHz to 10.25 GHz
LO quadrupler for up to 41 GHz
Matched 50 Ω, single-ended RF input, and complex IF outputs
Option between matched 100 Ω balanced or 50 Ω single-
ended LO inputs
100 Ω balanced baseband I/Q output impedance with
adjustable output common-mode voltage level
Image rejection optimization
Square law power detector for setting mixer input power
Variable attenuator for receiver power control
Programmable via a 4-wire SPI interface
32-terminal, 5 mm × 5 mm LGA package
APPLICATIONS
Point to point microwave radios
Radar, electronic warfare systems
Instrumentation, automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAM
90°
DET
SEN
SDI
GND
LO_N
LO_P
GND
VCC_MIXER
DVDD
SCLK
SDO
VCC_LNA_3P3
VCC_VVA
VCTRL
GND
VCC_VGA
VDET
VCC_IF_BB
Q_N
Q_P
IF_Q
GND
IF_I
I_P
I_N
VCC_QUAD
GND
RF_IN
GND
VCC_LNA_1P5
VCC_BG
RST
BG_RBIAS
0°
×4
ADMV1014
17172-001
Figure 1.
GENERAL DESCRIPTION
The ADMV1014 is a silicon germanium (SiGe), wideband,
microwave downconverter optimized for point to point microwave
radio designs operating in the 24 GHz to 44 GHz frequency range.
The downconverter offers two modes of frequency translation.
The device is capable of direct quadrature demodulation to
baseband inphase (I)/quadrature (Q) output signals, as well as
image rejection downconversion to a complex intermediate
frequency (IF) output carrier frequency. The baseband outputs
can be dc-coupled, or, more typically, the I/Q outputs are
ac-coupled with a sufficiently low high-pass corner frequency
to ensure adequate demodulation accuracy. The serial port
interface (SPI) allows fine adjustment of the quadrature phase
to allow the user to optimize I/Q demodulation performance.
Alternatively, the baseband I/Q outputs can be disabled, and the
I/Q signals can be passed through an on-chip active balun to
provide two single-ended complex IF outputs anywhere between
800 MHz and 6000 MHz. When used as an image rejecting
downconverter, the unwanted image term is typically
suppressed to better than 30 dBc below the wanted sideband.
The ADMV1014 offers a flexible local oscillator (LO) system,
including a frequency quadruple option allowing up to a 41 GHz
range of LO input frequencies to cover a radio frequency (RF)
input range as wide as 24 GHz to 44 GHz. A square law power
detector is provided to allow monitoring of the power levels at
the mixer inputs. The detector output provides closed-loop
control of the RF input variable attenuator through an external
op amp error integrator circuit option.
The ADMV1014 downconverter comes in a compact, thermally
enhanced, 5 mm × 5 mm LGA package. The ADMV1014 operates
over the −40°C to +85°C case temperature range.
ADMV1014 Data Sheet
Rev. A | Page 2 of 42
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Serial Port Register Timing ......................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
I/Q Mode ....................................................................................... 9
IF Mode ........................................................................................ 17
Output Detector Performance .................................................. 24
Return Loss and Isolations ........................................................ 25
M × N Spurious Performance ................................................... 27
Theory of Operation ...................................................................... 28
Start-Up Sequence ...................................................................... 28
Baseband Quadrature Demodulation (I/Q Mode) ................ 28
Image Rejection Downconversion ........................................... 29
Detector ....................................................................................... 29
LO Input Path ............................................................................. 29
Power-Down ............................................................................... 29
Serial Port Interface (SPI) ......................................................... 30
Applications Information .............................................................. 31
Error Vector Magnitude (EVM) Performance ....................... 31
Baseband Quadrature Demodulation to Very Low
Frequencies ................................................................................. 32
Performance at Different Quad Filter Settings ....................... 32
VVA Temperature Compensation............................................ 33
Performance Between Differential vs. Single-Ended LO Input
....................................................................................................... 33
Performance across RF Frequency at Fixed IF and Baseband
Frequencies ................................................................................. 34
Recommended Land Pattern .................................................... 35
Evaluation Board Information ................................................. 35
Register Summary .......................................................................... 36
Register Details ............................................................................... 37
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
4/2019—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Table 3 and Thermal Resistance Section ................... 6
Changes to Figure 3 and Table 5 ..................................................... 7
Changes to Figure 14 ...................................................................... 10
Changes to Figure 19 Caption ....................................................... 11
Changes to Figure 27 ...................................................................... 12
Changes to Figure 51 Caption and Figure 52 Caption .............. 17
Changes to Figure 63 Caption and Figure 64 Caption .............. 19
Changes to Figure 69 Caption and Figure 70 Caption .............. 20
Changes to Figure 75 ...................................................................... 21
Changes to Figure 79 ...................................................................... 22
Changes to Return Loss and Isolations Section, Figure 95, and
Figure 97 .......................................................................................... 25
Changes to Figure 99 and Figure 101 .......................................... 26
Changes to Start-Up Sequence Section and Baseband
Quadrature Demodulation (I/Q Mode) Section ....................... 28
Changes to Image Rejection Downconversion Section
and LO Input Path Section ............................................................ 29
Change to Serial Port Interface (SPI) Section ............................. 30
Changes to Figure 111 ................................................................... 32
Changes to Table 18 and Table 19 ................................................ 41
10/2018—Revision 0: Initial Version
Data Sheet ADMV1014
Rev. A | Page 3 of 42
SPECIFICATIONS
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B set to 0x727C, Register 0x03, Bits[12:13] set to 11, and
ambient temperature (TA) = 25°C, unless otherwise noted.
Measurements are in IF mode, performed with a 90° hybrid, Register 0x03, Bit 11 = 0, and Register 0x03, Bit 8 = 1, unless otherwise noted.
Measurements in I/Q mode are measured as a composite of the I and Q channel performance, common-mode voltage (VCM) = 1.15 V,
Register 0x03, Bit 11 = 1, and Register 0x03, Bit 8 = 0, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGES
RF Input 24 44 GHz
LO Input 5.4 10.25 GHz
LO Quadrupler 21.6 41 GHz
IF Output 0.8 6.0 GHz
Baseband (BB) I/Q Output DC 6.0 GHz
LO AMPLITUDE RANGE −6 0 +6 dBm
I/Q DEMODULATOR PERFORMANCE
Conversion Gain At maximum gain
24 GHz to 42 GHz 12.5 17 dB
42 GHz to 44 GHz 12.5 17 dB
Voltage Variable Attenuator (VVA) Control Range 19 dB
Single Sideband (SSB) Noise Figure At maximum gain
24 GHz to 42 GHz 5.5 8 dB
42 GHz to 44 GHz 6 8.5 dB
Input Third-Order Intercept (IP3) At maximum gain
24 GHz to 42 GHz 0 dBm
42 GHz to 44 GHz −1 dBm
Input Second-Order Intercept (IP2) 24 GHz to 44 GHz, at maximum gain 45 dBm
Input 1 dB Compression Point (P1dB) At maximum gain
24 GHz to 42 GHz −14 −10 dBm
42 GHz to 44 GHz −15 −11 dBm
Amplitude Balance ±0.5 dB
Phase Balance DC < baseband frequency (fBB) < 2 GHz 1 Degrees
2 GHz < fBB < 4 GHz 2 Degrees
4 GHz < fBB < 6 GHz 4 Degrees
Image Rejection 24 GHz to 44 GHz, at maximum gain
Uncalibrated 45 dBc
Calibrated 52 dBc
IF DOWNCONVERTER PERFORMANCE
Conversion Gain At maximum gain
24 GHz to 42 GHz 12.5 17 dB
42 GHz to 44 GHz 11.5 16 dB
VVA Control Range 19 dB
SSB Noise Figure At maximum gain
24 GHz to 42 GHz 5.5 8 dB
42 GHz to 44 GHz 6 8.5 dB
Input IP3 At maximum gain
24 GHz to 42 GHz 0 dBm
42 GHz to 44 GHz 0.5 dBm
ADMV1014 Data Sheet
Rev. A | Page 4 of 42
Parameter Test Conditions/Comments Min Typ Max Unit
Input P1dB At maximum gain
24 GHz to 42 GHz −14 −9 dBm
42 GHz to 44 GHz −15 −10 dBm
Amplitude Balance −0.5 dB
Phase Balance 800 MHz < IF frequency (fIF) < 2 GHz 0.5 Degrees
2 GHz < fIF < 4 GHz 1 Degrees
4 GHz < fIF < 6 GHz 2.5 Degrees
Image Rejection
Uncalibrated 30 dBc
Calibrated 35 dBc
RECEIVER (Rx) POWER DETECTOR PERFORMANCE
Input Level ±1 dB dynamic range
Minimum −35 dBm
Maximum −14 dBm
±1 dB Dynamic Range 20 dB
Output Voltage
Maximum DC Output 3.3 V
RETURN LOSS
RF Input 50 Ω single-ended −13 dB
LO Input 100 Ω differential −10 dB
IF Output 50 Ω single-ended −12 dB
BB Output 100 Ω differential −15 dB
BB I/Q Output Impedance 100 Ω
LEAKAGE At maximum gain
Fundamental LO to RF −70 dBm
4 × LO to RF −70 dBm
Fundamental LO to IF −60 dBm
Fundamental LO to I/Q −60 dBm
LOGIC INPUTS
Input Voltage Range
High, VINH DVDD − 0.4 1.8 V
Low, VINL 0 0.4 V
Input Current, IINH/IINL 100 μA
Input Capacitance, CIN 3 pF
LOGIC OUTPUTS
Output Voltage Range
High, VOH DVDD − 0.4 1.8 V
Low, VOL 0 0.4 V
Output High Current, IOH 500 μA
POWER INTERFACE
VCC_IF_BB, VCC_VGA, VCC_LNA_3P3, VCC_MIXER,
VCC_BG, VCC_QUAD
3.15 3.3 3.45 V
3.3 V Supply Current 437 mA
DVDD, VCC_VVA 1.7 1.8 1.9 V
1.8 V Supply Current 4.2 mA
VCC_LNA_1P5 1.43 1.5 1.57 V
1.5 V Supply Current 33 mA
Total Power Consumption 1.5 W
Power-Down 96 125 mW
Data Sheet ADMV1014
Rev. A | Page 5 of 42
SERIAL PORT REGISTER TIMING
Table 2.
Parameter 䡟escription Min Typ Max Unit
tSDI, SETUP Data to clock setup time 10 ns
tSDI, HOLD Data to clock hold time 10 ns
tSCLK, HIGH Clock high duration 40 to 60 %
tSCLK, LOW Clock low duration 40 to 60 %
tSCLK, SEN_SETUP Clock to SEN setup time 30 ns
tSCLK, DOT Clock to data out transition time 10 ns
tSCLK, DOV Clock to data out valid time 10 ns
tSCLK, SEN_INACTIVE Clock to SEN inactive 20 ns
tSEN_INACTIVE Inactive SEN (between two operations) 80 ns
Timing Diagram
tSCLK, LO W
tSCLK, DOT
SDO
tSCLK, DOV
SDI
tSDI, SETUP tSDI, HOLD
SCLK
tSEN_INACTIVE
tSCLK, HIG H
tSCLK, SEN_ INACTI VE
tSCLK, SEN_SE TU P
SEN
17172-106
Figure 2. Serial Port Register Timing Diagram
ADMV1014 Data Sheet
Rev. A | Page 6 of 42
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage
VCC_IF_BB, VCC_VGA, VCC_LNA_3P3,
VCC_MIXER, VCC_BG, VCC_QUAD, DVDD
4.3 V
VCC_VVA, VCC_LNA_1P5 2.3 V
RF Input Power 0 dBm
LO Input Power 9 dBm
Maximum Junction Temperature 125°C
Maximum Power Dissipation1 2.17 W
Lifetime at Maximum Junction Temperature (TJ) 1 ×106 hours
Operating Case Temperature Range −40°C to +85°C
Storage Temperature Range −55°C to +125°C
Lead Temperature (Soldering 60 sec) 260°C
Moisture Sensitivity Level (MSL) Rating2 MSL3
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM) 3000 V
Field Induced Charged Device Model
(FICDM)
750 V
1 The maximum power dissipation is a theoretical number calculated by
(TJ − 85°C)/θJC_TOP.
2 Based on IPC/JEDEC J-STD-20 MSL classifications.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Only use θJA and θJC to compare the thermal performance of
different packages when all test conditions listed are similar to
JEDEC specifications. Otherwise, use ѰJT and ѰJB to calculate
the device junction temperature using the following equations:
TJ = (P × ѰJT) + TTOP (1)
where:
TTOP is package top temperature (°C). TTOP is measured at the
top center of the package.
ѰJT is the junction to top thermal characterization number.
P is the total power dissipation in the chip (W).
TJ = (P × ѰJB) + TBOARD (2)
where:
TBOARD is the board temperature measured on the midpoint of
the longest side of the package no more than 1 mm from the
edge of the package body (°C).
ѰJB is the junction to board thermal characterization number.
P is the total power dissipation in the chip (W).
As stated in JEDEC51-12, only use Equation 1 and Equation 2
when no heat sink or heat spreader is present. When a heat sink
or heat spreader is added, use θJC_TOP to estimate or calculate the
junction temperature.
Table 4. Thermal Resistance
Package
Type1 θ
JA2 θJC_TOP3 θ
JB4 Ψ
JT5 ΨJB6 Unit
CC-32-6 33.6 18.4 13.3 4.9 12.6 °C/W
1 The thermal resistance values specified in Table 4 are simulated based on
JEDEC specifications, unless specified otherwise, and must be used in
compliance with JESD51-12.
2 θJA is the junction to ambient thermal resistance in a natural convection,
JEDEC environment.
3 θJC_TOP is the junction to case (top) JEDEC thermal resistance.
4 θJB is the junction to board JEDEC thermal resistance.
5 ΨJT is the junction to top JEDEC thermal characterization parameter.
6 ΨJB is the junction to board JEDEC thermal characterization parameter
ESD CAUTION
Data Sheet ADMV1014
Rev. A | Page 7 of 42
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17172-002
VCC_QUAD
BG_RBIAS
RST
VCC_BG
VCC_LNA_1P5
GND
RF_IN
GND
SEN
I_P
I_N
IF_I
GND
IF_Q
Q_N
Q_P
SDO
VCC_IF_BB
VDET
VCC_VGA
GND
VCTRL
VCC_VVA
VCC_LNA_3P3
SDI
SCLK
DVDD
VCC_MIXER
GND
LO_P
LO_N
GND
ADMV1014
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
910 11 12 13 14 15 16
17
3132 30 29 28 27 26 25
18
19
20
21
22
23
24
NOTES
1. EXPOSE D PAD. SOLDER THE EXPOSED PAD
TO A LO W IMP EDANCE GROUND P LANE .
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 SEN SPI Serial Enable. SEN is a high impedance pin with a logic of 1.8 V.
2, 3 I_P, I_N Negative (I_N) and Positive (I_P) Differential BB I Outputs. These pins are dc-coupled.
4, 6 IF_I, IF_Q IF I and IF Q Single-Ended Complex Quadrature Outputs. These pins are dc-coupled to GND, and
each pin is matched to 50 Ω.
5, 13, 17, 19, 25, 28 GND Ground.
7, 8 Q_N, Q_P Positive (Q_P) and Negative (Q_N) Differential Baseband Q Outputs. These pins are dc-coupled.
9 SDO SPI Serial Data Output.
10 VCC_IF_BB
3.3 V Power Supply for BB and IF Section. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this
pin.
11 VDET Square Law Detector Output Voltage.
12 VCC_VGA 3.3 V Power Supply for RF Amplifier. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
14 VCTRL
RF VVA Control Voltage. The voltage on this pin ranges from 1.8 V (minimum gain) to 0 V (maximum
gain). Refer to the ADMV1014-EVALZ user guide for the external component requirements.
15 VCC_VVA
1.8 V Power Supply for VVA Control Circuit. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to
this pin.
16 VCC_LNA_3P3 3.3 V Power Supply for LNA. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
18 RF_IN
RF Input. This pin is dc-coupled internally with a choke to GND, and matched to 50 Ω, single-
ended. A dc input above 0 V requires external ac coupling.
20 VCC_LNA_1P5
1.5 V Power Supply for Low Noise Amplifier (LNA). Place a 100 pF, 0.01 μF, and a 10 μF capacitor
close to this pin.
21 VCC_BG
3.3 V Power Supply for Band Gap Circuit. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this
pin.
22 RST SPI Reset. Connect this pin to logic high for normal operation.
23 BG_RBIAS
Bang Gap Circuit External High Precision Resistor. Place a 1.1 kΩ, high precision resistor shunt to
ground close to this pin.
24 VCC_QUAD 3.3 V Power Supply for Quadruple. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
ADMV1014 Data Sheet
Rev. A | Page 8 of 42
Pin No. Mnemonic Description
26, 27 LO_N, LO_P Negative (LO_N) and Positive (LO_P) Differential Local Oscillator Input. These pins are dc-coupled
internally with a choke to GND and matched to 100 Ω differential or 50 Ω single-ended. A dc input
above 0 V requires external ac coupling. When using the LO input as single-ended, terminate the
unused LO port with a 50 Ω impedance to ground.
29 VCC_MIXER 3.3 V Power Supply for the Mixer. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
30 DVDD 1.8 V SPI Digital Supply. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
31 SCLK SPI Clock Digital Input. SCLK is a high impedance pin.
32 SDI SPI Serial Data Input. SDI is a high impedance pin.
EPAD Exposed Pad. Solder the exposed pad to a low impedance ground plane.
Data Sheet ADMV1014
Rev. A | Page 9 of 42
TYPICAL PERFORMANCE CHARACTERISTICS
I/Q MODE
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, and TA = 25°C, unless otherwise noted. Register 0x0B is set to 0x727C,
Register 0x03, Bits[13:12] are set to 11, VCM = 1.15 V, Register 0x03, Bit 11 = 1, Register 0x03, Bit 8 = 0, and measurements are a composite
of the I and Q channels. VATT is the attenuation voltage at the VCTRL pin. VATT = 0 V, unless otherwise specified.
25
–30
–25
–20
–15
–10
–5
0
5
10
15
20
23 25 27 29 31 33 35 37 39 41 43 45
CONVE RS IO N GAI N ( dB)
RF FREQUENCY (G Hz )
+85°C AT 1.8V
+25°C AT 1.8V
–40° C AT 1.8V
+85°C AT 0.8V
+25°C AT 0.8V
–40° C AT 0.8V
+85°C AT 0 V
+25°C AT 0 V
–40° C AT 0V
17172-003
Figure 4. Conversion Gain vs. RF Frequency at Three Different Gain Settings
for Various Temperatures, fBB = 100 MHz (Upper Sideband)
25
–10
–5
0
5
10
15
20
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF F REQUE NCY (GHz )
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
17172-004
Figure 5. Conversion Gain vs. RF Frequency for Various Supply Voltages,
fBB = 100 MHz
25
–10
–5
0
5
10
15
20
23 25 27 29 31 33 35 37 39 41 43 45
CONVE RS IO N GAI N ( dB)
RF F REQUE NCY (GHz )
+6dBm UP P E R S IDEBAND
0dBm UPP ER SI DE BAND
–6dBm UP PE R SIDE BAND
17172-005
Figure 6. Conversion Gain vs. RF Frequency for Various LO Inputs, fBB = 100 MHz
25
–5
0
5
10
15
20
0 0.20.40.60.81.01.21.41.61.8
CONVERSION GAIN (dB)
V
ATT
(V)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40° C AT 39G H z
+85° C AT 28G Hz
+25° C AT 28G Hz
–40° C AT 28G H z
17172-006
Figure 7. Conversion Gain vs. VATT for Various RF Frequencies (fRF),
fBB = 100 MHz at fRF = 28 GHz and 39 GHz
25
0
5
10
15
20
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
CONVERSION GAIN (dB)
BASEBAND FREQUENCY (GHz)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
17172-007
Figure 8. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and
39 GHz (Upper Sideband)
25
0
5
10
15
20
CONVERSION GAIN (dB)
39GH z LOWE R SI DE BAND
28GH z LOWE R SI DE BAND
17172-008
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
Figure 9. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and
39 GHz (Lower Sideband)
ADMV1014 Data Sheet
Rev. A | Page 10 of 42
10
–10
–8
–6
–4
–2
0
2
4
6
8
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP3 (dBm)
RF F REQUENCY (G Hz )
+85° C UPP ER S I DEBAND
+25° C UPP ER S I DEBAND
–40°C UPPER SIDEBAND
17172-009
Figure 10. Input IP3 vs. RF Frequency at Maximum Gain for Various
Temperatures, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
10
–10
–8
–6
–4
–2
0
2
4
6
8
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP3 (dBm)
RF F REQUENCY (G Hz )
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
17172-010
Figure 11. Input IP3 vs. RF Frequency at Maximum Gain for Various Supply
Voltages, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
10
–10
–8
–6
–4
–2
0
2
4
6
8
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP3 (dBm)
RF F REQUENCY (G Hz )
+6d Bm UP P E R S IDEBAND
0dBm UPPER SIDEBAND
–6dBm UP PE R SI DE BAND
17172-011
Figure 12. Input IP3 vs. RF Frequency at Maximum Gain for Various LO
Inputs, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz
(Upper Sideband)
10.0
–5.0
–2.5
0
2.5
5.0
7.5
0 0.20.40.60.81.01.21.41.61.8
INPUT IP3 (dBm)
V
ATT
(V)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
17172-012
Figure 13. Input IP3 vs. VATT for Various RF Frequencies (fRF),
RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper
Sideband) at fRF = 28 GHz and 39 GHz
10.0
–10.0
–7.5
–5.0
–2.5
0
2.5
5.0
7.5 39GHz UPPE R S IDE BAN D
28GHz UPPER S IDE BAN D
39GHz L OW ER SIDEB AND
28GHz L OW ER SIDEB AND
INPUT IP3 (dBm)
17172-013
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBA ND FREQUE NCY (GHz)
Figure 14. Input IP3 vs. Baseband Frequency at Maximum Gain, RF
Amplitude = −30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and
39 GHz, Upper Sideband and Lower Sideband
5
4
–5
–2
–4
–3
–1
0
1
2
3
–30 –29 –28 –27 –26 –25 –24 –23 –22 –21 –20
INPUT IP3 (dBm)
INPUT POWER (dBm)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
17172-014
Figure 15. Input IP3 vs. Input Power for Various RF Frequencies (fRF) at 20 MHz
Spacing, fBB = 100 MHz, fRF = 28 GHz and 39 GHz
Data Sheet ADMV1014
Rev. A | Page 11 of 42
12
0
2
4
6
8
10
23 25 27 29 31 33 35 37 39 41 43 45
NOISE FI GURE ( dB)
RF F REQUENCY (G Hz )
+85° C UPP ER S I DEBAND
+25° C UPP ER S I DEBAND
–40°C UPPER SIDEBAND
17172-015
Figure 16. Noise Figure vs. RF Frequency at Maximum Gain for Various
Temperatures, fBB = 100 MHz
12
0
2
4
6
8
10
23 25 27 29 31 33 35 37 39 41 43 45
NOISE FI GURE ( dB)
RF F REQUENCY (G Hz )
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
17172-016
Figure 17. Noise Figure vs. RF Frequency for Various Supply Voltages,
fBB = 100 MHz
12
0
2
4
6
8
10
23 25 27 29 31 33 35 37 39 41 43 45
NOISE FI GURE ( dB)
RF F REQUENCY (G Hz )
+6d Bm UP P E R S IDEBAND
0dBm UPPER SIDEBAND
–6dBm UP PER S I DE BAND
17172-017
Figure 18. Noise Figure vs. RF Frequency for Various LO Inputs, fBB = 100 MHz
25
0
5
10
15
20
0 0.20.40.60.81.01.21.41.61.8
NOISE FI GURE (dB)
V
ATT
(V)
+85°C AT 39GHz
+25°C AT 39GHz
–40°C AT 39G Hz
+85°C AT 28GHz
+25°C AT 28GHz
–40°C AT 28G Hz
17172-018
Figure 19. Noise Figure vs. VATT for Various RF Frequencies and Temperatures,
fBB = 100 MHz at fRF = 28 GHz and 39 GHz
9
0
2
4
6
8
1
3
5
7
NOISE F I G URE (dB)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
17172-019
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
Figure 20. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz
(Upper Sideband)
9
0
2
4
6
8
1
3
5
7
NOISE FI GURE (dB)
39GH z LOWE R SI DE BAND
28GH z LOWE R SI DE BAND
17172-020
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENCY (GHz)
Figure 21. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz
(Lower Sideband)
ADMV1014 Data Sheet
Rev. A | Page 12 of 42
80
60
70
0
10
20
30
40
50
23 25 27 29 31 33 35 37 39 41 43 45
IM AGE RE J E CTI ON (dBc)
RF INPUT FREQUE NCY (GHz )
+85° C UPP ER S I DE BAND
+25° C UPP ER S I DE BAND
–40°C UPPER SIDEBAND
17172-021
Figure 22. Image Rejection vs. RF Input Frequency at Maximum Gain for
Various Temperatures, fBB = 100 MHz, Uncalibrated
23 25 27 29 31 33 35 37 39 41 43 45
IM AGE RE J E CTI ON (dBc)
80
60
70
0
10
20
30
40
50
RF INPUT FREQUE NCY (GHz )
+85° C UPP ER S I DE BAND
+25° C UPP ER S I DE BAND
–40°C UPPER SIDEBAND
17172-022
Figure 23. Image Rejection vs. RF Input Frequency at Maximum Gain for
Various Temperatures, fBB = 100 MHz, Calibrated
23 25 27 29 31 33 35 37 39 41 43 45
IM AG E REJE CTI O N ( dBc)
80
60
70
0
10
20
30
40
50
RF INPUT FREQUE NCY (GHz )
3.5V UP PE R SIDEBAND
3.3V UP PE R SIDEBAND
3.1V UP PE R SIDEBAND
17172-023
Figure 24. Image Rejection vs. RF Input Frequency for Various Supply
Voltages, fBB = 100 MHz
23 25 27 29 31 33 35 37 39 41 43 45
IM AGE RE J E CTI ON (dBc)
80
60
70
0
10
20
30
40
50
RF INPUT FREQUE NCY (GHz )
+6dBm UPPER SIDEBAND
0dBm UPP ER S I DE BAND
–6dBm UPPER SIDEBAND
17172-024
Figure 25. Image Rejection vs. RF Input Frequency for Various LO Inputs,
fBB = 100 MHz
80
60
70
0
10
20
30
40
50
IM AG E REJE C T ION ( d Bc )
0 0.20.40.60.81.01.21.41.61.8
V
ATT
(V)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
17172-025
Figure 26. Image Rejection vs. VATT for Various RF Frequencies (fRF),
fBB = 100 MHz at fRF = 28 GHz and 39 GHz
1234567
80
60
70
0
10
20
30
40
50
IMAG E REJE CT ION ( dBc)
0BASEBAND FREQUENCY (G Hz)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz L OW ER SIDEB AN D
28GHz L OW ER SIDEB AN D
17172-026
Figure 27. Image Rejection vs. Baseband Frequency at fRF = 28 GHz and
39 GHz (Upper Sideband and Lower Sideband)
Data Sheet ADMV1014
Rev. A | Page 13 of 42
60
0
10
20
30
40
50
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP2 (dBm)
RF F REQUENCY (GHz)
+85° C UPP E R SI DE BAND
+25° C UPP E R SI DE BAND
–40°C UPPER SIDEBAND
17172-027
Figure 28. Input IP2 vs. RF Frequency at Maximum Gain for Various
Temperatures, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
60
0
10
20
30
40
50
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP2 (dBm)
RF F REQUENCY (GHz)
3.5V UPPE R SIDE BAND
3.3V UPPE R SIDE BAND
3.1V UPPE R SIDE BAND
17172-028
Figure 29. Input IP2 vs. RF Frequency (fRF) at Maximum Gain for Various
Supply Voltages, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
23 25 27 29 31 33 35 37 39 41 43 45
60
0
10
20
30
40
50
INPUT IP2 (dBm)
RF F REQUENCY (GHz)
+6d Bm UPPER SIDEBA ND
0dBm UPPER SIDEBAND
–6dBm UPP E R SI DE BAND
17172-029
Figure 30. Input IP2 vs. RF Frequency at Maximum Gain for Various LO
Inputs, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz
(Upper Sideband)
60
0
10
20
30
40
50
INPUT IP2 (dBm)
0 0.20.40.60.81.01.21.41.61.8
V
ATT
(V)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
17172-030
Figure 31. Input IP2 vs. VATT for Various RF Frequencies (fRF), RF Amplitude = −30
dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) at
fRF = 28 GHz and 39 GHz
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
55
0
10
20
30
40
5
15
25
35
50
45
INPUT IP2 (dBm)
17172-031
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENC Y (GHz)
Figure 32. Input IP2 vs. Baseband Frequency at Maximum Gain, RF
Amplitude = −30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and
39 GHz, Upper Sideband
39GH z LOWE R SI DEBAND
28GH z LOWE R SI DEBAND
55
0
10
20
30
40
5
15
25
35
50
45
INPUT IP2 (dBm)
17172-032
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENC Y (GHz)
Figure 33. Input IP2 vs. Baseband Frequency for Various RF Frequencies (fRF)
at 20 MHz Spacing, fBB = 100 MHz, fRF = 28 GHz and 39 GHz
ADMV1014 Data Sheet
Rev. A | Page 14 of 42
0
–20
–18
–16
–14
–10
–12
–8
–6
–4
–2
23 25 27 29 31 33 35 37 39 41 43 45
INPUT P1dB (dBm)
RF F REQUENCY (GHz)
+85° C UPP E R SI DE BAND
+25° C UPP E R SI DE BAND
–40°C UPPER SIDEBAND
17172-033
Figure 34. Input P1dB vs. RF Frequency at Maximum Gain for Various
Temperatures, fBB = 100 MHz
0
–20
–18
–16
–14
–10
–12
–8
–6
–4
–2
23 25 27 29 31 33 35 37 39 41 43 45
INPUT P1dB (dBm)
RF F REQUENCY (GHz)
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
17172-034
Figure 35. Input P1dB vs. RF Frequency for Various Supply Voltages,
fBB = 100 MHz
0
–20
–18
–16
–14
–10
–12
–8
–6
–4
–2
23 25 27 29 31 33 35 37 39 41 43 45
INPUT P1dB (dBm)
RF F REQUENCY (GHz)
+6d Bm UPPER S IDEBAND
0dBm UPPER SIDEBAND
–6dBm UP PE R SIDEBAND
17172-035
Figure 36. Input P1dB vs. RF Frequency for Various LO Inputs, fBB = 100 MHz
0 0.20.40.60.81.01.21.41.61.8
V
ATT
(V)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40° C AT 39GHz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40° C AT 28GHz
0
–14
–10
–12
–8
–6
–4
–2
INPUT P1dB (dBm)
17172-036
Figure 37. Input P1dB vs. VATT for Various RF Frequencies (fRF),
fBB = 100 MHz at fRF = 28 GHz and 39 GHz
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
0
–20
–18
–16
–14
–10
–12
–8
–6
–4
–2
INPUT P1dB (dBm)
17172-037
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUE NCY (GH z )
Figure 38. Input P1dB vs. Baseband Output Frequency at
fRF = 28 GHz and 39 GHz (Upper Sideband)
39GH z LOWE R SI DEBAND
28GH z LOWE R SI DEBAND
0
–20
–18
–16
–14
–10
–12
–8
–6
–4
–2
INPUT P1dB (dBm)
17172-038
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
BASEBAND FREQUENC Y (GHz)
Figure 39. Input P1dB vs. Baseband Output Frequency at
fRF = 28 GHz and 39 GHz (Lower Sideband)
Data Sheet ADMV1014
Rev. A | Page 15 of 42
1.0
–1.0
–0.8
–0.4
0
0.4
0.8
–0.6
–0.2
0.2
0.6
01234567
MAG NIT UDE ERROR (dB)
BASEBAND OUTPUT FREQ UE NCY (GH z )
BB I_N + 85° C
BB I_N + 25° C
BB I_N –40°C
BB Q_N + 85°C
BB Q_N + 25°C
BB Q_N –4 0°C
BB Q_P + 8 5°C
BB Q_P + 2 5°C
BB Q_P –40 °C
17172-045
Figure 40. Magnitude Error vs. Baseband Output Frequency, Referenced to
I_P Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain
8
–8
–4
0
4
–6
–2
2
6
01234567
PHASE ERROR (Degrees)
BASEBAND OUTPUT FREQ UE NCY (GH z )
17172-046
BB I_N + 85°C
BB I_N + 25°C
BB I_N –40°C
BB Q_N + 85°C
BB Q_N + 25°C
BB Q_N –40°C
BB Q_P + 8 5°C
BB Q_P + 2 5°C
BB Q_P –40 °C
Figure 41. Phase Error vs. Baseband Output Frequency, Referenced to I_P
Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain
1.0
–1.0
–0.8
–0.4
0
0.4
0.8
–0.6
–0.2
0.2
0.6
01234567
MAG NIT UDE ERROR (dB)
BASEBAND OUTPUT FREQ UE NCY (GH z )
17172-047
BB I_N + 85°C
BB I_N + 25°C
BB I_N –40°C
BB Q_N +85°C
BB Q_N +25°C
BB Q _N –40 °C
BB Q_P +85°C
BB Q_P +25°C
BB Q_P –40°C
Figure 42. Magnitude Error vs. Baseband Output Frequency, Referenced to
I_P Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain
8
–8
–4
0
4
–6
–2
2
6
01234567
PHASE ERROR (Degrees)
BASEBAND OUTPUT FREQ UE NCY (GH z )
17172-048
BB I_N + 85°C
BB I_N + 25°C
BB I_N –40°C
BB Q_N +8 5°C
BB Q_N +2 5°C
BB Q_N –40°C
BB Q_P + 8 5°C
BB Q_P + 2 5°C
BB Q_P –40 °C
Figure 43. Phase Error vs. Baseband Output Frequency, Referenced to I_P
Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain
ADMV1014 Data Sheet
Rev. A | Page 16 of 42
25
0
5
10
15
20
CONV ERSI ON GAIN ( dB)
23 25 27 29 31 33 35 37 39 41 43 45
RF FREQUEN CY (GH z )
0
1
2
3
17172-042
Figure 44. Conversion Gain vs. RF Frequency at Four Different
BB_AMP_GAIN_CTRL (Register 0x0A, Bits[2:1]) Settings, fBB = 100 MHz
(Upper Sideband)
23 25 27 29 31 33 35 37 39 41 43 45
RF FREQUEN CY (GH z )
0
1
2
3
5
–5
–4
–3
–2
–1
0
1
2
3
4
INPUT IP3 (dBm)
17172-043
Figure 45. Input IP3 vs. RF Frequency at Four Different BB_AMP_GAIN_CTRL
(Register A, Bits[2:1]) Settings, fBB = 100 MHz (Upper Sideband)
23 25 27 29 31 33 35 37 39 41 43 45
RF FREQUEN CY (GH z )
0
1
2
3
12
0
2
4
6
8
10
NOISE FI GURE ( dB)
17172-044
Figure 46. Noise Figure vs. RF Frequency Four Different BB_AMP_GAIN_CTRL
(Register 0x0A, Bits[2:1]) Settings, fBB = 100 MHz (Upper Sideband)
Data Sheet ADMV1014
Rev. A | Page 17 of 42
IF MODE
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25°C unless otherwise specified. Register 0x0B set to 0x727C,
Register 0x03, Bits[12:13] set to 11, measurements performed with a 90° hybrid, Register 0x03, Bit 11 = 0, and Register 0x03, Bit 8 = 1.
25
–30
–25
–20
–15
–10
–5
0
5
10
15
20
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF F REQUENCY (G Hz )
+85° C UPP E R SI DE BAND
+25° C UPP E R SI DE BAND
–40°C UPPER SIDEBAND
+85° C L O WER SIDEBAND
+25° C L O WER SIDEBAND
–40° C LOWER S IDEBAND
17172-049
Figure 47. Conversion Gain vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
25
–30
–25
–20
–15
–10
–5
0
5
10
15
20
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF F REQUENCY (G Hz )
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
17172-050
Figure 48. Conversion Gain vs. RF Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
25
–30
–25
–20
–15
–10
–5
0
5
10
15
20
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF F REQUENCY (G Hz )
+6d Bm UPPE R SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPP E R SI DE BAND
+6d Bm LOW E R SI DE BAND
0dBm LOWER S IDEBAND
–6dBm L OW ER S I DE BAND
17172-051
Figure 49. Conversion Gain vs. RF Frequency at Maximum Gain for Various
LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
25
0
5
10
15
20
0.5 1.0 2.0 3.01.5 2.5 3.5 4.0 4.5 5.0 5.5 6.56.0 7.0
CONVERSION GAIN (dB)
IF F R E Q UENC Y
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz L OW E R SID E BAND
28GHz L OW E R SID E BAND
17172-052
Figure 50. Conversion Gain vs. IF Frequency (fIF) at Maximum Gain,
fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
25
–15
–10
–5
0
5
10
15
20
0 0.20.40.60.81.01.21.41.61.8
CONVERSION GAIN (dB)
V
ATT
(V)
+85° C AT 28G Hz
+25° C AT 28G Hz
–40° C AT 28G H z
+85° C AT 39G Hz
+25° C AT 39G Hz
–40° C AT 39G H z
17172-053
Figure 51. Conversion Gain vs. VATT at Various Temperatures, fIF = 3.5 GHz,
fRF = 28 GHz and 39 GHz (Upper Sideband)
25
–15
–10
–5
0
5
10
15
20
0 0.20.40.60.81.01.21.41.61.8
CONVERSION GAIN (dB)
V
ATT
(V)
+85° C AT 28G Hz
+25° C AT 28G Hz
–40° C AT 28G H z
+85° C AT 39G Hz
+25° C AT 39G Hz
–40° C AT 39G H z
17172-054
Figure 52. Conversion Gain vs. VATT at Various Temperatures, fIF = 3.5 GHz ,
fRF = 28 GHz and 39 GHz (Lower Sideband)
ADMV1014 Data Sheet
Rev. A | Page 18 of 42
12
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP3 (dBm)
RF F REQUENCY (G Hz )
+85°C UPPER SIDEBAND
+25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND
+85°C LOWER SIDEBAND
+25°C LOWER SIDEBAND
–40° C LOWER S IDEBAND
17172-055
Figure 53. Input IP3 vs. RF Frequency at Maximum Gain for Various
Temperatures, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
12
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP3 (dBm)
RF F REQUENCY (G Hz )
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
17172-056
Figure 54. Input IP3 vs. RF Frequency at Maximum Gain for Various Supply
Voltages, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz
(Upper Sideband and Lower Sideband)
12
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP3 (dBm)
RF F REQUENCY (G Hz )
+6d Bm UPPE R SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPP E R SI DE BAND
+6d Bm LOW E R SI DE BAND
0dBm LOWER S IDEBAND
–6dBm L OW ER S I DE BAND
17172-057
Figure 55. Input IP3 vs. RF Frequency at Maximum gain for Various LO Inputs,
RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz
(Upper Sideband and Lower Sideband)
10
–6
–4
0
4
8
–2
2
6
00.2 0.6 1.00.4 0.8 1.2 1.4 1.6 1.8
INPUT IP3 (dBm)
V
ATT
(V)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz L OW E R SID E BAND
28GHz L OW E R SID E BAND
17172-058
Figure 56. Input IP3 vs. VATT for Various RF Frequencies (fRF), RF Amplitude =
−30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz at fRF = 28 GHz and
39 GHz (Upper Sideband and Lower Sideband)
10
–10
–8
–6
–4
0
4
8
–2
2
6
INPUT IP3 (dBm)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz L OW E R SID E BAND
28GHz L OW E R SID E BAND
0.5 1.0 2.0 3.01.5 2.5 3.5 4.0 4.5 5.0 5.5 6.56.0 7.0
IF F REQUENCY (GHz)
17172-059
Figure 57. Input IP3 vs. IF Frequency at Maximum Gain, RF Amplitude =
−30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and 39 GHz
(Upper Sideband and Lower Sideband)
5
–5
–4
–3
–2
0
2
4
–1
1
3
INPUT IP3 (dBm)
39GHz UPPER S IDEBAND
28GHz UPPER S IDEBAND
39GHz LO WER S IDEBAND
28GHz LO WER S IDEBAND
–30 –29 –27 –25–28 –26 –24 –23 –22 –21 –20
INPUT POWER (dBm)
17172-060
Figure 58. Input IP3 vs. Input Power for Various RF Frequencies (fRF), at
20 MHz Spacing, fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz
(Upper Sideband and Lower Sideband)
Data Sheet ADMV1014
Rev. A | Page 19 of 42
12
0
2
4
6
8
10
23 25 27 29 31 33 35 37 39 41 43 45
NOISE FI GURE ( dB)
RF F REQUENCY (G Hz )
+85° C UPP ER S I DEBAND
+25° C UPP ER S I DEBAND
–40°C UPPER SIDEBAND
+85° C L O WER SI DE BAND
+25° C L O WER SI DE BAND
–40°C LO WER SIDE BAND
17172-061
Figure 59. Noise Figure vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
12
0
2
4
6
8
10
23 25 27 29 31 33 35 37 39 41 43 45
NOISE FI GURE ( dB)
RF F REQUENCY (G Hz )
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
17172-062
Figure 60. Noise Figure vs. RF Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
12
0
2
4
6
8
10
23 25 27 29 31 33 35 37 39 41 43 45
NOISE FI GURE ( dB)
RF F REQUENCY (G Hz )
+6d Bm UPPE R SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPP ER S I DE BAND
+6d Bm LOW E R SI DE BAND
0dBm LOWER S IDEBAND
–6dBm L O WER SIDEBAND
17172-063
Figure 61. Noise Figure vs. RF Frequency at Maximum Gain for Various LO
Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz LOWER SIDE BAND
28GHz LOWER SIDE BAND
0.5 1.0 2.0 3.01.5 2.5 3.5 4.0 4.5 5.0 5.5 6.56.0 7.0
IF FREQUENCY (GHz)
9
0
2
4
6
8
1
3
5
7
NOISE FI GURE (dB)
17172-064
Figure 62. Noise Figure vs. IF Frequency at Maximum Gain, fRF = 28 GHz and
39 GHz (Upper Sideband and Lower Sideband)
22
0
4
8
12
16
20
2
6
10
14
18
NOI S E F IGUR E (d B)
+85°C AT 2 8GHz
+25°C AT 2 8GHz
–40°C AT 28GHz
+85°C AT 3 9GHz
+25°C AT 3 9GHz
–40°C AT 39GHz
0 0.20.40.60.81.01.21.41.61.8
V
ATT
(V)
17172-065
Figure 63. Noise Figure vs. VATT at Various Temperatures, fIF = 3.5 GHz,
fRF = 28 GHz and 39 GHz (Upper Sideband)
22
0
4
8
12
16
20
2
6
10
14
18
NOI S E F IGUR E (d B)
+85°C AT 2 8GHz
+25°C AT 2 8GHz
–40°C AT 28GHz
+85°C AT 3 9GHz
+25°C AT 3 9GHz
–40°C AT 39GHz
0 0.20.40.60.81.01.21.41.61.8
V
ATT
(V)
17172-066
Figure 64. Noise Figure vs. VATT at Various Temperatures, fIF = 3.5 GHz,
fRF = 28 GHz and 39 GHz (Lower Sideband)
ADMV1014 Data Sheet
Rev. A | Page 20 of 42
0
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
23 25 27 29 31 33 35 37 39 41 43 45
INPUT P1dB (dBm)
RF F REQUENCY (G Hz )
+85° C UPP ER S I DEBAND
+25° C UPP ER S I DEBAND
–40°C UPPER SIDEBAND
+85° C L O WER SI DE BAND
+25° C L O WER SI DE BAND
–40°C LO WER SIDE BAND
17172-067
Figure 65. Input P1dB vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
0
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
23 25 27 29 31 33 35 37 39 41 43 45
INPUT P1dB (dBm)
RF F REQUENCY (G Hz )
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
17172-068
Figure 66. Input P1dB vs. RF Frequency at Maximum Gain for Various Supply
Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
0
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
24 26 28 30 32 34 36 38 40 42 44
INPUT P1dB (dBm)
RF F REQUENCY (G Hz )
+6d Bm UPPE R SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPP ER S I DE BAND
+6d Bm LOW E R SI DE BAND
0dBm LOWER S IDEBAND
–6dBm L O WER SIDEBAND
17172-069
Figure 67. Input P1dB vs. RF Frequency at Maximum Gain for Various LO
Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GH z LO WER S IDE BAND
28GH z LO WER S IDE BAND
0.5 1.0 2.0 3.01.5 2.5 3.5 4.0 4.5 5.0 5.5 6.56.0 7.0
IF FREQUENCY (GHz)
1
–15
–11
–7
–3
–13
–9
–5
–1
INPUT P1dB (dBm)
17172-070
Figure 68. Input P1dB vs. IF Frequency at Maximum Gain,
fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
2
–16
–14
–12
–10
–8
–6
–4
–2
0
0 0.20.40.60.81.01.21.41.61.8
INPUT P1dB (dBm)
V
ATT
(V)
+85°C AT 28GHz
+25°C AT 28GHz
–40°C AT 28G Hz
+85°C AT 39GHz
+25°C AT 39GHz
–40°C AT 39G Hz
17172-071
Figure 69. Input P1dB vs. VATT at Various Temperatures, fIF = 3.5 GHz,
fRF = 28 GHz and 39 GHz (Upper Sideband)
2
–16
–14
–12
–10
–8
–6
–4
–2
0
0 0.20.40.60.81.01.21.41.61.8
INPUT P1dB (dBm)
V
ATT
(V)
+85°C AT 28GHz
+25°C AT 28GHz
–40°C AT 28G Hz
+85°C AT 39GHz
+25°C AT 39GHz
–40°C AT 39G Hz
17172-072
Figure 70. Input P1dB vs. VATT at Various Temperatures, fIF = 3.5 GHz,
fRF = 28 GHz and 39 GHz (Lower Sideband)
Data Sheet ADMV1014
Rev. A | Page 21 of 42
23 25 27 29 31 33 35 37 39 41 43 45
IM AGE RE J E CTI ON (dBc)
60
0
10
20
30
40
50
RF INPUT FREQUE NCY (GHz )
+85° C UPP ER S I DEBAND
+25° C UPP ER S I DEBAND
–40°C UPPER SIDEBAND
+85° C L O WER SI DE BAND
+25° C L O WER SI DE BAND
–40°C LO WER SIDE BAND
17172-073
Figure 71. Image Rejection vs. RF Input Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband), Uncalibrated
23 25 27 29 31 33 35 37 39 41 43 45
IM AGE RE J E CTI ON (dBc)
60
0
10
20
30
40
50
RF INPUT FREQUE NCY (GHz )
+85° C UPP ER S I DEBAND
+25° C UPP ER S I DEBAND
–40°C UPPER SIDEBAND
+85° C L O WER SI DE BAND
+25° C L O WER SI DE BAND
–40°C LO WER SIDE BAND
17172-074
Figure 72. Image Rejection vs. RF Input Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband), Calibrated
23 25 27 29 31 33 35 37 39 41 43 45
IM AGE RE J E CTI ON (dBc)
60
0
10
20
30
40
50
RF INPUT FREQUE NCY (GHz )
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND
3.1V UPPER SIDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
17172-075
Figure 73. Image Rejection vs. RF Input Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
23 25 27 29 31 33 35 37 39 41 43 45
IM AGE REJ E CTION (dBc)
60
0
10
20
30
40
50
RF INPUT FREQUE NCY (GHz )
+6d Bm UPPE R SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPP E R SI DE BAND
+6d Bm LOW E R SI DE BAND
0dBm LOWER S IDEBAND
–6dBm L O WER SIDEBAND
17172-076
Figure 74. Image Rejection vs. RF Input Frequency at Maximum Gain for
Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
60
0
10
20
30
40
50
IM AGE RE JE C T IO N ( d B c)
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GHz L OW ER SIDEB AN D
28GHz L OW ER SIDEB AN D
0IF INPUT FREQUENCY (GHz)
17172-077
1234567
Figure 75. Image Rejection vs. IF Input Frequency at Maximum Gain,
fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
60
0
10
20
30
40
50
IM AG E RE JEC T IO N ( d Bc )
39GHz UPPER SIDEBAND
28GHz UPPER SIDEBAND
39GH z LOWE R SI DEBAND
28GH z LOWE R SI DEBAND
0 0.20.40.60.81.01.21.41.61.8
V
ATT
(V)
17172-078
Figure 76. Image Rejection vs. VATT at Various RF Frequencies (fRF),
fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
ADMV1014 Data Sheet
Rev. A | Page 22 of 42
23 25 27 29 31 33 35 37 39 41 43 45
20
0
2
6
4
8
10
12
14
16
18
CONVERSION GAIN (dB)
RF F RE QUENCY (GHz)
17172-079
0
1
3
7
15
Figure 77. Conversion Gain vs. RF Frequency at Different
IF_AMP_COARSE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for
Register 0x08, Bits[11:8] and Register 0x09, Bits[15:12] Are the Same
5
–5
–4
–2
–3
–1
0
1
2
3
4
23 25 27 29 31 33 35 37 4139 4543
INPUT IP3 (dBm)
RF F RE QUENCY (GHz)
17172-080
0
1
3
7
15
Figure 78. Input IP3 vs. RF Frequency at Different IF_AMP_COARSE_GAIN_x
Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[11:8]
and Register 0x09, Bits[15:12] Are the Same
23 25 27 29 31 33 35 37 39 41 43 45
10
0
1
3
2
4
5
6
7
8
9
NOISE FIGURE (dB )
RF FRE QUENC Y (G Hz )
17172-081
0
1
3
7
15
Figure 79. Noise Figure vs. RF Frequency at Different
IF_AMP_COARSE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for
Register 0x08, Bits[11:8] and Register 0x09, Bits[15:12] Are the Same
23 25 27 29 31 33 35 37 39 41 43 45
20
0
2
4
6
8
10
12
14
16
18
CONV ERSI ON GAIN ( dB)
RF F RE QUENCY (GHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17172-082
Figure 80. Conversion Gain vs. RF Frequency at Different IF_AMP_
FINE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Register 0x08, Bits[7:4]
and Bits[3:0] Are the Same
5
–5
–4
–2
–3
–1
0
1
2
3
4
23 25 27 29 31 33 35 37 4139 4543
INPUT IP3 (dBm)
RF F REQUENCY (GHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17172-083
Figure 81. Input IP3 vs. RF Frequency at Different IF_AMP_FINE_GAIN_x
Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[7:4]
and Bits[3:0] Are the Same
23 25 27 29 31 33 35 37 39 41 43 45
10
0
1
3
2
4
5
6
7
8
9
NOISE FIGURE ( dB)
RF F RE QUENCY (GHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17172-084
Figure 82. Noise Figure vs. RF Frequency at Different IF_AMP_FINE_GAIN_x
Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[7:4]
and Bits[3:0] Are the Same
Data Sheet ADMV1014
Rev. A | Page 23 of 42
02461357
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
I/Q MAG NITUDE ERROR (dB)
IF O UT PUT FREQ UENCY (GHz)
+85°C
+25°C
–40°C
17172-085
Figure 83. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I
Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain
02461357
5
–5
–4
–3
–2
–1
0
1
2
3
4
I/Q PHASE ERROR (dB)
IF O UT PUT FREQ UENCY (GHz)
+85°C
+25°C
–40°C
17172-086
Figure 84. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output,
fRF = 28 GHz, for Various Temperatures, at Maximum Gain
02461357
IF O UT PUT FREQ UENCY (GHz)
+85°C
+25°C
–40°C
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
I/Q MAG NITUDE ERROR (dB)
17172-087
Figure 85. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I
Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain
02461357
5
–5
–4
–3
–2
–1
0
1
2
3
4
I/Q PHASE ERROR (dB)
IF O UT PUT FREQ UENCY (GHz)
+85°C
+25°C
–40°C
17172-088
Figure 86. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output,
fRF = 39 GHz, for Various Temperatures, at Maximum Gain
ADMV1014 Data Sheet
Rev. A | Page 24 of 42
OUTPUT DETECTOR PERFORMANCE
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set to 0x727C, Register 0x03, Bit 6 = 0, Register 0x03,
Bits[13:12] set to 11, and TA = 25°C, unless otherwise noted.
3.5
0
0.5
1.0
1.5
2.5
2.0
3.0
–40 –35 –25–30 –20 –15 –10
VDET (V)
RF INPUT POWER ( d Bm)
+85°C = 64
+85°C = 8
+85°C = 0
+25°C = 64
+25°C = 8
+25°C = 0
–40° C = 64
–40° C = 8
–40° C = 0
17172-090
Figure 87. VDET vs. RF Input Power, fRF = 28 GHz for Various Temperatures
and DET_PROG Settings
3.5
0
0.5
1.0
1.5
2.5
2.0
3.0
–40 –35 –25–30 –20 –15 –10
VDET (V)
RF INPUT POWER ( d Bm)
+85°C = 64
+85°C = 8
+85°C = 0
+25°C = 64
+25°C = 8
+25°C = 0
–40° C = 64
–40° C = 8
–40° C = 0
17172-091
Figure 88. VDET vs. RF Input Power, fRF = 39 GHz for Various Temperatures
and DET_PROG Settings
23 25 27 29 31 33 35 37 39 41 43 45
3.0
0.5
1.0
1.5
2.0
2.5
VDET (V)
RF INPUT FREQUE NCY (GHz )
–22
–27
–32
17172-089
Figure 89. VDET vs. RF Input Frequency at Various Input Power Levels,
DET_PROG = 8
5
–5
–4
–3
–2
2
0
4
1
–1
3
–40 –35 –25–30 –20 –15 –10
VDET L I NE ARI T Y E RRO R (dB)
RF I NPUT P O WER (dBm)
+85°C = 64
+85°C = 8
+85°C = 0
+25°C = 64
+25°C = 8
+25°C = 0
–40° C = 64
–40° C = 8
–40° C = 0
17172-093
Figure 90. VDET Linearity Error vs. RF Input Power, fRF = 28 GHz for Various
Temperatures and DET_PROG Settings
5
–5
–4
–3
–2
2
0
4
1
–1
3
–40 –35 –25–30 –20 –15 –10
VDET L I NE ARI T Y E RRO R (dB)
RF INPUT POW ER (dBm)
+85°C = 64
+85°C = 8
+85°C = 0
+25°C = 64
+25°C = 8
+25°C = 0
–40°C = 64
–40°C = 8
–40°C = 0
17172-094
Figure 91. VDET Linearity Error vs. RF Input Power, fRF = 39 GHz for Various
Temperatures and DET_PROG Settings
Data Sheet ADMV1014
Rev. A | Page 25 of 42
RETURN LOSS AND ISOLATIONS
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set to 0x727C, Register 0x03, Bits[13:12] are set to 11,
and TA = 25°C, unless otherwise noted.
Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 11 = 0, Register 0x03, Bit 8 = 1, unless otherwise noted.
Measurements in I/Q mode are measured as a composite of the I and Q channel performed, VCM = 1.15 V, Register 0x03, Bit 11 = 1, and
Register 0x03, Bit 8 = 0, unless otherwise noted.
0
–35
–15
–25
–5
–20
–30
–10
23 27 3531 39 4325 3329 37 41 45
RF RE TURN LOS S ( dB)
RF F REQUE NCY (GHz )
17172-095
Figure 92. RF Input Return Loss vs. RF Frequency
0
–35
–15
–25
–5
–20
–30
–10
46 1085971112
LO RETURN LOSS (dB)
LO FRE QUENCY ( GHz)
LO
N
LO
P
LO
DIFF
17172-096
Figure 93. LO Return Loss vs. LO Frequency
46 1085971112
–
50
–100
–65
–80
–55
–70
–90
–85
–75
–95
–60
LO TO RF LEAKAGE ( dBm)
LO INP UT FREQUE NCY (GHz )
LOx1 = +85° C
LOx1 = +25° C
LOx1 = – 40°C
LOx4 = +85° C
LOx4 = +25° C
LOx4 = – 40°C
17172-097
Figure 94. LO to RF Leakage vs. LO Input Frequency for Various Temperatures
at Different Gain Settings
0
–35
–15
–30
–5
–20
–25
–10
0
I/Q DIFFERENTIAL RE TURN LOSS (d B)
I/ Q FREQ UENCY ( G Hz)
I
Q
17172-098
1234567
Figure 95. I/Q Differential Return Loss vs. I/Q Frequency (Taken Without
Hybrids or Baluns)
0
–35
–15
–30
–5
–20
–25
–10
02 641537
IF RETURN LOSS (dB)
IF FRE QUENCY ( GHz)
IF_I
IF_Q
17172-099
Figure 96. IF Return Loss vs. IF Frequency (Taken Without Hybrid)
46 1085971112
–
50
–100
–65
–80
–55
–70
–90
–85
–75
–95
–60
LO TO IF LEAKAGE (dBm)
LO INPUT FREQUENCY (GHz)
17172-100
LOx1 = 1.8
LOx1 = 0.9
LOx1 = 0
LOx4 = 1.8
LOx4 = 0.9
LOx4 = 0
Figure 97. LO to IF Leakage vs. LO Input Frequency at Different VCTRL Settings
ADMV1014 Data Sheet
Rev. A | Page 26 of 42
46 1085971112
–
30
–80
–45
–60
–35
–50
–70
–65
–55
–75
–40
LO TO IF LEAKAGE ( dBm)
LO INP UT FREQ UENCY (GHz)
I = +85° C
I = +25° C
I = –40°C
Q = +85° C
Q = +25° C
Q = –40 °C
17172-101
Figure 98. LO to IF Leakage vs. LO Input Frequency at Various Temperatures
–
40
–90
–55
–70
–45
–60
–80
–75
–65
–85
–50
46 10812
LO TO I/Q LEAKAGE (dBm)
LO INPUT FREQUENCY (GHz)
17172-102
I_P = +85°C
I_P = +25°C
I_P = –40° C
I_N = +85°C
I_N = +25°C
I_N = –40° C
Q_P = +85°C
Q_P = +25°C
Q_P = –40°C
Q_N = +85°C
Q_N = +25°C
Q_N = –40°C
Figure 99. LO to I/Q Leakage vs. LO Input Frequency at Various Temperatures
(Taken Without Hybrid)
46 1085971112
–
30
–80
–45
–60
–35
–50
–70
–65
–55
–75
–40
LO TO IF LEAKAGE ( dBm)
LO INP UT FREQ UENCY (GHz)
I = 0
I = 1
I = 3
I = 7
I = 15
Q = 0
Q = 1
Q = 3
Q = 7
Q = 15
17172-103
Figure 100. LO to IF Leakage, vs. LO Input Frequency at Different IF Amplifier
Gain Settings (Taken Without Hybrid)
46 1085971112
–
40
–90
–55
–70
–45
–60
–80
–75
–65
–85
–50
FUNDAMENTAL LO TO I/Q LEAKAGE (dBm)
LO INPUT FREQUENCY (GHz)
I_P = 0
I_P = 3
I_N = 0
I_N = 3
Q_P = 0
Q_P = 3
Q_N = 0
Q_N = 3
17172-104
Figure 101. Fundamental LO to I/Q Leakage vs. LO Input Frequency at
Different Baseband Amplifier Gain Settings
Data Sheet ADMV1014
Rev. A | Page 27 of 42
M × N SPURIOUS PERFORMANCE
Mixer spurious products are measured in dBc from the IF
output power level. Spurious values are measured using the
following equation:
|(M × RF)+ (N × LO)|
N/A means not applicable. Blank cells in the spurious
performance tables indicate that the frequency is above 50 GHz
and is not measured.
The LO frequencies are referred from the frequencies applied
to the LO_x pin of the ADMV1014. RF amplitude = −30 dBm,
measurements performed with a 0 mV dc bias. VCC_MIXER =
VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_
IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set
to 0x727C, Register 0x03, Bits[13:12] are set to 11, and TA =
25°C, unless otherwise noted.
Measurements in IF mode performed with Register 0x03, Bit 11 = 0
and Register 0x03, Bit 8 = 1, unless otherwise noted.
The measurements in I/Q mode are as follows: VCM = 1.15 V,
Register 0x03, Bit 11 = 1, and Register 0x03, Bit 8 = 0, unless
otherwise noted.
I/Q Mode
Measurements are made on the I_P port. Data is taken without
any hybrids or baluns.
BB frequency (fBB) =100 MHz, LO= 6.975 GHz at 0 dBm, and
fRF = 28 GHz at −30 dBm.
N × LO
0 1 2 3 4 5 6 7 8
M × RF
−2 85 87 87 82 86 103 96 59
−1 61 90 54 46 0 45 52 106 82
0 N/A 43 55 65 48 76 78 81
+1 61 91 80 82
fBB = 100 MHz, LO= 9.725 GHz at 0 dBm, and fRF = 39 GHz at
−30 dBm.
N × LO
0 1 2 3 4 5 6 7 8
M × RF
−2 85 88 87 92 87 60
−1 63 92 56 47 0 51 61 85 84
0 N/A 42 48 67 51 85
+1 42 48
IF Mode
Measurements are made on the IF_I port. Data is taken without
any 90° hybrid.
IF frequency (fIF) = 3.5 GHz, LO= 6.125 GHz at 0 dBm, and
fRF = 28 GHz at −30 dBm.
N × LO
0 1 2 3 4 5 6 7 8
M × RF
−2 81 93 85 93 93 99 96 䤁
Ĥ
−1 66 94 89 63 0 44 46 92 78
0 N/A 45 43 65 54 71 64 80 58
+1 66 84 84 81
fIF = 3.5 GHz, LO= 8.875 GHz at 0 dBm, and fRF = 39 GHz at
−30 dBm.
N × LO
0 1 2 3 4 5 6 7 8
M × RF
−2 84 92 91 93 59
−1 62 93 81 71 0 39 91 92 89
0 N/A 47 68 75 50 75
+1 62 89
fIF = 3.5 GHz, LO= 7.875 GHz at 0 dBm, and fRF = 28 GHz at
−30 dBm.
N × LO
0 1 2 3 4 5 6 7 8
M × RF
−2 90 86 83 95 94 83 89 58
−1 70 93 70 41 0 65 90 89 83
0 N/A 47 62 66 49 74 86
+1 70 90 88
fIF = 3.5 GHz, LO= 10.5 GHz at 0 dBm, and fRF =39 GHz at
−30 dBm
N × LO
0 1 2 3 4 5 6 7 8
M × RF
−2 85 87 94 94 90 58
−1 61 91 81 35 0 87 84 84 82
0 N/A 39 51 62 53
+1 61 89
ADMV1014 Data Sheet
Rev. A | Page 28 of 42
THEORY OF OPERATION
The ADMV1014 is a wideband microwave downconverter
optimized for microwave radio designs operating in the 24 GHz
to 44 GHz frequency range. See Figure 1 for a functional block
diagram of the device. The ADMV1014 digital settings are
controlled via the SPI. The ADMV1014 has two modes of
operation:
Baseband quadrature demodulation (I/Q mode)
Image reject I/Q downconversion (IF mode)
START-UP SEQUENCE
The ADMV1014 SPI settings require its default settings to be
changed during startup for optimum performance. To use the
SPI, toggle the RST pin to logic low and then logic high to
perform a hard reset before starting up the device.
Set Register 0x0B to 0x727C after every power-up or reset. Set
Register 0x03, Bits[13:12] to 11 after every power-up or reset.
BASEBAND QUADRATURE DEMODULATION (I/Q
MODE)
In I/Q mode, the output impedance of the baseband I/Q ports is
100 Ω differential. These outputs are designed to be loaded to a
dc-coupled, differential, 100 Ω load. I_P and I_N are the
differential baseband I outputs. Q_P and Q_N are the
differential baseband Q outputs.
To set the ADMV1014 in I/Q mode, set BB_AMP_PD
(Register 0x03, Bit 8) to 0 and set IF_AMP_PD (Register 0x03,
Bit 11) to 1.
The baseband I/Q ports are designed to operate from dc to
6.0 GHz at each I and Q channel.
The BB output VCM can be changed from 1.05 V to 1.85 V. To
change the VCM, set BB_SWITCH_HIGH_LOW_COMMMON
(Register 0x0A, Bit 0) to be the opposite of Register 0x0A, Bit 6.
Also, set the MIXER_VGATE bit field (Register 0x07, Bits[15:9])
and the BB_AMP_REF_GEN bit field (Register 0x0A, Bits[6:3])
based on Table 6.
Table 6 provides the correct setting for these bit fields vs. the
required common-mode voltage.
The VCM can be further adjusted on each I or Q channel by
±15 mV by setting the BB_AMP_OFFSET_I bit field
(Register 0x09, Bits[4:0]) and the BB_AMP_OFFSET_Q bit field
(Register 0x09, Bits[9:5]) for each VCM setting shown in Table 6.
The most significant bit (MSB) for each bit field is the sign bit.
When the MSB is 1, the values of the four lower bits are
positive. When the MSB is 0, the values of the four lower bits
are negative. These bits also offer input IP2 and common-mode
rejection optimization.
The BB I/Q section of the ADMV1014 also features a baseband
amplifier with a digital attenuator that is controlled by setting
the BB_AMP_GAIN_CTRL bit field (Register 0x0A, Bits[2:1]).
Figure 44, Figure 45, and Figure 46 show the performance of the
baseband digital attenuator.
The Baseband Quadrature Demodulation to Very Low
Frequencies section shows the baseband performance to very
low demodulation frequencies.
Table 6. Common-Mode Voltage Settings
VCM (V)
MIXER_VGATE
(Register 0x07, Bits[15:9])
BB_AMP_REF_GEN
(Register 0x0A, Bits[6:3])
BB_SWITCH_HIGH_LOW_COMMON_MODE
(Register 0x0A, Bit 0)
1.05 1101010 0000 1
1.10 1101011 0001 1
1.15 1101100 0010 1
1.20 1101110 0011 1
1.25 1101111 0100 1
1.30 1110000 0101 1
1.35 1110001 0110 1
1.40 1110010 0111 1
1.50 1110101 1000 0
1.55 1110110 1001 0
1.60 1110111 1010 0
1.65 1111000 1011 0
1.70 1111010 1100 0
1.75 1111011 1101 0
1.80 0101100 1110 0
1.85 0101101 1111 0
Data Sheet ADMV1014
Rev. A | Page 29 of 42
IMAGE REJECTION DOWNCONVERSION
The ADMV1014 features the ability to downconvert to a real IF
output anywhere from 800 MHz to 6000 MHz, while suppressing
the unwanted image sideband by typically better than 30 dBc.
The IF outputs are quadrature to each other, 50 Ω single-ended,
and are internally ac coupled. IF_I and IF_Q are the quadrature IF
outputs. An external 90° hybrid is required to select the appropriate
sideband.
To configure the ADMV1014 in IF mode, set BB_AMP_PD
(Register 0x03, Bit 8) to 1 and set IF_AMP_PD (Register 0x03,
Bit 11) to 0
Each IF output features an amplifier with a digital attenuator.
The digital attenuator can be adjusted using fine or coarse steps.
The coarse steps for the IF_I can be adjusted using the IF_AMP_
COARSE_GAIN_I bit field (Register 0x08, Bits[11:8]). The coarse
steps for the IF_Q can be adjusted using the IF_AMP_COARSE_
GAIN_Q bit field (Register 0x09, Bits[15:12]). Each course gain
bit field has five settings. The fine steps for IF_I can be adjusted
using the IF_AMP_FINE_GAIN_I bit field (Register 0x08,
Bits[3:0]). The fine steps for the IF_Q can be adjusted using the
IF_AMP_FINE_GAIN_Q bit field (Register 0x08, Bits[7:4]).
Figure 77 to Figure 82 show the performance of these four bit
fields.
DETECTOR
The ADMV1014 features a square law detector that produces a
voltage linearly, according to the square of the RF voltage
output from the low noise amplifier. The detector can be
enabled by setting the DET_EN bit (Register 0x03, Bit 6) to 0. The
detector can be turned off by setting this bit to 1. The detector
linear range can be adjusted by setting the DET_PROG bit field
(Register 0x07, Bits[6:0]). These ranges are specified based on
the input power into the detector coming from the output of the
low noise amplifier. Each DET_PROG setting offers an
approximate 20 dB of ±1 dB dynamic range based on a two-
point linear regression from an ideal line for one temperature at
each DET_PROG setting. See Figure 89 to Figure 91 for more
performance information of the detector.
LO INPUT PATH
The LO input path operates from 5.4 GHz to 10.25 GHz with an
LO amplitude range of −6 dBm to +6 dBm. The LO has an
internal quadrupler (×4) and a programmable band-pass filter.
The LO band-pass filter is programmable using QUAD_FILTERS
(Register 0x04 Bits[3:0]). See the Performance at Different
Quad Filter Settings section for more information on the
QUAD_FILTERS settings.
The LO path can operate either differentially or single-ended
(SE). LOIP and LOIN are the inputs to the LO path. The LO
path can switch from differential to single-ended operation by
setting the QUAD_SE_MODE bits (Register 0x04, Bits[9:6]).
See the Performance Between Differential vs. Single-Ended LO
Input section for more information.
Figure 102 shows a block diagram of the LO path.
AMP 4 × LO _N
4 × LO_P
LO_N
LO_P ×4
17172-105
Figure 102. LO Path Block Diagram
Enable the quadrupler by setting the QUAD_IBIAS_PD bit
(Register 0x03, Bit 7) to 0 and the QUAD_BG_PD bit
(Register 0x03, Bit 9) to 0. To power down the quadrupler, set
both of these bits to 1.
An unwanted image can be downconverted from the
quadrature error in generating the quadrature LO signals.
Deviation from ideal quadrature (that is, total image rejection
and no image tone is downconverted) on these signals limits the
amount of achievable image rejection.
The ADMV1014 offers about 25° of quadrature phase
adjustment in the LO path quadrature signals. Make these
adjustments through the LOAMP_PH_ADJ_I_FINE bits
(Register 0x05, Bits[15:9]) and the LOAMP_PH_ADJ_Q_FINE
(Register 0x05, Bits[8:2]) bits. These bits reject the unwanted
sideband signal. In IF mode amplitude adjustments can be made
to the complex outputs via IF_AMP_FINE_GAIN_Q
(Register 0x08, Bits[7:4]) and IF_AMP_FINE_GAIN_I
(Register 0x08, Bits[3:0]) to further reduce the unwanted
sideband.
POWER-DOWN
The SPI of the ADMV1014 allows the user to power down
device circuits and reduce power consumption. There are two
power-down modes: band gap power-down mode (BG_PD)
and individual power-down circuits mode. The BG_PD bit
(Register 0x03, Bit 5) and the QUAD_BG_PD bit (Register 0x03,
Bit 9) power down the band gap circuit. The QUAD_IBIAS_PD
bit (Register 0x03, Bit 7) and the IBIAS_PD bit (Register 0x03,
Bit 14) power down the specific circuits.
Table 7 shows the circuits that are controlled by their related
power-down bit, the typical power savings, and the latency
requirement to power the circuits back up.
ADMV1014 Data Sheet
Rev. A | Page 30 of 42
Table 7. Power-Down Power and Latency Requirements
Bit Name Circuit
Typical Power
Savings (mW)
Power-Up
Latency (μs)
Power-Down
Latency (μs)
IBIAS_PD Receiver bias current (IBIAS) 1172 5 <1
QUAD_IBIAS_PD LO path 238 4 <1
BG_PD and QUAD_BG_PD Band gap 1423 4.5 <1
IBIAS_PD, IF_AMP_PD, QUAD_BG_PD,
BB_AMP_PD, QUAD_IBIAS_PD, BG_PD
Entire chip 1435 5 <1
123456789101112131415161718192021222324
SCLK
SDI D11R/WA5A4A3A2A1A0D15D14D13D12 PD10D9D8D7D6D5D4D3D2D1D0
SEN
17172-107
Figure 103. Write Serial Port Timing Diagram
1 2 3 4 5 6 7 8 9 101112131415161718192021222324
S
CLK
SDI
SDO D0 PD5 D4 D3 D2 D1D10D9D8D7D6D15D14D13D12D11
A1 A0R/WA5A4A3A2
SEN
17172-108
Figure 104. Read Serial Port Timing Diagram
SERIAL PORT INTERFACE (SPI)
The SPI of the ADMV1014 allows the user to configure the device
for specific functions or operations via a 4-pin SPI port. This
interface provides users with added flexibility and customization.
The SPI consists of four control lines: SCLK, SDIN, SDO, and
SEN.
The ADMV1014 protocol consists of a write/read bit followed
by six register address bits, 16 data bits, and a parity bit. Both
the address and data fields are organized most significant bit
(MSB) first and end with the least significant bit. For a write, set
the first bit to 0. For a read, set the first bit to 1.
The write cycle sampling must be performed on the rising edge.
The 16 bits of the serial write data are shifted in, MSB to Lower
Sideband. The ADMV1014 input logic level for the write cycle
supports an 1.8 V interface.
For a read cycle, up to 16 bits of serial read data are shifted out,
MSB first. After the 16 bits of data shift out, the parity bit shifts
out. The output logic level for a read cycle is 1.8 V.
The parity bit always follows the direction of the data. If parity
is not used, the transmitting end transmits zero instead of parity.
The parity is odd, which means that the total number of ones
transmitted during a command, including the read/write bit,
the address bit, the data bit, and the parity bit, must be odd.
Figure 103 and Figure 104 show the SPI write and read
protocol, respectively.
Data Sheet ADMV1014
Rev. A | Page 31 of 42
APPLICATIONS INFORMATION
ERROR VECTOR MAGNITUDE (EVM)
PERFORMANCE
Figure 105 shows the EVM vs. input power performance of the
ADMV1014 in IF mode at maximum gain, upper sideband,
25°C and 0 dBm LO input power. The EVM measurement was
performed using four 100 MHz, 5G-NR, 256QAM waveforms.
The EVM shown is the average of the four channels. The EVM
of the test equipment was not de-embedded.
Figure 106 shows the constellation diagram and EVM statistics
of each of the four channels at −30 dBm input power.
–45 –40 –35 –30 –25 –20 –15
P
IN
(dBm)
EVM (%)
1.8
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
17172-109
Figure 105. EVM vs. Input Power at 28 GHz, VCTRL = 0 V, TA = 25°C,
LO = 0 dBm, Upper Sideband (Low-Side LO), IF = 3.5 GHz
17172-110
Figure 106. Constellation Diagram and EVM Statistics per Channel
ADMV1014 Data Sheet
Rev. A | Page 32 of 42
BASEBAND QUADRATURE DEMODULATION TO
VERY LOW FREQUENCIES
Figure 107 to Figure 111 show the I/Q mode performance at
low baseband frequencies. The measurements were performed
at 28 GHz, −25 dBm input power, VCM = 1.15 V, Register 0x03,
Bit 11 = 1, Register 0x03, Bit 8 = 0, 6 dBm LO input power, and
TA = 25°C.
350
0
100
250
50
150
200
300
1100M10M1M100k10k1k10010
I AND Q DI FFERENT IAL P E AK- TO - PEAK VOLTAG E
BASEBAND FREQUENCY ( Hz)
Q DI F FERE NTI AL
I DI FF E RENTI AL
17172-111
Figure 107. I and Q Differential Peak-to-Peak Voltage vs. Baseband Frequency
20
0
6
14
5
7
10
18
12
8
16
1100M10M1M100k10k1k10010
CONVERSION GAIN (dB)
BASEBAN D FREQUEN CY (Hz)
Q GAIN
I GAIN
17172-112
Figure 108. Conversion Gain vs. Baseband Frequency
5
0
2
4
1
3
AMPL ITUDE I MBALANCE (dB)/
PHASE IMBAL ANCE ( Deg rees)
BASEBAND FREQ UENCY ( Hz )
AMPLITUDE I M BALANCE
PHASE IM BALANCE
1 100M10M1M100k10k1k10010
17172-113
Figure 109. Amplitude Imbalance and Phase Imbalance vs. Baseband Frequency
BASEBAND FREQUENCY ( Hz )
IM AGE RE JE CT
50
0
10
20
30
40
45
5
15
25
35
IMAGE REJE CTION (dBc)
1 100M10M1M100k10k1k10010
17172-114
Figure 110. Image Rejection vs. Baseband Frequency
350
0
100
250
50
150
200
300
1 100M10M1M100k10k1k10010
DC OFFSET ERROR (mV)
BASEBAND FREQUENCY ( Hz )
Q DIF FERE NTI AL
I DIF FERE NTI AL
17172-111
Figure 111. DC Offset Error vs. Baseband Frequency
PERFORMANCE AT DIFFERENT QUAD FILTER
SETTINGS
Figure 112 shows the conversion gain vs. RF frequency in IF
mode at 25°C and LO input power = 6 dBm, for different
QUAD_FILTERS settings. Figure 113 shows the LO to IF_I and
LO to IF_Q leakage vs. LO frequency at different quad filter
settings.
23 25 27 29 31 33 35 37 39 41 43 45
RF F REQUENCY (G Hz )
QUAD_FILT E RS = 0
QUAD_FILT E RS = 5
QUAD_FILTERS = 10
QUAD_FILTERS = 15
25
–30
–25
–20
–15
–10
–5
0
5
10
15
20
CONVERSION GAIN (dB)
17172-116
Figure 112. Conversion Gain vs. RF Frequency for Four Different
QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband)
Data Sheet ADMV1014
Rev. A | Page 33 of 42
456789101112
LO FREQUE NCY (G Hz)
IF I: QUAD_ FILT ERS = 0
IF I: QUAD_ FILT ERS = 5
IF I: QUAD_ FILT ERS = 10
IF I: QUAD_ FILT ERS = 15
IF Q : Q UAD_FI L TERS = 0
IF Q : Q UAD_FI L TERS = 5
IF Q : Q UAD_FI L TERS = 10
IF Q : Q UAD_FI L TERS = 15
–
40
–80
–75
–65
–55
–45
–70
–60
–50
LO TO IF LEAKAGE ( dBm)
17172-117
Figure 113. LO To IF Leakage vs. RF Frequency for Four Different
QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband)
VVA TEMPERATURE COMPENSATION
Figure 114 shows the conversion gain vs. RF frequency at two
different Register 0x0B settings and three different temperatures
for IF mode. The recommended value suggested in the Start-Up
Sequence section provides the highest conversion gain. If the
priority is to decrease the conversion gain variation across
temperature, Register 0x0B can be set to 0x726C. However, at
this value, the conversion gain is lower at each temperature.
23 25 27 29 31 33 35 37 39 41 43 45
RF FREQUENCY ( GHz)
+85° C AT REG 0x0B = 0x7 27C
+25° C AT REG 0x0B = 0x7 27C
–40°C AT REG 0x0B = 0x7 27C
+85° C AT REG 0x0B = 0x7 26C
+25° C AT REG 0x0B = 0x7 26C
–40°C AT REG 0x0B = 0x7 26C
25
–10
–5
0
5
10
15
20
CONVERSION GAIN (dB)
17172-118
Figure 114. Conversion Gain vs. RF Frequency at Maximum Gain for Various
Register 0x0B Settings and Various Temperatures
PERFORMANCE BETWEEN DIFFERENTIAL vs.
SINGLE-ENDED LO INPUT
Figure 115 to Figure 117 show the conversion gain, input IP3
and image rejection performance for operating the ADMV1014
LO input as differential vs. SE. The measurements were
performed with 0 dBm LO input power, IF mode, with an IF
frequency of 3.5 GHz, upper sideband, and TA = 25°C.
23 25 27 29 31 33 35 37 39 41 43 45
RF F REQUENCY (GHz)
LO DIFF
LO SE P SI DE
LO SE N SI DE
25
0
5
10
15
20
CONVERSION GAIN (dB)
17172-119
Figure 115. Conversion Gain vs. RF Frequency for Three Different LO Mode
Settings, fIF = 3.5 GHz (Upper Sideband)
23 25 27 29 31 33 35 37 39 41 43 45
RF F REQUENCY (GHz)
10
–10
–8
–6
–4
–2
0
2
4
6
8
INPUT IP3 (dBm)
LO DIFF
LO SE P SI DE
LO SE N SI DE
17172-120
Figure 116. Input IP3 vs. RF Frequency for Three Different LO Mode Settings,
RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz
(Upper Sideband)
ADMV1014 Data Sheet
Rev. A | Page 34 of 42
24 26 28 30 32 34 36 38 40 42 44
RF INPUT FREQ UENCY (GHz )
40
0
10
20
30
5
15
25
35
IM AGE RE J E CTI ON (dBc)
17172-121
LO DIFF
LO SE P SIDE
LO SE N SIDE
Figure 117. Image Rejection vs. RF Input Frequency for Three Different LO
Mode Settings, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fIF = 3.5 GHz (Upper Sideband)
PERFORMANCE ACROSS RF FREQUENCY AT FIXED
IF AND BASEBAND FREQUENCIES
The ADMV1014 quadrupler operates from 21.6 GHz to
41 GHz. When using high-side LO injection, the conversion
gain starts rolling off gradually after the quadrupler frequency
reaches 41 GHz. When using low-side LO, the conversion gain
starts rolling off when the quadrupler frequency is 21.6 GHz.
Figure 118 and Figure 119 show the conversion gain vs. RF
frequency in IF mode for fixed IF frequencies (TA = 25°C, LO =
6 dBm) for upper sideband and lower sideband, respectively.
Figure 120 and Figure 121 show the conversion gain vs. RF
frequency in IQ mode for fixed BB frequencies (TA = 25°C, LO =
6 dBm) for upper sideband and lower sideband, respectively.
23 25 27 29 31 33 35 37 39 41 43 45
RF F REQUENCY (G Hz )
0.8GHz UPPER SIDEBAND
1.0GHz UPPER SIDEBAND
2.0GHz UPPER SIDEBAND
3.0GHz UPPER SIDEBAND
4.0GHz UPPER SIDEBAND
5.0GHz UPPER SIDEBAND
6.0GHz UPPER SIDEBAND
CONVERSION GAIN (dB)
25
–30
–25
–20
–15
–10
–5
0
5
10
15
20
17172-122
Figure 118. Conversion Gain vs. RF Frequency for Multiple IF Frequency
Settings (Upper Sideband)
23 25 27 29 31 33 35 37 39 41 43 45
RF F REQUENCY (G Hz )
CONVERSION GAIN (dB)
30
–70
–60
–50
–40
–30
–20
–10
0
10
20
17172-123
0.8GHz LO WER S IDEBAND
1.0GHz LO WER S IDEBAND
2.0GHz LO WER S IDEBAND
3.0GHz LO WER S IDEBAND
4.0GHz LO WER S IDEBAND
5.0GHz LO WER S IDEBAND
6.0GHz LO WER S IDEBAND
Figure 119. Conversion Gain vs. RF Frequency at Multiple IF Frequency
Settings (Lower Sideband)
23 25 27 29 31 33 35 37 39 41 43 45
RF F REQUENCY (G Hz )
CONVERSION GAIN (dB)
25
–30
–25
–20
–15
–10
–5
0
5
10
15
20
17172-124
0.8GHz UPPER SIDEBAND
1.0GHz UPPER SIDEBAND
2.0GHz UPPER SIDEBAND
3.0GHz UPPER SIDEBAND
4.0GHz UPPER SIDEBAND
5.0GHz UPPER SIDEBAND
6.0GHz UPPER SIDEBAND
Figure 120. Conversion Gain vs. RF Frequency at Multiple I/Q Frequency
Settings (Upper Sideband)
23 25 27 29 31 33 35 37 39 41 43 45
RF F REQUENCY (G Hz )
CONVERSION GAIN (dB)
30
–60
–50
–40
–30
–20
–10
0
10
20
17172-125
0.8GHz LOWER S IDEBAND
1.0GHz LOWER S IDEBAND
2.0GHz LOWER S IDEBAND
3.0GHz LOWER S IDEBAND
4.0GHz LOWER S IDEBAND
5.0GHz LOWER S IDEBAND
6.0GHz LOWER S IDEBAND
Figure 121. Conversion Gain vs. RF Frequency at Multiple IQ Frequency
Settings (Lower Sideband)
Data Sheet ADMV1014
Rev. A | Page 35 of 42
RECOMMENDED LAND PATTERN
Solder the exposed pad on the underside of the ADMV1014 to a
low thermal and electrical impedance ground plane. This pad is
typically soldered to an exposed opening in the solder mask on
the evaluation board. Connect these ground vias to all other
ground layers on the evaluation board to maximize heat
dissipation from the device package.
17172-126
Figure 122. Evaluation Board Layout for the LGA package
EVALUATION BOARD INFORMATION
For more information about the ADMV1014 evaluation board,
refer to the ADMV1014-EVALZ user guide.
ADMV1014 Data Sheet
Rev. A | Page 36 of 42
REGISTER SUMMARY
Table 8. Register Summary
Reg. Name Bits
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00 SPI_CONTROL [15:8] PARITY_EN SPI_SOFT_
RESET
RESERVED CHIP_ID[7:4] 0x0093 R/W
[7:0] CHIP_ID[3:0] REVISION
0x01 ALARM [15:8] PARITY_
ERROR
TOO_FEW_
ERRORS
TOO_MANY_
ERRORS
ADDRESS
_RANGE_
ERROR
RESERVED 0x0000 R
[7:0] RESERVED
0x02 ALARM_MASKS [15:8] PARITY_
ERROR_MASK
TOO_
FEW_
ERRORS_
MASK
TOO_MANY_
ERRORS_
MASK
ADDRESS
_RANGE_
ERROR_
MASK
RESERVED 0xFFFF R/W
[7:0] RESERVED
0x03 ENABLE [15:8] RESERVED IBIAS_PD P1DB_COMPENSATION IF_AMP_
PD
RESERVED QUAD_
BG_PD
BB_AMP_
PD
0x0157 R/W
[7:0]
QUAD_IBIAS_
PD
DET_EN BG_PD RESERVED
0x04 QUAD [15:8] RESERVED QUAD_SE_MODE[3:2] 0x5700 R/W
[7:0] QUAD_SE_MODE[1:0] RESERVED QUAD_FILTERS
0x05 LO_AMP_
PHASE_
ADJUST1
[15:8] LOAMP_PH_ADJ_I_FINE
LOAMP_
PH_ADJ_
Q_FINE[6]
0x4101 R/W
[7:0] LOAMP_PH_ADJ_Q_FINE[5:0] RESERVED
0x07 MIXER [15:8] MIXER_VGATE RESERVED 0xD808 R/W
[7:0] RESERVED DET_PROG
0x08 IF_AMP [15:8] RESERVED IF_AMP_COARSE_GAIN_I 0x0000 R/W
[7:0] IF_AMP_FINE_GAIN_Q IF_AMP_FINE_GAIN_I
0x09 IF_AMP_BB_
AMP
[15:8] IF_AMP_COARSE_GAIN_Q RESERVED BB_AMP_OFFSET_Q[4:3] 0x0000 R/W
[7:0] BB_AMP_OFFSET_Q[2:0] BB_AMP_OFFSET_I
0x0A BB_AMP__AGC [15:8] RESERVED 0x2390 R/W
[7:0] RESERVED BB_AMP_REF_GEN BB_AMP_GAIN_CTRL
BB_
SWITCH_
HIGH_
LOW_
COMMON_
MODE
0x0B VVA_TEMP_
COMP
[15:8] VVA_TEMPERATURE_COMPENSATION[15:8] 0x4A5C R/W
[7:0] VVA_TEMPERATURE_COMPENSATION[7:0]
Data Sheet ADMV1014
Rev. A | Page 37 of 42
REGISTER DETAILS
Address: 0x00, Reset: 0x0093, Name: SPI_CONTROL
Enable the Parity for Write Ex ecution Revision ID
SPI Soft Reset Chip ID
0
1
1
1
2
0
3
0
4
1
5
0
6
0
7
1
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
[15] P ARITY_EN ( R/ W) [3:0] REVI S ION (R)
[14] S PI_SO FT_RESET (R/ W) [11:4] CHIP _ID ( R)
[13:12] RESERVED
Table 9. Bit Descriptions for SPI_CONTROL
Bits Bit Name Settings Description Reset Access
15 PARITY_EN Enable the Parity for Write Execution 0x0 R/W
14 SPI_SOFT_RESET SPI Soft Reset 0x0 R/W
[13:12] RESERVED Reserved 0x0 R
[11:4] CHIP_ID Chip ID 0x9 R
[3:0] REVISION Revision ID 0x3 R
Address: 0x01, Reset: 0x0000, Name: ALARM
Parity Error
Too Few Errors Address Range Err or
Too_Many_Errors
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
[15] PARITY_ERROR (R) [11:0] RESERVED
[14] TOO_FEW_ERRORS (R ) [12] ADDRESS_RANG E_ERROR (R)
[13] TOO_MANY_E R R OR S (R)
Table 10. Bit Descriptions for ALARM
Bits Bit Name Settings Description Reset Access
15 PARITY_ERROR Parity Error 0x0 R
14 TOO_FEW_ERRORS Too Few Errors 0x0 R
13 TOO_MANY_ERRORS Too Many Errors 0x0 R
12 ADDRESS_RANGE_ERROR Address Range Error 0x0 R
[11:0] RESERVED Reserved 0x0 R
Address: 0x02, Reset: 0xFFFF, Name: ALARM_MASKS
Parity Error M ask
Too Few Errors Mask Address Range Err or Mask
Too Many Er rors M ask
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
1
10
1
11
1
12
1
13
1
14
1
15
1
[15] PARITY_ERROR_MASK (R/W) [11:0] RESERVED
[14] TOO_F E W_ERRORS_MASK (R/W) [12] ADDRE SS_RANG E _ERROR_MASK (R/W)
[13] TOO_MANY_ERRORS_MASK (R/W)
Table 11. Bit Descriptions for ALARM_MASKS
Bits Bit Name Settings Description Reset Access
15 PARITY_ERROR_MASK Parity Error Mask 0x1 R/W
14 TOO_FEW_ERRORS_MASK Too Few Errors Mask 0x1 R/W
13 TOO_MANY_ERRORS_MASK Too Many Errors Mask 0x1 R/W
12 ADDRESS_RANGE_ERROR_MASK Address Range Error Mask 0x1 R/W
[11:0] RESERVED Reserved 0xFFF R
ADMV1014 Data Sheet
Rev. A | Page 38 of 42
Address: 0x03, Reset: 0x0157, Name: ENABLE
Power Down th e RX I bia s Power Down the RX BG
Turn on bits to optimize P1dB Digital RX Detector Enable
Powe r Down the IF Amp Powe r Down the Q uadrupler B i as
Current.
Powe r Down the Ba se-Ba nd Amp
Power Down the Quadrupler B andGap
0
1
1
1
2
1
3
0
4
1
5
0
6
1
7
0
8
1
9
0
10
0
11
0
12
0
13
0
14
0
15
0
[15] RESE RVE D [4: 0] RESERVED
[14] IBIAS_PD (R/W) [5] BG_PD (R/W)
[13: 12] P1DB_COMPE NSATION (R/W) [6] DE T_EN (R/W)
[11] IF _AMP_PD (R/W) [7] QUAD_IBIAS_PD (R/W)
[10] RESE RVE D [8] BB_AMP _PD (R/W)
[9] QUAD_BG_PD (R/W)
Table 12. Bit Descriptions for ENABLE
Bits Bit Name Settings Description Reset Access
15 RESERVED Reserved 0x0 R
14 IBIAS_PD Power Down the Rx IBIAS 0x0 R/W
[13:12] P1DB_COMPENSATION Turn on bits to optimize P1dB 0x0 R/W
11 IF_AMP_PD Power Down the IF Amp 0x0 R/W
10 RESERVED Reserved 0x0 R
9 QUAD_BG_PD Power Down the Quadrupler Band Gap 0x0 R/W
8 BB_AMP_PD Power Down the Baseband Amp 0x1 R/W
7 QUAD_IBIAS_PD Power Down the Quadrupler Bias Current 0x0 R/W
6 DET_EN Digital Rx Detector Enable 0x1 R/W
5 BG_PD Power Down the Rx BG 0x0 R/W
[4:0] RESERVED Reserved 0x1 R
Address: 0x04, Reset: 0x5700, Name: QUAD
LO Filter s BW S elec tion
1111: LO F requency BW: 5. 4 to 7GHz.
1010: LO Frequency BW: 5.4 to 8GHz.
0101: LO Frequency BW: 6.6 to 9.2GHz.
0000: LO Frequency BW: 8.625 to 10.25GHz.
Switch Different ial/SE Modes
1100: Different ial Mode.
1001: SE_Mode_P_Side.
0110: SE_Mode_N_Side.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
1
9
1
10
1
11
0
12
1
13
0
14
1
15
0
[15: 10] RESE RVED [3:0] QU AD_FILT ER S (R / W)
[9:6] QUAD _SE_MODE (R/W)
[5:4] R ESERVED
Table 13. Bit Descriptions for QUAD
Bits Bit Name Settings Description Reset Access
[15:10] RESERVED Reserved 0x15 R
[9:6] QUAD_SE_MODE Switch Differential/SE Modes 0xC R/W
0110 SE Mode N Side
1001 SE Mode P Side
1100 Differential Mode
[5:4] RESERVED Reserved. 0x0 R
[3:0] QUAD_FILTERS LO Filters BW Selection 0x0 R/W
0000 LO Frequency BW: 8.625 GHz to 10.25 GHz
0101 LO Frequency BW: 6.6 GHz to 9.2 GHz
1010 LO Frequency BW: 5.4 GHz to 8 GHz
1111 LO Frequency BW: 5.4 GHz to 7 GHz
Data Sheet ADMV1014
Rev. A | Page 39 of 42
Address: 0x05, Reset: 0x4101, Name: LO_AMP_PHASE_ADJUST1
Mixer Image Reject ion Calibr ation
0x00: Maximum Phase, 0x7F: Minimum
Phase
Mixer Image Reject ion Calibr ation
0x00: Maximum Phase, 0x7F: Minimum
Phase
0
1
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
1
9
0
10
0
11
0
12
0
13
0
14
1
15
0
[15:9] L OA M P_P H_AD J_I_FI NE (R/W) [1:0] RESERVED
[8:2] L OA M P _P H_A DJ_Q_FI NE (R/ W)
Table 14. Bit Descriptions for LO_AMP_PHASE_ADJUST1
Bits Bit Name Settings Description Reset Access
[15:9] LOAMP_PH_ADJ_I_FINE Mixer Image Rejection Calibration 0x00: Maximum Phase, 0x7F:
Minimum Phase
0x20 R/W
[8:2] LOAMP_PH_ADJ_Q_FINE Mixer Image Rejection Calibration 0x0: Maximum Phase, 0x7F:
Minimum Phase
0x40 R/W
[1:0] RESERVED Reserved. 0x1 R
Address: 0x07, Reset: 0xD808, Name: MIXER
Control BB Common Mode Volt age
(P lease see the applic ation section
for more Information)
Digit al RX Det ec tor Pr ogr am
1000000: Fr om -18 t o - 2dBm.
100000: Fr om -17 t o - 1dBm.
10000: Fr om -16. 25 to -0.25dB m.
1000: From -15.5 t o +0. 5dB m.
100: From -15 to +1dB m.
10: From -14 to +2dB m.
1: From -13 to +3dB m.
0: From -12 to +4dB m.
0
0
1
0
2
0
3
1
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
1
12
1
13
0
14
1
15
1
[15: 9] MIXER_VGATE (R/W) [6:0] DE T_PROG (R/W)
[8:7] R ESERVED
Table 15. Bit Descriptions for MIXER
Bits Bit Name Settings Description Reset Access
[15:9] MIXER_VGATE Control BB Common Mode Voltage. See the Applications Information section for
more information)
0x6C R/W
[8:7] RESERVED Reserved. 0x0 R
[6:0] DET_PROG Digital Rx Detector Program. 0x8 R/W
0 From −12 dBm to +4 dBm.
1 From −13 dBm to +3 dBm.
10 From −14 dBm to +2 dBm.
100 From −15 dBm to +1 dBm.
1000 From −15.5 dBm to +0.5 dBm.
10000 From −16.25 dBm to −0.25 dBm.
100000 From −17 dBm to −1 dBm.
1000000 From −18 dBm to −2 dBm.
ADMV1014 Data Sheet
Rev. A | Page 40 of 42
Address: 0x08, Reset: 0x0000, Name: IF_AMP
IF A mp I, 10 Fine Steps from 0x0 to
0xA (Total attenuation ~1dB). Refer
t o Figure 80 t o Figure 82.
Digit al IF Amp 1dB Step Gain_I
1111: Refer to Figur e 77 to Figur e 79.
111: Ref er to Figur e 77 to Figur e 79.
11: Ref er to Figure 77 to Figur e 79.
1: Ref er to Figure 77 to Figur e 79.
0: Ref er to Figure 77 to Figur e 79.
IF A mp Q, 10 Fine Steps from 0x0
to 0xA (Total attenuation ~1dB). Refe
r
t o Figure 80 t o Figure 82.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
[15:12] RESERVED [3:0] I F_AM P _FINE_GAIN _I (R/ W)
[11:8] I F_AMP_CO ARSE_GA IN _I (R/W)
[7: 4] IF_AMP_FINE _GAIN_Q (R/W)
Table 16. Bit Descriptions for IF_AMP
Bits Bit Name Settings Description Reset Access
[15:12] RESERVED Reserved. 0x0 R
[11:8] IF_AMP_COARSE_GAIN_I Digital IF Amp Step Gain I. 0x0 R/W
0 Refer to Figure 77 to Figure 79.
1 Refer to Figure 77 to Figure 79.
11 Refer to Figure 77 to Figure 79.
111 Refer to Figure 77 to Figure 79.
1111 Refer to Figure 77 to Figure 79.
[7:4] IF_AMP_FINE_GAIN_Q IF Amp Q, 10 Fine Steps from 0x0 to 0xA. Refer to Figure 80 to Figure 82. 0x0 R/W
[3:0] IF_AMP_FINE_GAIN_I IF Amp I, 10 Fine Steps from 0x0 to 0xA. Refer to Figure 80 to Figure 82. 0x0 R/W
Address: 0x9, Reset: 0x0000, Name: IF_AMP__BB_AMP
Digit al IF Amp 1dB Step G ain_Q
1111: Ref er to Figur e 77 to Figur e 79.
111: Refer to Figur e 77 to Figur e 79.
11: Refer t o F i gur e 77 t o Figure 79.
1: Refer t o Figure 77 t o Figure 79.
0: Refer t o Figure 77 t o Figure 79. BB A mp I. Bit 4: Use as Sign Bit, b’1
is f or positive values and b’0 is for
negative values; B its [ 3:0] Minimum
Offset, 0xF: Max imum Offset.
BB Amp Q. Bit 9: Use as Sign Bit,
b’1is for posit ive values and b’0 is
for negat ive values; Bit [8:5] Minimum
Offset, 0xF: Max imum Offset.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
[15:12] IF_AMP_COARSE_GA IN_Q ( R/W) [4:0] BB _AMP_OFFSET_I (R/W)
[11:10] RESERVED
[9: 5] B B_A MP_OFFSET_Q (R / W)
Table 17. Bit Descriptions for IF_AMP__BB_AMP
Bits Bit Name Settings Description Reset Access
[15:12] IF_AMP_COARSE_GAIN_Q Digital IF Amp 1 dB Step Gain Q 0x0 R/W
0 Refer to Figure 77 to Figure 79
1 Refer to Figure 77 to Figure 79
11 Refer to Figure 77 to Figure 79
111 Refer to Figure 77 to Figure 79
1111 Refer to Figure 77 to Figure 79
[11:10] RESERVED Reserved. 0x0 R
[9:5] BB_AMP_OFFSET_Q BB Amp Q (Bit 9: Use as Sign Bit, 1 is for positive values and 0 is for
negative values; Bits[8:5]: Minimum Offset, 0xF: Maximum Offset)
0x0 R/W
[4:0] BB_AMP_OFFSET_I BB Amp I (Bit 4: Use as Sign Bit, 1 is for positive values and 0 is for
negative values; Bits[3:0]: Minimum Offset, 0xF: Maximum Offset)
0x0 R/W
Data Sheet ADMV1014
Rev. A | Page 41 of 42
Address: 0x0A, Reset: 0x2390, Name: BB_AMP_AGC
Setting bet ween High and Low Out put
Common Mode Voltage; S hould B e
Set to Opposite from RegA<bit6>
Control BB Common M ode Voltage
See t he B aseband Q uadrature Demodulat ion
(I/Q Mode) section for more information. See Figure 44 to Figure 46.
0
0
1
0
2
0
3
0
4
1
5
0
6
0
7
1
8
1
9
1
10
0
11
0
12
0
13
1
14
0
15
0
[15:7] RESERVED [0] BB_SWITCH_HIG H_LOW_COMMON_MODE (R/W)
[6:3] BB _AMP_REF_GEN (R /W)
[2:1] BB_AMP_GAIN_CTRL (R/W)
Table 18. Bit Descriptions for BB_AMP_AGC
Bits Bit Name Settings Description Reset Access
[15:7] RESERVED Reserved. 0x4 R
[6:3] BB_AMP_REF_GEN Control BB Common-Mode Voltage. See the
Baseband Quadrature Demodulation (I/Q Mode)
section for more information.
0x2 R/W
[2:1] BB_AMP_GAIN_CTRL See Figure 44 to Figure 46. 0x0 R/W
0 BB_SWITCH_HIGH_LOW_COMMON_MODE Setting between High and Low Output Common-
Mode Voltage. This bit must be set to opposite from
Register 0x0A, Bit 6. See the Baseband Quadrature
Demodulation (I/Q Mode) section for more
information.
0x0 R/W
Address: 0x0B, Reset: 0x4A5C, Name: VVA_TEMP_COMP
VVA Temperature Compensat i on
0
0
1
0
2
1
3
1
4
1
5
0
6
1
7
0
8
0
9
1
10
0
11
1
12
0
13
0
14
1
15
0
[15:0] VVA_TEMPPERATURE_COMPENSATION (R/W)
Table 19. Bit Descriptions for VVA_TEMP_COMP
Bits Bit Name Settings Description Reset Access
[15:0] VVA_TEMPERATURE_COMPENSATION VVA Temperature Compensation. Set to 0x727C. See the
Start-Up Sequence section and the VVA Temperature
Compensation section for more information. Disable
PARITY_EN when updating the VVA temperature
compensation.
0x4A5C R/W
ADMV1014 Data Sheet
Rev. A | Page 42 of 42
OUTLINE DIMENSIONS
02-12-2018-A
PKG-005727
5.10
5.00
4.90
TOP VIEW
SIDE VI EW
BO TTO M VIEW
1
8
9
16
17
24
25 32
0.50
BSC
0.75
BSC 0.165
BSC
0.275
REF
3.50 REF
SQ
0.40
0.35
0.30
0.32
0.27
0.22
FO R P RO PE R CO NNECT IO N O F
THE EXPOSED PADS, REFER TO
THE P I N CO NF I GURATION AND
FUNCT IO N DE S CRIPT IO NS
SECT ION OF THIS DATA SHEET.
0.81 BS C
SQ
PIN 1
INDIC
ATOR
3.57 BSC
SQ
3.77 BSC
PIN 1
CO RNE R ARE A
0.75 MAX
0.67 NO M
0.52
0.45
0.38
0.25
0.22
0.19
SEATING
PLANE
Figure 123. 32-Terminal Land Grid Array [LGA]
(CC-32-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADMV1014ACCZ −40°C to +85°C 32-Terminal Land Grid Array Package [LGA] CC-32-6
ADMV1014ACCZ-R7 −40°C to +85°C 32-Terminal Land Grid Array Package [LGA] CC-32-6
ADMV1014-EVALZ Evaluation Board
1 Z = RoHS-Compliant Part.
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17172-0-4/19(A)
