PMC-Sierra,Inc. Preliminary PM7380 FREEDM-32P672 Frame Engine and Data Link Manager FEATURES The FREEDM32P672 chip offers the following features: * Single-chip multi-channel HDLC controller with a 66 MHz, 32-bit Peripheral Component Interconnect (PCI) 2.1 compliant bus for configuration, monitoring, and transfer of packet data. * An on-chip DMA controller with scatter/ gather capabilities. * Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 H-MVIP digital telephony buses (at 2.048 Mbit/s per link) or 8 H-MVIP buses (at 8.192 Mbit/s per link). * Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 channelized T1/J1 or E1 links. * The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1). * Supports up to 32 bi-directional HDLC channels, each assigned to an unchannelized arbitrary-rate link, subject to a maximum aggregate link clock-rate of 64 MHz in each direction. * Channels assigned to links 0 to 2 support a clock rate of up to 52 MHz. Channels assigned to links 3 to 31 support a clock rate of up to 10 MHz. * In the special case, where no more than three high-speed links are used, the maximum aggregate link clock-rate is 156 MHz. * Links configured for channelized T1/ J1/E1 or unchannelized operation support the gapped-clock method for determining time-slots, which is backwards compatible with the FREEDM-8 and FREEDM-32 devices. * For each channel, the HDLC receiver supports programmable flag-sequence detection, bit de-stuffing, and frame-check sequence validation. * The receiver supports the validation of both CRC-CCITT and CRC-32 frame-check sequences. * For each channel, the HDLC transmitter supports programmable flag-sequence generation, bit stuffing and frame-check sequence generation. * The transmitter supports the generation of both CRC-CCITT and CRC-32 frame-check sequences. * The transmitter also aborts packets under the direction of the host, or automatically when the channel underflows. * Provides 32 kbytes of on-chip memory for partial-packet buffering in both the transmit and receive directions. RBD RBCLK RSTB SYSCLK PMCTEST BLOCK DIAGRAM RD[31:0] RCLK[31:0] RFPB[3:0] RMVCK[3:0] RMV8DC RMV8FPC RFP8B TD[31:0] TCLK[31:0] TFPB[3:0] TMVCK[3:0] TMV8DC TMV8FPC TFP8B Receive Channel Assigner (RCAS672) Receive HDLC Processor (RHDL672) 32 k Receive Partial Packet Buffer Receive DMA Controller (RMAC672) Performance Monitor (PMON) Transmit Channel Assigner (TCAS672) Transmit HDLC Processor (THDL672) 32 k Transmit Partial Packet Buffer PCI Controller (GPIC672) Transmit DMA Controller (TMAC672) PMC-980245 (P1) TRSTB TMS TCK TD1 TD0 TBD TBCLK JTAG AD[31:0] C/BEB[3:0] PAR FRAMEB TRDYB IRDYB STOPB DEVSELB IDSEL LOCKB REQB GNTB PERRB SERRB PCIINTB PCICLK PCICLKO M66EN PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1999 PMC-Sierra, Inc. PM7380 FREEDM-32P672 Frame Engine and Data Link Manager * You can configure the on-chip memory to support different channel configurations: from a single channel with 32 kbytes of buffering, to 672 channels, each with a minimum of 48 bytes of buffering. APPLICATIONS * Supports 5 Volt tolerant I/Os for non-PCI signals. Supports 3.3 Volt PCI signaling environment. Use the FREEDM32P672 chip in the following applications: * 329-pin plastic ball grid array (PBGA) package. * Remote Access Concentrators * Frame Relay/Multiservice Switches * Provides a standard five-signal P1149.1 JTAG test-port for boundary-scan board-test purposes. * Multiservice Access Concentrators * Internet/Edge Routers TYPICAL APPLICATIONS EIG HT LINK T1/E1 PO RT ADAPTER FO R PPP PRO CESSING Access End Uplink End PM4314 QDSX T1 Links PM4388 TOCTL PM7380 FREEDM32P672 PM4314 QDSX TDM Switch Fabric DS3 Link PCI Bus Packet Memory PM6388 EOCTL PM4314 QDSX DS3 LIU H-MVIP PM4314 QDSX E1 Links DS3 Framer Processor DSP Processing H-MVIP FRAM E RELAY TO ATM INTERW ORKING PM4314 QDSX T1 Links PM4388 TOCTL Packet Memory PM4314 QDSX PM7380 FREEDM32P672 Processor (FRF.5, FRF.8) PM4314 QDSX PM6388 EOCTL E1 Links PM4314 QDSX Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 PCI Bus AAL5 SAR PM7324 S/UNI-ATLAS UTOPIA To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-980245 (P1) 1999 PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE