GENERAL DESCRIPTION
The HI-3717A from Holt Integrated Circuits is a CMOS
device designed for interfacing an ARINC 717 compatible
bus to a Serial Peripheral Interface (SPI) enabled micro-
controller. The part includes a selectable Harvard Bi-Phase
(HBP) or Bi-Polar Return-to-Zero (BPRZ) receive channel
and transmit channels with HBP and BPRZ encoders and
line drivers. The receive channel has integrated analog line
receivers and the transmit channels have integrated line
drivers for the corresponding encoding method (HBP and
BPRZ). The part operates from a single +3.3V supply using
only four external capacitors. Each transmit and receive
channel has a 32-word by 12-bit FIFO for data buffering.
The HI-3717A is available in very small 44-pin 7mm x 7mm
Chip-scale (QFN) and 44-pin Quad Flat Pack (PQFP) plastic
packages.
PIN CONFIGURATIONS (Top View)
Single-Rail ARINC 717 Protocol IC
with SPI Interface
July 2016
HI-3717A
( 3717A Rev. C) 07/16DS
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
44 -
43 -
42 -
41 -
40 -
39 -
38 - GND
37 - C2+
36 - C2-
35 - V-
34 - TXHA
VDD
C1-
C1+
V+
NOCONV - 1
RINB-40 - 2
RINB - 3
RINA - 4
RINA-40 - 5
GND - 6
TFIFO - 7
TEMPTY - 8
INSYNC - 9
SYNC0 - 10
SYNC1 - 11
33 -
32 -
31 -
30 -
29 - TXHB
28 - TXBA
27 - OUTBA
26 - TXOUTBA
25 - TXOUTBB
24 - OUTBB
23 - TXBB
OUTHA
TXOUTHA
TXOUTHB
OUTHB
MATCH - 12
RFIFO - 13
ROVF - 14
-15
RSEL - 16
GND - 17
SI - 18
SCK - 19
SO - 20
-21
ACLK - 22
MR
CS
HI-3717APCI
HI-3717APCT
HI-3717APCM
HOLT INTEGRATED CIRCUITS
www.holtic.com
44 - Pin Plastic Quad Flat Pack (PQFP)
HI-3717APQI
HI-3717APQT
HI-3717APQM
44 -
43 -
42 -
41 -
40 -
39 -
38 - GND
37 - C2+
36 - C2-
35 - V-
34 - TXHA
VDD
C1-
C1+
V+
NOCONV - 1
RINB-40 - 2
RINB - 3
RINA - 4
RINA-40 - 5
GND - 6
TFIFO - 7
TEMPTY - 8
INSYNC - 9
SYNC0 - 10
SYNC1 - 11
33 -
32 -
31 -
30 -
29 - TXHB
28 - TXBA
27 - OUTBA
26 - TXOUTBA
25 - TXOUTBB
24 - OUTBB
23 - TXBB
OUTHA
TXOUTHA
TXOUTHB
OUTHB
MATCH - 12
RFIFO - 13
ROVF - 14
-15
RSEL - 16
GND - 17
SI - 18
SCK - 19
SO - 20
-21
ACLK - 22
MR
CS
FEATURES
·
·
·
·
·
·
·
·
·
·
·
·
·
·
Compliant with ARINC 717-15 (June 6, 2011)
μ
μμ
Operates from a single +3.3V supply with on-chip
converters to provide proper voltages for both Harvard
Bi-Phase (HPB) and Bi-Polar Return-to-Zero (BPRZ)
outputs
One selectable receive channel as HBP or BPRZ with
integrated analog line receiver
Both HBP and BPRZ transmitters have integrated line
drivers as well as digital outputs
32-word by 12-bit FIFOs for both the receive and the
transmit channel
Programmable slew rates on transmit channels: 1.5 s,
3.75 s, 7.5µs or 10 s
Digital transmitter outputs available for use with
external line drivers
Programmable bit rates: 384, 768, 1536, 3072, 6144,
12288, 24576, 49152 and 98304 bits/sec (32, 64, 128,
256, 512, 1024, 2048, 4096 and 8192 words/sec)
Enhanced Sync detection allows multiple false sync
marks in user data while still synchronizing within 8
seconds
Fast SPI transmitter write and receiver read modes
Match pin flags when preprogrammed word count /
subframe is received
Frame / subframe word count indicator
Industrial and Extended temperature ranges
Burn-in available
APPLICATIONS
·
·
·
·
Digital Flight Data Acquisition Units (DFDAU)
Digital Flight Data Recorders (DFDR)
Quick Access Recorders (cassette type)
Expandable Flight Data Acquisition and Recording
Systems
40 KΩ
37.5Ω
Control
Register 1
CTRL1
ARINC 717
Clock
Divider
TXBA
OUTBA
TXOUTBA
OUTBB
RINB-40
RINB
RINA-40
RINA
40 KΩ
SPI
Interface
Transmit
Rate
Selection
BPRZ
Encoder
HBP / BPRZ
Data
Sampler
HBP Line
Receiver
SYNC
Detect
Transmit FIFO
Status Register
TXFSTAT
Word Count
Utility Register
WRDCNT
DC / DC
Converter
Receive FIFO
Status Register
RXFSTAT
FIFO Status Pin
Assignment
Register
FSPIN
HBP / BPRZ
Clock
Recovery
&
Decoder
Slew
Rate
&
Loopback
Test
Control
RECEIVE
32 x 12-BIT
FIFO
BPRZ Line
Receiver
Line
Driver 37.5Ω
5Ω
5Ω
37.5Ω
Transmit
32 x 12-BIT
FIFO
Line
Driver
HBP
Encoder
Control
Register 0
CTRL0
SI
SO
ACLK
RSEL
GND
TXOUTBB
OUTHA
TXOUTHA
OUTHB
TXHB
TXOUTHB
V+
MATCH
TEMPTY
SCK
MR
NOCONV
ROVF
SYNC1
INSYNC
V-
C1+
C1-
C2+
C2-
TXBB
+3.3V
V-
V+
TXHA
SYNC0
FIGURE 1.
CS
37.5Ω
5Ω
5Ω
RFIFO
TFIFO
BLOCK DIAGRAM
HI-3717A
HOLT INTEGRATED CIRCUITS
2
VDD (3.3V)
10uF 0.1uF
CSUPPLY
COUT
COUT
CFLY+
CFLY-
SIGNAL FUNCTION DESCRIPTION Internal
Pull-up / Down
NOCONV INPUT Disables on-chip DC-DC voltage converter 50K pull-downΩ
RINB-40 INPUT Alternate receiver negative input. Requires external 40K ohm resistor
RINB INPUT Receiver negative input. Direct connection to ARINC 717 bus (BPRZ or HBP)
RINA INPUT Receiver positive input. Direct connection to ARINC 717 bus (BPRZ or HBP)
RINA-40 INPUT Alternate receiver positive input. Requires external 40K ohm resistor
GND POWER Chip 0V Supply (All GND pins on package must be connected)
TFIFO OUTPUT Output is user programmable to indicate the Transmit FIFO Full or Half-full state.
See FSPIN<5>, in Table 7, FIFO Status Pin Assignment Register.
TEMPTY OUTPUT Output goes high when the transmit FIFO is empty
INSYNC OUTPUT
Output goes high when the receiver is synchronized to the incoming data. Synchroni-
zation occurs at the next valid sync mark following the detection of the proper
number and order of consecutively spaced sync marks. See Table 5.
SYNC0 OUTPUT
Output in conjunction with SYNC1 output indicates when each of the four ARINC 717
subframe sync words are received. Only valid in 4 Sync-Word mode when the
INSYNC pin is high.
SYNC1 OUTPUT
Output in conjunction with SYNC0 output indicates when each of the four ARINC 717
subframe sync words are received. Only valid in 4 Sync-Word mode when the
INSYNC pin is high.
MATCH OUTPUT Output goes high when the value of the Frame Word Count Register matches the
value in the Frame Count Utility Register, WRDCNT.
RFIFO OUTPUT Output is user programmable to indicate the Receive FIFO Full, Half-full or Empty
state. See FSPIN<7:6> in Table 7, FIFO Status Pin Assignment Register.
ROVF OUTPUT Receive FIFO Overflow. Output goes high when an attempt is made to load a full
Receive FIFO
MR INPUT Master Reset, active low 50K pull-upΩ
RSEL INPUT Selects either HBP or BPRZ Receiver. OR’d with RXSEL bit in Control Register 0 50K pull-downΩ
SI INPUT SPI interface serial data input 50K pull-downΩ
SCK INPUT SPI Clock. Data is shifted into SI and out of SO when is low.
CS 50K pull-downΩ
SO OUTPUT SPI Interface seral data output
CS INPUT Chip Select CS
. Data is shifted into SI and out of SO using SCK when is low 50K pull-upΩ
ACLK INPUT Master timing source for receiver and transmitters. 24 MHZ ±0.1% 50K pull-downΩ
TABLE 1.
PIN DESCRIPTIONS
HOLT INTEGRATED CIRCUITS
3
HI-3717A
SIGNAL FUNCTION DESCRIPTION Internal
Pull-up / Down
TXBB OUTPUT Bi-Polar Return-to-Zero (BPRZ) digital low output (external line driver required)
OUTBB OUTPUT Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Requires external
32.5 ohm resistor
TXOUTBB OUTPUT Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Direct connect to ARINC 717
bus
TXOUTBA OUTPUT Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Direct connect to ARINC
717 bus
OUTBA OUTPUT Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Requires external
32.5 ohm resistor
TXBA OUTPUT Bi-Polar Return-to-Zero (BPRZ) digital high output (external line driver required)
TXHB OUTPUT Harvard Bi-Phase (HBP) digital low output (external line driver required)
OUTHB OUTPUT Alternate Harvard Bi-Phase (HBP) Line Driver low output. Requires external 32.5
ohm resistor
TXOUTHB OUTPUT Harvard Bi-Phase (HBP) Line Driver low output. Direct connect to ARINC 717 bus
TXOUTHA OUTPUT Harvard Bi-Phase (HBP) Line Driver high output. Direct connect to ARINC 717 bus
OUTHA OUTPUT Alternate Harvard Bi-Phase (HBP) Line Driver high output. Requires external 32.5
ohm resistor
TXHA OUTPUT Harvard Bi-Phase (HBP) digital high output (external line driver required)
V- CONVERTER DC/DC converter negative voltage
C2- CONVERTER DC/DC converter fly capacitor for V-
C2+ CONVERTER DC/DC converter fly capacitor for V-
V+ CONVERTER DC/DC converter positive voltage
C1+ CONVERTER DC/DC converter fly capacitor for V+
C1- CONVERTER DC/DC converter fly capacitor for V+
VDD POWER Chip +3.3V Supply
TABLE 1.
PIN DESCRIPTIONS (cont.)
HOLT INTEGRATED CIRCUITS
4
HI-3717A
TABLE 1 (cont.).
XXXXX
SPI INSTRUCTION FORMAT
76543210
MSB LSB
XX
R/W
MSB LSB
MSB LSB High Z
High Z
CS
SO
SI
SCK (SPI Mode 0)
FIGURE 2. Generalized Single-Byte Transfer Using SPI Protocol Mode 0
SERIAL PERIPHERAL
INTERFACE (SPI)
SPI BASICS
The HI-3717A uses an SPI (Serial Peripheral Interface) for host
access to internal registers and data FIFOs. Host serial
communication is enabled through the Chip Select ( ) pin,
and is accessed via a four-wire interface consisting of Serial
Data Input (SI) from the host, Serial Data Output (SO) to the
host and Serial Clock (SCK). All read / write cycles are
completely self-timed.
The SPI protocol specifies master and slave operation; the
HI-3717Aoperates as an SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible “SPI Modes”. Without
describing details of the SPI modes, the HI-3717A operates in
Mode 0 where input data for each device (master and slave) is
clocked on the rising edge of SCK, and output data for each
device changes on the falling edge (CPHA = 0, CPOL = 0). The
host SPI logic be set for Mode 0 for proper
communications with the HI-3717A.
As seen in Figure 2, SPI Mode 0 holds SCK in the low state
when idle. The SPI protocol transfers serial data as 8-bit bytes.
Once is asserted, the next 8 rising edges on SCK latch input
data into the master and slave devices, starting with each byte's
most-significant bit. A rising edge on terminates the serial
transfer and re-initializes the HI-3717A SPI for the next transfer.
If goes high before a full byte is clocked by SCK, the
incomplete byte clocked into the device SI pin is discarded.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex), per Figure 2 below.
However the HI-3717A operates half duplex, maintaining high
impedance on the SO output, except when actually transmitting
serial data. When the HI-3717A is sending data on SO during
read operations, activity on its SI input is ignored. Figure 3 and
Figure 4 show actual behavior for the HI-3717ASO output.
CS
must
CS
CS
CS
HI-3717A SPI INSTRUCTIONS
Since HI-3717A operates in half-duplex mode, the host
discards the dummy byte it receives while serially transmitting
the instruction op code to the HI-3717A.
Instruction op codes are used to read, write and configure the
HI-3717A. Each SPI read or write operation begins with an 8-bit
instruction. When goes low, the next 8 clocks at the SCK
pin shift an instruction op code into the decoder, starting with
the first rising edge. The op code is shifted into the SI pin, most
significant bit (MSB) first. The SPI can be clo cked up to10 MHz.
The SPI instructions are of a common format. The most
significant bit (MSB) specifies whether the instruction is a write
“0” or read “1” transfer.
For write instructions, the most significant bit of the data word
must immediately follow the instruction op code and is clocked
into its register on the next rising SCK edge. Data word length
varies depending on word type written: 8-bit Control & Status
Register writes, 16-bit Word Count Utility Register writes and
16-bit Transmit FIFO writes.
For read instructions, the most significant bit of the requested
data word appears at the SO pin at the next falling SCK edge
after the last op code bit is clocked into the decoder. As in write
instructions, the data field bit-length varies with read instruction
type.
CS
HOLT INTEGRATED CIRCUITS
5
HI-3717A
FIGURE 3. Single-Byte Read From a Register
CS
SO
SI
SCK
MSB LSB
01234567
High Z High Z
01234567
MSB LSB MSB
LSB
Data Byte
Op-Code Byte
FIGURE 4. 2-Byte SPI Write Example
CS
SO
SI
SCK
SPI Mode 0
MSB LSB
01234567
High Z
0123456701234567
MSB LSB MSB LSB
Data Byte 0 Data Byte 1
Op-Code Byte
Figure 3 and Figure 4 show read and write timing as it appears
for a single-byte and dual-byte register operation. The
instruction op code is immediately followed by a data byte
comprising the 8-bit data word read or written. For a register
read or write, is negated after the data byte is transferred.
Table 2 summarizes the HI-3717ASPI instruction set.
CS
Note: SPI Instruction op-codes not shown in Table 2 are
“reserved” and must not be used. Further, these op-codes will
not provide meaningful data in response to a read instruction.
Two instruction bytes cannot be “chained”; must be negated
after each instruction, and then reasserted for the following
Read or Write instruction.
CS
HOLT INTEGRATED CIRCUITS
6
HI-3717A
Note: Two instruction bytes cannot be “chained”;
must be negated after each instruction, and then
reasserted for the following Read or Write instruction.
CS
Note: Two instruction bytes cannot be “chained”;
must be negated after each instruction, and then
reasserted for the following Read or Write instruction.
CS
OP Code R/W # Data
bytes DESCRIPTION
0x64 W 1 Write Control Register 0
0x62 W 1 Write Control Register 1
0x6A W 1 Write Receiver FIFO Status Pin Assignment Register
0x72 W 2 Write Word Count Utility Register
0x74 W 2 Write Transmit FIFO word
0x2* W 1 Fast Write Transmit FIFO Word
0xE4 R 1 Read Control Register 0
0xE2 R 1 Read Control Register 1
0xE6 R 1 Read Receive FIFO Status Register
0xE8 R 1 Read Transmit FIFO Status Register
0xEA R 1 Read Receive FIFO Status Pin Assignment Register
0xF2 R 2 Read Word Count Utility Register
0xF6 R 2 Read Receive FIFO Word
0xFE R 4 Read Receive FIFO Word and Word Count
0xC* R 1 Fast Read Receive FIFO
* In the case of FAST instructions, the last four bits of the instruction byte are data
TABLE 2. SPI Instruction Set
HOLT INTEGRATED CIRCUITS
7
HI-3717A
SPI INSTRUCTION SET
TABLE 3.
7-
6 - 4 BR2:0
3 32WPS
2-1 SLEW1:0 R/W
0 RXSEL
Bit Name R/W Default Description
R/W 0 Not Used. Always reads a “0”
R/W 0 Setting these bits sets theARINC 717 data rate for both the receive and transmit data.
000 768 Bits/sec. ( 64 words/sec.)
001 1536 Bits/sec. (128 words/sec.)
010 3072 Bits/sec. (256 words/sec.)
011 6144 Bits/sec. (512 words /sec.)
100 12288 Bits/sec. (1024 words/sec.)
101 24576 Bits/sec. (2048 words/sec.)
110 49152 Bits/sec. (4096 words/sec.)
111 98304 Bits/sec. (8192 words/sec.)
R/W 0 Setting this bit overrides the state of BR2:0 and sets the data rate at 384 Bits/sec. (32 words/sec.)
0 Setting these bits controls the nominal slew rate on both the HBP & BPRZ transmit channel outputs.
00 7.5 s
01 3.75 s (ARINC 717 data rates)
10 10.0 s ( Same asARINC 429 Low Speed)
11 1.5 s ( Higher data rates beyondARINC 717 – same asARINC 429 High Speed)
R/W 0 Selects either the HBP (”0”) or BPRZ (”1”) Receiver. This bit is logically OR’d with the RSEL input
pin.
µ
µ
µ
µ
76543210
MSB LSB
BR0
32WPS
SLEW1
SLEW0
RXSEL
BR1
BR2
CONTROL REGISTER 0: CTRL0
Read: SPI Op-code 0xE4
Write: SPI Op-code 0x64
REGISTER DESCRIPTIONS
X
HOLT INTEGRATED CIRCUITS
8
HI-3717A
7-4 -
3 SRST
2 SFTSYNC
1 NOSYNC R/W
0 TEST
Bit Name R/W Default Description
R/W 0 Not Used,Always reads a “0”
R/W 0 Software Reset - Setting this bit to “1” empties all the FIFO’s, clears the Sync detection logic and
sets the analog line drivers to Hi-Z state. All other register bits remain unchanged.
R/W 0 2 Sync-Word Mode: Setting the bit to “1” will result in the INSYNC output pin going high when the
third of three consecutively occurring sync marks is detected.
0 No Synchronization - Setting this bit to “1” will result in all data captured being loaded into the
receive FIFO. WARNING: In this mode there is no way the HI-3717A can determine frame or sub-
frame boundaries. This sync mode overrides all the other sync modes when set to “1”.
R/W 0 Test Mode - A “1” in this bit position will disable the line receiver and both line drivers and the digital
transmitted data will be looped back to the HBP or BPRZ data sampler selected by RXSEL.
76543210
MSB LSB
SRST
TEST
CONTROL REGISTER 1: CTRL1
Read: SPI Op-code 0xE2
Write: SPI Op-code 0x62
XXX
X
NOSYNC
SFTSYNC
TABLE 4.
HI-3717A
HOLT INTEGRATED CIRCUITS
9
7 INSYNC
6-5 SYNC0:1
4 RFFULL
3 RFHALF R
2 RFEMPTY
Bit Name R/W Default Description
R 0 Receive channel sync indicator. The bit is set to”1” when synchronization is achieved on the
receive channel.
4 Sync-Word Mode occurs when four consecutive valid sync marks (Octal 1107, 2670, 5107 and
6670 respectively) are received exactly 1 second apart. The bit is set when the next valid and
properly spaced subframe sync mark (Octal 1107) is detected.
2 Sync-Word Mode (CTRL1<2> = “1”) occurs when two consecutively valid sync marks are
received exactly 1 second apart and in the proper order but the first sync mark does not have to be
Octal 1107. The bit is set when the next valid and properly spaced subframe sync mark is detected.
The bit remains set until synchronization is lost at which time the device automatically attempts to
re-synchronize. No data is passed to the receive FIFO until Synchronization is re-established.
Existing data in the FIFO remains intact and can be read at any time.
R 0 The two bits are realtime indicators of when each of the four ARINC 717 subframe sync marks are
received. They are updated when the sync mark is detected and passed to the Receive FIFO. The
two bits are only valid in 4 Sync-Word Mode when the INSYNC pin is high. See Application Note
AN-170 for detecting SYNC phase in SFTSYNC mode.
00 Subframe SYNC1 mark received (Octal 1107)
01 Subframe SYNC2 mark received (Octal 2670)
10 Subframe SYNC3 mark received (Octal 5107)
11 Subframe SYNC4 mark received (Octal 6670)
R 0 Bit is set when the Receive FIFO contains 32 words.
0 Bit is set when the Receive FIFO contains 16 words.
R 1 Bit is set when the Receive FIFO is empty. It is reset to”0” when the first valid word is passed to the
Receive FIFO.
1 RFOVF R 0 FIFO Overflow bit and ROVF pin are set to “1” when devices attempts to load a valid word to a full
Receive FIFO. The Receive FIFO will ignore additional words if it is full.
0 - R 0 Not used, Always reads “0”
exactly
MSB
RECEIVE FIFO STATUS REGISTER: RXFSTAT
Read: SPI Op-code 0xE6
Write: Read Only
TABLE 5.
76543210
LSB
RFFULL
RFHALF
TEST
SYNC0
INSYNC
XXXX
RFOVF
RFEMPTY
SYNC1
XXXX
HOLT INTEGRATED CIRCUITS
10
HI-3717A
The Word Count Utility Register can be programmed to generate an interrupt on the MATCH pin when the data for the specified word
count of the specified subframe is loaded into the Receive FIFO. The Word Count Utility Register can used with any of the standard
ARINC 717 data rates and all of the expanded data rates, except 8192 wps.
15 - 3 C12:0
2 - R/W 0 Not used,Always reads “0”
1 - 0 S1:0 R/W
Bit Name R/W Default Description
R/W 0 Subframe Word Count - The value is compared to the current word count in the Receive FIFO and
sets the MATCH pin to “1” whenever there is a match. The MATCH pin will stay at “1” for one word
time.
0 Subframe ID
00 Subframe One
01 Subframe Two
10 Subframe Three
11 Subframe Four
76543210
LSB
C1
C0
SO
C2
C4
WORD COUNT UTILITY REGISTER: WRDCNT
Read: SPI Op-code 0xF2
Write: SPI Op-code 0x72 XXXX
S1
FFEMPTY
C3
XXXX
REGISTER DESCRIPTIONS (cont.)
7 TFIFO
6 TFHALF
TFEMPTY
4-0 - R
Bit Name R/W Default Description
R 0 This bit mirrors the status of the TFIFO pin. See register FSPIN below for TFIFO pin assignment.
R 0 Set when the Transmit FIFO contains 16 words
5 R 1 Set when the Transmit FIFO is empty. Reset to “0” when at least one word is loaded to the Transmit
FIFO.
0 Not used,Always reads “0”
exactly
76543210
MSB LSB
FFFULL
FFHALF
TEST
TFEMPTY
TFIFO
TRANSMIT FIFO STATUS REGISTER: TXFSTAT
Read: SPI Op-code 0xE8
Write: Read Only
XXXX
FFOVFW
FFEMPTY
TFHALF
XXXX
7 - 6 RFIFO1:0
5 TFASIGN R/W 0 This bit programs the TFIFO pin to reflect the Transmit FIFO Status (FIFO Full or FIFO Half-Full).
4-0 - R
Bit Name R/W Default Description
R/W 0 These bits program which Receive FIFO Status Register bit is represented by the RFIFO pin .
00 RFIFO pin is set “1” when Receive FIFO Status Register Bit 2, RFEMPTY, is “1”.
01 RFIFO pin is set “1” when Receive FIFO Status Register Bit 3, RFHALF, is “1”.
10 RFIFO pin is set “1” when Receive FIFO Status Register Bit 3, RFHALF, is “1”.
11 RFIFO pin is set “1” when Receive FIFO Status Register Bit 4, RFFULL, is “1”.
0 TFIFO pin is set “1” when Transmit FIFO is Full (contains 32 words).
1 TFIFO pin is set “1” when Transmit FIFO is Half-Full (contains exactly 16 words).
0 Not used,Always reads “0”
76543210
MSB LSB
FFFULL
FFHALF
TEST
TFASIGN
RFIFO1
FIFO STATUS PIN ASSIGNMENT
REGISTER: FSPIN
Read: SPI Op-code 0xEA
Write: SPI Op-code 0x6A
XXXX
FFOVFW
FFEMPTY
RFIFO0
XXX
X
15 14 13 12 11 10 9 8
MSB
C9
C8
C5
C10
C12
XXXX
C6
C7
C11
XXXX
TABLE 6.
TABLE 7.
TABLE 8.
time
1 Second
1Second 1Second
MSB LSB
011 821
1st Subframe Sync Code (1107)
LSB MSB
9
10
1
0
003
Example 1. Write Transmit FIFO Subframe Sync or Data Word .(Op-Code 0x74)
6547
LSB MSB
03910
Nth Data Word
2
1118
56 7
4
Subframe Sync or Data Word BitsSPI Op-Code
Example 3. Fast Write Transmit FIFO Subframe Sync or Data Word .(Op-Code 0x2-)
MSB LSB
985X1
6
7
10
1112 00
32 14
Word Count Bits
0
SPI Op-Code
MSB LSB
1110010
Example 4. Write Word Count Utility Register, WRDCNT .(Op-Code 0x72)
MSB LSB
11 821
9
10 03
65 47
Sync Bits
Always “0”
1
SPI Op-Code
MSB LSB
1111110
Example 5. Read Receive FIFO Data Word with Word Count .(Op-Code 0xFE)
MSB LSB
98501
6
7
10
1112 00
32 1
4
Subframe Sync or Data Word Bits Word Count Bits
MSB LSB
011 821
9
10
0
00 03
65 47
Subframe Sync or Data Word BitsAlways “0”
1
SPI Op-Code
MSB LSB
1100110
Example 2. Read Receive FIFO Subframe Sync or Data Word .(Op-Code 0xF6)
Always “0”
0
SPI Op-Code Don’t Care
MSB LSB
1110100
MSB LSB
X11 821
Subframe Sync or Data Word Bits
9
10
X
XX 03
65 47
LSB MSB
2nd Data Word
4 Seconds
1 Second
Sync Bits
0
1304200101100
001
The first 12- bit word of a subframe that appears on the ARINC 717
bus is the synchronization code with the least significant bit (LSB)
first. This is immediately followed by up to 8191 12-bit data words,
all within from the start of the synchronization code. The
next three subframes immediately follow the first subframe with
their synchronization code as the first 12-bit word of the subframe
followed by the same number of data words as the first subframe.
ARINC 717 data is transmitted between the HI-3717A and host
microcontroller using the four-wire Serial Peripheral Interface
(SPI). A read or write operation consists of a single-byte op-code
followed by 8-bit data words. Figure 5 shows examples of how the
SPI data bytes are mapped to the ARINC 717 message.
1 second
Frame
MSB
Subframe 3
LSB MSB
LSB
MSB
LSB
Subframe 4Subframe 1
1 Second
MSB
LSB
Subframe 2
ARINC717 Subframe Format
ARINC717 Message as received / transmitted on the ARINC 717 serial bus
ARINC 717 messages consist of 12-bit words sent in a 4 second
frame divided into four 1 second subframes. Each subframe
consists of 64 (basic rate), 128, 256, 512, 1024, 2048, 4096 or
8192 12 bit words, depending on the data rate of the target
system.
The first word of each subframe contains a unique
synchronization pattern that identifies the subframe. The octal
synchronization code for subframes 1 through 4 are 1107, 2507,
5107 and 6670 respectively.
Barker Code
111098765
1
00
0
ARINC 717 MESSAGE AND BIT ORDERING
ARINC 717 Message as transferred on the SPI bus
HI-3717A
HOLT INTEGRATED CIRCUITS
11
FIGURE 5. ARINC 717 & SPI Bit Ordering
OVERVIEW
ARINC 717 is a continuous transmission of 12-bit words in 4 second
frames divided into four 1 second subframes. The programmed
data rate (32 to 8192 wps) determines the number of words per
subframe. The first word of each subframe is reserved for a unique
sync mark. Figure 5 illustrates the relationship between ARINC 717
frames, subframes and words.
The HI-3717A is comprised of independent ARINC 717 receive and
transmit sections easily accessible via a four wire SPI
communications bus. It supports the ARINC 717 Harvard Bi-Phase
(HBP) protocol as well as the Bi-Polar Return to Zero (BPRZ)
auxiliary protocol.
The receiver accepts data from either a Harvard Bi-Phase (HBP) or
a Bi-Polar Return to Zero (BPRZ) bus, recovers the clock, decodes
the data, synchronizes the ARINC 717 data frames using the
unique subframe sync marks and stores the recovered data in a 32
word x 12 bit Receive FIFO.
The ARINC 717 Transmitter accesses data from a 32 word x 12 bit
Transmit FIFO, encodes it into both HBP and BPRZ data streams at
the selected data rate, and converts the digital data stream to
ARINC 717 bus compatible outputs. There are separate outputs for
the HBP and BPRZARINC 717 buses.
The receive and transmit sections operate at the same data rate
and they are configured and monitored via the SPI interface.
Refer to Figure 1 for the Block Diagram of the HI-3717A
INITIALIZATION AND RESET
The HI-3717A generates a full reset upon application power. The
power-on-reset (POR) sets all registers to their default values,
places the Receive and Transmit FIFOs to their empty state, and
clears the sync detection logic. It also sets both the HBP and BPRZ
outputs to the high impedance state and the input sampling and
decoders are disabled. See Register Descriptions for complete
definition of the default values.
The part can also be initialized to the full reset state by applying a
100ns active low pulse to the external pin.
A software reset is also possible via the SPI communications
interface by writing a “1” to the CTRL1<3>. This bit places both the
Receive and Transmit FIFO’s in the empty state, clears the sync
detection logic, and sets both the HBP and BPRZ line drivers to a
high impedance state. . The
device is held in the reset state until a “0” is written to CTRL1<3>.
MR
All other registers remain unchanged
CONFIGURATION
The HI-3717A is configured via the SPI communications bus by
writing to Control Register 0, CTRL0, and Control Register 1,
CTRL1. They are reset to 0x00 following a Power On Reset
(POR) or a Master Reset ( ) but remain unchanged on a
Software Reset, CTRL1<3>, SRST. The function of each register
bit is shown in the Register Descriptions.
MR
In order to avoid inadvertent transceiver operation, Control
Register 0, CTRL0, should be programmed last. Writing
CTRL0 sets the desired data rate which, after one bit period,
enables the internal clocks. This in turn makes the transmitter
or receiver operational. Changing the data rate on the fly may
result in unpredictable operation during the transition to the
new programmed state. A full reset, POR or , should be
issued before reprogramming the data rate.
MR
Data Rate
Line Driver Output Slew Rates
Receiver Format
Input Synchronization Mode
For correct ARINC 717 date rate reception, transmission and bit
timing, the HI-3717A requires a 24 MHz reference clock source
applied to the ACLK input. This clock is divided down to achieve the
data rate programmed with CTRL0<6:4>. The input receive data is
8X oversampled relative to the programmed data rate.
ARINC 717 requires a basic data rate of 64 wps with support for
128, 256 and 512 wps. The HI-3717A offers an expanded range of
32 to 8192 wps for testing purposes and future expansion.
CTRL0<3>, 32WPS, overrides the state of CTRL0<6:4> and sets
the data rate to 32 wps. The required 0.1% timing tolerance is
maintained over all data rates.
The ARINC 717 format of the receiver is selectable as HBP or
BPRZ by the state in <0>, RXSEL, OR’d with the state of the
external RSEL input pin. A “0” on RSEL and <0> selects
HBP and a “1” on either RSEL or <0> selects BPRZ.
Refer to Table 3 for the detail description of each bit in Control
Register 0.
The HI-3717A has three different synchronization modes:
1. 4 Sync-Word Mode
This is the default synchronization mode at power up or after a
Master Reset. In this mode the HI-3717A searches for the four
subframe sync marks:
SYNC1 = Octal 1107
SYNC2 = Octal 2670
SYNC3 = Octal 5107
SYNC4 = Octal 6670
in the correct sequential order starting from SYNC1 and the
exact bit time determined by the programmed word rate. When
synchronization is achieved the INSYNC pin as well as the
INSYNC bit of the Receive FIFO Status Register, RXFSTAT<7>
are set to “1” on the next valid SYNC1 mark. The valid SYNC1
mark and following data words are stored in the Receive FIFO.
The slew rate of the HBP and BPRZ outputs is controllable with
CTRL0<2:1>. A 3.75µs slew rate conforms to all the required
ARINC 717 data rates. A 1.5µs is provided for higher data rates
beyond the standard. In addition, slower slew rates of 7.5µs and
10µs are available to further optimize the application.
CTRL0
CTRL0
CTRL0
FUNCTIONAL DESCRIPTION
HOLT INTEGRATED CIRCUITS
12
HI-3717A
0
MSB
1001110101
+5V
Harvard Bi-Phase
-5V
+10V
Bi-Polar Return to Zero
-10V
FIGURE 6. ARINC 717 HBP & BPRZ Differential Input Signal Format
FUNCTIONAL DESCRIPTION (cont.)
Data 1
LSB
Sync time varies from 4 seconds to a worst case of 8 seconds
for a valid data stream.
The first word stored in the Receive FIFO is available when
RXFSTAT<2>, RFEMPTY, is reset to “0”, which is 12-bit periods
(one word time) after INSYNC is set to “1”.
The HI-3717A remains in sync as long as the proper sync
sequence is maintained. INSYNC is reset to “0” when the next
expected subframe sync mark is not present. The HI-3717A will
initiate a new synchronization process at the next valid SYNC1
mark.
Once the part falls out of sync, the whole previous subframe
should be discarded.
2. 2 Sync-Word Mode
In this mode the HI-3717A searches for any two subframe sync
marks in the correct sequential order and the exact starting time
for the sync mark. INSYNC is set to “1” when the third valid sync
mark is detected. The part must continue to detect each sync
mark in the correct order and with the correct starting time to
stay in sync.
This method reduces the time required to obtain sync to about 2
seconds typical and a worst case of 3 seconds.
3. No Sync Detect Mode
In this mode, the INSYNC is set to “1” and all data is stored in
the Receive FIFO. Without sync detection, the Receive FIFO
just records the sequential bits, not words, from the bus. It is up
to the user to detect the sync marks and determine the word
boundaries in this mode.
In both the 4 Sync-Word and 2 Sync-Word Modes, the HI-3717A
uses a proprietary sync tracking and detection method which allows
correct synchronization to occur in the presence of up to three false
sync marks without increasing the sync time.
NOTE: If the part does not synchronize in 8 seconds
(INSYNC = “0”), a Software Reset should be performed by
setting CTRL1<3>, SRST.
Digital Loopback
FIFO Status Pin Assignment Register, FSPIN
Word Count Utility Register, WRDCNT
Normal HI-3717A operation is with CTRL1<0> set to “0”. Setting it
to “1” places the part in digital loopback mode. In this mode the
analog line receivers are disconnected from the data samplers
and both output line drivers are placed in a high impedance state.
The output encoders are connected to input sampler / decoder.
The part may be verified by selecting the desired receive decode
format with RSEL pin or CTRL0<0>, writing the transmit FIFO and
reading the receive FIFO. All status pins and registers reflect the
status of the loopback operation.
The MATCH pin goes high when the HI-3717A is in the INSYNC
condition and the word count and subframe count matches the
value programmed in the Word Count Utility Register. Note: The
INSYNC pin is set to “1” when the second consecutive SYNC1
mark of the proper sync sequence is received. The Word Count
Utility Register and Match pin function can be used for the
standard ARINC 717 data rates and all of the expanded data rates,
except 8192 wps.
This register assigns the function of the external RFIFO and
TFIFO pins. The RFIFO pin reflects the state of one of the three
Receive FIFO status flags (RFFULL, RFHALF and RFEMPTY) in
the Receive FIFO Status Register, RXFSTAT. The TFIFO pin
reflects the state of one of two Transmit FIFO states (Transmit
FIFO Full or Transmit FIFO Half-Full). Refer to the FSPIN Register
Description in Table 7 for register assignment details.
HI-3717A
HOLT INTEGRATED CIRCUITS
13
ARINC 717 RECEIVER
The input data stream for ARINC 717 can be one of two formats.
The main ARINC 717 bus to a Digital Flight Data Recorder (DFDR)
uses Harvard Bi-phase (HBP) encoding and the auxiliary output
bus to an Aircraft Integrated Data System (AIDS) uses Bi-Polar
Return to Zero (BPRZ) encoding as shown in Figure 6.
The HI-3717A has an independent ARINC 717 receive channel with
a selectable on-chip HBP analog line receiver for connection to the
main incoming ARINC 717 data bus or a BPRZ analog line receiver
for connection to an auxiliary data bus.
TheARINC 717 specification requires the following detection levels
for the HBP inputs:
HI +2 Volts to +8 Volts
NULL NA
LO -2 Volts to -8 Volts
ONE +6.5 Volts to +13 Volts
NULL +2.5 Volts to -2.5 Volts
ZERO -6.5 Volts to -13 Volts
The HI-3717A guarantees recognition of these levels with a
common mode voltage with respect to GND less than ±25V for the
worst case conditions (3.15V supply, 8V HBP signal level and 13V
BPRZ signal level).
Design tolerances guarantee detection of the above levels, so the
actual acceptance ranges are slightly larger. If the signal (including
nulls) is outside the differential voltage ranges, the HI-3717A
receiver rejects the data.
STATE DIFFERENTIAL VOLTAGE
The auxiliary BPRZ input detection levels are the same as
standard ARINC 429 levels:
STATE DIFFERENTIAL VOLTAGE
Bit Timing & Input Sampling
The bit timing for both the receive and transmit functions is the data
rate programmed in CTRL0<6:3>. The HI-3717A allows the
following word / bit rates:
The input data from the selected analog line receiver is
oversampled at 8X relative to the word rate programmed in
CTRL0<6:3>. This is 4X oversample of the transition rate since the
code rate for both methods is double the data rate.
The sampler uses three separate shift registers, one each for
Ones, Zero and Null detection. When the input signal is within the
differential voltage range of one of the valid states (One, Zero or
Null) of the selected data format, the sampler clocks “1” into that
register and a “0” into the other two. When the signal is outside the
differential voltage ranges defined for all the shift registers, a “0” is
clocked into all three registers. Only one shift register can clock “1”
for a given sample. The Null shift register is only used for the BPNZ
format.
For Havard Bi-phase, HBP, coding, the sampler validates a HI
(One) or LO (Zero) if the signal is in that state for at least two
samples. There is no Null state for the HBP format.
The Bi-Polar Return to Zero, BPRZ, coding sampler validates that
at least two consecutive Ones or two consecutive Zeroes are
followed by at least two consecutive Null states.
32 words/sec. = 384 Bits/sec
64 words /sec. = 768 Bits/sec.
128 words/sec. = 1536 Bits/sec.
256 words/sec. = 3072 Bits/sec.
512 words /sec. = 6144 Bits/sec.
1024 words/sec. = 12288 Bits/sec.
2048 words/sec. = 24576 Bits/sec.
4096 words/sec. = 49152 Bits/sec.
8192 words/sec. = 98304 Bits/sec.
The 32 WPS data rate is typically used for testing purposes.
FUNCTIONAL DESCRIPTION (cont.)
HOLT INTEGRATED CIRCUITS
14
HI-3717A
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
FIGURE 7. ARINC 717 Receiver Inputs
RINA-40
RINA
RINB
RINB-40
VDD
GND
VDD
GND
ONE
NULL
ZERO
CNTL0<0>
RSEL
Decoders
SYNC Detect
The decoder recovers the clock and resynchronizes each valid one
or zero to the transition bit period.
The Harvard Bi-phase, HBP, decoder confirms the sampler only
provided a valid One or Zero, not both, then detects the presence or
absence of an edge in the data bit period. The output of the decoder
is a “1” if there was a transition, otherwise a “0”.
The Bi-Polar Return to Zero, BPRZ, decoder confirms the sampler
only provided a valid One or Zero, followed by a valid Null. The
decoder output is a “1” for a valid One and “0” for a valid Zero.
Once the data is captured, it is re-sampled to the recovered
transition rate clock (sample clock sent to the sync detector) and re-
sampled to recover the data bit rate clock.
The decoders will operate correctly when the input data bit period is
not more than 2 sample clocks (25%) larger or 1 sample clock
(12.5%) smaller than the nominal value. The slower input frequency
causes a mismatch between the sampled data and the recovered
clock. The faster input frequency causes issues with internal edge
detection logic.
The HI-3717A employs a proprietary, four level sync algorithm that
samples each bit and compares each combination of 12-bits
against the four validARINC 717 subframe sync marks.
In 4 Sync-Word Mode, once a valid SYNC1 mark is discovered, it
continues to look for each of the next three subframe sync marks in
the proper order and timing. If any one is not found, the search
starts over looking for SYNC1 again. Once all four sync marks are
detected in the proper order and location in a frame, the INSYNC
pin is set to “1” at the next SYNC1 subframe sync mark if it is the
correct value and it occurs at the proper relationship to the previous
valid sync mark. This is the default synchronization mode for the
HI-3717A.
In the 2 Sync-Word Mode, CTRL1<2> = “1”, once two consecutive
valid subframe sync marks are detected, the INSYNC bit is set to “1”
at the next consecutive valid subframe sync mark if it occurs at the
proper relationship to the previous valid sync marks. The first valid
subframe sync mark does not have to be SYNC1 in this mode but
each successive subframe sync marks must be the next in the
sequence and properly spaced from the preceding valid subframe
sync mark.
INSYNC is set to “0” when the next expected subframe sync mark is
missed in the 4 Sync-Word or 2 Sync-Word Modes. The HI-3717A
sync detection logic is reset and the part initiates the full synchroni-
zation process again. The data from the subframe preceding the
first incorrect subframe sync mark should be discarded. No data is
passed to the Receive FIFO until synchronization is reestablished.
There are also two bits in the Receive FIFO Status Register,
RXFSTAT<6:5> that provide a realtime indicator when each of the
four ARINC 717 subframe sync marks are received. The bits are
valid only when INSYNC is “1” and are updated when the subframe
sync word is loaded into the Receive FIFO.
The final mode is No Synchronization, CRTL1<1> = “1”. In this
mode data is captured and loaded directly to the Receive FIFO in
the order it was received. It is the responsibility of the user to extract
the data from the FIFO and determine word, frame and subframe
boundaries. The INSYNC bit remains “0” while in this mode.
Data is transferred from the Receive FIFO starting with the valid
subframe sync mark when INSYNC was set to “1” and continues
with each consecutive 12-bit word until INSYNC is set to “0”.
Each time a validARINC 717 word is loaded to the Receive FIFO the
RFFULL, RFHALF and RFEMPTY bits in the Receive FIFO Status
Register (RXFSTAT<4:2>) are updated. Each word is retrieved
from the Receive FIFO via the SPI interface using SPI Op-code
instruction 0xF6 (word only), 0xFE (word & word count) or 0xC
(Fast Read).
Receive FIFO and Retrieving Data
FUNCTIONAL DESCRIPTION (cont.)
HOLT INTEGRATED CIRCUITS
15
HI-3717A
FIGURE 8. ARINC 717 Receiver Block Diagram
BPRZ
DECODER
SHIFT REGISTER
SHIFT REGISTER
ONES
RSEL
SHIFT REGISTER
RFIFO
to Line Drivers
HBP / BPRZ
SELECT
HBP
DECODER
SYNC DETECTION
WORD
CLOCK
DATA CLOCK
DIVIDER
CTRL0<0>
ZEROS
12-BIT SERIAL
REGISTER
WORD COUNT
&
SUBFRAME
DETECTION
32 WORD x 12-BIT
RECEIVE FIFO
12-BIT SERIAL
INPUT REGISTER
12-BIT SERIAL
INPUT REGISTER
INSYNC
ROVF
SYNC1
SYNC0
12-BIT COMPARATOR
ACLK
NULL
CTRL0<6:4>
The SPI read instruction 0xF6 format is an 8-bit op-code followed by
two 8-bit data words. The four most significant bits (MSB) of the first
data word are always “0” followed by the first four MSB of the ARINC
717 word. The second data word contains the remaining 8-bits of
the ARINC 717 word. The least significant bit (LSB) of the ARINC
717 word is the LSB of the second 8-bit data word.
The format for read word and word count instruction 0xFE is the
same as the read instruction with the addition of two additional 8-bit
data bytes that contain the word count and the corresponding sync
subframe information. The third 8-bit SPI data byte contains the 8
MSB bits of the word count. The fourth data byte is comprised of
remaining 5 bits of the word count as well as the two bit code for the
subframe number in the same format as described in the RFXSTAT
Register Description. Refer to Example 5 in Figure 5 for more
details on the format for this instruction.
The Fast Read instruction 0xC uses only one SPI data byte for a
read operation. This is accomplished by using only first four bits for
the SPI op-code and placing the first four most significant bits of the
ARINC 717 word in the four remaining bit locations of what are
normally part of an op-code. The remaining 8-bits of the ARINC 717
word are in a normal SPI data byte. This method use one less SPI
data byte than a normal read instruction.
Up to 32 ARINC 717 words may be held in the Receive FIFO. The
RFFULL bit (RXFSTAT<4>) is set to “1” when the Receive FIFO is
full. Failure to unload the Receive FIFO when full will result in loss
of new data words until there are less than 32 words in the FIFO.
The RFOVF bit (RXFSTAT<1>) and external FROV pin are set to “1”
when an attempt is made to write to a full Receive FIFO.
The Receive FIFO half-full flag, the RFHALF bit (RXFSTAT<3), is
set to “1” whenever the Receive FIFO contains exactly 16 words.
The RFHALF bit provides a useful indicator to the host CPU that the
FIFO is filling up.
The Receive FIFO empty, the RFEMPTY bit (RXFSTAT<2>), is set
to “1” when the Receive FIFO is empty. It is reset to “0” when there
is at least one word in the Receive FIFO.
When the HI-3717A attempts to load a valid word to a full Receive
FIF0, the RFOVF flag, RXFSTAT<1>, and the external RFOV pin
are set to “1”. The Receive FIFO ignores any attempt to load any
additional words if it is full. The RFOVF flag and RFOV pin are reset
to “0” when either the INSYNC goes to “0” or the device is reset.
The external RFIFO pin is programmable in the FIFO Status Pin
Assignment Register (FSPIN<7:6>) to reflect the value of the
RFFULL, RFHALF or the RFEMPTY status bit. Refer to the FSPIN
Register Description for the bit values that assign the RFFULL,
RFHALF or RFEMPTY status bit to the RFIFO pin. The default
state is assignment of the RFEMPTY bit to the RFIFO pin.
Word Count Utility Register, WRDCNT, is used to cause the
external MATCH pin to be set to”1” when a specific word count is
reached in a specific subframe. WRDCNT<15:3> specifies the
location in the subframe and WRDCNT<1:0> specifies the
subframe that is monitored. MATCH is “1” until the next word is
loaded into the Receive FIFO.
The Match word and subframe bit assignments of the Word Count
Utility Register, WRDCNT, are found in Table 8.
FUNCTIONAL DESCRIPTION (cont.)
HOLT INTEGRATED CIRCUITS
16
HI-3717A
BPRZ
ENCODER
FIGURE 9. ARINC 717 Transmitter Block Diagram
DATA
CLOCK ACLK
HBP
ENCODER SLEW RATE
&
LOOPBACK
TEST
CONTROL
HBP
LINE DRIVER
WORD CLOCK
&
BIT CLOCK
START
SEQUENCE
WORD COUNTER
&
FIFO CONTROL
INCREMENT
WORD COUNT
DATA CLOCK
DIVIDER
FIFO
LOADING
SEQUENCER
TXBA
TXOUTHB, OUTHB
32 word x 12 bit FIFO
12 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
WORD CLOCK
ADDRESS
CTRL0<6:4>
TFIFO
NOCONV
TEMPTY
SPI INTERFACE
SCK
CS
SI
SO
SPI COMMANDS
SPI COMMANDS
BPRZ
LINE DRIVER
TXOUTBA, OUTBA
TXOUTBB, OUTBB
LOAD
TXOUTHA, OUTHA
TXBB
TXHA
TXHB
TRANSMITTER
FIFO Operation
Data Transmission
The HI-3717A Transmit FIFO is loaded with ARINC 717 words
awaiting transmission. SPI words are written to the next Transmit
FIFO location with op-code 0x74 or 0x2 (Fast Write). If Transmit
FIFO Status Register empty flag, the TFEMPTY (TXFSTAT<5>)
bit, is “1” (FIFO empty), then up to 32 ARINC 717 12-bit words can
be safely loaded via the SPI interface. If the TFEMPTY bit is “0”
then less than 32 positions are available. If all 32 positions are
filled, then the Transmit FIFO is full. Any further attempt to load the
Transmit FIFO is ignored until the FIFO contains less than 32
words.
The Transmit FIFO half-full flag, the TFHALF (TXFSTAT<6>) bit in
the Transmit FIFO Status Register, is equal to “0” when there are
less than or more than 16 ARINC 717 words in the Transmit FIFO
and equal to “1” when there are exactly 16 words in the FIFO. The
host CPU can safely load 16 ARINC 717 words into the Transmit
FIFO only when TFHALF is “1”.
The Transmit FIFO status (Full or Half-Full) is available on the
external TFIFO pin, depending on the value in FSPIN<5> of the
FIFO Status Pin Assignment Register (See Table 7). The state of
the TFIFO pin is reflected in bit TFIFO in TXFSTAT<7>. The state
of TFEMPTY flag is always on the external TEMPTY pin.
It is the user’s responsibility to load the correct subframe sync
mark in the first word of each subframe and ensure the Transmit
FIFO is not left empty for more than one word time for continuous
transmissions.
The SPI format for writing an ARINC 717 word and Fast Word to
the HI-3717A Transmit FIFO is the same as the read format,
except the most significant bit of the op-code instruction is “0”
rather than a “1”.
The ARINC 717 transmission begins when the first word is loaded
into the Transmit FIFO. Each word is serially fed to both the HBP
and BPRZ encoders at the data rate programmed in Control
Register 0, CNTL0<6:4>. The output of each encoder drives its
own ARINC 717 analog line driver. The slew rate of both the HBP
and the BPRZ auxiliary outputs is controllable with CNTL0<2:1>.
Refer to the CTRL0 Register Description for the individual bit
values required for setting the desired data and output slew rate.
SYSTEM OPERATION
The receiver and transmitter always operate at the same data rate.
Otherwise, they operate completely independent of each other.
The only restrictions are:
1. The Receive FIFO ignores any attempt to load any additional
words if it is full and at least one location is not retrieved
before the next validARINC 717 is received.
2. The Transmit FIFO can store a maximum of 32 words and
ignores any attempt to store additional words when it is full.
DC/DC Converter
Line Driver Operation
The HI-3717A requires only a single +3.3V power supply. An
integrated inverting / non-inverting voltage doubler generates the
rail voltages (±5.7V) which then power the line drivers to produce
the required +5V ARINC 717 HBP and ±5V ARINC 717 BPRZ
signal levels.
The internal dual-polarity charge pump requires four external
capacitors, two for each polarity generated by the charge pump.
Pins C1+ and C1- connect the external “fly” capacitor, CFLY, to the
positive portion of the charge pump, resulting in 5.7V at the V+ pin
that is generated by an on-board bandgap reference voltage. An
output “hold” capacitor, COUT, is placed between V+ and GND.
The inverting negative portion of the converter works in a similar
fashion, with CFLY and COUT placed between C2+ / C2- and V- /
GND respectively (see block diagram page 2). See Converter
Characteristics table for recommended capacitor specifications.
The line drivers in the HI-3717A directly drive the ARINC 717
buses. The two ARINC 717 HBP outputs (TXOUTHA and
TXOUTHB) provide a differential voltage of ±5V in accordance
with the Harvard Bi-Phase format. Control Register 0
(CTRL0<6:4) controls the transmitter data rate and CTRL0<2:1>
controls the output slew rate.
The two auxillary ARINC 717 BPRZ outputs (TXOUTBA and
TXOUTBB) provide a differential voltage to produce a +10V One,
a -10V Zero, and a 0 Volt Null. The transmitter data rate is the
same as the HBP output which is also controlled by the same bits
in Control Register 0 (CTRL0<6:4). The slew rate of the differen-
tial output signal is also controlled by Control Register 0
(CTRL0<2:1>. No additional hardware is required to control the
slope. Slope rate is set by on-chip resistors and capacitors.
FUNCTIONAL DESCRIPTION (cont.)
HOLT INTEGRATED CIRCUITS
17
HI-3717A
Line Driver Output Pins
Line Receiver Input Pins
The Harvard Bi-phase (HBP) TXOUTHA and TXOUTHB pins as
well as the Bi-Polar Return to Zero (BPRZ) TXOUTBA and
TXOUTBB pins have 37.5 Ohms in series with each line driver
output, and may be directly connected to an ARINC 717 bus.
The OUTHA, OUTHB, OUTBA and OUTBB pins have 5 Ohms of
internal series resistance and require an external 32.5 ohm
resistor in series with each pin. OUTHA, OUTHB, OUTBA and
OUTBB pins are for applications where external series resis-
tance is applied, typically for lightning protection devices.
Either the TXOUTHA & TXOUTHB outputs or the OUTHA &
OUTHB outputs are used in an application but not both sets at
the same time. Likewise, only one set of the auxiliary BPRZ
output pins (TXOUTBA & TXOUTBB or OUTBA & OUTBB) are
used. Using both set of pins on either output will produce
unpredictable results.
The line driver outputs TXOUTHA, TXOUTHB, OUTHA, OUTHB,
TXOUTBA, TXOUTBB, OUTBA & OUTBB are in a high imped-
ance state after any reset and when in the digital loopback test
mode (CTRL1<0> = “1”) allowing multiple line drivers to be
connected to a single ARINC 717 bus. Note that both analog line
receivers are also disconnected from the HBP and BPRZ input
data samplers during reset and when in the digital loopback
mode.
The HI-3717A also has digital outputs from both the HBP (TXHA
& TXHB) and the BPRZ (TXBA & TXBB) encoders allowing the
use of external ARINC 717 line drivers. All four of these output
pins are active all the time and reflect the digital data sent to the
data sampler in the digital loopback mode.
The HI-3717A has two sets of Line Receiver input pins that are
shared with the HBP and BPRZ line receivers, RINA/B and
RINA/B-40. Only one pair may be used to connect to the ARINC
717 bus. The unused pair must be left floating. The RINA/B pins
may be connected directly to the ARINC 717 bus.
The RINA/B-40 pins require an external 40K ohm resistor in se-
ries with each ARINC 717 input. The resistors do not affect the
ARINC 717 receiver level detection thresholds .
When using the RINA/B-40 pins, each side of the ARINC 717
bus must be connected through a 40K ohm series resistor in or-
der for the chip to detect the correct ARINC 717 levels. The typi-
cal ARINC 717 differential signal is translated and input to a win-
dow comparator and latch. The comparator levels are set so
that with the external 40K ohm resistors, they are just below the
standard minimum data threshold and in the case of the auxil-
iary BPRZ line receiver, just above the standard 2.5 volt BPRZ
(ARINC 429) null threshold.
By keeping excessive voltage outside the device, the RINA/B-40
input option is helpful in applications where lightning protection is
required.
The NOCONV pin is set to “1” to disable the internal DC/DC Con-
verter and supply +5V & -5V to the V+ & V- pins respectively from
an external power source. The “fly” capacitor pins can be left
floating.
The HI-3717A can be used without the internal line drivers if only
the ARINC 717 receive function is required or if the user wants to
use his own external ARINC 717 line drivers connected to the
TXHA, TXHB, TXBA & TXBB digital transmitter outputs. For this
option, NOCONV pin is set to “1” to disable the internal line driv-
ers, V+ is connected to VDD & V- is left unconnected.
Please refer to the Holt AN-300 Application Note for additional in-
formation and recommendations on lightning protection of Holt
line drivers and line receivers.
Application of a Master Reset with a 100ns active low pulse to the
external pin sets all registers to their default values, places
the Receive and Transmit FIFOs to their empty state, and clears
the sync detection logic. It also sets both the HBP and BPRZ out-
puts to the high impedance state and disables input sampling of
both analog line receivers..
A software reset is also possible via the SPI communications in-
terface by writing a “1” to the CTRL1<3>. This bit places both the
Receive and Transmit FIFO’s in the empty state, clears the sync
detection logic, sets both the HBP and BPRZ line drivers to a high
impedance state and disables the input sampling of both analog
line receivers. Unlike POR and ,
. The device is held in the reset state until a “0” is writ-
ten to CTRL1<3>.
Master Reset
Software Reset
No DC/DC Converter Option
No Internal Line Drive Option
MR
MR ALL other registers remain
unchanged
FUNCTIONAL DESCRIPTION (cont.)
HOLT INTEGRATED CIRCUITS
18
HI-3717A
CS
SCK
SO
CHZ
t
Hi Impedance
SCKH
t
tDV
LSB
CPH
t
tSCKL
MSB Hi Impedance
CS
SCK
SI
CHH
t
CEH
t
MSB
CES
t
DS
tt
DH
LSB
CPH
t
SCKR
t
SCKF
t
CYC
t
CYC
t
TIMING DIAGRAMS
HBP DATA
LAST TRANSMIT FIFO WORD
TEMPTY
2nd to
LAST WORD
Bit 5 Bit 11Bit 10Bit 9
Bit 8
Bit 7Bit 6
Bit 4
Bit 3Bit 2Bit 1
Bit 0
Bit 11Bit 10
BPRZ DATA
tTEMPTY
HBP DATA
ROVF
BPRZ DATA
tROVF
INSYNC
12 Data Bits
RFIFO (RFEMPTY)
12 Data Bits
tREMPTY
RFIFO ( )RFFULL
FIGURE 13. Transmit FIFO Empty Flag Timing
FIGURE 10. SPI Serial Input Timing
FIGURE 11. SPI Serial Output Timing
FIGURE 12. Receive FIFO Flag Timing
HOLT INTEGRATED CIRCUITS
19
HI-3717A
FIGURE 14. Harvard Bi-Phase (HBP) Output Waveforms
HBP BIT
Data Bit 1
HBP BIT
Data Bit 11
HBP BIT
Data Bit 0
+5V
-5V
-5V
one level zero level
90%
90%
10%
10%
tfx trx
0V 0V
+5V
+5V
+5V
+5V
0V
+5V
0V
+5V
0V
0V
TXOUTHA & OUTHA
TXOUTHB & OUTHB
V
(TXOUTHA - TXOUTHB
&
OUTHA - OUTHB)
DIFF
+3.3V
+5V
tBf
tBr
0V
0V
+3.3V
+3.3V
0V
+3.3V
0V
TXBA
TXBB
0V
+3.3V
+3.3V
0V
+3.3V
0V
BI-POLAR RETURN ZERO (BPRZ)
TXHB
FIGURE 16. Harvard Bi-Phase (HBP) & Bi-Polar Return to Zero (BPRZ) Logic Output Waveforms
Data Bit 1 Data Bit 11Data Bit 0
FIGURE 15. Bi-Polar Return to Zero (BPRZ) Output Waveforms
BPRZ BIT
Data Bit 1
BPRZ BIT
Data Bit 11
BPRZ BIT
Data Bit 0
+5V +5V
+5V
+10V +10V
-10V
-5V -5V
-5V
one level zero level null level
90%
90%
10%
10%
tfx
trx
tfx
trx
one level null level
90% 90%
10% 10%
tHf
TXOUTBA & OUTBA
TXOUTBB & OUTBB
V
(TXOUTBA - TXOUTBB
&
OUTBA - OUTBB)
DIFF
0V 0V
+3.3V
0V
TXHA
HARVARD BI-PHASE (HBP)
tHr
90% 90%
10% 10%
zero level
TIMING DIAGRAMS (cont.)
HOLT INTEGRATED CIRCUITS
20
HI-3717A
V = 3.3V, TA = Operating Temperature Range (unless otherwise specified).DD
DC ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER CONDITIONS UNIT
SYMBOL
HBP Differential Input Voltage: (RINAto RINB) HI V Common mode voltages less than 2.0 5.0 8.0 V
LO V ±25V with respect to GND -8.0 -5.0 -2.0. V
HBP Input Voltage (Ref. to DFDAU Signal Ground)
RINA HI 3.5 5.0 6.5 V
L
Input Resistance: Differential R - 140 - K
To GND R - 140 - K
To V R - 100 - K
Input Current: Input Sink I 200 µA
Input Source I -450 µA
Input Capacitance: Differential C 20 pF
(Guaranteed but not tested) To GND C 20 pF
To V C 20 pF
Input Voltage: Input Voltage HI V V
Input Voltage LO V V
Input Current: Input Sink I 1.5 µA
Input Source I -1.5 A
MIN TYP MAX
HARVARD BI-PHASE (HBP) INPUTS - Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms)
LOGIC INPUTS
IHH
ILH
I
G
DD H
IH
IL
I
G
DD H
IH
IL
IH
IL
V
O V -1.5 0 +1.5 V
RINB HI V -1.5 0 +1.5 V
LO V 3.5 5.0 6.5 V
BPRZ Differential Input Voltage: (RINA to RINB) ONE V Common mode voltages less than 6.5 10.0 13.0 V
ZERO V ±25V with respect to GND -13.0 -10.0 -6.5 V
NULL V -2.5 0 +2.5 V
BPRZ Input Voltage (Ref. to DFDAU Signal Ground)
RINA ONE V 3.25 5.0 6.5 V
ZERO V -6.5 -5.0 -3.25 V
RINB ONE V -6.5 -5.0 -3.25 V
ZERO V 3.25 5.0 6.5 V
(RINAto RINB)
µ
Pull-down Current (MR, SI, SCK,ACLK pins) I 60 µA
Pull-up current ( pin) I -60 µA
IHHA
ILHA
IHHB
ILHB
IHB
ILB
INUL
IHBA
ILBA
IHBB
ILBB
PD
PU
BI-POLAR RETURN TO ZERO (BPRZ) INPUTS - Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms)
HARVARD BI-PHASE (HBP) & BI-POLAR RETURN TO ZERO (BPRZ) INPUTS
Ω
Ω
Ω
80% VDD
0% VDD2
CS
HOLT INTEGRATED CIRCUITS
21
HI-3717A
Supply Voltages V ......................................... -0.3V to +5.0V
V+ ......................................................... +7.0V
V- ......................................................... -7.0V
Voltage at pins RINxx-xx .................................. -120V to +120V
Voltage at pins TXAOUT, TXBOUT, AMPA, AMPB ......... V- to V+
Voltage at any other pin ...............................-0.3V to V +0.3V
Solder temperature (Reflow) ............................................. 260
DD
DD
°C
Power Dissipation at 25°C
Plastic Quad Flat Pack ............... 1.5 W, derate 10mW/ C
DC Current Drain per digital input pin ........................... ±10mA
Operating Temperature Range (Industrial): ..... -40°C to +85°C
(Hi-Temp): ..... -55°C to +125°C
°
Storage Temperature Range ........................ -65°C to +150°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
HARVARD BI-PHASE (HBP) OUTPUTS - Pins TXOUTHA, TXOUTHB, (or OUTHA, OUTHB with external 32.5 Ohms)
BI-POLAR RETURN TO ZERO (BPRZ) OUTPUTS - Pins TXOUTBA, TXOUTBB, (or OUTBA, OUTBB with external 32.5 Ohms)
HARVARD BI-PHASE (HBP) and BI-POLAR RETURN TO ZERO (BPRZ) OUTPUTS
LOGIC OUTPUTS (Including TXHA, TXHB, TXBA & TXBB)
OPERATING VOLTAGE RANGE
OPERATING SUPPLY CURRENT
HBP output voltage (Differential) HI V 600 ohm load 4.0 5.0 6.0 V
(TXOUTHA to TXOUTHB or OUTHA to OUTHB) LO V -6.0 -5.0 -4.0 V
HBP output voltage (Ref to GND)
TXOUTHA or OUTHA HI V 600 ohm load 4.5 5.0 5.5 V
LO V -0.5 0 +0.5 V
TXOUTHB or OUTHB HI V -0.5 0 +0.5 V
LO V 4.5 5.0 5.5 V
BPRZ output voltage (Differential) ONE V No load 9.0 10.0 11.0 V
(TXOUTBA to TXOUTBB or OUTBA to OUTBB) ZERO V -11.0 -10.0 -9.0 V
NULL V -0.5 0 +0.5 V
BPRZ output voltage (Ref to GND)
TXOUTBA or OUTBA ONE V No load 4.5 5.0 5.5 V
ZERO V -5.5 -5.0 -4.5 V
TXOUTBB or OUTBB ONE V -5.5 -5.0 -4.5 V
ZERO V 4.5 5.0 5.5 V
Output current I Momentary short-circuit current 80 mA
Output Voltage: Logic "1" Output Voltage V I = -100µA V
Logic "0" Output Voltage V I = 1.0mA V
Output Current: Output Sink I V = 0.4V 1.6 mA
Output Source I V = V - 0.4V -1.0 mA
Output Capacitance: C 15 pF
V 3.15 3.45 V
Transmitting Data at 8192 words/sec. I Outputs Unloaded 35 mA
Transmitting Data in 8192 words/sec. I 600 Ohm Differential Output Load 120 mA
400 Ohm Differential Output Load
OHH
OLH
OHHA
OLHA
OHHB
OLHB
OHB
OLB
ONUL
OHBA
OLBA
OHBB
OLBB
OUT
OH OH
OL OL
OL OUT
OH OUT DD
O
DD
90%VDD
10% VDD
HBP
BPRZ
DD
DDL
V = 3.3V, TA = Operating Temperature Range (unless otherwise specified).DD
DC ELECTRICAL CHARACTERISTICS (cont.)
LIMITS
PARAMETER CONDITIONS UNIT
SYMBOL MIN TYP MAX
HOLT INTEGRATED CIRCUITS
22
HI-3717A
SPI INTERFACE TIMING
RECEIVER TIMING
SCK clock period
active after last SCK rising edge t 5 ns
setup time to first SCK rising edge t 5 ns
hold time after last SCK falling edge t 5 ns
inactive between SPI instructions t
Delay - INSYNC high to REMPTY low (plus 12 data bits) t 100 ns
TFEMPY flag high to beginningt of first data bit of last word in Transmit FIFO
Line driver transition differential times (Both the Harvard Bi-Phase and Bi-Polar Return to Zero are set to the same slew rate)
t 100 ns
55 ns
SPI SI Data set-up time to SCK rising edge t 10 ns
SPI SI Data hold time after SCK rising edge t 10 ns
SCK rise time t 10 ns
SCK fall ime t 10 ns
SCK pulse width high t 20 ns
SCK pulse width low t 25 ns
SO valid after SCK falling edge t 35 ns
SO high-impedance after inactive t 30 ns
MR pulse width t 40 ns
Delay - RFFULL high to ROVF high (plus 12 data bits) t 100 ns
32 words / sec. t 2604 µs
64 words / sec. t 1302 µs
128 words / sec. t 651 µs
256 words / sec. t 326 µs
512 words / sec. t 163 µs
1024 words / sec. t 81.4 µs
2048 words / sec. t 41.7 µs
4094 words / sec. t 20.4 µs
8192 words / sec. t 10.2 µs
CNTL0<2:1> = 00 high to low t 5.0 7.5 10 µs
low to high t 5.0 7.5 10 µs
CNTL0<2:1> = 01 high to low t 2.5 3.75 5.0 µs
low to high t 2.5 3.75 5.0 µs
CNTL0<2:1> = 10 high to low t 5.0 10 15 µs
low to high t 5.0 10 15 µs
CNTL0<2:1> = 11 high to low t 1.0 1.5 2.0 µs
low to high t 1.0 1.5 2.0 µs
Transmitter digital outputs transition times
Harvard Bi-Phase (HBP) high to low t 3.0 5.0 ns
low to high t 3.0 5.0 ns
Bi-Polar Return to Zero (BPRZ) high to low t 3.0 5.0 ns
low to high t 3.0 5.0 ns
CYC
CPH
DS
DH
SCKR
SCKF
SCKH
SCKL
DV
CHZ
ROVF
TEMPTY (32 wps)
TEMPTY (64 wps)
TEMPTY (128 wps)
TEMPTY (256 wps)
TEMPTY (512 wps)
TEMPTY (1024 wps)
TEMPTY (2048 wps)
TEMPTY (4096 wps)
TEMPTY (8192 wps)
fx
rx
fx
rx
fx
rx
fx
rx
Hf
Hr
Bf
Br
CS
CS
CS
CS
CHH
CES
CEH
REMPTY
CS
MR
TRANSMITTER TIMING
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, TA = Operating Temperature Range and ACLK=24MHz 0.1%+
LIMITS
PARAMETER SYMBOL UNITS
MIN TYP MAX
HOLT INTEGRATED CIRCUITS
23
HI-3717A
HOLT INTEGRATED CIRCUITS
24
HI-3717A
LIMITS
PARAMETER TEST CONDITIONS UNITS
MIN TYP MAX
SYMBOL
Capacitor Requirements (see block diagram on p. 2 for capacitor placement)
Start-up transient (V+, V-)
Operating Switching Frequency f - 650 - kHz
Worst case maximum voltage doubler output V - 6.93 V
t--10ms
V
V - -6.93 V
V+ Fly-back capacitor, non-polarized C 0.47 - - µF
x7R MLCC, 10V minimum ESR 500 kHz 500 m
V- Fly-back capacitor, non-polarized C 2.2 - - µF
x7R MLCC, 10V minimum ESR 500 kHz 500 m
Two bulk storage capacitors, non-polarized C 10 - 47 µF
X7R MLCC or tantalum, 10V minimum ESR 500 kHz 300 m
Supply de-coupling capacitors, C Two parallel capacitors - 0.1 - µF
x7R MLCC or tantalum, 10V minimum 10 47 µF
START
DD = 3.6V, T= -55C, Open load
DD2-(max)
OUT
SW
DD2+(max)
FLY+
(CFLY+)
FLY-
(CFLY-)
(COUT)
SUPPLY
W
W
W
CONVERTER CHARACTERISTICS
V = +3.3V, T = Operating Temperature (unlesss otherwise stated)DD A
ORDERING INFORMATION
HI - 3717A xx x x
PACKAGE
DESCRIPTION
44 PIN PLASTIC CHIP-SCALE, QFN (44PCS)
PART
NUMBER
PC
44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PMQS)
PQ
LEAD
FINISH
PART
NUMBER
100% Matte Tin (Pb-free, RoHS compliant)
F
Tin / Lead (Sn / Pb) Solder
Blank
TEMPERATURE
RANGE
BURN
IN
-40°C TO +85°C No
-55°C TO +125°C No
T
PART
NUMBER
T
I
FLOW
I
HOLT INTEGRATED CIRCUITS
25
HI-3717A
-55°C TO +125°C Yes
M
M
The HI-3717APCx uses a 44-pin plastic chip-scale
package. This package has a metal heat sink pad on its
bottom surface. This heat sink is electrically isolated from
the die. To enhance thermal dissipation, the heat sink can
be soldered to matching circuit board pad.
HEAT SINK - CHIP-SCALE PACKAGE ONLY
REVISION HISTORY
P/N Rev Date Description of Change
DS3717B NEW 03/12/15 Initial Release.
A 05/4/15 Clarify that CS must be asserted for every word read from the FIFO (cannot hold
CS low and read multiple words). Remove reference to ARINC 573 standard.
B 08/31/15 Eliminate “Flight” and “Test” mode nomenclature and rename to 4 Sync-Word
mode and 2 Sync-Word mode respectively. Both modes are equally valid to
achieve synchronization. Add note on p. 13 regarding synchronization. Update
SPI Serial Output Timing diagram. Correct numerous typos.
C 07/29/16 FIFO operation: TFIFO pin indicates Transmit FIFO status is Full or Half-Full
(not Full or Empty).
Correct labeling error on Figure 10, SPI Serial Input Timing Diagram.
HOLT INTEGRATED CIRCUITS
26
HI-3717A
HI-3717A PACKAGE DIMENSIONS
HOLT INTEGRATED CIRCUITS
27
44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
Package Type: 44PCS
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
5.50 ± 0.050
(0.217 ± 0.002)
0.400 ± 0.050
(0.016 ± 0.002)
0.25 ± 0.050
(0.010 )± 0.002
0.50
(0.0197)
0.200
(0.008)
1.00
(0.039)
7.00
(0.276)
BSC
5.50 ± 0.050
(0.217 ± 0.002)
typ
Bottom
View
Top View
BSC
7.00
(0.276)BSC
max
millimeters (inches)
Electrically isolated heat
sink pad on bottom of
package
Connect to any ground or
power plane for optimum
thermal dissipation
Package Type:
0° £ Q £ 7°
Detail A
See Detail A
SQ.
44PMQS
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
0.230
(0.009)
13.200
(0.520)
10.000
(0.394
SQ.
MAX.
0.370 ± 0.080
(0.015 ± 0.003)
0.880 .150±0
(0.035 ± 0.006)
0.13
(0.005)R MIN.
0.30
(0.012)R MAX.
2.00 .20±0
(0.079 .008)±0
2.70
(0.106)MAX.
0.80
(0.031)
millimeters (inches)
BSC
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
BSC BSC
0.20
(0.008)min
1.60
(0.063)
typ
