212 Series of Decoders
Selection Table
Function Address
No.
Data VT Oscillator Trigger Package
Part No. No. Type
HT12D 8 4 L ÖRC oscillator DIN active ²Hi²18 DIP/20 SOP
HT12F 12 0 ¾Ö
RC oscillator DIN active ²Hi²18 DIP/20 SOP
Notes: Data type: L stands for latch type data output.
VT can be used as a momentary data output.
1 July 12, 1999
General Description
The 212 decoders are a series of CMOS LSIs for
remote control system applications. They are
paired with Holtek¢s2
12 series of encoders (re-
fer to the encoder/decoder cross reference ta-
ble). For proper operation, a pair of
encoder/decoder with the same number of ad-
dresses and data format should be chosen.
The decoders receive serial addresses and data
from a programmed 212 series of encoders that
are transmitted by a carrier using an RF or an
IR transmission medium. They compare the se-
rial input data three times continuously with
their local addresses. If no error or unmatched
codes are found, the input data codes are de-
coded and then transferred to the output pins.
The VT pin also goes high to indicate a valid
transmission.
The 212 series of decoders are capable of decod-
ing informations that consist of N bits of ad-
dress and 12-N bits of data. Of this series, the
HT12D is arranged to provide 8 address bits
and 4 data bits, and HT12F is used to decode 12
bits of address information.
Features
·Operating voltage: 2.4V~12V
·Low power and high noise immunity CMOS
technology
·Low standby current
·Capable of decoding 12 bits of information
·Pair with Holtek¢s2
12 series of encoders
·Binary address setting
·Received codes are checked 3 times
·Address/Data number combination
-HT12D: 8 address bits and 4 data bits
-HT12F: 12 address bits only
·Built-in oscillator needs only 5% resistor
·Valid transmission indicator
·Easy interface with an RF or an infrared
transmission medium
·Minimal external components
Applications
·Burglar alarm system
·Smoke and fire alarm system
·Garage door controllers
·Car door controllers
·Car alarm system
·Security system
·Cordless telephones
·Other remote control systems
Block Diagram
Note: The address/data pins are available in various combinations (see the address/data table).
Pin Assignment
212 Series of Decoders
2 July 12, 1999
D ata Shift
R egister
O scillator
Buffer
S y n c . D e te c to r
D ivider
C om parator C om parator
Buffer T ra n s m is s io n G a te C irc u it
D a ta D e te c to r
C ontrol Logic
OSC1OSC2
DIN
VDD VSS
VT
Data
Latch C ircuit
Address
8-Address
4-D ata
12-A ddress
0 -D a ta
A0
A1
A2
A3
A4
A5
A6
A7
VSS
VDD
VT
OSC1
OSC2
DIN
D11
D10
D9
D8
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
12-A ddress
0 -D a ta
A0
A1
A2
A3
A4
A5
A6
A7
VSS
VDD
VT
OSC1
OSC2
DIN
A11
A10
A9
A8
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
VDD
VT
OSC1
OSC2
DIN
A11
A10
A9
A8
NC
A0
A1
A2
A3
A4
A5
A6
A7
VSS
8-Address
4-D ata
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
VDD
VT
OSC1
OSC2
DIN
D11
D10
D9
D8
NC
A0
A1
A2
A3
A4
A5
A6
A7
VSS
HT12F
2 0 S O P
H T12F
18 D IP
H T12D
18 D IP
HT12D
2 0 S O P
Pin Description
Pin Name I/O Internal
Connection Description
A0~A11 I
NMOS
TRANSMISSION
GATE
Input pins for address A0~A11 setting
They can be externally set to VDD or VSS.
D8~D11 O CMOS OUT Output data pins
DIN I CMOS IN Serial data input pin
VT O CMOS OUT Valid transmission, active high
OSC1 I OSCILLATOR Oscillator input pin
OSC2 O OSCILLATOR Oscillator output pin
VSS I ¾Negative power supply (GND)
VDD I ¾Positive power supply
Approximate internal connection circuits
Absolute Maximum Ratings
Supply Voltage...............................-0.3V to 13V Storage Temperature.................-50°Cto125°C
Input Voltage....................VSS-0.3 to VDD+0.3V Operating Temperature ..............-20°Cto75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-
mum Ratings²may cause substantial damage to the device. Functional operation of this de-
vice at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
212 Series of Decoders
3 July 12, 1999
NMOS
TRANSM ISSION
GATE
C M O S IN
O SC ILLATO R
OSC1 OSC2
CMOS OUT
EN
Electrical Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾¾ 2.4 5 12 V
ISTB Standby Current 5V Oscillator stops ¾0.1 1 mA
12V ¾24
mA
IDD Operating Current 5V No load
fOSC=150kHz ¾200 400 mA
IO
Data Output Source
Current (D8~D11) 5V VOH=4.5V -1-1.6 ¾mA
Data Output Sink
Current (D8~D11) 5V VOL=0.5V 1 1.6 ¾mA
IVT
VT Output Source Current 5V
VOH=4.5V -1-1.6 ¾mA
VT Output Sink Current VOL=0.5V 1 1.6 ¾mA
VIH ²H²Input Voltage 5V ¾3.5 ¾5V
VIL ²L²Input Voltage 5V ¾0¾1V
fOSC Oscillator Frequency 5V ROSC=51kW¾
150 ¾kHz
212 Series of Decoders
4 July 12, 1999
212 Series of Decoders
5 July 12, 1999
Functional Description
Operation
The 212 series of decoders provides various com-
binations of addresses and data pins in differ-
ent packages so as to pair with the 212 series of
encoders.
The decoders receive data that are transmitted
by an encoder and interpret the first N bits of
code period as addresses and the last 12-N bits
as data, where N is the address code number. A
signal on the DIN pin activates the oscillator
which in turn decodes the incoming address
and data. The decoders will then check the re-
ceived address three times continuously. If the
received address codes all match the contents of
the decoder¢s local address, the 12-N bits of
data are decoded to activate the output pins
and the VT pin is set high to indicate a valid
transmission. This will last unless the address
code is incorrect or no signal is received.
The output of the VT pin is high only when the
transmission is valid. Otherwise it is always
low.
Output type
Of the 212 series of decoders, the HT12F has no
data output pin but its VT pin can be used as a
momentary data output. The HT12D, on the
other hand, provides 4 latch type data pins
whose data remain unchanged until new data
are received.
Part
No.
Data
Pins
Address
Pins
Output
Type
Operating
Voltage
HT12D 4 8 Latch 2.4V~12V
HT12F 0 12 ¾2.4V~12V
Flowchart
The oscillator is disabled in the standby state
and activated when a logic ²high²signal applies
to the DIN pin. That is to say, the DIN should be
kept low if there is no signal input.
Yes
C ode in ?
Store data
No
Yes
No
No
No
Yes
Standby m ode
D isable V T &
ignore the rest of
th is w o rd
Yes
No
Yes
Address or
data error ?
Latch data
to o u tp u t &
a c tiv a te V T
Address bits
m atched ?
Match
previous stored
data ?
Power on
3 tim es
of checking
com pleted ?
Decoder timing
Encoder/Decoder cross reference table
Decoders
Part No. Data Pins Address Pins VT Pair Encoder
Package
Encoder Decoder
DIP SOP DIP SOP
HT12D 4 8 ÖHT12A 18 20 18 20
HT12E 18 20
HT12F 0 12 ÖHT12A 18 20 18 20
HT12E 18 20
Address/Data sequence
The following table provides address/data sequence for various models of the 212 series of decoders. A
correct device should be chosen according to the requirements of the individual addresses and data.
Part No. Address/Data Bits
0 1 2 3 4 5 6 7 8 9 10 11
HT12D A0 A1 A2 A3 A4 A5 A6 A7 D8 D9 D10 D11
HT12F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
212 Series of Decoders
6 July 12, 1999
2 c lo c k s
14
check
4 w ords 4 w ords
Encoder
DOUT
Transm itted
C ontinuously
< 1 w ord
Encoder
Transm ission
Enable
check
D ecoder VT
Latched
Data Out
2 clocks
14
Oscillator frequency vs supply voltage
The recommended oscillator frequency is fOSCD (decoder) @50 fOSCE (HT12E encoder)
@1
3fOSCE (HT12A encoder).
212 Series of Decoders
7 July 12, 1999
fo s c
(S cale)
Rosc (
9
)
0.50
(100kH z)1.00
1.50
2 .0 0
2 .5 0
3.50
4.00
3.00
0.25
2345678910111213VDD (V DC)
68k
62k
56k
51k
47k
43k
39k
36k
33k
30k
27k
75k
82k
100k
120k
150k
180k
220k
Application Circuits
Notes: Typical infrared receiver: PIC-12043T/PIC-12043S (KODESHI CORP.)
or LTM9052 (LITEON CORP.)
Typical RF receiver: JR-200 (JUWA CORP.)
RE-99 (MING MICROSYSTEM, U.S.A.)
212 Series of Decoders
8 July 12, 1999
Receiver Circuit
H T12D
A0
A1
A2
A3
A4
A5
A6
A7
VSS
VDD
VT
OSC1
OSC2
DIN
D11
D10
D9
D8
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
R
OSC
VDD
R e c e iv e r C ir c u it
H T12F
A0
A1
A2
A3
A4
A5
A6
A7
VSS
VDD
VT
OSC1
OSC2
DIN
A11
A10
A9
A8
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
R
OSC
VDD
212 Series of Decoders
9 July 12, 1999
Copyright ã1999 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Microelectronics Enterprises Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
