Low Noise, Low Drift, Low Power, 3-Axis MEMS Accelerometers ADXL356/ADXL357 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS V1P8ANA LDO VSUPPLY V1P8DIG RANGE POWER MANAGEMENT LDO XOUT Y X ANALOG FILTER TEMP SENSOR TEMP ST1 3-AXIS SENSOR ZOUT CONTROL LOGIC ADXL356 VSSIO ST2 STBY VDDIO 15429-001 YOUT Z VSS Figure 1. ADXL356 V1P8ANA LDO VSUPPLY V1P8DIG LDO X 3-AXIS SENSOR APPLICATIONS ADXL357 POWER MANAGEMENT ADC Y Z VDDIO DIGITAL FILTER ANALOG FILTER ADC TEMP SENSOR ADC FIFO VSSIO VSS CONTROL LOGIC ADC SERIAL I/O INT1 INT2 DRDY CS/SCL SCLK/VSSIO MOSI/SDA MISO/ASEL 15429-002 Hermetic package offers optimal long-term stability 0 g offset vs. temperature (all axes): 0.75 mg/C maximum Ultralow noise spectral density (all axes): 75 g/Hz Low power, VSUPPLY (LDO regulator enabled) ADXL356 in measurement mode: 150 A ADXL357 in measurement mode: 200 A ADXL356/ADXL357 in standby mode: 21 A ADXL356 has user adjustable analog output bandwidth ADXL357 digital output features Digital SPI and limited I2C interfaces supported 20-bit ADC Data interpolation routine for synchronous sampling Programmable high- and low-pass digital filters Integrated temperature sensor Voltage range options VSUPPLY with internal regulators: 2.25 V to 3.6 V V1P8ANA, V1P8DIG with internal LDO regulator bypassed: 1.8 V typical 10% Operating temperature range: -40C to +125C 14-terminal, 6 mm x 5.6 mm x 2.2 mm, LCC package Figure 2. ADXL357 Inertial measurement units (IMUs)/attitude and heading reference systems (AHRSs) Platform stabilization systems Structural health monitoring Seismic imaging Tilt sensing Robotics Condition monitoring GENERAL DESCRIPTION The analog output ADXL356 and the digital output ADXL357 are low noise density, low 0 g offset drift, low power, 3-axis accelerometers with selectable measurement ranges. The ADXL356B supports the 10 g and 20 g ranges, the ADXL356C supports the 10 g and 40 g ranges, and the ADXL357 supports the 10 g, 20 g, and 40 g ranges. The ADXL356/ADXL357 offer industry leading noise, minimal offset drift over temperature, and long-term stability, enabling precision applications with minimal calibration. 1 The low drift, low noise, and low power ADXL357 enables accurate tilt measurement in an environment with high vibration. The low noise of the ADXL356 over higher frequencies is ideal for condition-based monitoring and other vibration sensing applications. The ADXL357 multifunction pin names may be referenced only by their relevant function for either the serial peripheral interface (SPI) or limited I2C interface. Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADXL356/ADXL357 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DRDY Pin .................................................................................... 29 Applications ....................................................................................... 1 FIFO_FULL................................................................................. 29 Functional Block Diagrams ............................................................. 1 FIFO_OVR .................................................................................. 29 General Description ......................................................................... 1 Activity ......................................................................................... 29 Revision History ............................................................................... 3 External Synchronization and Interpolation .......................... 29 Specifications..................................................................................... 4 ADXL357 Register Map ................................................................. 32 Analog Output for the ADXL356 ............................................... 4 Register Definitions........................................................................ 33 Digital Output for the ADXL357 ............................................... 5 Analog Devices ID Register ...................................................... 33 SPI Digital Interface Characteristics for the ADXL357 .......... 7 Analog Devices MEMS ID Register......................................... 33 2 I C Digital Interface Characteristics for the ADXL357 ........... 8 Device ID Register ..................................................................... 33 Absolute Maximum Ratings............................................................ 9 Product Revision ID Register ................................................... 33 Thermal Resistance ...................................................................... 9 Status Register ............................................................................. 33 Recommended Soldering Profile ............................................... 9 FIFO Entries Register ................................................................ 34 ESD Caution .................................................................................. 9 Temperature Data Registers ...................................................... 34 Pin Configurations and Function Descriptions ......................... 10 X-Axis Data Registers ................................................................ 34 Typical Performance Characteristics ........................................... 12 Y-Axis Data Registers ................................................................ 35 Root Allan Variance (RAV) ADXL357 Characteristics ......... 20 Z-Axis Data Registers ................................................................ 35 Theory of Operation ...................................................................... 21 FIFO Access Register ................................................................. 36 Applications Information .............................................................. 22 X-Axis Offset Trim Registers .................................................... 36 Analog Output ............................................................................ 22 Y-Axis Offset Trim Registers .................................................... 36 Digital Output ............................................................................. 22 Z-Axis Offset Trim Registers .................................................... 37 Axes of Acceleration Sensitivity ............................................... 23 Activity Enable Register ............................................................ 37 Power Sequencing ...................................................................... 23 Activity Threshold Registers ..................................................... 37 Power Supply Description ......................................................... 23 Activity Count Register ............................................................. 37 Overrange Protection................................................................. 23 Filter Settings Register ............................................................... 38 Self Test ........................................................................................ 23 FIFO Samples Register .............................................................. 38 Filter ............................................................................................. 24 Interrupt Pin (INTx) Function Map Register......................... 38 Serial Communications ................................................................. 26 Data Synchronization ................................................................ 39 SPI Protocol ................................................................................. 26 I2C Speed, Interrupt Polarity, and Range Register ................. 39 SPI Bus Sharing ........................................................................... 26 Power Control Register ............................................................. 39 I2C Protocol ................................................................................. 27 Self Test Register ......................................................................... 40 Reading Acceleration or Temperature Data from the Interface ....................................................................................................... 27 Reset Register .............................................................................. 40 PCB Footprint Pattern ................................................................... 41 FIFO ................................................................................................. 28 Outline Dimensions ....................................................................... 42 Interrupts ......................................................................................... 29 Ordering Guide .......................................................................... 42 DATA_RDY................................................................................. 29 Rev. A | Page 2 of 42 Data Sheet ADXL356/ADXL357 REVISION HISTORY 6/2020--Rev. 0 to Rev. A Changes to Features Section, Applications Section, and General Description Section ........................................................................... 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 5 Changes to Input Current Parameter, Table 3 ............................... 7 Changes to Acceleration (Any Axis, 0.1 ms) Parameter, Table 5; Thermal Resistance Section; and Table 6 ....................................... 9 Moved Recommended Soldering Profile Section, Figure 5, and Table 7 ................................................................................................. 9 Changes to Table 8 ..........................................................................10 Changes to Typical Performance Section and Figure 8 to Figure 13 ...........................................................................................12 Changes to Figure 14 to Figure 19 ................................................13 Changes to Figure 23 to Figure 25 ................................................14 Changes to Figure 32 to Figure 37 ................................................16 Changes to Figure 44 Caption, Figure 47 Caption, and Figure 48 Caption .............................................................................................18 Changes to Figure 50 Caption, Figure 52 Caption, and Figure 53 ...........................................................................................19 Changes to Theory of Operation Section ....................................21 Changes to Power Sequencing Section, V1P8ANA Section, and Overrange Protection Section .......................................................23 Changes to Self Test Section, Filter Section, Figure 62, and Figure 63 ...........................................................................................24 Changes to Table 11 ........................................................................25 Changes to Serial Communications Section and Figure 64 ......26 Added SPI Bus Sharing Section and Figure 65; Renumbered Sequentially ......................................................................................26 Changes to I2C Protocol Section ...................................................27 Changes to FIFO Section ...............................................................28 Changes to DRDY Pin Section, FIFO_OVR Section, Activity Section, NVM_BUSY Section, and External Synchronization and Interpolation Section .............................................................. 29 Changed EXT_SYNC = 00--No External Sync or Interpolation Section to EXT_SYNC = 00, EXT_CLK = 0--No External Synchronization or Interpolation Section; EXT_SYNC = 10-- External Sync with Interpolation Section to EXT_SYNC = 10, EXT_CLK = 0--External Synchronization with Interpolation Section; and EXT_SYNC = 01--External Sync and External Clock, No Interpolation Filter Section to EXT_SYNC = 01, EXT_CLK = 1--External Synchronization and External Clock, No Interpolation Filter Section ..................................................... 30 Changes to EXT_SYNC = 00, EXT_CLK = 0--No External Synchronization or Interpolation Section, EXT_SYNC = 10, EXT_CLK = 0--External Synchronization with Interpolation Section, Table 13, and EXT_SYNC = 01, EXT_CLK = 1-- External Synchronization and External Clock, No Interpolation Filter Section .................................................................................... 30 Added EXT_SYNC = 10, EXT_CLK = 1--External Synchronization and External Clock, with Interpolation Filter Section .............................................................................................. 30 Changes to Table 14 ........................................................................ 31 Changes to Figure 74, Figure 75 Caption, and Figure 76 .......... 31 Changes to Temperature Data Registers Section, Table 23, Table 24, and Table 25..................................................................... 34 Changes to Table 27, Table 28, Table 30 and Table 31 ................ 35 Change to Table 42 Title ................................................................. 37 Changes to Table 44 ........................................................................ 38 Changes to Reset Register Section ................................................ 40 Changes to Figure 77 ...................................................................... 41 Changes to Ordering Guide ........................................................... 42 2/2017--Revision 0: Initial Version Rev. A | Page 3 of 42 ADXL356/ADXL357 Data Sheet SPECIFICATIONS ANALOG OUTPUT FOR THE ADXL356 TA = 25C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, z-axis acceleration = 1 g, and full-scale range = 10 g, unless otherwise noted. Table 1. Parameter SENSOR INPUT Output Full-Scale Range (FSR) Resonant Frequency1 Nonlinearity Cross Axis Sensitivity SENSITIVITY Sensitivity at XOUT, YOUT, ZOUT Sensitivity Change Due to Temperature Repeatability2 0 g OFFSET 0 g Output for XOUT, YOUT, ZOUT 0 g Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)3 Repeatability2 Vibration Rectification Error (VRE)4 NOISE Spectral Density5 X-Axis, Y-Axis, and Z-Axis Velocity Random Walk X-Axis and Y-Axis Z-Axis BANDWIDTH SELF TEST Output Change Z-Axis POWER SUPPLY Voltage Range VSUPPLY8 VDDIO V1P8ANA, V1P8DIG Current Measurement Mode VSUPPLY V1P8ANA V1P8DIG Test Conditions/Comments Each axis ADXL356B supports two ranges ADXL356C supports two ranges Min Max Unit g g kHz % FSR % FSR % 10, 20 10, 40 5.5 0.1 1.3 1 10 g 40 g Ratiometric to V1P8ANA 10 g 20 g 40 g TA = -40C to +125C X-axis and y-axis Z-axis Each axis, 10 g Referred to V1P8ANA/2 TA = -40C to +125C Typ 73.6 36.8 18.4 80 40 20 0.01 0.1 0.2 86.4 43.2 21.6 mV/g mV/g mV/g %/C % % -375 -0.75 125 0.2 +375 +0.75 mg mg/C X-axis and y-axis Z-axis Offset due to 7.5 g rms vibration, 10 g range, in a 1 g orientation 4.25 5 <0.1 mg mg g 10 g 40 g 10 g 75 110 g/Hz g/Hz 38.2 26.5 mm/sec/Hr mm/sec/Hr kHz -3 dB, overall transfer function6 10 g range7 Internal low dropout (LDO) regulator bypassed, VSUPPLY = 0 V LDO regulator enabled LDO regulator disabled LDO regulator disabled Rev. A | Page 4 of 42 2.4 0.5 1.25 3.0 g 2.25 V1P8DIG 1.62 2.5 2.5 1.8 3.6 3.6 1.98 V V V 150 138 12 A A A Data Sheet Parameter Standby Mode VSUPPLY V1P8ANA V1P8DIG Turn On Time9 OUTPUT AMPLIFIER Swing Output Series Resistance TEMPERATURE SENSOR Output at 25C Scale Factor TEMPERATURE Operating Temperature Range ADXL356/ADXL357 Test Conditions/Comments LDO regulator enabled LDO regulator disabled LDO regulator disabled 10 g range Power-off to standby XOUT, YOUT, ZOUT, and TEMP pins No load Min Typ Max Unit 21 7 10 <10 <10 0.03 A A A ms ms 32 V1P8ANA - 0.03 V k 967 3.0 mV mV/C -40 +125 C 1 The resonant frequency is a sensor characteristic. Repeatability is predicted for a 10 year life and includes shifts due to the high temperature operating life (HTOL) (TA = 150C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (-55C to +125C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: 4.25 mg x (2.5 years/10 years) = 2.125 mg. 3 The temperature change is -40C to +25C, or +25C to +125C. 4 The VRE measurement is the shift in dc offset while the device is subject to 7.5 g rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is configured for the 10 g range and an output data rate of 4 kHz. The VRE scales with the range setting. 5 Based on characterization. 6 Overall transfer function includes the sensor mechanical response and all other filters on the signal chain. 7 10 g indicates a test condition. The self test result converted to the acceleration value is independent of the selected range. 8 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS. 9 Standby to measurement mode. This specification is valid when the output is within 5 mg of the final value. 2 DIGITAL OUTPUT FOR THE ADXL357 TA = 25C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, z-axis acceleration = 1 g, full-scale range = 10 g, and output data rate (ODR) = 500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced only by their relevant function. Table 2. Parameter SENSOR INPUT Output Full Scale Range (FSR) Nonlinearity Cross Axis Sensitivity SENSITIVITY1 X-Axis, Y-Axis, and Z-Axis Sensitivity X-Axis, Y-Axis, and Z-Axis Scale Factor Sensitivity Change due to Temperature Repeatability2 0 g OFFSET X-Axis, Y-Axis, and Z-Axis 0 g Output 0 g Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)3 Test Conditions/Comments Each axis User selectable, supports three ranges Min TA = -40C to +125C Rev. A | Page 5 of 42 Max 10, 20, 40 0.1 1.3 1 10 g 40 g Each axis 10 g 20 g 40 g 10 g 20 g 40 g TA = -40C to +125C X-axis and y-axis Z-axis Each axis, 10 g Typ Unit g % FSR % FSR % 47,104 23,552 11,776 51,200 25,600 12,800 19.5 39 78 0.01 0.1 0.2 55,296 27,648 13,824 LSB/g LSB/g LSB/g g/LSB g/LSB g/LSB %/C % % -375 -0.75 125 0.20 +375 +0.75 mg mg/C ADXL356/ADXL357 Parameter Repeatability2 VRE4 NOISE Spectral Density5 X-Axis, Y-Axis, and Z-Axis Velocity Random Walk X-Axis and Y-Axis Z-Axis BANDWIDTH AND OUTPUT DATA RATE Analog-to-Digital Converter (ADC) Resolution Low-Pass Filter Passband Frequency High-Pass Filter Passband Frequency When Enabled (Disabled by Default) SELF TEST Output Change Z-Axis POWER SUPPLY Voltage Range VSUPPLY Operating7 VDDIO V1P8ANA and V1P8DIG Current Measurement Mode VSUPPLY V1P8ANA V1P8DIG Standby Mode VSUPPLY V1P8ANA V1P8DIG Turn On Time8 Data Sheet Test Conditions/Comments X-axis and y-axis Z-axis Offset due to 7.5 g rms vibration, 10 g range, in a 1 g orientation Min 10 g 40 g 10 g Typ 4.25 5 <0.1 Max 75 90 g/Hz g/Hz 38.2 26.5 mm/sec/Hr mm/sec/Hr 20 User programmable, Register 0x28 User programmable, Register 0x28 for 4 kHz ODR 0.977 0.0095 10 g range6 0.5 Internal LDO regulator bypassed, VSUPPLY = 0 V 2.25 V1P8DIG 1.62 Unit mg mg g 1000 10 Bits Hz Hz 1.25 3.0 g 2.5 2.5 1.8 3.6 3.6 1.98 V V V LDO regulator enabled LDO regulator disabled LDO regulator disabled 200 160 35.5 A A A LDO regulator enabled LDO regulator disabled LDO regulator disabled 10 g range Power-off to standby 21 7 10 <10 <10 A A A ms ms 1885 -9.05 LSB LSB/C TEMPERATURE SENSOR Output at 25C Scale Factor TEMPERATURE Operating Temperature Range -40 1 +125 C Characterized but not 100% tested. Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (TA = 150C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (-55C to +125C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: 4.25 mg x (2.5 years/10 years) = 2.125 mg. 3 The temperature change is -40C to +25C or +25C to +125C. 4 The VRE measurement is the shift in dc offset while the device is subject to 7.5 g rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the 10 g range and an output data rate of 4 kHz. The VRE scales with the range setting. 5 Based on characterization. 6 10 g indicates a test condition. The self test result converted to the acceleration value is independent of the selected range. 7 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS. 8 Standby to measurement mode. This specification is valid when the output is within 1 mg of final value. 2 Rev. A | Page 6 of 42 Data Sheet ADXL356/ADXL357 SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357 Note that multifunction pin names may be referenced by their relevant function only. Table 3. Parameter DC INPUT LEVELS Input Voltage Low Level High Level Input Current Low Level High Level DC OUTPUT LEVELS Output Voltage Low Level High Level Output Current Low Level High Level AC INPUT LEVELS SCLK Frequency SCLK High Time SCLK Low Time CS Setup Time CS Hold Time CS Disable Time Rising SCLK Setup Time MOSI Setup Time MOSI Hold Time AC OUTPUT LEVELS Propagation Delay Enable MISO Time Disable MISO Time Symbol Test Conditions/Comments VIL VIH Min Typ Max Unit 0.3 x VDDIO V V 0.7 x VDDIO IIL IIH Input voltage (VIN) = 0 V VIN = VDDIO VOL VOH IOL = IOL, MIN IOH = IOH, MAX IOL IOH VOL = VOL, MAX VOH = VOH, MIN -0.2 0.2 x VDDIO 0.8 x VDDIO -10 0.1 40 40 20 20 40 20 20 20 Load capacitance (CLOAD) = 30 pF 10 MHz ns ns ns ns ns ns ns ns 30 ns ns ns 30 20 tCSD CS tCSS tHIGH tLOW tCSH tSCLKS SCLK tSU tHD MOSI tP tDIS 15429-003 tEN MISO Figure 3. SPI Interface Timing Diagram Rev. A | Page 7 of 42 V V mA mA 4 tHIGH tLOW tCSS tCSH tCSD tSCLKS tSU tHD tP tEN tDIS A A 0.2 ADXL356/ADXL357 Data Sheet I2C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357 Note that multifunction pin names may be referenced only by their relevant function. Table 4. Parameter DC INPUT LEVELS Input Voltage Low Level High Level Hysteresis of Schmitt Triggered Inputs Input Current DC OUTPUT LEVELS Output Voltage Low Level Symbol VIL VIH VHYS IIL VOL1 VOL2 Output Current Low Level IOL AC INPUT LEVELS SCL Frequency SCL High Time SCL Low Time Start Setup Time Start Hold Time SDA Setup Time SDA Hold Time Stop Setup Time Bus Free Time SCL Input Rise Time SCL Input Fall Time SDA Input Rise Time SDA Input Fall Time Width of Spikes to Suppress AC OUTPUT LEVELS Propagation Delay Data Acknowledge Output Fall Time Test Conditions/ Comments tHIGH tLOW tSUSTA tHDSTA tSUDAT tHDDAT tSUSTO tBUF tRCL tFCL tRDA tFDA tSP Min I2C_HS = 0 (Fast Mode) Typ Max I2C_HS = 1 (High Speed Mode) Min Typ Max 0.3 x VDDIO 0.7 x VDDIO 0.05 x VDDIO 0.1 x VDDIO < VIN < 0.9 x VDDIO 0.3 x VDDIO +10 IOL = 3 mA VDDIO > 2 V VDDIO 2 V A 0.4 0.2 x VDDIO VOL = 0.4 V VOL = 0.6 V V V V 0.7 x VDDIO 0.1 x VDDIO -10 20 6 0.4 0.2 x VDDIO V V 20 6 0 260 500 260 260 50 0 260 500 1 mA mA 0 60 160 160 160 10 0 160 3.4 120 120 120 120 50 Not shown in Figure 4 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 80 80 160 160 10 CLOAD = 500 pF tVDDAT tVDACK tF 97 Not shown in Figure 4 450 450 120 20 x (VDDIO/5.5) 27 tFDA 135 tRDA ns ns ns tBUF SDA tSUDAT tHDDAT tLOW tVDDAT tHIGH tVDDAT SCL Figure 4. I2C Interface Timing Diagram Rev. A | Page 8 of 42 tFCL tRCL tVDACK tSUSTO tSUSTA 15429-004 tSUSTA tHDSTA Unit Data Sheet ADXL356/ADXL357 ABSOLUTE MAXIMUM RATINGS Table 5. RECOMMENDED SOLDERING PROFILE Rating Figure 5 and Table 7 provide details about the recommended soldering profile. 10,000 g 10,000 g 5.4 V 1.98 V RAMP-UP -0.3 V to VDDIO + 0.3 V tL TSMAX TSMIN tS t25C TO PEAK TIME Figure 5. Recommended Soldering Profile Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JB is the junction to board thermal resistance. Table 7. Recommended Soldering Profile Profile Feature Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time from TSMIN to TSMAX (tS) TSMAX to TL Ramp-Up Rate Liquid Temperature (TL) Time Maintained Above TL (tL) Table 6. Thermal Resistance JA 42 JB 17.6 RAMP-DOWN PREHEAT -40C to +125C -55C to +150C THERMAL RESISTANCE 1 TL 15429-005 -0.3 V to VDDIO + 0.3 V -0.3 V to V1P8ANA + 0.3 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Package Type E-14-11 CRITICAL ZONE TL TO TP tP TP TEMPERATURE Parameter Acceleration (Any Axis, 0.1 ms) Unpowered Powered VSUPPLY, VDDIO V1P8ANA, V1P8DIG Configured as Inputs ADXL356 Digital Inputs (RANGE, ST1, ST2, STBY) Analog Outputs (XOUT, YOUT, ZOUT, TEMP) ADXL357 Digital Pins (CS/SCL, SCLK/VSSIO, MOSI/SDA, MISO/ASEL, INT1, INT2, DRDY) Operating Temperature Range Storage Temperature Range Unit C/W Peak Temperature (TP) Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51. Time of Actual TP - 5C (tP) Ramp-Down Rate Time from 25C to Peak Temperature (t25C TO PEAK) ESD CAUTION Rev. A | Page 9 of 42 Condition Sn63/Pb37 Pb-Free 3C/sec 3C/sec maximum maximum 100C 150C 150C 200C 60 sec to 120 sec 3C/sec maximum 183C 60 sec to 150 sec 240C + 0C/-5C 10 sec to 30 sec 6C/sec maximum 6 minutes maximum 60 sec to 180 sec 3C/sec maximum 217C 60 sec to 150 sec 260C + 0C/-5C 20 sec to 40 sec 6C/sec maximum 8 minutes maximum ADXL356/ADXL357 Data Sheet 12 XOUT Y 11 VSUPPLY RANGE 1 ST1 2 ADXL356 10 V1P8ANA ST2 3 TOP VIEW (Not to Scale) 9 VSS 8 V1P8DIG X Z STBY 7 VSSIO 6 VDDIO 5 TEMP 4 15429-006 13 YOUT 14 ZOUT PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. ADXL356 Pin Configuration Table 8. ADXL356 Pin Function Descriptions Pin No. 1 Mnemonic RANGE 2 3 ST1 ST2 4 5 6 7 TEMP VDDIO VSSIO STBY 8 V1P8DIG 9 10 VSS V1P8ANA 11 VSUPPLY 12 13 14 XOUT YOUT ZOUT Description Range Selection Pin. Set this pin to ground to select the 10 g range, or set this pin to VDDIO to select the 20 g or 40 g range. This pin is model dependent (see the Ordering Guide section). Self Test Pin 1. This pin enables self test mode. This pin must be forced low when not in self test mode. Self Test Pin 2. This pin activates electromechanical self test actuation. This pin must be forced low when not in self test mode. Temperature Sensor Output. Digital Interface Supply Voltage. Digital Ground. Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin to VDDIO to enter measurement mode. Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally. Analog Ground. Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally. Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDO regulators to generate V1P8DIG and V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied. X-Axis Output. Y-Axis Output. Z-Axis Output. Rev. A | Page 10 of 42 12 INT1 CS/SCL 1 11 VSUPPLY SCLK/VSSIO 2 ADXL357 10 V1P8ANA MOSI/SDA 3 TOP VIEW (Not to Scale) 9 VSS 8 V1P8DIG X Z RESERVED 7 VSSIO 6 VDDIO 5 MISO/ASEL 4 Y 15429-007 13 INT2 ADXL356/ADXL357 14 DRDY Data Sheet Figure 7. ADXL357 Pin Configuration (SPI/I2C) Table 9. ADXL357 Pin Function Descriptions Pin No. 1 Mnemonic CS/SCL 2 SCLK/VSSIO 3 MOSI/SDA 4 MISO/ASEL 5 6 7 8 VDDIO VSSIO RESERVED V1P8DIG 9 10 VSS V1P8ANA 11 VSUPPLY 12 13 14 INT1 INT2 DRDY Description Chip Select for SPI (CS). Serial Communications Clock for I2C (SCL). Serial Communications Clock for SPI (SCLK). I2C Mode Enable (VSSIO). Connect this pin to Pin 6 (VSSIO) to enable I2C mode. Master Output, Slave Input for SPI (MOSI). Serial Data for I2C (SDA). Master Input, Slave Output for SPI (MISO). Alternate I2C Address Select for I2C (ASEL). Digital Interface Supply Voltage. Digital Ground. Reserved. This pin can be connected to ground or left open. Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally. Analog Ground. Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally. Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDO regulators to generate V1P8DIG and V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied. Interrupt Pin 1. Interrupt Pin 2. Data Ready Pin. Rev. A | Page 11 of 42 ADXL356/ADXL357 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS All figures include data for multiple devices and multiple lots, and they were taken in the 10 g range and TA = 25C, unless otherwise noted. For Figure 52, the ODR is derived from a master clock, with a frequency of 1.024 MHz and 1.4% device to device variation (similar to ODR device to device variation). For a given device, however, clock frequency variation over the temperature range (-40C to +125C) is no more than 1.2%, guaranteed by design. 1 100 1k 10k FREQUENCY (Hz) 0.01 10 100 1k 10k 0.1 0.01 10 100 1k 10k FREQUENCY (Hz) Figure 9. ADXL356 Frequency Response for Y-Axis 15429-012 RELATIVE YOUT (g) 1 15429-009 RELATIVE YOUT (g) 1 FREQUENCY (Hz) Figure 12. ADXL357 Frequency Response for Y-Axis at 4 kHz ODR 1 RELATIVE ZOUT (g) 10 1 100 1k FREQUENCY (Hz) 10k 15429-010 RELATIVE ZOUT (g) 10k Figure 11. ADXL357 Frequency Response for X-Axis at 4 kHz ODR 10 0.1 10 1k FREQUENCY (Hz) Figure 8. ADXL356 Frequency Response for X-Axis 0.1 10 100 Figure 10. ADXL356 Frequency Response for Z-Axis 0.1 0.01 10 100 1k 10k FREQUENCY (Hz) Figure 13. ADXL357 Frequency Response for Z-Axis at 4 kHz ODR Rev. A | Page 12 of 42 15429-013 0.1 10 0.1 15429-011 RELATIVE XOUT (g) 1 15429-008 RELATIVE XOUT (g) 10 Data Sheet ADXL356/ADXL357 1.0 SENSITIVITY NORMALIZED RELATIVE TO 25C (%) 50 25 0 -25 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) -0.5 -1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 17. ADXL356 Sensitivity Normalized Relative to 25C vs. Temperature X-Axis Figure 14. ADXL356 Zero g Offset Normalized Relative to 25C vs. Temperature, X-Axis 1.0 75 SENSITIVITY NORMALIZED RELATIVE TO 25C (%) 50 25 0 -25 0.5 0 -0.5 -75 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) -1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 15429-018 -50 15429-015 Figure 18. ADXL356 Sensitivity Normalized Relative to 25C vs. Temperature, Y-Axis Figure 15. ADXL356 Zero g Offset Normalized Relative to 25C vs. Temperature, Y-Axis 1.0 75 SENSITIVITY NORMALIZED RELATIVE TO 25C (%) 50 25 0 -25 0.5 0 -0.5 -50 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 16. ADXL356 Zero g Offset Normalized Relative to 25C vs. Temperature, Z-Axis -1.0 -40 15429-016 -75 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 15429-019 ZERO g OFFSET NORMALIZED RELATIVE TO 25C (mg) 0 15429-017 -75 -40 ZERO g OFFSET NORMALIZED RELATIVE TO 25C (mg) 0.5 -50 15429-014 ZERO g OFFSET NORMALIZED RELATIVE TO 25C (mg) 75 Figure 19. ADXL356 Sensitivity Normalized Relative to 25C vs. Temperature, Z-Axis Rev. A | Page 13 of 42 0 Z-AXIS OFFSET AT 25C (mg) 0 Figure 20. ADXL356 Zero g Offset Histogram at 25C, X-Axis 20 15 10 5 15 10 5 X-AXIS SENSITIVITY AT 25C (LSB/g) 30 0 Figure 21. ADXL356 Zero g Offset Histogram at 25C, Y-Axis Y-AXIS SENSITIVITY AT 25C (LSB/g) 25 20 20 0 Figure 22. ADXL356 Zero g Offset Histogram at 25C, Z-Axis Figure 25. ADXL356 Sensitivity Histogram at 25C, Z-Axis Rev. A | Page 14 of 42 Z-AXIS SENSITIVITY AT 25C (LSB/g) 15429-023 10 15429-024 15 15429-025 20 0.0736 0.0740 0.0744 0.0748 0.0752 0.0756 0.0760 0.0764 0.0768 0.0772 0.0776 0.0780 0.0784 0.0788 0.0792 0.0796 0.0800 0.0804 0.0808 0.0812 0.0816 0.0820 0.0824 0.0828 0.0832 0.0836 0.0840 0.0844 0.0848 0.0852 0.0856 0.0860 0.0864 25 PERCENT OF POPULATION (%) 30 0.0736 0.0740 0.0744 0.0748 0.0752 0.0756 0.0760 0.0764 0.0768 0.0772 0.0776 0.0780 0.0784 0.0788 0.0792 0.0796 0.0800 0.0804 0.0808 0.0812 0.0816 0.0820 0.0824 0.0828 0.0832 0.0836 0.0840 0.0844 0.0848 0.0852 0.0856 0.0860 0.0864 25 PERCENT OF POPULATION (%) 15429-020 375 325 275 225 175 125 75 25 -25 -75 -125 -175 -225 -275 -325 -375 PERCENT OF POPULATION (%) 40 0.0736 0.0740 0.0744 0.0748 0.0752 0.0756 0.0760 0.0764 0.0768 0.0772 0.0776 0.0780 0.0784 0.0788 0.0792 0.0796 0.0800 0.0804 0.0808 0.0812 0.0816 0.0820 0.0824 0.0828 0.0832 0.0836 0.0840 0.0844 0.0848 0.0852 0.0856 0.0860 0.0864 25 PERCENT OF POPULATION (%) Y-AXIS OFFSET AT 25C (mg) 15429-021 375 325 275 225 175 125 75 25 -25 -75 -125 -175 -225 -275 X-AXIS OFFSET AT 25C (mg) 15429-022 375 325 275 225 175 125 75 25 -25 -75 -125 -175 -225 -275 -325 -375 0 -325 PERCENT OF POPULATION (%) 0 -375 PERCENT OF POPULATION (%) ADXL356/ADXL357 Data Sheet 25 35 20 15 10 5 5 Figure 23. ADXL356 Sensitivity Histogram at 25C, X-Axis 25 20 15 10 5 Figure 24. ADXL356 Sensitivity Histogram at 25C, Y-Axis 15 10 5 Data Sheet ADXL356/ADXL357 0.20 0.10 0.15 0.05 OFFSET SHIFT (g) OFFSET SHIFT (g) 0.10 0.05 0 -0.05 -0.10 0 -0.05 0 2 4 6 8 10 INPUT VIBRATION (g rms) -0.10 15429-026 -0.20 0 5 10 15 20 25 INPUT VIBRATION (g rms) Figure 26. ADXL356 VRE, X-Axis Offset from +1 g, 10 g Range, X-Axis Orientation = +1 g 15429-029 -0.15 Figure 29. ADXL356 VRE, X-Axis Offset from -1 g, 40 g Range, X-Axis Orientation = -1 g 0.20 0.2 0.15 0.1 OFFSET SHIFT (g) OFFSET SHIFT (g) 0.10 0.05 0 -0.05 -0.10 0 -0.1 0 2 4 6 8 10 INPUT VIBRATION (g rms) -0.2 15429-027 -0.20 0 5 10 15 20 25 INPUT VIBRATION (g rms) Figure 27. ADXL356 VRE, Y-Axis Offset from +1 g, 10 g Range, Y-Axis Orientation = +1 g 15429-030 -0.15 Figure 30. ADXL356 VRE, Y-Axis Offset from -1 g, 40 g Range, Y-Axis Orientation = -1 g 0.20 0.2 0.15 OFFSET SHIFT (g) 0.1 0.05 0 -0.05 -0.10 0 -0.1 -0.20 0 2 4 6 8 10 INPUT VIBRATION (g rms) Figure 28. ADXL356 VRE, Z-Axis Offset from +1 g, 10 g Range, Z-Axis Orientation = +1 g -0.2 0 5 10 15 20 25 INPUT VIBRATION (g rms) Figure 31. ADXL356 VRE, Z-Axis Offset from -1 g, 40 g Range, Z-Axis Orientation = -1 g Rev. A | Page 15 of 42 15429-031 -0.15 15429-028 OFFSET SHIFT (g) 0.10 ADXL356/ADXL357 Data Sheet 75 1.0 0.8 SENSITIVITY NORMALIZED RELATIVE TO 25C (%) ZERO g OFFSET NORMALIZED RELATIVE TO 25C (mg) 50 25 0 -25 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -50 15 30 45 60 75 90 105 120 135 TEMPERATURE (C) -1.0 -40 15429-032 0 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 15429-035 -0.8 -75 -45 -30 -15 Figure 35. ADXL357 Sensitivity Normalized Relative to 25C vs. Temperature X-Axis Figure 32. ADXL357 Zero g Offset Normalized Relative to 25C vs. Temperature, X-Axis 1.0 75 SENSITIVITY NORMALIZED RELATIVE TO 25C (%) ZERO g OFFSET NORMALIZED RELATIVE TO 25C (mg) 0.8 50 25 0 -25 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -50 -5 15 35 55 75 95 115 TEMPERATURE (C) -1.0 -40 15429-033 -25 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 15429-036 -0.8 -75 -45 Figure 36. ADXL357 Sensitivity Normalized Relative to 25C vs. Temperature Y-Axis Figure 33. ADXL357 Zero g Offset Normalized Relative to 25C vs. Temperature, Y-Axis 1.0 75 SENSITIVITY NORMALIZED RELATIVE TO 25C (%) ZERO g OFFSET NORMALIZED RELATIVE TO 25C (mg) 0.8 50 25 0 -25 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -50 -25 -5 15 35 55 75 95 115 TEMPERATURE (C) Figure 34. ADXL357 Zero g Offset Normalized Relative to 25C vs. Temperature, Z-Axis -1.0 -40 15429-034 -75 -45 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 15429-037 -0.8 Figure 37. ADXL357 Sensitivity Normalized Relative to 25C vs. Temperature Z-Axis Rev. A | Page 16 of 42 ADXL356/ADXL357 40 30 35 35 40 55296 54784 54272 53760 53248 52736 52224 51712 51200 15429-041 55296 15429-042 55296 15429-043 54784 54272 53760 53248 52736 52224 51712 51200 15429-039 375 325 275 225 175 125 75 25 -25 -75 -125 -175 -225 0 -275 0 -325 5 50688 10 5 -375 50688 15 50176 10 20 49664 15 25 49152 20 30 48640 25 35 48128 30 47616 PERCENT OF POPULATION (%) 45 Y-AXIS SENSITIVITY AT 25C (LSB/g) Figure 42. ADXL357 Sensitivity Histogram at 25C, Y-Axis Figure 39. ADXL357 Zero g Offset Histogram at 25C, Y-Axis 30 Z-AXIS OFFSET AT 25C (mg) 10 54784 54272 53760 53248 52736 52224 51712 51200 50688 50176 49664 49152 5 0 15429-040 375 325 275 225 175 125 75 25 -25 -75 -125 -175 -225 -275 -325 -375 5 15 48640 10 20 48128 15 25 47616 PERCENT OF POPULATION (%) 20 47104 25 0 50176 Figure 41. ADXL357 Sensitivity Histogram at 25C, X-Axis 40 Y-AXIS OFFSET AT 25C (mg) 49664 X-AXIS SENSITIVITY AT 25C (LSB/g) 47104 375 15429-038 325 275 225 175 75 125 25 -25 -75 -125 -175 -225 0 -275 0 -325 5 Figure 38. ADXL357 Zero g Offset Histogram at 25C, X-Axis PERCENT OF POPULATION (%) 10 5 X-AXIS OFFSET AT 25C (mg) PERCENT OF POPULATION (%) 15 49152 10 20 48640 15 25 48128 20 30 47616 25 47104 PERCENT OF POPULATION (%) 35 -375 PERCENT OF POPULATION (%) Data Sheet Z-AXIS SENSITIVITY AT 25C (LSB/g) Figure 43. ADXL357 Sensitivity Histogram at 25C, Z-Axis Figure 40. ADXL357 Zero g Offset Histogram at 25C, Z-Axis Rev. A | Page 17 of 42 Data Sheet 0.5 0.20 0 0.15 0.10 -0.05 OFFSET SHIFT (g) -0.10 -0.15 -0.20 4 6 8 10 -0.20 10 15 20 25 Figure 47. ADXL357 VRE, X-Axis Offset from -1 g, 40 g Range, X-Axis Orientation = -1 g 0.20 0 0.15 0.10 OFFSET SHIFT (g) -0.05 -0.10 -0.15 -0.20 0.05 0 -0.05 -0.10 -0.25 2 4 6 8 10 -0.20 15429-045 0 0 5 10 15 20 25 INPUT VIBRATION (g rms) Figure 45. ADXL357 VRE, Y-Axis Offset from +1 g, 10 g Range, Y-Axis Orientation = +1 g 15429-048 -0.15 INPUT VIBRATION (g rms) Figure 48. ADXL357 VRE, Y-Axis Offset from -1 g, 40 g Range, Y-Axis Orientation = -1 g 0.5 0.20 0 0.15 0.10 OFFSET SHIFT (g) -0.05 -0.10 -0.15 -0.20 0.05 0 -0.05 -0.10 -0.25 -0.15 0 2 4 6 8 10 INPUT VIBRATION (g rms) 15429-046 -0.30 5 INPUT VIBRATION (g rms) 0.5 -0.30 0 15429-047 2 15429-044 0 Figure 44. ADXL357 VRE, X-Axis Offset from +1 g, 10 g Range, X-Axis Orientation = +1 g OFFSET CHANGE (g) -0.05 -0.15 INPUT VIBRATION (g rms) OFFSET CHANGE (g) 0 -0.10 -0.25 -0.30 0.05 Figure 46. ADXL357 VRE, Z-Axis Offset from +1 g, 10 g Range, Z-Axis Orientation = +1 g -0.20 0 5 10 15 20 25 INPUT VIBRATION (g rms) Figure 49. ADXL357 VRE, Z-Axis Offset from +1 g, 40 g Range, Z-Axis Orientation = +1 g Rev. A | Page 18 of 42 15429-049 OFFSET CHANGE (g) ADXL356/ADXL357 Data Sheet 0.0030 2500 1.1 0.0020 0.0015 1.0 0.0010 0.9 0.0005 LINEAR OFFSET (V) 0.0025 0 0.8 -0.0005 -20 0 20 40 60 80 100 120 -0.0010 15429-050 TEMPERATURE (C) Figure 50. ADXL356 Temperature Sensor Output and Linear Offset vs. Temperature 2100 1500 -2 1300 1100 -4 TEMPERATURE SENSOR OUTPUT LINEAR OFFSET 900 700 -40 -20 0 20 40 60 80 100 120 -6 TEMPERATURE (C) Figure 53. ADXL357 Temperature Sensor Output and Linear Offset vs. Temperature 30 25 20 15 10 TOTAL SUPPLY CURRENT AT 25C (A) 15429-051 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 5 Figure 51. ADXL356 Total Supply Current, 3.3 V 30 25 20 15 10 4200 ODR FREQUENCY (Hz) 15429-052 4160 4120 4080 4040 4000 3960 3920 3880 5 3840 20 15 10 5 0 TOTAL SUPPLY CURRENT AT 25C (A) Figure 54. ADXL357 Total Supply Current, 3.3 V 35 3800 25 Figure 52. ADXL357 Output Data Rate (Internal Clock) Histogram Rev. A | Page 19 of 42 15429-054 PERCENT OF POPULATION (%) PERCENT OF POPULATION (%) 0 1700 30 0 2 1900 35 0 4 2300 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 0.7 -40 6 LINEAR OFFSET (LSB) 2600 15429-053 0.0035 TEMPERATURE SENSOR OUTPUT (LSB) TEMPERATURE SENSOR OUTPUT LINEAR OFFSET 1.2 PERCENT OF POPULATION (%) TEMPERATURE SENSOR OUTPUT (V) 1.3 ADXL356/ADXL357 ADXL356/ADXL357 Data Sheet ROOT ALLAN VARIANCE (RAV) ADXL357 CHARACTERISTICS Figure 55 to Figure 57 include data for multiple devices and multiple lots, and they were taken in the 10 g range, unless otherwise noted. 100 10 1 0.01 0.1 1 10 100 1000 INTEGRATION TIME (Seconds) Figure 55. ADXL357 RAV, X-Axis 10 1 10 INTEGRATION TIME (Seconds) 100 1000 15429-056 ROOT ALLAN VARIANCE (g) 100 0.1 10 1 0.01 0.1 1 10 INTEGRATION TIME (Seconds) Figure 57. ADXL357 RAV, Z-Axis 1000 1 0.01 100 Figure 56. ADXL357 RAV, Y-Axis Rev. A | Page 20 of 42 100 1000 15429-057 ROOT ALLAN VARIANCE (g) 1000 15429-055 ROOT ALLAN VARIANCE (g) 1000 Data Sheet ADXL356/ADXL357 THEORY OF OPERATION The ADXL356 is a complete 3-axis, ultralow noise and ultrastable offset microelectromechanical systems (MEMS) accelerometer with outputs ratiometric to the analog 1.8 V supply, V1P8ANA. The ADXL357 adds three high resolution ADCs that use the analog 1.8 V supply as a reference to provide digital outputs insensitive to the supply voltage. The ADXL356B is pin selectable for 10 g or 20 g full scale, the ADXL356C is pin selectable for 10 g or 40 g full scale, and the ADXL357 is programmable for 10 g, 20 g, or 40 g full scale. The ADXL357 offers both SPI and I2C communications ports. The analog accelerometer outputs of the ADXL356 are ratiometric to V1P8ANA. Therefore, digitize them carefully. The temperature sensor output is not ratiometric. The XOUT, YOUT, and ZOUT analog outputs are filtered internally with an antialiasing filter. These analog outputs also have an internal 32 k series resistor that can be used with an external capacitor to set the bandwidth of the output. The micromachined, sensing elements are fully differential, comprising the lateral x-axis and y-axis sensors and the vertical, teeter totter z-axis sensors. The x-axis and y-axis sensors and the z-axis sensors go through separate signal paths that minimize The ADXL357 includes antialias filters before and after the high resolution - ADC. User-selectable output data rates and filter corners are provided. The temperature sensor is digitized with a 12-bit successive approximation register (SAR) ADC. offset drift and noise. The signal path is fully differential, except for a differential to single-ended conversion at the analog outputs of the ADXL356. Rev. A | Page 21 of 42 ADXL356/ADXL357 Data Sheet APPLICATIONS INFORMATION and noise reduction prior to the external ADC. The antialias filter cutoff frequency must be significantly higher than the desired signal bandwidth. If the antialias filter corner is too low, ratiometricity can degrade where the signal attenuation is different from the reference attenuation. ANALOG OUTPUT Figure 58 shows the ADXL356 application circuit. The analog outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V analog voltage from the V1P8ANA pin. V1P8ANA can be powered with an on-chip LDO regulator that is powered from VSUPPLY. V1P8ANA can also be supplied externally by forcing VSUPPLY to VSS, which disables the LDO regulator. Due to the ratiometric response, the analog output requires referencing to the V1P8ANA supply when digitizing to achieve the inherent noise and offset performance of the ADXL356. The 0 g bias output is nominally equal to V1P8ANA/2. The recommended option is to use the ADXL356 with a ratiometric ADC (for example, the Analog Devices, Inc., AD7682) and V1P8ANA providing the voltage reference. This configuration results in self cancellation of errors due to minor supply variations. DIGITAL OUTPUT Figure 59 shows the ADXL357 application circuit with the recommended bypass capacitors. The communications interface is either SPI or I2C (see the Serial Communications section for additional information). The ADXL357 includes an internal configurable digital bandpass filter. Both the high-pass and low-pass poles of the filter are adjustable, as detailed in the Filter Settings Register section and Table 44. At power-up, the default conditions for the filters are as follows: VDDIO (20g, 40g) GND ( 10g) High-pass filter (HPF) = dc (off) Low-pass filter (LPF) = 1000 Hz Output data rate = 4000 Hz 2.25V TO 3.6V 12 XOUT 14 ZOUT 13 YOUT The ADXL356 outputs two forms of filtering: internal antialiasing filtering with a cutoff frequency of approximately 1.5 kHz, and external filtering. The external filter uses a fixed, on-chip, 32 k resistance in series with each output in conjunction with the external capacitors to implement the low-pass filter antialiasing 0.1F 11 VSUPPLY RANGE 1 10 V1P8ANA ST1 2 ADXL356 ST2 3 STBY 7 VSSIO 6 VDDIO 5 TEMP 4 9 VSS 8 V1P8DIG 0.1F 1F 1F ADC V REF VDDIO (MEASUREMENT) GND (STANDBY) 1F 1F 0.1F 0.1F 15429-058 2.25V TO 3.6V 12 INT1 11 VSUPPLY SCLK/VSSIO 2 10 V1P8ANA MOSI/SDA 3 ADXL357 TOP VIEW (Not to Scale) VSS 8 V1P8DIG 0.1F 1F 1F RESERVED 7 VSSIO 6 MISO/ASEL 4 9 0.1F 1F 1F 0.1F 0.1F 2.25V TO 3.6V Figure 59. ADXL357 Application Circuit Rev. A | Page 22 of 42 15429-060 13 INT2 2.25V TO 3.6V CS/SCL 1 VDDIO 5 SPI/I2C INTERFACE 14 DRDY Figure 58. ADXL356 Application Circuit Data Sheet ADXL356/ADXL357 AXES OF ACCELERATION SENSITIVITY V1P8ANA Figure 60 shows the axes of acceleration sensitivity. Note that the output voltage increases when accelerated along the sensitive axis. All sensor and analog signal processing circuitry operates in this domain. Offset and sensitivity of the analog output ADXL356 are ratiometric to this supply voltage. When using external ADCs, use V1P8ANA as the reference voltage. The ADXL357 includes ADCs that are ratiometric to V1P8ANA, thereby rendering the offset and sensitivity of the digital output ADXL357 insensitive to the value of V1P8ANA. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage. Z Y V1P8DIG 15429-059 X V1P8DIG is the supply voltage for the internal logic circuitry. A separate LDO regulator decouples the digital supply noise from the analog signal path. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage. If driven externally, V1P8DIG must be the same voltage as the V1P8ANA voltage. Figure 60. Axes of Acceleration Sensitivity POWER SEQUENCING VDDIO There are two methods for applying power to the device. Typically, internal LDO regulators generate the 1.8 V power for the analog and digital supplies, V1P8ANA and V1P8DIG, respectively. Optionally, the internal LDO regulators can be disabled and V1P8ANA and V1P8DIG are driven by external 1.8 V supplies. The VDDIO value determines the logic high levels. On the analog output ADXL356, VDDIO sets the logic high level for the self test pins, ST1 and ST2, as well as the STBY pin. On the digital output ADXL357, VDDIO sets the logic high level for communications interface ports, as well as the interrupt and DRDY outputs. When using the internal LDO regulators, connect VSUPPLY to a voltage source between 2.25 V and 3.6 V. In this case, the recommended power sequence is to apply power to VDDIO, followed by applying power to VSUPPLY approximately 10 s later. If necessary, VSUPPLY and VDDIO can be powered from the same voltage source, so that both are powered at the same time. However, VSUPPLY cannot be powered before VDDIO. The LDO regulators are operational when VSUPPLY is between 2.25 V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs in this mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA and V1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range. To disable the internal LDO regulators, tie VSUPPLY to ground and use external 1.8 V supplies to power V1P8ANA and V1P8DIG. V1P8ANA and V1P8DIG must have the same voltage level. The maximum acceptable tolerance between the external V1P8ANA and V1P8DIG voltage levels is 50 mV. In the case of bypassing the LDO regulators, the recommended power sequence is to apply power to VDDIO, followed by applying power to V1P8DIG approximately 10 s later, and then applying power to V1P8ANA approximately 10 s later. If necessary, V1P8DIG and VDDIO can be powered from the same external 1.8 V supply, which can also be tied to V1P8ANA with proper isolation, so that all are powered at the same time. In this case, proper decoupling and low frequency isolation are important to maintain the noise performance of the sensor. POWER SUPPLY DESCRIPTION The ADXL356/ADXL357 have four different power supply domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal analog and digital circuitry operates at 1.8 V nominal. VSUPPLY VSUPPLY is 2.25 V to 3.6 V, which is the input range to the two LDO regulators that generate the nominal 1.8 V outputs for V1P8ANA and V1P8DIG. Connect VSUPPLY to VSS to disable the LDO regulators, which allows driving V1P8ANA and V1P8DIG from an external source. OVERRANGE PROTECTION To avoid electrostatic capture of the proof mass when the accelerometer is subject to input acceleration beyond its fullscale range, all sensor drive clocks turn off for 0.5 ms. In the 10 g range setting, the overrange protection activates for input signals beyond approximately 40 g (25%), and for the 20 g and 40 g range settings, the threshold corresponds to about 80 g (25%). When overrange protection occurs, the XOUT, YOUT, and ZOUT pins on the ADXL356 begin to drive to midscale, whereas the ADXL357 floats toward zero, and the first in, first out (FIFO) buffer begins filling with this data. SELF TEST The ADXL356 and ADXL357 incorporate a self test feature that effectively tests the mechanical and electronic system. Enabling self test stimulates the sensor electrostatically to produce an output corresponding to the test signal applied as well as the mechanical force exerted. Only the z-axis response is specified to validate device functionality. In the ADXL356, drive the ST1 pin to VDDIO to invoke self test mode. Then, by driving the ST2 pin to VDDIO, the ADXL356 applies an electrostatic force to the mechanical sensor and induces a change in output in response to the force. The self test delta (or response) is the difference in output voltage in the z-axis when ST2 is high vs. ST2 is low, while ST1 is asserted. Rev. A | Page 23 of 42 ADXL356/ADXL357 Data Sheet 0 After the self test measurement is complete, bring both pins low to resume normal operation. -20 -30 -40 -50 FILTER -70 The ADXL357 provides an internal 20-bit, - ADC to digitize the filtered analog signal. Additional digital filtering (beyond the analog, low-pass, antialiasing filter) consists of a low-pass digital decimation filter and a bypassable high-pass filter that supports output data rates between 4 kHz and 3.906 Hz. The decimation filter consists of two stages. The first stage is fixed decimation with a 4 kHz ODR and a low-pass filter cutoff (3 dB) at about 1 kHz. A variable second stage decimation filter is used for the 2 kHz output data rate and below (it is bypassed for 4 kHz ODR). Figure 61 shows the low-pass filter response with a 1 kHz corner (4 kHz ODR) for the ADXL357. Note that Figure 61 does not include the fixed frequency analog, low-pass, antialiasing filter with a fixed 3 dB bandwidth of approximately 1.5 kHz. The ADXL357 pass band of the signal path relates to the combined filter responses, including the analog filter previously described, and the digital decimation filter/ODR setting. Table 10 shows the delay associated with the decimation filter for each setting and provides the attenuation at the ODR/4 corner. 100 1k 10k The ADXL357 also includes an optional digital high-pass filter with a programmable corner frequency. By default, the highpass filter is disabled. The high-pass corner frequency, where the output is attenuated by 3 dB, is related to the ODR, and the HPF_CORNER setting in the filter register (Register 0x28, Bits[6:4]). Table 11 shows the HPF_CORNER response. Figure 62 and Figure 63 show the simulated high-pass filter pass-band and delay responses for a 9.88 Hz cutoff. 0 -3 -10 -20 -30 -40 -50 0 9.8801 100 FREQUENCY (Hz) 15429-062 The ADXL356 x-axis, y-axis, and z-axis analog outputs include an amplifier followed by a series 32 k resistor, and output to the XOUT, the YOUT, and the ZOUT pins, respectively. 10 Figure 61. ADXL357 Digital LPF Response for 4 kHz ODR AMPLITUDE RELATIVE TO FULL SCALE (dB) The analog, low-pass antialiasing filter in the ADXL356/ ADXL357 provides a fixed 3 dB bandwidth of approximately 1.5 kHz, the frequency at which the voltage output response is attenuated by approximately 30%. The shape of the filter response in the frequency domain is that of a sinc filter. While the analog antialiasing filter attenuates the output response around and above its cutoff frequency, the MEMS sensor has a resonance at 5.5 kHz and mechanically amplifies the output response at around 2 kHz and above. These competing trends are apparent in the overall transfer function of the ADXL356, as shown in Figure 8 to Figure 10. Therefore, the overall -3 dB bandwidth of the ADXL356 is 2.4 kHz, and the overall bandwidth with 4 dB flatness is about 4.4 kHz. 1 INPUT FREQUENCY (Hz) Figure 62. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4]) 40 32.2122 DELAY (ODR CYCLES) The ADXL356/ADXL357 use an analog, low-pass, antialiasing filter to reduce out of band noise and to limit bandwidth. The ADXL357 provides further digital filtering options to maintain optimal noise performance at various ODRs. 15429-061 -60 30 20 10 1 0 0 100 9.8801 FREQUENCY (Hz) Figure 63. High-Pass Filter Delay Response for a 4 kHz ODR and an HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4]) Rev. A | Page 24 of 42 15429-063 The self test feature rejects externally applied acceleration and only responds to the self test force, which allows an accurate measurement of the self test, even in the presence of external mechanical noise. When the self test feature is not used, both ST1 and ST2 must be kept low. -10 DIGITAL LPF RESPONSE (dB) The self test operation is similar in the ADXL357, except ST1 and ST2 can be accessed through the SELF_TEST register (Register 0x2E). Data Sheet ADXL356/ADXL357 The ADXL357 also includes an interpolation filter after the decimation filters that produces oversampled/upconverted data and provides an external synchronization option. See the Data Synchronization section for more details. Table 12 shows the delay and attenuation relative to the programmed ODR. Group delay is the digital filter delay from the input to the ADC until data is available at the interface (see the Filter section). This delay is the largest component of the total delay from sensor to serial interface. Table 10. Digital Filter Group Delay and Profile Delay ODR (Cycles) Time (ms) 2.52 0.63 2.00 1.00 1.78 1.78 1.63 3.26 1.57 6.27 1.54 12.34 1.51 24.18 1.49 47.59 1.50 96.25 1.50 189.58 1.50 384.31 Programmed ODR (Hz) 4000 4000/2 = 2000 4000/4 = 1000 4000/8 = 500 4000/16 = 250 4000/32 = 125 4000/64 = 62.5 4000/128 31 4000/256 16 4000/512 8 4000/1024 4 Attenuation Decimator at ODR/4 (dB) Full Path at ODR/4 (dB) -3.44 -3.63 -2.21 -2.26 -1.92 -1.93 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 -1.83 Table 11. Digital High-Pass Filter Response HPF_CORNER Register Setting (Register 0x28, Bits[6:4]) 000 001 010 011 100 101 110 HPF_CORNER Frequency, -3 dB Point Relative to ODR Setting Not applicable, no high-pass filter enabled 24.7 x 10-4 x ODR 6.2084 x 10-4 x ODR 1.5545 x 10-4 x ODR 0.3862 x 10-4 x ODR 0.0954 x 10-4 x ODR 0.0238 x 10-4 x ODR -3 dB at 4 kHz ODR (Hz) Off 9.88 2.48 0.62 0.1545 0.03816 0.00952 Table 12. Combined Digital Interpolation Filter and Decimation Filter Response Interpolator Data Rate Resolution Relative to 64 x ODR (Hz) 64 x 4000 = 256,000 64 x 2000 = 128,000 64 x 1000 = 64,000 64 x 500 = 32,000 64 x 250 = 16,000 64 x 125 = 8000 64 x 62.5 = 4000 64 x 31.25 = 2000 64 x 15.625 = 1000 64 x 7.8125 = 500 64 x 3.90625 = 250 Combined Interpolator/ Decimator Delay (ODR Cycles) 3.51661 3.0126 2.752 2.6346 2.5773 2.5473 2.53257 2.52452 2.52045 2.5194 2.51714 Combined Interpolator/ Decimator Delay (ms) 0.88 1.51 2.75 5.27 10.31 20.38 40.52 80.78 161.31 322.48 644.39 Rev. A | Page 25 of 42 Combined Interpolator/Decimator Output Attenuation at ODR/4 (dB) -6.18 -4.93 -4.66 -4.58 -4.55 -4.55 -4.55 -4.55 -4.55 -4.55 -4.55 ADXL356/ADXL357 Data Sheet SERIAL COMMUNICATIONS The 4-wire serial interface communicates in either the SPI or I2C protocol. The interface affectively autodetects the format being used, requiring no configuration control to select the format. SPI BUS SHARING Use a gated buffer on the SCLK line for the ADXL357 device to achieve the ultralow noise performance and possibly offset shift when the ADXL357 must share a SPI bus with another slave device. This gated SCLK allows the clock signal through only when the chip select (CS) line is low. See Figure 65 for the example circuit that provides this type of protection. The ADXL357 multifunction pins are referred to by a single function of the pin, for example, CS, when only that function is relevant. SPI PROTOCOL ADXL357 ADXL357 PROCESSOR Wire the ADXL357 for SPI communication as shown in the connection diagram in Figure 64. The SPI protocol timing is shown in Figure 66 to Figure 69. The timing scheme follows the clock polarity (CPOL) = 0 and clock phase (CPHA) = 0. The SPI clock speed ranges from 100 kHz to 10 MHz. CS SS1 SS2 SCLK SCLK SN74LVC1G125 PROCESSOR MOSI MISO MISO SCLK SCLK TO SPI SLAVE 2 Figure 65. SCLK Protection Example 15429-064 MOSI 15429-165 SS CS Figure 64. 4-Wire SPI Connection CS 1 2 3 4 5 6 7 A6 A5 A4 A3 A2 A1 8 9 10 11 12 13 14 15 16 D7 D6 D5 D4 D3 D2 D1 D0 15 16 SCLK A0 RW MISO 15429-065 MOSI Figure 66. SPI Timing Diagram--Single-Byte Read CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 MOSI MISO 15429-066 SCLK Figure 67. SPI Timing Diagram--Single-Byte Write CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SCLK A6 A5 A4 A3 A2 A1 A0 RW BYTE n BYTE 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 MISO D0 D7 D6 D5 D4 D3 D2 D1 D0 15429-067 MOSI Figure 68. SPI Timing Diagram--Multibyte Read CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SCLK A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 MISO Figure 69. SPI Timing Diagram--Multibyte Write Rev. A | Page 26 of 42 15429-068 BYTE n BYTE 1 MOSI Data Sheet ADXL356/ADXL357 I2C PROTOCOL Figure 70 to Figure 72 detail the I2C protocol timing. The I2C interface can be used on most buses operating in I2C standard mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high speed mode (3.4 MHz). The ADXL357 I2C device ID is as follows: The ADXL357 supports point to point I2C communication. However, when sharing an SDA bus, the ADXL357 may prevent communication with other devices on that bus. If at any point, even when the ADXL357 is not being addressed, the 0x3A and 0x3B bytes (when the ADXL357 device address is set to 0x1D), or the 0xA6 and 0xA7 bytes (when the ADXL357 device address is set to 0x53) are transmitted on the SDA bus, the ADXL357 responds with an acknowledge bit and pulls the SDA line down. For example, this response can occur when reading or writing the data bytes (0x3A/0x3B or 0xA6/0xA7) to another sensor on the bus. When the ADXL357 pulls the SDA line down, communication with other devices on the bus may be interrupted. To resolve this interruption, the ADXL357 must be connected to a separate SDA bus, or the CS/SCL pin must be switched high when communication with the ADXL357 is not desired (it is normally grounded). If other devices are connected to the same I2C bus, the nominal operating voltage level of these other devices cannot exceed VDDIO by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I2C operation. READING ACCELERATION OR TEMPERATURE DATA FROM THE INTERFACE Acceleration data is left justified and has a register address order of most significant data to least significant data, which allows the user to use multibyte transfers and to take only as much data as required--8 bits, 16 bits, or 20 bits, plus the marker. Temperature data is 12 bits unsigned, right justified. The ADXL357 temperature value is split over two bytes, but is not double buffered, meaning the value can update between readings of the two registers. The data in XDATA, YDATA, and ZDATA is always the most recent available. It is not guaranteed that XDATA, YDATA, and ZDATA form a set corresponding to one sample point in time. The routine used to retrieve the data from the device controls this data set continuity. If data transfers are initiated when the DATA_RDY bit goes high and completes in a time approximately equal to 1/ODR, XDATA, YDATA, and ZDATA apply to the same data set. The ADXL357 supports standard (100 kHz), fast (up to 1 MHz) and high speed (up to 3.4 MHz) data transfer modes when the bus parameters in Table 4 are met. There is no minimum SCL frequency, with the exception that, when reading data, the clock must be fast enough to read an entire sample set before new data overwrites it. Single-byte or multiple byte reads/writes are supported. With the MISO/ASEL pin low, the I2C address for the device is 0x1D and an alternate I2C address of 0x53 can be chosen by pulling the MISO/ASEL pin high. There are no internal pull-up or pull-down resistors for any unused pins. Therefore, there is no known state or default state for the pins if left floating or unconnected. SCLK/VSSIO must be connected to ground when communicating to the ADXL357 using I2C. For multibyte read or write transactions through either serial interface, the internal register address auto-increments. When the top of the register address range, 0x3FF, is reached, the autoincrement stops and does not wrap back to Address 0x00. Due to communication speed limitations, the maximum output data rate when using the 400 kHz I2C mode is 800 Hz, and it scales linearly with a change in the I2C communication speed. For example, using I2C at 100 kHz limits the maximum ODR to 200 Hz. Operation at an output data rate above the recommended maximum may result in an undesirable effect on the acceleration data, including missing samples or additional noise. 1 2 3 4 5 6 7 8 MISO/ASEL pin = 0, device address = 0x1D MISO/ASEL pin = 1, device address = 0x53 The address auto-increment function disables when the FIFO address is used, so that data can be read continuously from the FIFO as a multibyte transaction. In cases where the starting address of a multibyte transaction is less than the FIFO address, the address auto-increments until reaching the FIFO address, and then stops at the FIFO address. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SCL SDA REGISTER ADDRESS A6 A5 A4 A3 A2 A1 A0 RW AK 0 REPEAT START A6 A5 A4 A3 A2 A1 A0 AK DEVICE ADDRESS DATA BYTE A6 A5 A4 A3 A2 A1 A0 RW AK 0 STOP D6 D5 D4 D3 D2 D1 D0 SINGLE BYTE READ AK INDICATE SDA IS CONTROLLED BY ADXL357 15429-069 DEVICE ADDRESS START Figure 70. I2C Timing Diagram--Single-Byte Read 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 DEVICE ADDRESS START REGISTER ADDRESS A6 A5 A4 A3 A2 A1 A0 RW AK SDA 0 DATA BYTE A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK STOP 15429-070 SCL Figure 71. I2C Timing Diagram--Single-Byte Write 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19 START SDA DEVICE ADDRESS A6 A5 A4 A3 A2 A1 A0 RW AK REGISTER ADDRESS 0 DATA BYTE 1 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK D7 Figure 72. I2C Timing Diagram--Multibyte Write Rev. A | Page 27 of 42 DATA BYTE n D0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK 15429-071 SCL ADXL356/ADXL357 Data Sheet FIFO The FIFO operates in a stream mode. That is, when the FIFO overruns, new data overwrites the oldest data in the FIFO. A read from the FIFO address guarantees that the three bytes associated with the acceleration measurement on an axis all pertain to the same measurement. The FIFO never overflows, and the data is always taken out in sets (multiples of three data points). control logic inserts the two virtual bits (0b00) between the data bits and the empty indicator bit. Bit 1 indicates that an attempt was made to read an empty FIFO, and that the data is not valid acceleration data. Bit 0 is a marker bit to identify the x-axis, which allows a user to verify that the FIFO data was correctly read. An acceleration data point for a given axis occupies one FIFO location. The read pointer, RD_PTR, points to the oldest stored data that was not read already from the interface (see Figure 73). There are no physical x-acceleration, y-acceleration, or z-acceleration data registers. The data read from data registers (Register 0x08 to Register 0x10) also comes directly from the most recent data set in the FIFO, which is pointed to by the z pointer, Z_PTR (see Figure 73). There are 96 21-bit locations in the FIFO. Each location contains 20 bits of data and a marker bit for the x-axis data. A single-byte read from the FIFO address pops one location from the FIFO. A multibyte read to the FIFO location pops the FIFO on the read of the first byte and every third byte read thereafter. Figure 73 shows the organization of the data in the FIFO. The acceleration data is twos complement, 20-bit data. The FIFO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Z_PTR Z19 Z18 Z17 Z16 Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 0 0 Z_PTR - 1 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0 Z_PTR - 2 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 0 1 Z19 Z18 Z17 Z16 Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 0 0 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 0 1 RD_PTR VIRTUAL BITS (NOT ALLOCATED IN THE FIFO) ACCELERATION DATA EMPTY INDICATOR X-AXIS MARKER ASCENDING SPI ADDRESSES Figure 73. FIFO Data Organization Rev. A | Page 28 of 42 15429-072 DATA SET. SAMPLE POINT ASCENDING IS THE SAME ACROSS A SINGLE X-AXIS, Y-AXIS, SPI ADDRESSES AND Z-AXIS DATA SET. ASCENDING FIFO ADDRESSES Z_PTR + 1 Data Sheet ADXL356/ADXL357 INTERRUPTS The status register (Register 0x04) contains five individual bits, four of which can be mapped to either the INT1 pin, the INT2 pin, or both. The polarity of the interrupt, active high or active low, is also selectable via the INT_POL bit in the range (Register 0x2C) register. In general, the status register clears when read, but this is not the case if the condition that caused the interrupt persists after the read of the register. The definition of persist varies slightly in each case, but it is described in the DATA_RDY, DRDY Pin, FIFO_FULL, FIFO_OVR, and Activity sections. The DRDY pin is similar to an interrupt pins (INTx) but clears differently. This case is also described. DATA_RDY The DATA_RDY bit is set when new acceleration data is available to the interface and clears on a read of the status register. This bit is not set again until acceleration data that is newer than the status register read is available. Special logic on the clearing of the DATA_RDY bit covers the corner case where new data arrives during the read of the status register. In this case, the data ready condition may be missed completely. This logic results in a delay of the clearing of DATA_RDY of up to four 512 kHz cycles. DRDY PIN The DRDY pin is not a status register bit. DRDY instead behaves similar to an unmaskable interrupt. DRDY is set when new acceleration data is available to the interface. DRDY clears on a read of the FIFO, on a read of XDATA, YDATA, or ZDATA, or by an autoclear function that occurs approximately halfway between output acceleration data sets. DRDY is always active high. The INT_POL bit does not affect DRDY. In external synchronization modes (EXT_SYNC = 01, EXT_SYNC = 10), the first few DRDY pulses after initial synchronization can be lost or corrupted. The length of this potential corruption is equal to or less than the group delay. Therefore, the samples within one group delay is lost or corrupted after the first synchronization signal. Depending on the decimation setting and interpolation setting (see Table 12), between one and three samples after the first synchronization pulse is lost, provided that all the restrictions set in the External Synchronization and Interpolation section is met. FIFO_OVR The FIFO_OVR bit is set when the FIFO is so far overrange that data is lost. The specified size of the FIFO is 96 locations. The FIFO_OVR bit is set only when there is an attempt to write past this 96-location limit. A read of the status register clears FIFO_OVR. FIFO_OVR is not set again until data is lost subsequent to this status register read. ACTIVITY The activity bit (Register 0x04, Bit 3) is set when the measured acceleration on any axis is above the value set in the ACT_ THRESH bits for ACT_COUNT consecutive measurements. An overthreshold condition can shift from one axis to another on successive measurements and is still counted toward the consecutive ACT_COUNT count. A read of the status register clears the activity bit (Register 0x04, Bit 3), but the bit sets again at the end of the next measurement if the activity bit (Register 0x04, Bit 3) conditions are still satisfied. NVM_BUSY The NVM_BUSY bit indicates that the nonvolatile memory (NVM) controller is busy and, therefore, the NVM cannot be accessed to read or write. The interrupt functionality requires the NVM_BUSY bit to be cleared to function. A status register read that occurs after the NVM controller is no longer busy clears NVM_BUSY. EXTERNAL SYNCHRONIZATION AND INTERPOLATION There are four possible synchronization options for the ADXL357, three of which are shown in Figure 74 to Figure 76. For clarity, the clock frequencies and delays are drawn to scale. The labels in Figure 74 to Figure 76 are defined as follows: The four possible synchronization options are as follows: FIFO_FULL The FIFO_FULL bit is set when the entries in the FIFO are equal to the setting of the FIFO_SAMPLES bits. FIFO_FULL clears as follows: If the number of entries in the FIFO is less than the number of samples indicated by the FIFO_SAMPLES bits, which is only the case if sufficient data is read from the FIFO. On a read of the status register, but only when the entries in the FIFO are less than the FIFO_SAMPLES bits. Internal ODR is the alignment of the decimated output data based on the internal clock. ADC modulator clock shows the internal master clock rate. DRDY is an output indicator signaling a sample is ready. Rev. A | Page 29 of 42 No external synchronization (internal clocks used) Synchronization with an external synchronization signal and internal clock, interpolation filter enabled Synchronization with external synchronization and clock signals, no interpolation filter Synchronization with external synchronization and clock signals, interpolation filter enabled ADXL356/ADXL357 Data Sheet EXT_SYNC = 00, EXT_CLK = 0--No External Synchronization or Interpolation EXT_SYNC = 01, EXT_CLK = 1--External Synchronization and External Clock, No Interpolation Filter This is the default mode of operation for the device. The sensor runs on an internal ODR and an internal clock that is generated by an internal oscillator. The internal ODR serves as the synchronization master, which generates the data. Register 0x28 is used to program the ODR. No external signals are required, and this mode is used typically when the external processor retrieves data from the device asynchronously and absolute synchronization to an external source is not required. When configured for EXT_SYNC = 01 and EXT_CLK = 1 (sync register, see Table 47), the user must supply an external clock (enabled via the EXT_CLK bit) at 1.024 MHz on the INT2 pin (Pin 13) and an external synchronization signal, SYNC, on the DRDY pin (Pin 14), as shown in Table 14. If configured in this mode and an external clock is not supplied, the device does not process any data and reading from the output results in null values. This mode is schematically shown in Figure 76. The device outputs a DRDY (active high) to signal that a new sample is available, and data is retrieved from the real-time registers or the FIFO. The group delay is based on the decimation setting, as shown in Table 10. This mode is shown in Figure 74. Special restrictions when using this mode include the following: EXT_SYNC = 10, EXT_CLK = 0--External Synchronization with Interpolation Synchronization using interpolation filters and an external ODR clock is commonly used when the external processor can provide a synchronization signal, SYNC, that is asynchronous to the internal clock at the desired ODR. In this case, an interpolation filter provides additional time resolution of 64 times the programmed ODR (see Table 12). Synchronization with the interpolation filter enabled (EXT_SYNC = 10) allows the sensor to operate on an internal clock and output data most closely associated with the SYNC rising edge. The advantage of this mode is that data is available at an arbitrary user defined SYNC sample rate and is asynchronous to the internal clock oscillator. The maximum sample rate cannot exceed 4000 SPS. The disadvantage of this mode is that the group delay is increased, with increased attenuation at the band edge. Additionally, because there is a limit to the time resolution, there is some distortion related to the mismatch of the external synchronization relative to the internal clock oscillator. This mismatch degrades spectral performance. The group delay is based on the decimation setting and interpolation setting (see Table 12). Figure 75 schematically shows the timings in this mode, and Table 13 shows the delay between the SYNC signal (input) to DRDY (output). When using the EXT_SYNC mode and without providing the SYNC signal, the device runs on its own internal ODR. Similarly, after external synchronization, the device continues to run synchronized to the last SYNC pulse it received, which means that EXT_SYNC = 01 mode can be used with only a single synchronization pulse. For more information about the lost sample in Figure 76, see the DRDY Pin section. EXT_SYNC = 10, EXT_CLK = 1--External Synchronization and External Clock, with Interpolation Filter This mode can be used to run the device on an external clock and synchronization with an arbitrary sample rate set by the SYNC signal rate. Conditions for external SYNC and external clock signals is the same as EXT_SYNC = 01, EXT_CLK = 1 mode. The interpolation filter provides a frequency resolution related to the ODR (see Table 12). In this case, the data provided corresponds to the external SYNC signal, which can be greater than the set ODR and less than 4000 SPS, but the output pass band remains the same it was prior to the interpolation filter. Table 13. EXT_SYNC = 10, DRDY Delay ODR_LPF 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA The external clock frequency on INT2 (Pin 13, see Table 14) must be 1.024 MHz. The pulse width of the SYNC signal must be at least 3.91 s, which represents four cycles of the external clock (4 / 1.024 MHz = ~3.91 s). The phase of SYNC must meet an approximate 25 ns setup time to the external clock rising edge. SYNC to DRDY Delay (Oscillator Cycles) 8 10 14 22 38 70 134 262 1031 2054 4102 Rev. A | Page 30 of 42 Data Sheet ADXL356/ADXL357 Table 14. Multiplexing of INT2 and DRDY EXT_CLK 0 0 1 1 0 0 1 1 Register or Bit Fields EXT_SYNC, INT_MAP, Bits[1:0] Bits[7:4] 00 0000 00 Not 0000 00 0000 00 Not 00001 01 0000 013 Not 0000 0000 013 Not 00001 013 INT2 (Pin 13) Low INT2 EXT_CLK EXT_CLK DRDY2 INT2 EXT_CLK EXT_CLK DRDY (Pin 14) DRDY DRDY DRDY DRDY SYNC SYNC SYNC SYNC 0 0 1 1 10 103 103 103 DRDY2 INT2 EXT_CLK EXT_CLK SYNC SYNC SYNC SYNC External synchronization, no interpolation filter, and DRDY (active high) signals that data is ready. Data represents a sample point group delay earlier in time. External synchronization, interpolation filter, and DRDY (active high) signals that data is ready. Data sample group delay earlier in time. No INT2, even though it is enabled. DRDY routing through the INT_MAP register takes precedence over the default, per Table 14. No DRDY. SAMPLE POINT GROUP DELAY (FIXED RELATIVE TO DRDY) INTERNAL ODR ADC MODULATOR CLOCK 15429-073 3 These options reset the digital filters on every synchronization pulse and are not recommended. DRDY Figure 74. EXT_SYNC = 00, EXT_CLK = 0, Internal Synchronization, Internal Clock SAMPLE POINT GROUP DELAY (FIXED RELATIVE TO SYNC) INTERFACE SYNCHRONIZATION DELAY INTERNAL ODR INTERPOLATOR 64x ODR SYNC 110% ODR 15429-074 2 Comments Synchronization is to the internal clocks, and there is no external clock synchronization. DRDY Figure 75. EXT_SYNC = 10, EXT_CLK = 0, External Synchronization, Internal Clock, Interpolation Filter SAMPLE POINT GROUP DELAY (FIXED RELATIVE TO SYNC) INTERNAL ODR EXTERNAL CLOCK 1.024MHz SYNC SYNCHRONIZE LOST SAMPLE DRDY Figure 76. EXT_SYNC = 01, EXT_CLK = 1, External Synchronization, External Clock, No Interpolation Filter Rev. A | Page 31 of 42 15429-075 1 0000 Not 0000 0000 Not 0000 Pins ADXL356/ADXL357 Data Sheet ADXL357 REGISTER MAP Note that while configuring the ADXL357 in an application, all configuration registers must be programmed before enabling measurement mode in the POWER_CTL register. When the ADXL357 is in measurement mode, only the following configurations can change: the HPF_CORNER bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register. Table 15. ADXL357 Register Map Hex. Addr. 0x00 0x01 0x02 0x03 0x04 Register Name DEVID_AD DEVID_MST PARTID REVID Status Bit 7 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F FIFO_ENTRIES TEMP2 TEMP1 XDATA3 XDATA2 XDATA1 YDATA3 YDATA2 YDATA1 ZDATA3 ZDATA2 ZDATA1 FIFO_DATA OFFSET_X_H OFFSET_X_L OFFSET_Y_H OFFSET_Y_L OFFSET_Z_H OFFSET_Z_L ACT_EN ACT_THRESH_H ACT_THRESH_L ACT_COUNT Filter FIFO_SAMPLES INT_MAP Sync Range POWER_CTL SELF_TEST Reset Reserved Reserved Reserved ACT_EN2 I2C_HS Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEVID_AD DEVID_MST PARTID REVID Reserved NVM_ Activity FIFO_OVR FIFO_FULL DATA_RDY BUSY FIFO_ENTRIES Reserved Temperature, Bits[11:8] Temperature, Bits[7:0] XDATA, Bits[19:12] XDATA, Bits[11:4] XDATA, Bits[3:0] Reserved YDATA, Bits[19:12] YDATA, Bits[11:4] YDATA, Bits[3:0] Reserved ZDATA, Bits[19:12] ZDATA, Bits[11:4] ZDATA, Bits[3:0] Reserved FIFO_DATA OFFSET_X, Bits[15:8] OFFSET_X, Bits[7:0] OFFSET_Y, Bits[15:8] OFFSET_Y, Bits[7:0] OFFSET_Z, Bits[15:8] OFFSET_Z, Bits[7:0] Reserved ACT_Z ACT_Y ACT_X ACT_THRESH, Bits[15:8] ACT_THRESH, Bits[7:0] ACT_COUNT HPF_CORNER ODR_LPF FIFO_SAMPLES OVR_EN2 FULL_EN2 RDY_EN2 ACT_EN1 OVR_EN1 FULL_EN1 RDY_EN1 Reserved EXT_CLK EXT_SYNC INT_POL Reserved Range Reserved DRDY_OFF TEMP_OFF Standby Reserved ST2 ST1 Reset Rev. A | Page 32 of 42 Reset 0xAD 0x1D 0xED 0x01 0x00 R/W R R R R R 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x60 0x00 0x00 0x81 0x01 0x00 0x00 R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Data Sheet ADXL356/ADXL357 REGISTER DEFINITIONS This section describes the functions of the ADXL357 registers. The ADXL357 powers up with the default register values, as shown in the reset column of Table 15. ANALOG DEVICES ID REGISTER This register contains the Analog Devices ID, 0xAD. Address: 0x00, Reset: 0xAD, Name: DEVID_AD Table 16. Bit Descriptions for DEVID_AD Bits [7:0] Bit Name DEVID_AD Settings Description Analog Devices ID Reset 0xAD Access R ANALOG DEVICES MEMS ID REGISTER This register contains the Analog Devices MEMS ID, 0x1D. Address: 0x01, Reset: 0x1D, Name: DEVID_MST Table 17. Bit Descriptions for DEVID_MST Bits [7:0] Bit Name DEVID_MST Settings Description Analog Devices MEMS ID Reset 0x1D Access R DEVICE ID REGISTER This register contains the device ID, 0xED (355 octal). Address: 0x02, Reset: 0xED, Name: PARTID Table 18. Bit Descriptions for PARTID Bits [7:0] Bit Name PARTID Settings Description Device ID (355 octal) Reset 0xED Access R PRODUCT REVISION ID REGISTER This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision. Address: 0x03, Reset: 0x01, Name: REVID Table 19. Bit Descriptions for REVID Bits [7:0] Bit Name REVID Settings Description Mask revision Reset 0x01 Access R STATUS REGISTER This register includes bits that describe the various conditions of the ADXL357. Address: 0x04, Reset: 0x00, Name: Status Table 20. Bit Descriptions for Status Bits [7:5] 4 3 2 1 0 Bit Name Reserved NVM_BUSY Activity FIFO_OVR FIFO_FULL DATA_RDY Settings Description Reserved. NVM controller is busy with a refresh, programming, or a built in self test (BIST). Activity, as defined in the ACT_THRESH_x and ACT_COUNT registers, is detected. FIFO has overrun, and the oldest data is lost. FIFO watermark is reached. A complete x-axis, y-axis, and z-axis measurement was made and results can be read. Rev. A | Page 33 of 42 Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R ADXL356/ADXL357 Data Sheet FIFO ENTRIES REGISTER This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96. Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES Table 21. Bit Descriptions for FIFO_ENTRIES Bits 7 [6:0] Bit Name Reserved FIFO_ENTRIES Settings Description Reserved Number of data samples stored in the FIFO Reset 0x0 0x0 Access R R TEMPERATURE DATA REGISTERS These two registers contain the uncalibrated temperature data. The nominal intercept is 1885 LSB at 25C and the nominal slope is -9.05 LSB/C. TEMP2 contains the four most significant bits, and TEMP1 contains the eight least significant bits of the 12-bit value. The ADXL357 temperature value is not double buffered, meaning the value can update between reading of the two registers. Address: 0x06, Reset: 0x00, Name: TEMP2 Table 22. Bit Descriptions for TEMP2 Bits [7:4] [3:0] Bit Name Reserved Temperature, Bits[11:8] Settings Description Reserved Uncalibrated temperature data Reset Access 0x0 R Reset 0x00 Access R Address: 0x07, Reset: 0x00, Name: TEMP1 Table 23. Bit Descriptions for TEMP1 Bits [7:0] Bit Name Temperature, Bits[7:0] Settings Description Uncalibrated temperature data X-AXIS DATA REGISTERS These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement. Address: 0x08, Reset: 0x00, Name: XDATA3 Table 24. Bit Descriptions for XDATA3 Bits [7:0] Bit Name XDATA, Bits[19:12] Settings Description X-axis data Reset 0x00 Access R Reset 0x00 Access R Reset 0x0 0x0 Access R R Address: 0x09, Reset: 0x00, Name: XDATA2 Table 25. Bit Descriptions for XDATA2 Bits [7:0] Bit Name XDATA, Bits[11:4] Settings Description X-axis data Address: 0x0A, Reset: 0x00, Name: XDATA1 Table 26. Bit Descriptions for XDATA1 Bits [7:4] [3:0] Bit Name XDATA, Bits[3:0] Reserved Settings Description X-axis data Reserved Rev. A | Page 34 of 42 Data Sheet ADXL356/ADXL357 Y-AXIS DATA REGISTERS These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement. Address: 0x0B, Reset: 0x00, Name: YDATA3 Table 27. Bit Descriptions for YDATA3 Bits [7:0] Bit Name YDATA, Bits[19:12] Settings Description Y-axis data Reset 0x00 Access R Reset 0x00 Access R Reset 0x0 0x0 Access R R Address: 0x0C, Reset: 0x00, Name: YDATA2 Table 28. Bit Descriptions for YDATA2 Bits [7:0] Bit Name YDATA, Bits[11:4] Settings Description Y-axis data Address: 0x0D, Reset: 0x00, Name: YDATA1 Table 29. Bit Descriptions for YDATA1 Bits [7:4] [3:0] Bit Name YDATA, Bits[3:0] Reserved Settings Description Y-axis data Reserved Z-AXIS DATA REGISTERS These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement. Address: 0x0E, Reset: 0x00, Name: ZDATA3 Table 30. Bit Descriptions for ZDATA3 Bits [7:0] Bit Name ZDATA, Bits[19:12] Settings Description Z-axis data Reset 0x00 Access R Reset 0x00 Access R Address: 0x0F, Reset: 0x00, Name: ZDATA2 Table 31. Bit Descriptions for ZDATA2 Bits [7:0] Bit Name ZDATA, Bits[11:4] Settings Description Z-axis data Address: 0x10, Reset: 0x00, Name: ZDATA1 Table 32. Bit Descriptions for ZDATA1 Bits [7:4] [3:0] Bit Name ZDATA, Bits[3:0] Reserved Settings Description Z-axis data Reserved Rev. A | Page 35 of 42 Reset 0x0 0x0 Access R R ADXL356/ADXL357 Data Sheet FIFO ACCESS REGISTER Address: 0x11, Reset: 0x00, Name: FIFO_DATA Read this register to access data stored in the FIFO. Table 33. Bit Descriptions for FIFO_DATA Bits [7:0] Bit Name FIFO_DATA Settings Description FIFO data is formatted to 24 bits, three bytes, most significant byte first. A read to this address pops an effective three equal byte words of axis data from the FIFO. Two subsequent reads or a multibyte read completes the transaction of this data onto the interface. Continued reading or a sustained multibyte read of this field continues to pop the FIFO every third byte. Multibyte reads to this address do not increment the address pointer. If this address is read due to an auto-increment from the previous address, it does not pop the FIFO. Instead, it returns zeros and increments on to the next address. Reset 0x0 Access R Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W X-AXIS OFFSET TRIM REGISTERS Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H Table 34. Bit Descriptions for OFFSET_X_H Bits [7:0] Bit Name OFFSET_X, Bits[15:8] Settings Description Offset added to x-axis data after all other signal processing. Data is in twos complement format. The significance of OFFSET_X, Bits[15:0] matches the significance of XDATA, Bits[19:4]. Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L Table 35. Bit Descriptions for OFFSET_X_L Bits [7:0] Bit Name OFFSET_X, Bits[7:0] Settings Description Offset added to x-axis data after all other signal processing. Data is in twos complement format. The significance of OFFSET_X, Bits[15:0] matches the significance of XDATA, Bits[19:4]. Y-AXIS OFFSET TRIM REGISTERS Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H Table 36. Bit Descriptions for OFFSET_Y_H Bits [7:0] Bit Name OFFSET_Y, Bits[15:8] Settings Description Offset added to y-axis data after all other signal processing. Data is in twos complement format. The significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA, Bits[19:4]. Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L Table 37. Bit Descriptions for OFFSET_Y_L Bits [7:0] Bit Name OFFSET_Y, Bits[7:0] Settings Description Offset added to y-axis data after all other signal processing. Data is in twos complement format. The significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA, Bits[19:4]. Rev. A | Page 36 of 42 Data Sheet ADXL356/ADXL357 Z-AXIS OFFSET TRIM REGISTERS Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H Table 38. Bit Descriptions for OFFSET_Z_H Bits [7:0] Bit Name OFFSET_Z, Bits[15:8] Settings Description Offset added to z-axis data after all other signal processing. Data is in twos complement format. The significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA, Bits[19:4]. Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L Table 39. Bit Descriptions for OFFSET_Z_L Bits [7:0] Bit Name OFFSET_Z, Bits[7:0] Settings Description Offset added to z-axis data after all other signal processing. Data is in twos complement format. The significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA, Bits[19:4]. ACTIVITY ENABLE REGISTER Address: 0x24, Reset: 0x00, Name: ACT_EN Table 40. Bit Descriptions for ACT_EN Bits [7:3] 2 1 0 Bit Name Reserved ACT_Z ACT_Y ACT_X Settings Description Reserved. Z-axis data is a component of the activity detection algorithm. Y-axis data is a component of the activity detection algorithm. X-axis data is a component of the activity detection algorithm. Reset 0x0 0x0 0x0 0x0 Access R R/W R/W R/W ACTIVITY THRESHOLD REGISTERS Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H Table 41. Bit Descriptions for ACT_THRESH_H Bits [7:0] Bit Name ACT_THRESH, Bits[15:8] Settings Description Threshold for activity detection. Acceleration magnitude must be above ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned magnitude. The significance of ACT_THRESH, Bits[15:0] matches the significance of Bits[18:3] of XDATA, YDATA, and ZDATA. Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L Table 42. Bit Descriptions for ACT_THRESH_L Bits [7:0] Bit Name ACT_THRESH, Bits[7:0] Settings Description Threshold for activity detection. The acceleration magnitude must be greater than the value in ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned magnitude. The significance of ACT_THRESH, Bits[15:0] matches the significance of Bits[18:3] of XDATA, YDATA, and ZDATA. ACTIVITY COUNT REGISTER Address: 0x27, Reset: 0x01, Name: ACT_COUNT Table 43. Bit Descriptions for ACT_COUNT Bits [7:0] Bit Name ACT_COUNT Settings Description Number of consecutive events above threshold (from ACT_THRESH) required to detect activity Rev. A | Page 37 of 42 Reset 0x1 Access R/W ADXL356/ADXL357 Data Sheet FILTER SETTINGS REGISTER Address: 0x28, Reset: 0x00, Name: Filter Use this register to specify parameters for the internal high-pass and low-pass filters. Table 44. Bit Descriptions for Filter Bits 7 [6:4] Bit Name Reserved HPF_CORNER Settings 000 001 010 011 100 101 110 [3:0] ODR_LPF 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Description Reserved -3 dB filter corner for the first-order, high-pass filter relative to the ODR Not applicable, no high-pass filter enabled 24.7 x 10-4 x ODR 6.2084 x 10-4 x ODR 1.5545 x 10-4 x ODR 0.3862 x 10-4 x ODR 0.0954 x 10-4 x ODR 0.0238 x 10-4 x ODR ODR and low-pass filter corner 4000 Hz and 1000 Hz 2000 Hz and 500 Hz 1000 Hz and 250 Hz 500 Hz and 125 Hz 250 Hz and 62.5 Hz 125 Hz and 31.25 Hz 62.5 Hz and 15.625 Hz 31.25 Hz and 7.813 Hz 15.625 Hz and 3.906 Hz 7.813 Hz and 1.953 Hz 3.906 Hz and 0.977 Hz Reset 0x0 0x0 Access R R/W 0x0 R/W FIFO SAMPLES REGISTER Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid triggering the FIFO watermark interrupt. Table 45. Bit Descriptions for FIFO_SAMPLES Bits 7 [6:0] Bit Name Reserved FIFO_SAMPLES Settings Description Reserved. Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition. Values range from 1 to 96. Reset 0x0 0x60 Access R R/W INTERRUPT PIN (INTx) FUNCTION MAP REGISTER Address: 0x2A, Reset: 0x00, Name: INT_MAP The INT_MAP register configures the interrupt pins. Bits[7:0] select which functions generate an interrupt on the INT1 and INT2 pins. Multiple events can be configured. If the corresponding bit is set to 1, the function generates an interrupt on the interrupt pins. Table 46. Bit Descriptions for INT_MAP Bits 7 6 5 4 3 2 1 0 Bit Name ACT_EN2 OVR_EN2 FULL_EN2 RDY_EN2 ACT_EN1 OVR_EN1 FULL_EN1 RDY_EN1 Settings Description Activity interrupt enable on INT2 FIFO_OVR interrupt enable on INT2 FIFO_FULL interrupt enable on INT2 DATA_RDY interrupt enable on INT2 Activity interrupt enable on INT1 FIFO_OVR interrupt enable on INT1 FIFO_FULL interrupt enable on INT1 DATA_RDY interrupt enable on INT1 Rev. A | Page 38 of 42 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W Data Sheet ADXL356/ADXL357 DATA SYNCHRONIZATION Address: 0x2B, Reset: 0x00, Name: Sync Use this register to control the external timing triggers. Table 47. Bit Descriptions for Sync Bits [7:3] 2 [1:0] Bit Name Reserved EXT_CLK EXT_SYNC Settings 00 01 10 11 Description Reserved. Enable external clock. See Table 14 for configuration details. Enable external synchronization control. Internal synchronization. External synchronization, no interpolation filter. After synchronization, and for EXT_SYNC within specification, DATA_RDY occurs on EXT_SYNC. External synchronization, interpolation filter, next available data indicated by DATA_RDY 14 to 8204 oscillator cycles later (longer delay for higher ODR_LPF setting), data represents a sample point group delay earlier in time. Reserved. Reset 0x0 0x0 0x0 Access R R/W R/W I2C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER Address: 0x2C, Reset: 0x81, Name: Range Table 48. Bit Descriptions for Range Bits 7 Bit Name I2C_HS Settings 1 0 6 INT_POL 0 1 [5:2] [1:0] Reserved Range 01 10 11 Description I2C speed. High speed mode. Fast mode. Interrupt polarity. INT1 and INT2 are active low. INT1 and INT2 are active high. Reserved. Range. 10 g. 20 g. 40 g. Reset 0x1 Access R/W 0x0 R/W 0x0 0x1 R R/W POWER CONTROL REGISTER Address: 0x2D, Reset: 0x01, Name: POWER_CTL Table 49. Bit Descriptions for POWER_CTL Bits [7:3] 2 1 Bit Name Reserved DRDY_OFF TEMP_OFF 0 Standby Settings 1 0 Description Reserved. Set to 1 to force the DRDY output to 0 in modes where it is normally signal data ready. Set to 1 to disable temperature processing. Temperature processing is also disabled when standby = 1. Standby or measurement mode. Standby mode. In standby mode, the device is in a low power state, and the temperature and acceleration datapaths are not operating. In addition, digital functions, including FIFO pointers, reset. Changes to the configuration setting of the device must be made when standby = 1. An exception is a high-pass filter that can be changed when the device is operating. Measurement mode. Rev. A | Page 39 of 42 Reset 0x0 0x0 0x0 Access R R/W R/W 0x1 R/W ADXL356/ADXL357 Data Sheet SELF TEST REGISTER Address: 0x2E, Reset: 0x00, Name: SELF_TEST Refer to the Self Test section for more information on the operation of the self test feature. Table 50. Bit Descriptions for SELF_TEST Bits [7:2] 1 0 Bit Name Reserved ST2 ST1 Settings Description Reserved. Set to 1 to enable self test force Set to 1 to enable self test mode Reset 0x0 0x0 0x0 Access R R/W R/W RESET REGISTER Address: 0x2F, Reset: 0x00, Name: Reset Table 51. Bit Descriptions for Reset Bits [7:0] Bit Name Reset Settings Description Write Code 0x52 to reset the device, similar to a power-on reset (POR) Reset 0x0 Access W In case of a software reset, an unlikely race condition may occur in products with REVID = 0x01 or earlier. If the race condition occurs, some factory settings in the NVM load incorrectly to shadow registers (the registers from which the internal logic configures the sensor and calculates the output after a power-on or a software reset). The incorrect loading of the NVM affects overall performance of the sensor, such as an incorrect 0 g bias and other performance issues. The incorrect loading of NVM does not occur from a power-on or after a power cycle. To guarantee reliable operation of the sensor after a software reset, the user can access the shadow registers after a power-on, read and store the values on the host microprocessor, and compare the values read from the same shadow registers after a software reset. This method guarantees proper operation in all devices and under all conditions. The recommended steps are as follows: 1. 2. 3. Read the shadow registers, Register 0x50 to Register 0x54 (five 8-bit registers) after power-up, but before any software reset. Store these values in a host device (for example, a host microprocessor). After each software reset, read the same five registers. If the values differ, perform a software reset again until they match. Rev. A | Page 40 of 42 Data Sheet ADXL356/ADXL357 PCB FOOTPRINT PATTERN Figure 77 shows the PCB footprint pattern and dimensions in millimeters. 3.22mm 0.68mm 0.70mm 0.70mm 3.80mm 14 PLCS 1.8mm x 0.68mm 15429-076 4.5mm TRIANGULAR MARKER, DETAIL A, POINTS TO PIN 1, WHICH IS NOT ROUTED INTERNALLY AND DOES NOT NEED TO BE GROUNDED 3.80mm Figure 77. PCB Footprint Pattern and Dimensions in Millimeters Rev. A | Page 41 of 42 ADXL356/ADXL357 Data Sheet OUTLINE DIMENSIONS DETAIL A 6.25 6.00 SQ 5.85 0.80 BSC 2.25 2.05 1.85 1.674 BSC 0.510 REF 0.30 SQ 12 14 11 1 (PIN 1 INDEX) DETAIL A 5.60 SQ R 0.103 (14 PLCS) 3.81 REF 0.508 BSC 4 8 7 TOP VIEW 0.10 BSC R 0.203 (14 PLCS) 0.15 BSC 5 BOTTOM VIEW SIDE VIEW 2.20 REF 2.54 REF 0.914 BSC 05-27-2016-B PKG-004554 R 0.25 (4 PLCS) Figure 78. 14-Terminal Ceramic Leadless Chip Carrier [LCC] (E-14-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADXL356BEZ ADXL356BEZ-RL ADXL356BEZ-RL7 ADXL356CEZ ADXL356CEZ-RL ADXL356CEZ-RL7 ADXL357BEZ ADXL357BEZ-RL ADXL357BEZ-RL7 EVAL-ADXL356BZ EVAL-ADXL356CZ EVAL-ADXL357Z 1 Output Mode Analog Analog Analog Analog Analog Analog Digital Digital Digital Measurement Range (g) 10, 20 10, 20 10, 20 10, 40 10, 40 10, 40 10, 20, 40 10, 20, 40 10, 20, 40 Specified Voltage (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 14-Terminal LCC 14-Terminal LCC, 13" Reel 14-Terminal LCC, 7" Reel 14-Terminal LCC 14-Terminal LCC, 13" Reel 14-Terminal LCC, 7" Reel 14-Terminal LCC 14-Terminal LCC 14-Terminal LCC Evaluation Board for ADXL356B Evaluation Board for ADXL356C Evaluation Board for ADXL357 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2017-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15429-6/20(A) Rev. A | Page 42 of 42 Package Option E-14-1 E-14-1 E-14-1 E-14-1 E-14-1 E-14-1 E-14-1 E-14-1 E-14-1