Low Noise, Low Drift, Low Power,
3-Axis MEMS Accelerometers
Data Sheet ADXL356/ADXL357
Rev. A Document Feedback
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Technical Support www.analog.com
FEATURES
Hermetic package offers optimal long-term stability
0 g offset vs. temperature (all axes): 0.75 mg/°C maximum
Ultralow noise spectral density (all axes): 75 μg/√Hz
Low power, VSUPPLY (LDO regulator enabled)
ADXL356 in measurement mode: 150 μA
ADXL357 in measurement mode: 200 μA
ADXL356/ADXL357 in standby mode: 21 μA
ADXL356 has user adjustable analog output bandwidth
ADXL357 digital output features
Digital SPI and limited I2C interfaces supported
20-bit ADC
Data interpolation routine for synchronous sampling
Programmable high- and low-pass digital filters
Integrated temperature sensor
Voltage range options
VSUPPLY with internal regulators: 2.25 V to 3.6 V
V1P8ANA, V1P8DIG with internal LDO regulator bypassed: 1.8 V
typical ± 10%
Operating temperature range: −40°C to +125°C
14-terminal, 6 mm × 5.6 mm × 2.2 mm, LCC package
APPLICATIONS
Inertial measurement units (IMUs)/attitude and heading
reference systems (AHRSs)
Platform stabilization systems
Structural health monitoring
Seismic imaging
Tilt sensing
Robotics
Condition monitoring
FUNCTIONAL BLOCK DIAGRAMS
TEMP
Z
OUT
Y
OUT
X
OUT
V
SUPPLY
V
SSIO
V
SS
ST1
ST2
ADXL356
STBY
V
DDIO
CONTROL
LOGIC
RANGE
TEMP
SENSOR
POWER
MANAGEMENT
ANALOG
FILTER
X
Y
Z
3-AXIS
SENSOR
V
1P8ANA
LDO
V
1P8DIG
LDO
15429-001
Figure 1. ADXL356
ADC
ADC
ADC
ADC
TEMP
SENSOR
V
1P8ANA
DIGITAL
FILTER
FIFO
POWER
MANAGEMENT
V
SUPPLY
V
DDIO
LDO
V
1P8DIG
LDO
X
Y
ZANALOG
FILTER
3-AXIS
SENSOR SCLK/V
SSIO
MOSI/SDA
MISO/ASEL
V
SSIO
V
SS
INT1
INT2
CS/SCL
ADXL357
DRDY
SERIAL
I/O
CONTROL
LOGIC
15429-002
Figure 2. ADXL357
GENERAL DESCRIPTION
The analog output ADXL356 and the digital output ADXL357
are low noise density, low 0 g offset drift, low power, 3-axis
accelerometers with selectable measurement ranges. The
ADXL356B supports the ±10 g and ±20 g ranges, the ADXL356C
supports the ±10 g and ±40 g ranges, and the ADXL357 supports
the ±10 g, ±20 g, and ±40 g ranges.
The ADXL356/ADXL357 offer industry leading noise, minimal
offset drift over temperature, and long-term stability, enabling
precision applications with minimal calibration.
The low drift, low noise, and low power ADXL357 enables
accurate tilt measurement in an environment with high
vibration. The low noise of the ADXL356 over higher
frequencies is ideal for condition-based monitoring and other
vibration sensing applications.
The ADXL357 multifunction pin names may be referenced only
by their relevant function for either the serial peripheral
interface (SPI) or limited I2C interface.
1 Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621.
ADXL356/ADXL357 Data Sheet
Rev. A | Page 2 of 42
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Analog Output for the ADXL356 ............................................... 4
Digital Output for the ADXL357 ............................................... 5
SPI Digital Interface Characteristics for the ADXL357 .......... 7
I2C Digital Interface Characteristics for the ADXL357 ........... 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
Recommended Soldering Profile ............................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 12
Root Allan Variance (RAV) ADXL357 Characteristics ......... 20
Theory of Operation ...................................................................... 21
Applications Information .............................................................. 22
Analog Output ............................................................................ 22
Digital Output ............................................................................. 22
Axes of Acceleration Sensitivity ............................................... 23
Power Sequencing ...................................................................... 23
Power Supply Description ......................................................... 23
Overrange Protection ................................................................. 23
Self Test ........................................................................................ 23
Filter ............................................................................................. 24
Serial Communications ................................................................. 26
SPI Protocol ................................................................................. 26
SPI Bus Sharing ........................................................................... 26
I2C Protocol ................................................................................. 27
Reading Acceleration or Temperature Data from the Interface
....................................................................................................... 27
FIFO ................................................................................................. 28
Interrupts ......................................................................................... 29
DATA_ RDY ................................................................................. 29
DRDY Pin .................................................................................... 29
FIFO_FULL ................................................................................. 29
FIFO_OVR .................................................................................. 29
Activity ......................................................................................... 29
External Synchronization and Interpolation .......................... 29
ADXL357 Register Map ................................................................. 32
Register Definitions........................................................................ 33
Analog Devices ID Register ...................................................... 33
Analog Devices MEMS ID Register ......................................... 33
Device ID Register ..................................................................... 33
Product Revision ID Register ................................................... 33
Status Register ............................................................................. 33
FIFO Entries Register ................................................................ 34
Temperature Data Registers ...................................................... 34
X-Axis Data Registers ................................................................ 34
Y-Axis Data Registers ................................................................ 35
Z-Axis Data Registers ................................................................ 35
FIFO Access Register ................................................................. 36
X-Axis Offset Trim Registers .................................................... 36
Y-Axis Offset Trim Registers .................................................... 36
Z-Axis Offset Trim Registers .................................................... 37
Activity Enable Register ............................................................ 37
Activity Threshold Registers ..................................................... 37
Activity Count Register ............................................................. 37
Filter Settings Register ............................................................... 38
FIFO Samples Register .............................................................. 38
Interrupt Pin (INTx) Function Map Register......................... 38
Data Synchronization ................................................................ 39
I2C Speed, Interrupt Polarity, and Range Register ................. 39
Power Control Register ............................................................. 39
Self Test Register ......................................................................... 40
Reset Register .............................................................................. 40
PCB Footprint Pattern ................................................................... 41
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
Data Sheet ADXL356/ADXL357
Rev. A | Page 3 of 42
REVISION HISTORY
6/2020—Rev. 0 to Rev. A
Changes to Features Section, Applications Section, and General
Description Section ........................................................................... 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 5
Changes to Input Current Parameter, Table 3 ............................... 7
Changes to Acceleration (Any Axis, 0.1 ms) Parameter, Table 5;
Thermal Resistance Section; and Table 6 ....................................... 9
Moved Recommended Soldering Profile Section, Figure 5, and
Table 7 ................................................................................................. 9
Changes to Table 8 .......................................................................... 10
Changes to Typical Performance Section and Figure 8 to
Figure 13 ........................................................................................... 12
Changes to Figure 14 to Figure 19 ................................................ 13
Changes to Figure 23 to Figure 25 ................................................ 14
Changes to Figure 32 to Figure 37 ................................................ 16
Changes to Figure 44 Caption, Figure 47 Caption, and Figure 48
Caption ............................................................................................. 18
Changes to Figure 50 Caption, Figure 52 Caption, and
Figure 53 ........................................................................................... 19
Changes to Theory of Operation Section .................................... 21
Changes to Power Sequencing Section, V1P8ANA Section, and
Overrange Protection Section ....................................................... 23
Changes to Self Test Section, Filter Section, Figure 62, and
Figure 63 ........................................................................................... 24
Changes to Table 11 ........................................................................ 25
Changes to Serial Communications Section and Figure 64 ...... 26
Added SPI Bus Sharing Section and Figure 65; Renumbered
Sequentially ...................................................................................... 26
Changes to I2C Protocol Section ................................................... 27
Changes to FIFO Section ............................................................... 28
Changes to DRDY Pin Section, FIFO_OVR Section, Activity
Section, NVM_BUSY Section, and External Synchronization
and Interpolation Section .............................................................. 29
Changed EXT_SYNC = 00—No External Sync or Interpolation
Section to EXT_SYNC = 00, EXT_CLK = 0—No External
Synchronization or Interpolation Section; EXT_SYNC = 10—
External Sync with Interpolation Section to EXT_SYNC = 10,
EXT_CLK = 0—External Synchronization with Interpolation
Section; and EXT_SYNC = 01—External Sync and External
Clock, No Interpolation Filter Section to EXT_SYNC = 01,
EXT_CLK = 1—External Synchronization and External Clock,
No Interpolation Filter Section ..................................................... 30
Changes to EXT_SYNC = 00, EXT_CLK = 0—No External
Synchronization or Interpolation Section, EXT_SYNC = 10,
EXT_CLK = 0—External Synchronization with Interpolation
Section, Table 13, and EXT_SYNC = 01, EXT_CLK = 1—
External Synchronization and External Clock, No Interpolation
Filter Section .................................................................................... 30
Added EXT_SYNC = 10, EXT_CLK = 1—External
Synchronization and External Clock, with Interpolation Filter
Section .............................................................................................. 30
Changes to Table 14 ........................................................................ 31
Changes to Figure 74, Figure 75 Caption, and Figure 76 .......... 31
Changes to Temperature Data Registers Section, Table 23,
Table 24, and Table 25 ..................................................................... 34
Changes to Table 27, Table 28, Table 30 and Table 31 ................ 35
Change to Table 42 Title ................................................................. 37
Changes to Table 44 ........................................................................ 38
Changes to Reset Register Section ................................................ 40
Changes to Figure 77 ...................................................................... 41
Changes to Ordering Guide ........................................................... 42
2/2017—Revision 0: Initial Version
ADXL356/ADXL357 Data Sheet
Rev. A | Page 4 of 42
SPECIFICATIONS
ANALOG OUTPUT FOR THE ADXL356
TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, z-axis acceleration = 1 g, and full-scale range = ±10 g, unless
otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
SENSOR INPUT Each axis
Output Full-Scale Range (FSR) ADXL356B supports two ranges ±10, ±20 g
ADXL356C supports two ranges ±10, ±40 g
Resonant Frequency1 5.5 kHz
Nonlinearity ±10 g 0.1 % FSR
±40 g 1.3 % FSR
Cross Axis Sensitivity 1 %
SENSITIVITY Ratiometric to V1P8ANA
Sensitivity at XOUT, YOUT, ZOUT ±10 g 73.6 80 86.4 mV/g
±20 g 36.8 40 43.2 mV/g
±40 g 18.4 20 21.6 mV/g
Sensitivity Change Due to Temperature TA = −40°C to +125°C ±0.01 %/°C
Repeatability2 X-axis and y-axis 0.1 %
Z-axis 0.2 %
0 g OFFSET Each axis, ±10 g
0 g Output for XOUT, YOUT, ZOUT Referred to V1P8ANA/2 −375 ±125 +375 mg
0 g Offset vs. Temperature (X-Axis, Y-Axis,
and Z-Axis)3
TA = −40°C to +125°C −0.75 ±0.2 +0.75 mg/°C
Repeatability2 X-axis and y-axis ±4.25 mg
Z-axis ±5 mg
Vibration Rectification Error (VRE)4 Offset due to 7.5 g rms vibration, ±10 g
range, in a 1 g orientation
<0.1 g
NOISE
Spectral Density5
X-Axis, Y-Axis, and Z-Axis ±10 g 75 μg/√Hz
±40 g 110 μg/√Hz
Velocity Random Walk ±10 g
X-Axis and Y-Axis 38.2 mm/sec/Hr
Z-Axis 26.5
mm/sec/Hr
BANDWIDTH −3 dB, overall transfer function6 2.4 kHz
SELF TEST
Output Change
Z-Axis ±10 g range7 0.5 1.25 3.0
g
POWER SUPPLY
Voltage Range
VSUPPLY8 2.25 2.5 3.6 V
VDDIO V1P8DIG 2.5 3.6 V
V1P8ANA, V1P8DIG Internal low dropout (LDO) regulator
bypassed, VSUPPLY = 0 V
1.62 1.8 1.98 V
Current
Measurement Mode
VSUPPLY LDO regulator enabled 150 μA
V1P8ANA LDO regulator disabled 138 μA
V1P8DIG LDO regulator disabled 12 μA
Data Sheet ADXL356/ADXL357
Rev. A | Page 5 of 42
Parameter Test Conditions/Comments Min Typ Max Unit
Standby Mode
VSUPPLY LDO regulator enabled 21 μA
V1P8ANA LDO regulator disabled 7 μA
V1P8DIG LDO regulator disabled 10 μA
Turn On Time9 10 g range <10 ms
Power-off to standby <10 ms
OUTPUT AMPLIFIER XOUT, YOUT, ZOUT, and TEMP pins
Swing No load 0.03 V1P8ANA − 0.03 V
Output Series Resistance 32 kΩ
TEMPERATURE SENSOR
Output at 25°C 967 mV
Scale Factor 3.0 mV/°C
TEMPERATURE
Operating Temperature Range −40 +125 °C
1 The resonant frequency is a sensor characteristic.
2 Repeatability is predicted for a 10 year life and includes shifts due to the high temperature operating life (HTOL) (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours),
temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows
the square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: ±4.25 mg × √(2.5 years/10 years) = ±2.125 mg.
3 The temperature change is −40°C to +25°C, or +25°C to +125°C.
4 The VRE measurement is the shift in dc offset while the device is subject to 7.5 g rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is
configured for the ±10 g range and an output data rate of 4 kHz. The VRE scales with the range setting.
5 Based on characterization.
6 Overall transfer function includes the sensor mechanical response and all other filters on the signal chain.
7 ±10 g indicates a test condition. The self test result converted to the acceleration value is independent of the selected range.
8 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
9 Standby to measurement mode. This specification is valid when the output is within 5 mg of the final value.
DIGITAL OUTPUT FOR THE ADXL357
TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, z-axis acceleration = 1 g, full-scale range = ±10 g, and output
data rate (ODR) = 500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced only by their relevant function.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
SENSOR INPUT Each axis
Output Full Scale Range (FSR) User selectable, supports three ranges ±10,
±20,
±40
g
Nonlinearity ±10 g 0.1 % FSR
±40 g 1.3 % FSR
Cross Axis Sensitivity 1 %
SENSITIVITY1 Each axis
X-Axis, Y-Axis, and Z-Axis Sensitivity ±10 g 47,104 51,200 55,296 LSB/g
±20 g 23,552 25,600 27,648 LSB/g
±40 g 11,776 12,800 13,824 LSB/g
X-Axis, Y-Axis, and Z-Axis Scale Factor ±10 g 19.5 μg/LSB
±20 g 39 μg/LSB
±40 g 78 μg/LSB
Sensitivity Change due to Temperature TA = −40°C to +125°C ±0.01 %/°C
Repeatability2 X-axis and y-axis 0.1 %
Z-axis 0.2 %
0 g OFFSET Each axis, ±10 g
X-Axis, Y-Axis, and Z-Axis 0 g Output −375 ±125 +375 mg
0 g Offset vs. Temperature (X-Axis, Y-Axis, and
Z-Axis)3
TA = −40°C to +125°C −0.75 ±0.20 +0.75 mg/°C
ADXL356/ADXL357 Data Sheet
Rev. A | Page 6 of 42
Parameter Test Conditions/Comments Min Typ Max Unit
Repeatability2 X-axis and y-axis ±4.25 mg
Z-axis ±5 mg
VRE4 Offset due to 7.5 g rms vibration, ±10 g
range, in a 1 g orientation
<0.1 g
NOISE
Spectral Density5
X-Axis, Y-Axis, and Z-Axis ±10 g 75 μg/√Hz
±40 g 90 μg/√Hz
Velocity Random Walk ±10 g
X-Axis and Y-Axis 38.2 mm/sec/Hr
Z-Axis 26.5
mm/sec/Hr
BANDWIDTH AND OUTPUT DATA RATE
Analog-to-Digital Converter (ADC) Resolution 20 Bits
Low-Pass Filter Passband Frequency User programmable, Register 0x28 0.977 1000 Hz
High-Pass Filter Passband Frequency When
Enabled (Disabled by Default)
User programmable, Register 0x28 for 4 kHz
ODR
0.0095 10 Hz
SELF TEST
Output Change
Z-Axis ±10 g range6 0.5 1.25 3.0
g
POWER SUPPLY
Voltage Range
VSUPPLY Operating7 2.25 2.5 3.6 V
VDDIO V
1P8DIG 2.5 3.6 V
V1P8ANA and V1P8DIG Internal LDO regulator bypassed, VSUPPLY = 0 V 1.62 1.8 1.98 V
Current
Measurement Mode
VSUPPLY LDO regulator enabled 200 μA
V1P8ANA LDO regulator disabled 160 μA
V1P8DIG LDO regulator disabled 35.5 μA
Standby Mode
VSUPPLY LDO regulator enabled 21 μA
V1P8ANA LDO regulator disabled 7 μA
V1P8DIG LDO regulator disabled 10 μA
Turn On Time8 ±10 g range <10 ms
Power-off to standby <10 ms
TEMPERATURE SENSOR
Output at 25°C 1885 LSB
Scale Factor −9.05 LSB/°C
TEMPERATURE
Operating Temperature Range −40 +125 °C
1 Characterized but not 100% tested.
2 Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and
1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain
offset repeatability of the x-axis for 2.5 years, use the following equation: ±4.25 mg × √(2.5 years/10 years) = ±2.125 mg.
3 The temperature change is −40°C to +25°C or +25°C to +125°C.
4 The VRE measurement is the shift in dc offset while the device is subject to 7.5 g rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the ±10 g range
and an output data rate of 4 kHz. The VRE scales with the range setting.
5 Based on characterization.
6 ±10 g indicates a test condition. The self test result converted to the acceleration value is independent of the selected range.
7 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
8 Standby to measurement mode. This specification is valid when the output is within 1 mg of final value.
Data Sheet ADXL356/ADXL357
Rev. A | Page 7 of 42
SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357
Note that multifunction pin names may be referenced by their relevant function only.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC INPUT LEVELS
Input Voltage
Low Level VIL 0.3 × VDDIO V
High Level VIH 0.7 × VDDIO V
Input Current
Low Level IIL Input voltage (VIN) = 0 V −0.2 μA
High Level IIH V
IN = VDDIO 0.2 μA
DC OUTPUT LEVELS
Output Voltage
Low Level VOL I
OL = IOL, MIN 0.2 × VDDIO V
High Level VOH I
OH = IOH, MAX 0.8 × VDDIO V
Output Current
Low Level IOL V
OL = VOL, MAX −10 mA
High Level IOH V
OH = VOH, MIN 4 mA
AC INPUT LEVELS
SCLK Frequency 0.1 10 MHz
SCLK High Time tHIGH 40 ns
SCLK Low Time tLOW 40 ns
CS Setup Time tCSS 20 ns
CS Hold Time tCSH 20 ns
CS Disable Time tCSD 40 ns
Rising SCLK Setup Time tSCLKS 20 ns
MOSI Setup Time tSU 20 ns
MOSI Hold Time tHD 20 ns
AC OUTPUT LEVELS
Propagation Delay tP Load capacitance (CLOAD) = 30 pF 30 ns
Enable MISO Time tEN 30 ns
Disable MISO Time tDIS 20 ns
t
SU
t
CSS
t
LOW
t
HIGH
t
CSD
t
CSH
t
SCLKS
t
EN
t
P
t
DIS
CS
SCLK
MISO
MOSI
t
HD
15429-003
Figure 3. SPI Interface Timing Diagram
ADXL356/ADXL357 Data Sheet
Rev. A | Page 8 of 42
I2C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357
Note that multifunction pin names may be referenced only by their relevant function.
Table 4.
Test Conditions/ I2C_HS = 0 (Fast Mode) I2C_HS = 1 (High Speed Mode)
Parameter Symbol Comments Min Typ Max Min Typ Max Unit
DC INPUT LEVELS
Input Voltage
Low Level VIL 0.3 × VDDIO 0.3 × VDDIO V
High Level VIH 0.7 × VDDIO 0.7 × VDDIO V
Hysteresis of Schmitt
Triggered Inputs
VHYS 0.05 × VDDIO 0.1 × VDDIO V
Input Current IIL 0.1 × VDDIO < VIN <
0.9 × VDDIO
−10 +10 μA
DC OUTPUT LEVELS
Output Voltage IOL = 3 mA
Low Level VOL1 V
DDIO > 2 V 0.4 0.4 V
V
OL2 V
DDIO ≤ 2 V 0.2 × VDDIO 0.2 × VDDIO V
Output Current
Low Level IOL V
OL = 0.4 V 20 20 mA
V
OL = 0.6 V 6 6 mA
AC INPUT LEVELS
SCL Frequency 0 1 0 3.4 MHz
SCL High Time tHIGH 260 60 ns
SCL Low Time tLOW 500 160 ns
Start Setup Time tSUSTA 260 160 ns
Start Hold Time tHDSTA 260 160 ns
SDA Setup Time tSUDAT 50 10 ns
SDA Hold Time tHDDAT 0 0 ns
Stop Setup Time tSUSTO 260 160 ns
Bus Free Time tBUF 500 ns
SCL Input Rise Time tRCL 120 80 ns
SCL Input Fall Time tFCL 120 80 ns
SDA Input Rise Time tRDA 120 160 ns
SDA Input Fall Time tFDA 120 160 ns
Width of Spikes to
Suppress
tSP Not shown in Figure 4 50 10 ns
AC OUTPUT LEVELS
Propagation Delay CLOAD = 500 pF
Data tVDDAT 97 450 27 135 ns
Acknowledge tVDACK 450 ns
Output Fall Time tF Not shown in Figure 4 20 ×
(VDDIO/5.5)
120 ns
t
SUDAT
t
HDDAT
t
HDSTA
t
LOW
t
HIGH
t
BUF
t
SUSTO
t
SUSTA
t
VDACK
SDA
SCL
t
RCL
t
FCL
t
FDA
t
RDA
t
SUSTA
t
VDDAT
t
VDDAT
15429-004
Figure 4. I2C Interface Timing Diagram
Data Sheet ADXL356/ADXL357
Rev. A | Page 9 of 42
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Acceleration (Any Axis, 0.1 ms)
Unpowered 10,000 g
Powered 10,000 g
VSUPPLY, VDDIO 5.4 V
V1P8ANA, V1P8DIG Configured as Inputs 1.98 V
ADXL356
Digital Inputs (RANGE, ST1, ST2, STBY) −0.3 V to VDDIO + 0.3 V
Analog Outputs (XOUT, YOUT, ZOUT, TEMP) −0.3 V to V1P8ANA + 0.3 V
ADXL357
Digital Pins (CS/SCL, SCLK/VSSIO,
MOSI/SDA, MISO/ASEL, INT1, INT2,
DRDY)
−0.3 V to VDDIO + 0.3 V
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −55°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. ψJB is
the junction to board thermal resistance.
Table 6. Thermal Resistance
Package Type θJA ψ
JB Unit
E-14-11 42 17.6 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD51.
RECOMMENDED SOLDERING PROFILE
Figure 5 and Table 7 provide details about the recommended
soldering profile.
t
P
t
L
t
25°C TO PEAK
t
S
PREHEAT
CRITICAL ZONE
T
L
TO T
P
TEMPERATURE
TIME
RAMP-DOWN
RAMP-UP
T
SMIN
T
SMAX
T
P
T
L
15429-005
Figure 5. Recommended Soldering Profile
Table 7. Recommended Soldering Profile
Condition
Profile Feature Sn63/Pb37 Pb-Free
Average Ramp Rate from Liquid
Temperature (TL) to Peak
Temperature (TP)
3°C/sec
maximum
3°C/sec
maximum
Preheat
Minimum Temperature
(TSMIN)
100°C 150°C
Maximum Temperature
(TSMAX)
150°C 200°C
Time from TSMIN to TSMAX (tS) 60 sec to
120 sec
60 sec to
180 sec
TSMAX to TL Ramp-Up Rate 3°C/sec
maximum
3°C/sec
maximum
Liquid Temperature (TL) 183°C 217°C
Time Maintained Above TL (tL) 60 sec to
150 sec
60 sec to
150 sec
Peak Temperature (TP) 240°C +
0°C/−5°C
260°C +
0°C/−5°C
Time of Actual TP − 5°C (tP) 10 sec to
30 sec
20 sec to
40 sec
Ramp-Down Rate 6°C/sec
maximum
6°C/sec
maximum
Time from 25°C to Peak
Temperature (t25°C TO PEAK)
6 minutes
maximum
8 minutes
maximum
ESD CAUTION
ADXL356/ADXL357 Data Sheet
Rev. A | Page 10 of 42
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADXL356
TOP VIEW
(Not to Scale)
V
SUPPLY
V
1P8ANA
V
SS
V
1P8DIG
RANGE
ST1
ST2
TEMP
11
10
9
Z
OUT
Y
OU
T
X
OU
T
14
13
12
8
1
2
3
V
DDIO
V
SSIO
STBY
5
6
7
4
X
Z
Y
15429-006
Figure 6. ADXL356 Pin Configuration
Table 8. ADXL356 Pin Function Descriptions
Pin No. Mnemonic Description
1 RANGE Range Selection Pin. Set this pin to ground to select the ±10 g range, or set this pin to VDDIO to select the
±20 g or ±40 g range. This pin is model dependent (see the Ordering Guide section).
2 ST1 Self Test Pin 1. This pin enables self test mode. This pin must be forced low when not in self test mode.
3 ST2 Self Test Pin 2. This pin activates electromechanical self test actuation. This pin must be forced low when not
in self test mode.
4 TEMP Temperature Sensor Output.
5 VDDIO Digital Interface Supply Voltage.
6 VSSIO Digital Ground.
7 STBY Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin
to VDDIO to enter measurement mode.
8 V1P8DIG Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this
pin externally.
9 VSS Analog Ground.
10 V1P8ANA Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this
pin externally.
11 VSUPPLY Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDO regulators to generate
V1P8DIG and V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
12 XOUT X-Axis Output.
13 YOUT Y-Axis Output.
14 ZOUT Z-Axis Output.
Data Sheet ADXL356/ADXL357
Rev. A | Page 11 of 42
ADXL357
TOP VIEW
(Not to Scale)
V
SUPPLY
X
Z
Y
V
1P8ANA
V
SS
V
1P8DIG
CS/SCL
S
CLK/V
SSIO
MOSI/SDA
MISO/ASEL
11
10
9
DRDY
INT2
INT1
14
13
12
8
1
2
3
V
DDIO
V
SSIO
RESERVED
5
6
7
4
15429-007
Figure 7. ADXL357 Pin Configuration (SPI/I2C)
Table 9. ADXL357 Pin Function Descriptions
Pin No. Mnemonic Description
1 CS/SCL Chip Select for SPI (CS).
Serial Communications Clock for I2C (SCL).
2 SCLK/VSSIO Serial Communications Clock for SPI (SCLK).
I
2C Mode Enable (VSSIO). Connect this pin to Pin 6 (VSSIO) to enable I2C mode.
3 MOSI/SDA Master Output, Slave Input for SPI (MOSI).
Serial Data for I2C (SDA).
4 MISO/ASEL Master Input, Slave Output for SPI (MISO).
Alternate I2C Address Select for I2C (ASEL).
5 VDDIO Digital Interface Supply Voltage.
6 VSSIO Digital Ground.
7 RESERVED Reserved. This pin can be connected to ground or left open.
8 V1P8DIG Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this
pin externally.
9 VSS Analog Ground.
10 V1P8ANA Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this
pin externally.
11 VSUPPLY Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDO regulators to generate
V1P8DIG and V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
12 INT1 Interrupt Pin 1.
13 INT2 Interrupt Pin 2.
14 DRDY Data Ready Pin.
ADXL356/ADXL357 Data Sheet
Rev. A | Page 12 of 42
TYPICAL PERFORMANCE CHARACTERISTICS
All figures include data for multiple devices and multiple lots, and they were taken in the ±10 g range and TA = 25°C, unless otherwise noted. For
Figure 52, the ODR is derived from a master clock, with a frequency of 1.024 MHz and ±1.4% device to device variation (similar to ODR device
to device variation). For a given device, however, clock frequency variation over the temperature range (−40°C to +125°C) is no more than
±1.2%, guaranteed by design.
10
0.1
1
10 10k1k100
RELATIVE X
OUT
(
g)
FREQUENCY (Hz)
15429-008
Figure 8. ADXL356 Frequency Response for X-Axis
10
0.1
1
10 10k1k100
RELATIVE Y
OUT
(
g)
FREQUENCY (Hz)
15429-009
Figure 9. ADXL356 Frequency Response for Y-Axis
10
0.1
1
10 10k1k100
RELATIVE Z
OUT
(
g)
FREQUENCY (Hz)
15429-010
Figure 10. ADXL356 Frequency Response for Z-Axis
1
0.01
0.1
10 10k1k100
RELATIVE X
OUT
(
g)
FREQUENCY (Hz)
15429-011
Figure 11. ADXL357 Frequency Response for X-Axis at 4 kHz ODR
1
0.01
0.1
10 10k1k100
RELATIVE Y
OUT
(
g)
FREQUENCY (Hz)
15429-012
Figure 12. ADXL357 Frequency Response for Y-Axis at 4 kHz ODR
1
0.01
0.1
10 10k1k100
RELATIVE Z
OUT
(
g)
FREQUENCY (Hz)
15429-013
Figure 13. ADXL357 Frequency Response for Z-Axis at 4 kHz ODR
Data Sheet ADXL356/ADXL357
Rev. A | Page 13 of 42
75
–75
–50
–25
0
25
50
–40 –25 –10 5 20 35 50 65 80 95 110 125
ZERO g OFFSET NORMALIZED
RELATIVE TO 25°C (mg)
TEMPERATURE (°C)
15429-014
Figure 14. ADXL356 Zero g Offset Normalized Relative to 25°C vs.
Temperature, X-Axis
75
–75
–50
–25
0
25
50
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
15429-015
ZER
O
g OFFSET NORMALIZED
RELATIVE TO 25°C (mg)
Figure 15. ADXL356 Zero g Offset Normalized Relative to 25°C vs.
Temperature, Y-Axis
75
–75
–50
–25
0
25
50
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
15429-016
ZERO g OFFSET NORMALIZED
RELATIVE TO 25°C (mg)
Figure 16. ADXL356 Zero g Offset Normalized Relative to 25°C vs.
Temperature, Z-Axis
1.0
–1.0
–0.5
0
0.5
–40 –25 –10 5 20 35 50 65 80 95 110 125
SENSITIVITY NORMALIZED
RELATIVE TO 25°C (%)
TEMPERATURE (°C)
15429-017
Figure 17. ADXL356 Sensitivity Normalized Relative to 25°C vs. Temperature
X-Axis
1.0
–1.0
–0.5
0
0.5
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
15429-018
SENSITIVITY NORMALIZED
RELATIVE TO 25°C (%)
Figure 18. ADXL356 Sensitivity Normalized Relative to 25°C vs. Temperature,
Y-Axis
1.0
–1.0
–0.5
0
0.5
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
15429-019
SENSITIVITY NORMALIZED
RELATIVE TO 25°C (%)
Figure 19. ADXL356 Sensitivity Normalized Relative to 25°C vs. Temperature,
Z-Axis
ADXL356/ADXL357 Data Sheet
Rev. A | Page 14 of 42
40
0
10
20
30
5
15
25
35
PERCENT OF POPULATION (%)
X-AXIS OFFSET AT 25°C (mg)
–375
–325
–275
–225
–175
–125
–75
–25
25
75
125
175
225
275
325
375
15429-020
Figure 20. ADXL356 Zero g Offset Histogram at 25°C, X-Axis
30
0
10
20
5
15
25
PERCENT OF POPULATION (%)
Y-AXIS OFFSET AT 25°C (mg)
–375
–325
–275
–225
–175
–125
–75
–25
25
75
125
175
225
275
325
375
15429-021
Figure 21. ADXL356 Zero g Offset Histogram at 25°C, Y-Axis
25
0
10
20
5
15
PERCENT OF POPULATION (%)
Z-AXIS OFFSET AT 25°C (mg)
–375
–325
–275
–225
–175
–125
–75
–25
25
75
125
175
225
275
325
375
15429-022
Figure 22. ADXL356 Zero g Offset Histogram at 25°C, Z-Axis
25
0
10
20
5
15
PERCENT OF POPULATION (%)
X-AXIS SENSITIVITY AT 25°C (LSB/g)
0.0736
0.0740
0.0744
0.0748
0.0752
0.0756
0.0760
0.0764
0.0768
0.0772
0.0776
0.0780
0.0784
0.0788
0.0792
0.0796
0.0800
0.0804
0.0808
0.0812
0.0816
0.0820
0.0824
0.0828
0.0832
0.0836
0.0840
0.0844
0.0848
0.0852
0.0856
0.0860
0.0864
15429-023
Figure 23. ADXL356 Sensitivity Histogram at 25°C, X-Axis
25
0
10
20
5
15
PERCENT OF POPULATION (%)
Y-AXIS SENSITIVITY AT 25°C (LSB/g)
0.0736
0.0740
0.0744
0.0748
0.0752
0.0756
0.0760
0.0764
0.0768
0.0772
0.0776
0.0780
0.0784
0.0788
0.0792
0.0796
0.0800
0.0804
0.0808
0.0812
0.0816
0.0820
0.0824
0.0828
0.0832
0.0836
0.0840
0.0844
0.0848
0.0852
0.0856
0.0860
0.0864
15429-024
Figure 24. ADXL356 Sensitivity Histogram at 25°C, Y-Axis
25
0
10
20
5
15
PERCENT OF POPULATION (%)
Z-AXIS SENSITIVITY AT 25°C (LSB/g)
0.0736
0.0740
0.0744
0.0748
0.0752
0.0756
0.0760
0.0764
0.0768
0.0772
0.0776
0.0780
0.0784
0.0788
0.0792
0.0796
0.0800
0.0804
0.0808
0.0812
0.0816
0.0820
0.0824
0.0828
0.0832
0.0836
0.0840
0.0844
0.0848
0.0852
0.0856
0.0860
0.0864
15429-025
Figure 25. ADXL356 Sensitivity Histogram at 25°C, Z-Axis
Data Sheet ADXL356/ADXL357
Rev. A | Page 15 of 42
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0108642
OFFSET SHIFT (g)
INPUT VIBRATION (
g
rms)
15429-026
Figure 26. ADXL356 VRE, X-Axis Offset from +1 g, ±10 g Range,
X-Axis Orientation = +1 g
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0108642
OFFSET SHIFT (g)
INPUT VIBRATION (
g
rms)
15429-027
Figure 27. ADXL356 VRE, Y-Axis Offset from +1 g, ±10 g Range,
Y-Axis Orientation = +1 g
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0108642
OFFSET SHIFT (g)
INPUT VIBRATION (
g
rms)
15429-028
Figure 28. ADXL356 VRE, Z-Axis Offset from +1 g, ±10 g Range,
Z-Axis Orientation = +1 g
0.10
–0.10
–0.05
0
0.05
0252015105
OFFSET SHIFT (g)
INPUT VIBRATION (
g
rms)
15429-029
Figure 29. ADXL356 VRE, X-Axis Offset from −1 g, ±40 g Range,
X-Axis Orientation = −1 g
0.2
–0.2
–0.1
0
0.1
0252015105
OFFSET SHIFT (g)
INPUT VIBRATION (
g
rms)
15429-030
Figure 30. ADXL356 VRE, Y-Axis Offset from −1 g, ±40 g Range,
Y-Axis Orientation = −1 g
0.2
–0.2
–0.1
0
0.1
0252015105
OFFSET SHIFT (g)
INPUT VIBRATION (
g
rms)
15429-031
Figure 31. ADXL356 VRE, Z-Axis Offset from −1 g, ±40 g Range,
Z-Axis Orientation = −1 g
ADXL356/ADXL357 Data Sheet
Rev. A | Page 16 of 42
75
–75
–50
–25
0
25
50
–45 –30 –15 0 15 30 45 60 75 90 105 120 135
TEMPERATURE (°C)
15429-032
ZERO g OFFSET NORMALIZED
RELATIVE TO 25°C (mg)
Figure 32. ADXL357 Zero g Offset Normalized Relative to 25°C vs.
Temperature, X-Axis
75
–75
–50
–25
0
25
50
–45 –25 –5 15 35 55 75 95 115
TEMPERATURE (°C)
15429-033
ZER
O
g OFFSET NORMALIZED
RELATIVE TO 25°C (mg)
Figure 33. ADXL357 Zero g Offset Normalized Relative to 25°C vs.
Temperature, Y-Axis
75
–75
–50
–25
0
25
50
–45 –25 –5 15 35 55 75 95 115
TEMPERATURE (°C)
15429-034
ZERO g OFFSET NORMALIZED
RELATIVE TO 25°C (mg)
Figure 34. ADXL357 Zero g Offset Normalized Relative to 25°C vs.
Temperature, Z-Axis
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
15429-035
SENSITIVITY NORMALIZED
RELATIVE TO 25°C (%)
Figure 35. ADXL357 Sensitivity Normalized Relative to 25°C vs. Temperature
X-Axis
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
15429-036
SENSITIVITY NORMALIZED
RELATIVE TO 25°C (%)
Figure 36. ADXL357 Sensitivity Normalized Relative to 25°C vs. Temperature
Y-Axis
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
15429-037
SENSITIVITY NORMALIZED
RELATIVE TO 25°C (%)
Figure 37. ADXL357 Sensitivity Normalized Relative to 25°C vs. Temperature
Z-Axis
Data Sheet ADXL356/ADXL357
Rev. A | Page 17 of 42
35
0
10
20
30
5
15
25
PERCENT OF POPULATION (%)
X-AXIS OFFSET AT 25°C (m
g
)
–375
–325
–275
–225
–175
–125
–75
–25
25
75
125
175
225
275
325
375
15429-038
Figure 38. ADXL357 Zero g Offset Histogram at 25°C, X-Axis
40
35
0
10
20
30
5
15
25
PERCENT OF POPULATION (%)
Y-AXIS OFFSET AT 25°C (m
g
)
–375
–325
–275
–225
–175
–125
–75
–25
25
75
125
175
225
275
325
375
15429-039
Figure 39. ADXL357 Zero g Offset Histogram at 25°C, Y-Axis
25
0
10
20
5
15
PERCENT OF POPULATION (%)
Z-AXIS OFFSET AT 25°C (m
g
)
–375
–325
–275
–225
–175
–125
–75
–25
25
75
125
175
225
275
325
375
15429-040
Figure 40. ADXL357 Zero g Offset Histogram at 25°C, Z-Axis
40
0
10
20
30
5
15
25
35
PERCENT OF POPULATION (%)
X-AXIS SENSITIVITY AT 25°C (LSB/
g
)
47104
47616
48128
48640
49152
49664
50176
50688
51200
51712
52224
52736
53248
53760
54272
54784
55296
15429-041
Figure 41. ADXL357 Sensitivity Histogram at 25°C, X-Axis
45
40
0
10
20
30
5
15
25
35
PERCENT OF POPULATION (%)
Y-AXIS SENSITIVITY AT 25°C (LSB/
g
)
47104
47616
48128
48640
49152
49664
50176
50688
51200
51712
52224
52736
53248
53760
54272
54784
55296
15429-042
Figure 42. ADXL357 Sensitivity Histogram at 25°C, Y-Axis
30
0
10
20
5
15
25
PERCENT OF POPULATION (%)
Z-AXIS SENSITIVITY AT 25°C (LSB/
g
)
47104
47616
48128
48640
49152
49664
50176
50688
51200
51712
52224
52736
53248
53760
54272
54784
55296
15429-043
Figure 43. ADXL357 Sensitivity Histogram at 25°C, Z-Axis
ADXL356/ADXL357 Data Sheet
Rev. A | Page 18 of 42
0.5
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0108642
OFFSET CHANGE (g)
INPUT VIBRATION (
g
rms)
15429-044
Figure 44. ADXL357 VRE, X-Axis Offset from +1 g, ±10 g Range,
X-Axis Orientation = +1 g
0.5
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0108642
OFFSET CHANGE (g)
INPUT VIBRATION (
g
rms)
15429-045
Figure 45. ADXL357 VRE, Y-Axis Offset from +1 g, ±10 g Range,
Y-Axis Orientation = +1 g
0.5
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0108642
OFFSET CHANGE (g)
INPUT VIBRATION (
g
rms)
15429-046
Figure 46. ADXL357 VRE, Z-Axis Offset from +1 g, ±10 g Range,
Z-Axis Orientation = +1 g
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0252015105
OFFSET SHIFT (g)
INPUT VIBRATION (
g
rms)
15429-047
Figure 47. ADXL357 VRE, X-Axis Offset from −1 g, ±40 g Range,
X-Axis Orientation = −1 g
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0252015105
OFFSET SHIFT (g)
INPUT VIBRATION (
g
rms)
15429-048
Figure 48. ADXL357 VRE, Y-Axis Offset from −1 g, ±40 g Range,
Y-Axis Orientation = −1 g
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0252015105
OFFSET SHIFT (g)
INPUT VIBRATION (
g
rms)
15429-049
Figure 49. ADXL357 VRE, Z-Axis Offset from +1 g, ±40 g Range,
Z-Axis Orientation = +1 g
Data Sheet ADXL356/ADXL357
Rev. A | Page 19 of 42
–0.0010
–0.0005
0
0.0005
0.0010
0.0015
0.0020
0.0025
0.0030
0.0035
0.7
0.8
0.9
1.0
1.1
1.2
1.3
–40 –20 120100806040200
LINEAR OFFSET (V)
TEMPERATURE SENSOR OUTPUT (V)
TEMPERATURE (°C)
TEMPERATURE SENSOR OUTPUT
LINEAR OFFSET
15429-050
Figure 50. ADXL356 Temperature Sensor Output and Linear Offset vs.
Temperature
35
30
25
0
10
20
5
15
PERCENT OF POPULATION (%)
TOTAL SUPPLY CURRENT AT 25°C (µA)
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
175
173
15429-051
Figure 51. ADXL356 Total Supply Current, 3.3 V
35
30
25
0
10
20
5
15
PERCENT OF POPULATION (%)
ODR FREQUENCY (Hz)
3800
3840
3880
3920
3960
4000
4040
4080
4120
4160
4200
15429-052
Figure 52. ADXL357 Output Data Rate (Internal Clock) Histogram
–6
6
4
2
0
–2
–4
700
900
1100
1300
1500
1700
1900
2100
2600
2500
2300
–40 –20 120100806040200
LINEAR OFFSET (LSB)
TEMPERATURE SENSOR OUTPUT (LSB)
TEMPERATURE (°C)
TEMPERATURE SENSOR OUTPUT
LINEAR OFFSET
15429-053
Figure 53. ADXL357 Temperature Sensor Output and Linear Offset vs.
Temperature
30
25
0
10
20
5
15
PERCENT OF POPULATION (%)
TOTAL SUPPLY CURRENT AT 25°C (µA)
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
15429-054
Figure 54. ADXL357 Total Supply Current, 3.3 V
ADXL356/ADXL357 Data Sheet
Rev. A | Page 20 of 42
ROOT ALLAN VARIANCE (RAV) ADXL357 CHARACTERISTICS
Figure 55 to Figure 57 include data for multiple devices and multiple lots, and they were taken in the ±10 g range, unless otherwise noted.
1000
1
10
100
0.01 10001001010.1
ROOT ALLAN VARIANCE (µg)
INTEGRATION TIME (Seconds)
15429-055
Figure 55. ADXL357 RAV, X-Axis
1000
1
10
100
0.01 10001001010.1
ROOT ALLAN VARIANCE (µg)
INTEGRATION TIME (Seconds)
15429-056
Figure 56. ADXL357 RAV, Y-Axis
1000
1
10
100
0.01 10001001010.1
ROOT ALLAN VARIANCE (µg)
INTEGRATION TIME (Seconds)
15429-057
Figure 57. ADXL357 RAV, Z-Axis
Data Sheet ADXL356/ADXL357
Rev. A | Page 21 of 42
THEORY OF OPERATION
The ADXL356 is a complete 3-axis, ultralow noise and ultrastable
offset microelectromechanical systems (MEMS) accelerometer
with outputs ratiometric to the analog 1.8 V supply, V1P8ANA. The
ADXL357 adds three high resolution ADCs that use the analog
1.8 V supply as a reference to provide digital outputs insensitive
to the supply voltage. The ADXL356B is pin selectable for ±10 g
or ±20 g full scale, the ADXL356C is pin selectable for ±10 g or
±40 g full scale, and the ADXL357 is programmable for ±10 g,
±20 g, or ±40 g full scale. The ADXL357 offers both SPI and I2C
communications ports.
The micromachined, sensing elements are fully differential,
comprising the lateral x-axis and y-axis sensors and the vertical,
teeter totter z-axis sensors. The x-axis and y-axis sensors and
the z-axis sensors go through separate signal paths that minimize
offset drift and noise. The signal path is fully differential, except
for a differential to single-ended conversion at the analog
outputs of the ADXL356.
The analog accelerometer outputs of the ADXL356 are ratiometric
to V1P8ANA. Therefore, digitize them carefully. The temperature
sensor output is not ratiometric. The XOUT, YOUT, and ZOUT analog
outputs are filtered internally with an antialiasing filter. These
analog outputs also have an internal 32 kΩ series resistor that
can be used with an external capacitor to set the bandwidth of
the output.
The ADXL357 includes antialias filters before and after the high
resolution Σ-Δ ADC. User-selectable output data rates and filter
corners are provided. The temperature sensor is digitized with a
12-bit successive approximation register (SAR) ADC.
ADXL356/ADXL357 Data Sheet
Rev. A | Page 22 of 42
APPLICATIONS INFORMATION
ANALOG OUTPUT
Figure 58 shows the ADXL356 application circuit. The analog
outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V
analog voltage from the V1P8ANA pin. V1P8ANA can be powered
with an on-chip LDO regulator that is powered from VSUPPLY.
V1P8ANA can also be supplied externally by forcing VSUPPLY to VSS,
which disables the LDO regulator. Due to the ratiometric
response, the analog output requires referencing to the V1P8ANA
supply when digitizing to achieve the inherent noise and offset
performance of the ADXL356. The 0 g bias output is nominally
equal to V1P8ANA/2. The recommended option is to use the
ADXL356 with a ratiometric ADC (for example, the Analog
Devices, Inc., AD7682) and V1P8ANA providing the voltage
reference. This configuration results in self cancellation of
errors due to minor supply variations.
The ADXL356 outputs two forms of filtering: internal anti-
aliasing filtering with a cutoff frequency of approximately 1.5 kHz,
and external filtering. The external filter uses a fixed, on-chip,
32 kΩ resistance in series with each output in conjunction with
the external capacitors to implement the low-pass filter antialiasing
and noise reduction prior to the external ADC. The antialias
filter cutoff frequency must be significantly higher than the
desired signal bandwidth. If the antialias filter corner is too low,
ratiometricity can degrade where the signal attenuation is
different from the reference attenuation.
DIGITAL OUTPUT
Figure 59 shows the ADXL357 application circuit with the
recommended bypass capacitors. The communications interface
is either SPI or I2C (see the Serial Communications section for
additional information).
The ADXL357 includes an internal configurable digital band-
pass filter. Both the high-pass and low-pass poles of the filter
are adjustable, as detailed in the Filter Settings Register section
and Table 44. At power-up, the default conditions for the filters
are as follows:
High-pass filter (HPF) = dc (off)
Low-pass filter (LPF) = 1000 Hz
Output data rate = 4000 Hz
ADXL356
V
SUPPLY
V
DDIO
(±20g, ±40g)
GND ( ±10g)
V
DDIO
(MEASUREMENT)
GND (STANDBY)
V
1P8ANA
V
SS
V
1P8DIG
ADC V
REF
RANGE
ST1
ST2
TEMP
11
10
9
Z
OUT
Y
OUT
X
OUT
14
13
12
8
1
2
3
V
DDIO
V
SSIO
STBY
5
6
7
4
2.25V TO 3.6
V
1µF0.1µF
1µF0.1µF
1µF
0.1µF
1µF
0.1µF
.25V TO 3.6
15429-058
Figure 58. ADXL356 Application Circuit
ADXL357
TOP VIEW
(Not to Scale)
V
SUPPLY
V
1P8ANA
V
SS
V
1P8DIG
11
10
9
DRD
Y
INT2
INT1
14
13
12
8
1
2
3
V
DDIO
V
SSIO
RESERVED
5
6
7
4
2.25V TO 3.6V
1µF0.1µF
1µF0.1µF
1µF
0.1µF
1µF
0.1µF
2.25V TO 3.6V
SPI/I
2
C
INTERFACE
CS/SCL
SCLK/V
SSIO
MOSI/SDA
MISO/ASEL
15429-060
Figure 59. ADXL357 Application Circuit
Data Sheet ADXL356/ADXL357
Rev. A | Page 23 of 42
AXES OF ACCELERATION SENSITIVITY
Figure 60 shows the axes of acceleration sensitivity. Note that
the output voltage increases when accelerated along the
sensitive axis.
Y
Z
X
15429-059
Figure 60. Axes of Acceleration Sensitivity
POWER SEQUENCING
There are two methods for applying power to the device.
Typically, internal LDO regulators generate the 1.8 V power for
the analog and digital supplies, V1P8ANA and V1P8DIG, respectively.
Optionally, the internal LDO regulators can be disabled and
V1P8ANA and V1P8DIG are driven by external 1.8 V supplies.
When using the internal LDO regulators, connect VSUPPLY to a
voltage source between 2.25 V and 3.6 V. In this case, the
recommended power sequence is to apply power to VDDIO,
followed by applying power to VSUPPLY approximately 10 μs later.
If necessary, VSUPPLY and VDDIO can be powered from the same
voltage source, so that both are powered at the same time.
However, VSUPPLY cannot be powered before VDDIO.
To disable the internal LDO regulators, tie VSUPPLY to ground and
use external 1.8 V supplies to power V1P8ANA and V1P8DIG. V1P8ANA
and V1P8DIG must have the same voltage level. The maximum
acceptable tolerance between the external V1P8ANA and V1P8DIG
voltage levels is 50 mV. In the case of bypassing the LDO regulators,
the recommended power sequence is to apply power to VDDIO,
followed by applying power to V1P8DIG approximately 10 μs later,
and then applying power to V1P8ANA approximately 10 μs later. If
necessary, V1P8DIG and VDDIO can be powered from the same
external 1.8 V supply, which can also be tied to V1P8ANA with
proper isolation, so that all are powered at the same time. In this
case, proper decoupling and low frequency isolation are
important to maintain the noise performance of the sensor.
POWER SUPPLY DESCRIPTION
The ADXL356/ADXL357 have four different power supply
domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal
analog and digital circuitry operates at 1.8 V nominal.
VSUPPLY
VSUPPLY is 2.25 V to 3.6 V, which is the input range to the two
LDO regulators that generate the nominal 1.8 V outputs for
V1P8ANA and V1P8DIG. Connect VSUPPLY to VSS to disable the LDO
regulators, which allows driving V1P8ANA and V1P8DIG from an
external source.
V1P8ANA
All sensor and analog signal processing circuitry operates in
this domain. Offset and sensitivity of the analog output
ADXL356 are ratiometric to this supply voltage. When using
external ADCs, use V1P8ANA as the reference voltage. The
ADXL357 includes ADCs that are ratiometric to V1P8ANA,
thereby rendering the offset and sensitivity of the digital output
ADXL357 insensitive to the value of V1P8ANA. V1P8ANA can be an
input or an output as defined by the state of the VSUPPLY voltage.
V1P8DIG
V1P8DIG is the supply voltage for the internal logic circuitry. A
separate LDO regulator decouples the digital supply noise from
the analog signal path. V1P8ANA can be an input or an output as
defined by the state of the VSUPPLY voltage. If driven externally,
V1P8DIG must be the same voltage as the V1P8ANA voltage.
VDDIO
The VDDIO value determines the logic high levels. On the analog
output ADXL356, VDDIO sets the logic high level for the self test
pins, ST1 and ST2, as well as the STBY pin. On the digital output
ADXL357, VDDIO sets the logic high level for communications
interface ports, as well as the interrupt and DRDY outputs.
The LDO regulators are operational when VSUPPLY is between
2.25 V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs in
this mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA and
V1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range.
OVERRANGE PROTECTION
To avoid electrostatic capture of the proof mass when the
accelerometer is subject to input acceleration beyond its full-
scale range, all sensor drive clocks turn off for 0.5 ms. In the
±10 g range setting, the overrange protection activates for input
signals beyond approximately ±40 g (±25%), and for the ±20 g
and ±40 g range settings, the threshold corresponds to about
±80 g (±25%).
When overrange protection occurs, the XOUT, YOUT, and ZOUT pins
on the ADXL356 begin to drive to midscale, whereas the
ADXL357 floats toward zero, and the first in, first out (FIFO)
buffer begins filling with this data.
SELF TEST
The ADXL356 and ADXL357 incorporate a self test feature
that effectively tests the mechanical and electronic system.
Enabling self test stimulates the sensor electrostatically to
produce an output corresponding to the test signal applied as
well as the mechanical force exerted. Only the z-axis response is
specified to validate device functionality.
In the ADXL356, drive the ST1 pin to VDDIO to invoke self test
mode. Then, by driving the ST2 pin to VDDIO, the ADXL356
applies an electrostatic force to the mechanical sensor and
induces a change in output in response to the force. The self test
delta (or response) is the difference in output voltage in the
z-axis when ST2 is high vs. ST2 is low, while ST1 is asserted.
ADXL356/ADXL357 Data Sheet
Rev. A | Page 24 of 42
After the self test measurement is complete, bring both pins low
to resume normal operation.
The self test operation is similar in the ADXL357, except ST1
and ST2 can be accessed through the SELF_TEST register
(Register 0x2E).
The self test feature rejects externally applied acceleration and
only responds to the self test force, which allows an accurate
measurement of the self test, even in the presence of external
mechanical noise. When the self test feature is not used, both
ST1 and ST2 must be kept low.
FILTER
The ADXL356/ADXL357 use an analog, low-pass, antialiasing
filter to reduce out of band noise and to limit bandwidth. The
ADXL357 provides further digital filtering options to maintain
optimal noise performance at various ODRs.
The analog, low-pass antialiasing filter in the ADXL356/
ADXL357 provides a fixed 3 dB bandwidth of approximately
1.5 kHz, the frequency at which the voltage output response is
attenuated by approximately 30%. The shape of the filter
response in the frequency domain is that of a sinc filter. While
the analog antialiasing filter attenuates the output response
around and above its cutoff frequency, the MEMS sensor has a
resonance at 5.5 kHz and mechanically amplifies the output
response at around 2 kHz and above. These competing trends
are apparent in the overall transfer function of the ADXL356, as
shown in Figure 8 to Figure 10. Therefore, the overall −3 dB
bandwidth of the ADXL356 is 2.4 kHz, and the overall
bandwidth with ±4 dB flatness is about 4.4 kHz.
The ADXL356 x-axis, y-axis, and z-axis analog outputs include
an amplifier followed by a series 32 kΩ resistor, and output to
the XOUT, the YOUT, and the ZOUT pins, respectively.
The ADXL357 provides an internal 20-bit, Σ-Δ ADC to digitize
the filtered analog signal. Additional digital filtering (beyond the
analog, low-pass, antialiasing filter) consists of a low-pass digital
decimation filter and a bypassable high-pass filter that supports
output data rates between 4 kHz and 3.906 Hz. The decimation
filter consists of two stages. The first stage is fixed decimation
with a 4 kHz ODR and a low-pass filter cutoff (3 dB) at about
1 kHz. A variable second stage decimation filter is used for the
2 kHz output data rate and below (it is bypassed for 4 kHz ODR).
Figure 61 shows the low-pass filter response with a 1 kHz corner
(4 kHz ODR) for the ADXL357. Note that Figure 61 does not
include the fixed frequency analog, low-pass, antialiasing filter
with a fixed 3 dB bandwidth of approximately 1.5 kHz.
The ADXL357 pass band of the signal path relates to the
combined filter responses, including the analog filter previously
described, and the digital decimation filter/ODR setting. Table 10
shows the delay associated with the decimation filter for each
setting and provides the attenuation at the ODR/4 corner.
–70
–60
–50
–40
–30
–20
–10
0
110100 10k1k
DIGITAL LPF RESPONSE (dB)
INPUT FREQUENCY (Hz)
15429-061
Figure 61. ADXL357 Digital LPF Response for 4 kHz ODR
The ADXL357 also includes an optional digital high-pass filter
with a programmable corner frequency. By default, the high-
pass filter is disabled. The high-pass corner frequency, where
the output is attenuated by 3 dB, is related to the ODR, and the
HPF_CORNER setting in the filter register (Register 0x28,
Bits[6:4]). Table 11 shows the HPF_CORNER response. Figure 62
and Figure 63 show the simulated high-pass filter pass-band
and delay responses for a 9.88 Hz cutoff.
AMPLITUDE REL
A
TIVE TO FULL SCALE (dB)
0
–3
–10
–20
–30
–40
–50
0 9.8801 100
FREQUENCY (Hz)
15429-062
Figure 62. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an
HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])
DEL
A
Y (ODR CYCLES)
40
32.2122
30
20
10
1
00 9.8801
100
FREQUENCY (Hz)
15429-063
Figure 63. High-Pass Filter Delay Response for a 4 kHz ODR and an
HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])
Data Sheet ADXL356/ADXL357
Rev. A | Page 25 of 42
The ADXL357 also includes an interpolation filter after the
decimation filters that produces oversampled/upconverted data
and provides an external synchronization option. See the Data
Synchronization section for more details. Table 12 shows the
delay and attenuation relative to the programmed ODR.
Group delay is the digital filter delay from the input to the ADC
until data is available at the interface (see the Filter section).
This delay is the largest component of the total delay from
sensor to serial interface.
Table 10. Digital Filter Group Delay and Profile
Delay Attenuation
Programmed ODR (Hz) ODR (Cycles) Time (ms) Decimator at ODR/4 (dB) Full Path at ODR/4 (dB)
4000 2.52 0.63 −3.44 −3.63
4000/2 = 2000 2.00 1.00 −2.21 −2.26
4000/4 = 1000 1.78 1.78 −1.92 −1.93
4000/8 = 500 1.63 3.26 −1.83 −1.83
4000/16 = 250 1.57 6.27 −1.83 −1.83
4000/32 = 125 1.54 12.34 −1.83 −1.83
4000/64 = 62.5 1.51 24.18 −1.83 −1.83
4000/128 ≈ 31 1.49 47.59 −1.83 −1.83
4000/256 ≈ 16 1.50 96.25 −1.83 −1.83
4000/512 ≈ 8 1.50 189.58 −1.83 −1.83
4000/1024 ≈ 4 1.50 384.31 −1.83 −1.83
Table 11. Digital High-Pass Filter Response
HPF_CORNER Register Setting
(Register 0x28, Bits[6:4]) HPF_CORNER Frequency, −3 dB Point Relative to ODR Setting −3 dB at 4 kHz ODR (Hz)
000 Not applicable, no high-pass filter enabled Off
001 24.7 × 10−4 × ODR 9.88
010 6.2084 × 10−4 × ODR 2.48
011 1.5545 × 10−4 × ODR 0.62
100 0.3862 × 10−4 × ODR 0.1545
101 0.0954 × 10−4 × ODR 0.03816
110 0.0238 × 10−4 × ODR 0.00952
Table 12. Combined Digital Interpolation Filter and Decimation Filter Response
Interpolator Data Rate Resolution
Relative to 64 × ODR (Hz)
Combined Interpolator/
Decimator Delay (ODR Cycles)
Combined Interpolator/
Decimator Delay (ms)
Combined Interpolator/Decimator
Output Attenuation at ODR/4 (dB)
64 × 4000 = 256,000 3.51661 0.88 −6.18
64 × 2000 = 128,000 3.0126 1.51 −4.93
64 × 1000 = 64,000 2.752 2.75 −4.66
64 × 500 = 32,000 2.6346 5.27 −4.58
64 × 250 = 16,000 2.5773 10.31 −4.55
64 × 125 = 8000 2.5473 20.38 −4.55
64 × 62.5 = 4000 2.53257 40.52 −4.55
64 × 31.25 = 2000 2.52452 80.78 −4.55
64 × 15.625 = 1000 2.52045 161.31 −4.55
64 × 7.8125 = 500 2.5194 322.48 −4.55
64 × 3.90625 = 250 2.51714 644.39 −4.55
ADXL356/ADXL357 Data Sheet
Rev. A | Page 26 of 42
SERIAL COMMUNICATIONS
The 4-wire serial interface communicates in either the SPI or
I2C protocol. The interface affectively autodetects the format
being used, requiring no configuration control to select the format.
The ADXL357 multifunction pins are referred to by a single
function of the pin, for example, CS, when only that function is
relevant.
SPI PROTOCOL
Wire the ADXL357 for SPI communication as shown in the
connection diagram in Figure 64. The SPI protocol timing is
shown in Figure 66 to Figure 69. The timing scheme follows the
clock polarity (CPOL) = 0 and clock phase (CPHA) = 0. The
SPI clock speed ranges from 100 kHz to 10 MHz.
PROCESSOR
CS
MOSI
MISO
SCLK
SS
MOSI
MISO
SCLK
ADXL357
15429-064
Figure 64. 4-Wire SPI Connection
SPI BUS SHARING
Use a gated buffer on the SCLK line for the ADXL357 device to
achieve the ultralow noise performance and possibly offset shift
when the ADXL357 must share a SPI bus with another slave
device. This gated SCLK allows the clock signal through only
when the chip select (CS) line is low. See Figure 65 for the
example circuit that provides this type of protection.
CS
SCLK
TO SPI SLAVE 2
SS1
SS2
SCLK
ADXL357
15429-165
PROCESSOR
SN74LVC1G125
Figure 65. SCLK Protection Example
RWA6 A5 A4 A3 A2 A1 A0
12345678910111213141516
CS
SCLK
MOSI
MISO D7 D6 D5 D4 D3 D2 D1 D0
15429-065
Figure 66. SPI Timing Diagram—Single-Byte Read
D7 D6 D5 D4 D3 D2 D1 D0
12345678910 11 12 13 14 15 16
SCLK
MOSI
MISO
RWA6 A5 A4 A3 A2 A1 A0
CS
15429-066
Figure 67. SPI Timing Diagram—Single-Byte Write
10 11 12 13 14 15 16 17123456789
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0D0 D7
BYTE 1 BYTE n
RWA6 A5 A4 A3 A2 A1 A0
SCLK
MOSI
MISO
CS
15429-067
Figure 68. SPI Timing Diagram—Multibyte Read
10 11 12 13 14 15 16 17
BYTE 1 BYTE n
123456789
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0D0 D7RWA6 A5 A4 A3 A2 A1 A0
SCLK
MOSI
MISO
CS
15429-068
Figure 69. SPI Timing Diagram—Multibyte Write
Data Sheet ADXL356/ADXL357
Rev. A | Page 27 of 42
I2C PROTOCOL
The ADXL357 supports point to point I2C communication.
However, when sharing an SDA bus, the ADXL357 may prevent
communication with other devices on that bus. If at any point,
even when the ADXL357 is not being addressed, the 0x3A and
0x3B bytes (when the ADXL357 device address is set to 0x1D),
or the 0xA6 and 0xA7 bytes (when the ADXL357 device address
is set to 0x53) are transmitted on the SDA bus, the ADXL357
responds with an acknowledge bit and pulls the SDA line down.
For example, this response can occur when reading or writing
the data bytes (0x3A/0x3B or 0xA6/0xA7) to another sensor on
the bus. When the ADXL357 pulls the SDA line down,
communication with other devices on the bus may be
interrupted. To resolve this interruption, the ADXL357 must be
connected to a separate SDA bus, or the CS/SCL pin must be
switched high when communication with the ADXL357 is not
desired (it is normally grounded).
The ADXL357 supports standard (100 kHz), fast (up to 1 MHz)
and high speed (up to 3.4 MHz) data transfer modes when the
bus parameters in Table 4 are met. There is no minimum SCL
frequency, with the exception that, when reading data, the clock
must be fast enough to read an entire sample set before new data
overwrites it. Single-byte or multiple byte reads/writes are
supported. With the MISO/ASEL pin low, the I2C address for
the device is 0x1D and an alternate I2C address of 0x53 can be
chosen by pulling the MISO/ASEL pin high.
There are no internal pull-up or pull-down resistors for any unused
pins. Therefore, there is no known state or default state for the pins
if left floating or unconnected. SCLK/VSSIO must be connected
to ground when communicating to the ADXL357 using I2C.
Due to communication speed limitations, the maximum output
data rate when using the 400 kHz I2C mode is 800 Hz, and it
scales linearly with a change in the I2C communication speed.
For example, using I2C at 100 kHz limits the maximum ODR to
200 Hz. Operation at an output data rate above the recommended
maximum may result in an undesirable effect on the acceleration
data, including missing samples or additional noise.
Figure 70 to Figure 72 detail the I2C protocol timing. The I2C
interface can be used on most buses operating in I2C standard
mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz),
and high speed mode (3.4 MHz). The ADXL357 I2C device ID
is as follows:
MISO/ASEL pin = 0, device address = 0x1D
MISO/ASEL pin = 1, device address = 0x53
If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed
VDDIO by more than 0.3 V. External pull-up resistors, RP, are
necessary for proper I2C operation.
READING ACCELERATION OR TEMPERATURE
DATA FROM THE INTERFACE
Acceleration data is left justified and has a register address order of
most significant data to least significant data, which allows the
user to use multibyte transfers and to take only as much data as
required—8 bits, 16 bits, or 20 bits, plus the marker. Temperature
data is 12 bits unsigned, right justified. The ADXL357 temperature
value is split over two bytes, but is not double buffered, meaning
the value can update between readings of the two registers. The
data in XDATA, YDATA, and ZDATA is always the most recent
available. It is not guaranteed that XDATA, YDATA, and ZDATA
form a set corresponding to one sample point in time. The routine
used to retrieve the data from the device controls this data set
continuity. If data transfers are initiated when the DATA_RDY bit
goes high and completes in a time approximately equal to 1/ODR,
XDATA, YDATA, and ZDATA apply to the same data set.
For multibyte read or write transactions through either serial
interface, the internal register address auto-increments. When
the top of the register address range, 0x3FF, is reached, the auto-
increment stops and does not wrap back to Address 0x00.
The address auto-increment function disables when the FIFO
address is used, so that data can be read continuously from the
FIFO as a multibyte transaction. In cases where the starting
address of a multibyte transaction is less than the FIFO address,
the address auto-increments until reaching the FIFO address,
and then stops at the FIFO address.
10 11 12 13 14 15 16 17 18 19 28 2920 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37123456789
A60 A5A4A3A2A1A0 D60 D5D4D3D2D1D0 AKAKAK A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0 RW
RW
SCL
START REPEAT
START
DEVICE ADDRESS
SINGLE BYTE READ
REGISTER ADDRESS DEVICE ADDRESS DATA BYTE STOP
SDA AK
INDICATE SDA IS
CONTROLLED BY ADXL357
15429-069
Figure 70. I2C Timing Diagram—Single-Byte Read
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27123456789
START
DEVICE ADDRESS REGISTER ADDRESS DATA BYTE
STOP
SCL
SDA
A60 A5A4A3A2A1A0AK D6D7 D5 D4 D3 D2 D1 D0 AK
A6 A5 A4 A3 A2 A1 A0 RW AK
15429-070
Figure 71. I2C Timing Diagram—Single-Byte Write
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19123456789
SCL
START
DEVICE ADDRESS REGISTER ADDRESS DATA BYTE 1 DATA BYTE n
SD
A
A60 A5A4A3A2A1A0AK D6D7 D5 D4 D3 D2 D1 D0 D7AK D0 AK D6D7 D5 D4 D3 D2 D1 D0 AK
A6 A5 A4 A3 A2 A1 A0 RW AK
15429-071
Figure 72. I2C Timing Diagram—Multibyte Write
ADXL356/ADXL357 Data Sheet
Rev. A | Page 28 of 42
FIFO
The FIFO operates in a stream mode. That is, when the FIFO
overruns, new data overwrites the oldest data in the FIFO. A
read from the FIFO address guarantees that the three bytes
associated with the acceleration measurement on an axis all
pertain to the same measurement. The FIFO never overflows,
and the data is always taken out in sets (multiples of three data
points).
There are 96 21-bit locations in the FIFO. Each location
contains 20 bits of data and a marker bit for the x-axis data. A
single-byte read from the FIFO address pops one location from
the FIFO. A multibyte read to the FIFO location pops the FIFO
on the read of the first byte and every third byte read thereafter.
Figure 73 shows the organization of the data in the FIFO. The
acceleration data is twos complement, 20-bit data. The FIFO
control logic inserts the two virtual bits (0b00) between the data
bits and the empty indicator bit. Bit 1 indicates that an attempt
was made to read an empty FIFO, and that the data is not valid
acceleration data. Bit 0 is a marker bit to identify the x-axis,
which allows a user to verify that the FIFO data was correctly
read. An acceleration data point for a given axis occupies one
FIFO location. The read pointer, RD_PTR, points to the oldest
stored data that was not read already from the interface (see
Figure 73). There are no physical x-acceleration, y-acceleration, or
z-acceleration data registers. The data read from data registers
(Register 0x08 to Register 0x10) also comes directly from the most
recent data set in the FIFO, which is pointed to by the z pointer,
Z_PTR (see Figure 73).
1
0
0
1
0
Z17 Z16 Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0
Z3 Z2 Z1 Z0
Y3 Y2 Y1 Y0
X3 X2 X1 X0
X3 X2 X1 X0
Y3 Y2 Y1 Y0
0
DATA SET. SAMPLE POINT
IS THE SAME ACROSS
A SINGLE X-AXIS, Y-AXIS,
AND Z-AXIS DATA SET.
RD_PTR
Z_PTR
Z_PTR – 1
Z_PTR – 2
X-AXIS MARKER
VIRTUAL BITS
(NOT ALLOCATED IN THE FIFO)
ACCELERATION DATA
ASCENDING SPI ADDRESSES
Z19 Z18
Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4Y19 Y18
Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4Y19 Y18
X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4X19 X18
X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4X19 X18
Z17 Z16 Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4Z19 Z18
1Z_PTR + 1 00000000 00000000 0000001
0
0
0
0
0
0
EMPTY INDICATOR
ASCENDING FIFO ADDRESSES
ASCENDING
SPI ADDRESSES
15429-072
Figure 73. FIFO Data Organization
Data Sheet ADXL356/ADXL357
Rev. A | Page 29 of 42
INTERRUPTS
The status register (Register 0x04) contains five individual bits,
four of which can be mapped to either the INT1 pin, the INT2 pin,
or both. The polarity of the interrupt, active high or active low,
is also selectable via the INT_POL bit in the range (Register 0x2C)
register. In general, the status register clears when read, but this
is not the case if the condition that caused the interrupt persists
after the read of the register. The definition of persist varies
slightly in each case, but it is described in the DATA_RDY,
DRDY Pin, FIFO_FULL, FIFO_OVR, and Activity sections.
The DRDY pin is similar to an interrupt pins (INTx) but clears
differently. This case is also described.
DATA_RDY
The DATA_RDY bit is set when new acceleration data is
available to the interface and clears on a read of the status
register. This bit is not set again until acceleration data that is
newer than the status register read is available.
Special logic on the clearing of the DATA_RDY bit covers the
corner case where new data arrives during the read of the status
register. In this case, the data ready condition may be missed
completely. This logic results in a delay of the clearing of
DATA_RDY of up to four 512 kHz cycles.
DRDY PIN
The DRDY pin is not a status register bit. DRDY instead
behaves similar to an unmaskable interrupt. DRDY is set when
new acceleration data is available to the interface. DRDY clears
on a read of the FIFO, on a read of XDATA, YDATA, or
ZDATA, or by an autoclear function that occurs approximately
halfway between output acceleration data sets.
DRDY is always active high. The INT_POL bit does not affect
DRDY. In external synchronization modes (EXT_SYNC = 01,
EXT_SYNC = 10), the first few DRDY pulses after initial
synchronization can be lost or corrupted. The length of this
potential corruption is equal to or less than the group delay.
Therefore, the samples within one group delay is lost or
corrupted after the first synchronization signal. Depending on
the decimation setting and interpolation setting (see Table 12),
between one and three samples after the first synchronization
pulse is lost, provided that all the restrictions set in the External
Synchronization and Interpolation section is met.
FIFO_FULL
The FIFO_FULL bit is set when the entries in the FIFO are
equal to the setting of the FIFO_SAMPLES bits. FIFO_FULL
clears as follows:
If the number of entries in the FIFO is less than the
number of samples indicated by the FIFO_SAMPLES bits,
which is only the case if sufficient data is read from the
FIFO.
On a read of the status register, but only when the entries
in the FIFO are less than the FIFO_SAMPLES bits.
FIFO_OVR
The FIFO_OVR bit is set when the FIFO is so far overrange that
data is lost. The specified size of the FIFO is 96 locations. The
FIFO_OVR bit is set only when there is an attempt to write past
this 96-location limit.
A read of the status register clears FIFO_OVR. FIFO_OVR is
not set again until data is lost subsequent to this status register
read.
ACTIVITY
The activity bit (Register 0x04, Bit 3) is set when the measured
acceleration on any axis is above the value set in the ACT_
THRESH bits for ACT_COUNT consecutive measurements.
An overthreshold condition can shift from one axis to another
on successive measurements and is still counted toward the
consecutive ACT_COUNT count.
A read of the status register clears the activity bit (Register 0x04,
Bit 3), but the bit sets again at the end of the next measurement if
the activity bit (Register 0x04, Bit 3) conditions are still satisfied.
NVM_BUSY
The NVM_BUSY bit indicates that the nonvolatile memory
(NVM) controller is busy and, therefore, the NVM cannot be
accessed to read or write. The interrupt functionality requires
the NVM_BUSY bit to be cleared to function.
A status register read that occurs after the NVM controller is no
longer busy clears NVM_BUSY.
EXTERNAL SYNCHRONIZATION AND
INTERPOLATION
There are four possible synchronization options for the ADXL357,
three of which are shown in Figure 74 to Figure 76. For clarity, the
clock frequencies and delays are drawn to scale. The labels in
Figure 74 to Figure 76 are defined as follows:
Internal ODR is the alignment of the decimated output
data based on the internal clock.
ADC modulator clock shows the internal master clock rate.
DRDY is an output indicator signaling a sample is ready.
The four possible synchronization options are as follows:
No external synchronization (internal clocks used)
Synchronization with an external synchronization signal
and internal clock, interpolation filter enabled
Synchronization with external synchronization and clock
signals, no interpolation filter
Synchronization with external synchronization and clock
signals, interpolation filter enabled
ADXL356/ADXL357 Data Sheet
Rev. A | Page 30 of 42
EXT_SYNC = 00, EXT_CLK = 0—No External
Synchronization or Interpolation
This is the default mode of operation for the device. The sensor
runs on an internal ODR and an internal clock that is generated by
an internal oscillator. The internal ODR serves as the synchroniza-
tion master, which generates the data. Register 0x28 is used to
program the ODR. No external signals are required, and this
mode is used typically when the external processor retrieves
data from the device asynchronously and absolute synchronization
to an external source is not required.
The device outputs a DRDY (active high) to signal that a new
sample is available, and data is retrieved from the real-time
registers or the FIFO. The group delay is based on the
decimation setting, as shown in Table 10. This mode is shown
in Figure 74.
EXT_SYNC = 10, EXT_CLK = 0—External Synchronization
with Interpolation
Synchronization using interpolation filters and an external ODR
clock is commonly used when the external processor can
provide a synchronization signal, SYNC, that is asynchronous
to the internal clock at the desired ODR. In this case, an
interpolation filter provides additional time resolution of 64
times the programmed ODR (see Table 12). Synchronization
with the interpolation filter enabled (EXT_SYNC = 10) allows
the sensor to operate on an internal clock and output data most
closely associated with the SYNC rising edge.
The advantage of this mode is that data is available at an arbitrary
user defined SYNC sample rate and is asynchronous to the internal
clock oscillator. The maximum sample rate cannot exceed
4000 SPS. The disadvantage of this mode is that the group delay
is increased, with increased attenuation at the band edge.
Additionally, because there is a limit to the time resolution,
there is some distortion related to the mismatch of the external
synchronization relative to the internal clock oscillator. This
mismatch degrades spectral performance. The group delay is
based on the decimation setting and interpolation setting (see
Table 12). Figure 75 schematically shows the timings in this
mode, and Table 13 shows the delay between the SYNC signal
(input) to DRDY (output).
Table 13. EXT_SYNC = 10, DRDY Delay
ODR_LPF SYNC to DRDY Delay (Oscillator Cycles)
0x0 8
0x1 10
0x2 14
0x3 22
0x4 38
0x5 70
0x6 134
0x7 262
0x8 1031
0x9 2054
0xA 4102
EXT_SYNC = 01, EXT_CLK = 1—External Synchronization
and External Clock, No Interpolation Filter
When configured for EXT_SYNC = 01 and EXT_CLK = 1 (sync
register, see Table 47), the user must supply an external clock
(enabled via the EXT_CLK bit) at 1.024 MHz on the INT2 pin
(Pin 13) and an external synchronization signal, SYNC, on the
DRDY pin (Pin 14), as shown in Table 14. If configured in this
mode and an external clock is not supplied, the device does not
process any data and reading from the output results in null
values. This mode is schematically shown in Figure 76.
Special restrictions when using this mode include the following:
The external clock frequency on INT2 (Pin 13, see Table 14)
must be 1.024 MHz.
The pulse width of the SYNC signal must be at least
3.91 μs, which represents four cycles of the external clock
(4 ÷ 1.024 MHz = ~3.91 μs).
The phase of SYNC must meet an approximate 25 ns setup
time to the external clock rising edge.
When using the EXT_SYNC mode and without providing the
SYNC signal, the device runs on its own internal ODR. Similarly,
after external synchronization, the device continues to run
synchronized to the last SYNC pulse it received, which means that
EXT_SYNC = 01 mode can be used with only a single
synchronization pulse.
For more information about the lost sample in Figure 76, see the
DRDY Pin section.
EXT_SYNC = 10, EXT_CLK = 1—External Synchronization
and External Clock, with Interpolation Filter
This mode can be used to run the device on an external clock
and synchronization with an arbitrary sample rate set by the
SYNC signal rate. Conditions for external SYNC and external
clock signals is the same as EXT_SYNC = 01, EXT_CLK = 1
mode. The interpolation filter provides a frequency resolution
related to the ODR (see Table 12). In this case, the data
provided corresponds to the external SYNC signal, which can
be greater than the set ODR and less than 4000 SPS, but the
output pass band remains the same it was prior to the
interpolation filter.
Data Sheet ADXL356/ADXL357
Rev. A | Page 31 of 42
Table 14. Multiplexing of INT2 and DRDY
Register or Bit Fields Pins
EXT_CLK
EXT_SYNC,
Bits[1:0]
INT_MAP,
Bits[7:4] INT2 (Pin 13) DRDY (Pin 14) Comments
0 00 0000 Low DRDY Synchronization is to the internal clocks, and there is no
external clock synchronization.
0 00 Not 0000 INT2 DRDY
1 00 0000 EXT_CLK DRDY
1 00 Not 00001 EXT_CLK DRDY
0 01 0000 DRDY2 SYNC These options reset the digital filters on every
synchronization pulse and are not recommended.
0 013 Not 0000 INT2 SYNC
1 013 0000 EXT_CLK SYNC External synchronization, no interpolation filter, and
DRDY (active high) signals that data is ready. Data
represents a sample point group delay earlier in time.
1 013 Not 00001 EXT_CLK SYNC
0 10 0000 DRDY2 SYNC External synchronization, interpolation filter, and DRDY
(active high) signals that data is ready. Data sample
group delay earlier in time.
0 103 Not 0000 INT2 SYNC
1 103 0000 EXT_CLK SYNC
1 103 Not 0000 EXT_CLK SYNC
1 No INT2, even though it is enabled.
2 DRDY routing through the INT_MAP register takes precedence over the default, per Table 14.
3 No DRDY.
INTERNAL ODR
GROUP DE
L
A
Y
(FIXED RELATIVE TO DRDY)
SAMPLE POINT
ADC MODULATOR CLOCK
DRDY
15429-073
Figure 74. EXT_SYNC = 00, EXT_CLK = 0, Internal Synchronization, Internal Clock
INTERNAL ODR
INTERPOLATOR
64× ODR
DRDY
GROUP DEL
A
Y
(FIXED RELATIVE TO SYNC) INTERFACE SYNCHRONIZATION DELAYSAMPLE POINT
SYNC
110% ODR
15429-074
Figure 75. EXT_SYNC = 10, EXT_CLK = 0, External Synchronization, Internal Clock, Interpolation Filter
INTERNAL ODR
DRDY
GROUP DELAY
(FIXED RELATIVE TO SYNC)
SAMPLE POINT
LOST SAMPLE
SYNCHRONIZE
EXTERNAL CLOCK
1.024MHz
SYNC
15429-075
Figure 76. EXT_SYNC = 01, EXT_CLK = 1, External Synchronization, External Clock, No Interpolation Filter
ADXL356/ADXL357 Data Sheet
Rev. A | Page 32 of 42
ADXL357 REGISTER MAP
Note that while configuring the ADXL357 in an application, all configuration registers must be programmed before enabling measurement
mode in the POWER_CTL register. When the ADXL357 is in measurement mode, only the following configurations can change: the
HPF_CORNER bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register.
Table 15. ADXL357 Register Map
Hex.
Addr. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x00 DEVID_AD DEVID_AD 0xAD R
0x01 DEVID_MST DEVID_MST 0x1D R
0x02 PARTID PARTID 0xED R
0x03 REVID REVID 0x01 R
0x04 Status Reserved NVM_
BUSY
Activity FIFO_OVR FIFO_FULL DATA_RDY 0x00 R
0x05 FIFO_ENTRIES Reserved FIFO_ENTRIES 0x00 R
0x06 TEMP2 Reserved Temperature, Bits[11:8] 0x00 R
0x07 TEMP1 Temperature, Bits[7:0] 0x00 R
0x08 XDATA3 XDATA, Bits[19:12] 0x00 R
0x09 XDATA2 XDATA, Bits[11:4] 0x00 R
0x0A XDATA1 XDATA, Bits[3:0] Reserved 0x00 R
0x0B YDATA3 YDATA, Bits[19:12] 0x00 R
0x0C YDATA2 YDATA, Bits[11:4] 0x00 R
0x0D YDATA1 YDATA, Bits[3:0] Reserved 0x00 R
0x0E ZDATA3 ZDATA, Bits[19:12] 0x00 R
0x0F ZDATA2 ZDATA, Bits[11:4] 0x00 R
0x10 ZDATA1 ZDATA, Bits[3:0] Reserved 0x00 R
0x11 FIFO_DATA FIFO_DATA 0x00 R
0x1E OFFSET_X_H OFFSET_X, Bits[15:8] 0x00 R/W
0x1F OFFSET_X_L OFFSET_X, Bits[7:0] 0x00 R/W
0x20 OFFSET_Y_H OFFSET_Y, Bits[15:8] 0x00 R/W
0x21 OFFSET_Y_L OFFSET_Y, Bits[7:0] 0x00 R/W
0x22 OFFSET_Z_H OFFSET_Z, Bits[15:8] 0x00 R/W
0x23 OFFSET_Z_L OFFSET_Z, Bits[7:0] 0x00 R/W
0x24 ACT_EN Reserved ACT_Z ACT_Y ACT_X 0x00 R/W
0x25 ACT_THRESH_H ACT_THRESH, Bits[15:8] 0x00 R/W
0x26 ACT_THRESH_L ACT_THRESH, Bits[7:0] 0x00 R/W
0x27 ACT_COUNT ACT_COUNT 0x01 R/W
0x28 Filter Reserved HPF_CORNER ODR_LPF 0x00 R/W
0x29 FIFO_SAMPLES Reserved FIFO_SAMPLES 0x60 R/W
0x2A INT_MAP ACT_EN2 OVR_EN2 FULL_EN2 RDY_EN2 ACT_EN1 OVR_EN1 FULL_EN1 RDY_EN1 0x00 R/W
0x2B Sync Reserved EXT_CLK EXT_SYNC 0x00 R/W
0x2C Range I2C_HS INT_POL Reserved Range 0x81 R/W
0x2D POWER_CTL Reserved DRDY_OFF TEMP_OFF Standby 0x01 R/W
0x2E SELF_TEST Reserved ST2 ST1 0x00 R/W
0x2F Reset Reset 0x00 W
Data Sheet ADXL356/ADXL357
Rev. A | Page 33 of 42
REGISTER DEFINITIONS
This section describes the functions of the ADXL357 registers. The ADXL357 powers up with the default register values, as shown in the
reset column of Table 15.
ANALOG DEVICES ID REGISTER
This register contains the Analog Devices ID, 0xAD.
Address: 0x00, Reset: 0xAD, Name: DEVID_AD
Table 16. Bit Descriptions for DEVID_AD
Bits Bit Name Settings Description Reset Access
[7:0] DEVID_AD Analog Devices ID 0xAD R
ANALOG DEVICES MEMS ID REGISTER
This register contains the Analog Devices MEMS ID, 0x1D.
Address: 0x01, Reset: 0x1D, Name: DEVID_MST
Table 17. Bit Descriptions for DEVID_MST
Bits Bit Name Settings Description Reset Access
[7:0] DEVID_MST Analog Devices MEMS ID 0x1D R
DEVICE ID REGISTER
This register contains the device ID, 0xED (355 octal).
Address: 0x02, Reset: 0xED, Name: PARTID
Table 18. Bit Descriptions for PARTID
Bits Bit Name Settings Description Reset Access
[7:0] PARTID Device ID (355 octal) 0xED R
PRODUCT REVISION ID REGISTER
This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision.
Address: 0x03, Reset: 0x01, Name: REVID
Table 19. Bit Descriptions for REVID
Bits Bit Name Settings Description Reset Access
[7:0] REVID Mask revision 0x01 R
STATUS REGISTER
This register includes bits that describe the various conditions of the ADXL357.
Address: 0x04, Reset: 0x00, Name: Status
Table 20. Bit Descriptions for Status
Bits Bit Name Settings Description Reset Access
[7:5] Reserved Reserved. 0x0 R
4 NVM_BUSY NVM controller is busy with a refresh, programming, or a built in self test (BIST). 0x0 R
3 Activity Activity, as defined in the ACT_THRESH_x and ACT_COUNT registers, is detected. 0x0 R
2 FIFO_OVR FIFO has overrun, and the oldest data is lost. 0x0 R
1 FIFO_FULL FIFO watermark is reached. 0x0 R
0 DATA_RDY A complete x-axis, y-axis, and z-axis measurement was made and results can be read. 0x0 R
ADXL356/ADXL357 Data Sheet
Rev. A | Page 34 of 42
FIFO ENTRIES REGISTER
This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96.
Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES
Table 21. Bit Descriptions for FIFO_ENTRIES
Bits Bit Name Settings Description Reset Access
7 Reserved Reserved 0x0 R
[6:0] FIFO_ENTRIES Number of data samples stored in the FIFO 0x0 R
TEMPERATURE DATA REGISTERS
These two registers contain the uncalibrated temperature data. The nominal intercept is 1885 LSB at 25°C and the nominal slope is
−9.05 LSB/°C. TEMP2 contains the four most significant bits, and TEMP1 contains the eight least significant bits of the 12-bit value. The
ADXL357 temperature value is not double buffered, meaning the value can update between reading of the two registers.
Address: 0x06, Reset: 0x00, Name: TEMP2
Table 22. Bit Descriptions for TEMP2
Bits Bit Name Settings Description Reset Access
[7:4] Reserved Reserved
[3:0] Temperature, Bits[11:8] Uncalibrated temperature data 0x0 R
Address: 0x07, Reset: 0x00, Name: TEMP1
Table 23. Bit Descriptions for TEMP1
Bits Bit Name Settings Description Reset Access
[7:0] Temperature, Bits[7:0] Uncalibrated temperature data 0x00 R
X-AXIS DATA REGISTERS
These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement.
Address: 0x08, Reset: 0x00, Name: XDATA3
Table 24. Bit Descriptions for XDATA3
Bits Bit Name Settings Description Reset Access
[7:0] XDATA, Bits[19:12] X-axis data 0x00 R
Address: 0x09, Reset: 0x00, Name: XDATA2
Table 25. Bit Descriptions for XDATA2
Bits Bit Name Settings Description Reset Access
[7:0] XDATA, Bits[11:4] X-axis data 0x00 R
Address: 0x0A, Reset: 0x00, Name: XDATA1
Table 26. Bit Descriptions for XDATA1
Bits Bit Name Settings Description Reset Access
[7:4] XDATA, Bits[3:0] X-axis data 0x0 R
[3:0] Reserved Reserved 0x0 R
Data Sheet ADXL356/ADXL357
Rev. A | Page 35 of 42
Y-AXIS DATA REGISTERS
These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement.
Address: 0x0B, Reset: 0x00, Name: YDATA3
Table 27. Bit Descriptions for YDATA3
Bits Bit Name Settings Description Reset Access
[7:0] YDATA, Bits[19:12] Y-axis data 0x00 R
Address: 0x0C, Reset: 0x00, Name: YDATA2
Table 28. Bit Descriptions for YDATA2
Bits Bit Name Settings Description Reset Access
[7:0] YDATA, Bits[11:4] Y-axis data 0x00 R
Address: 0x0D, Reset: 0x00, Name: YDATA1
Table 29. Bit Descriptions for YDATA1
Bits Bit Name Settings Description Reset Access
[7:4] YDATA, Bits[3:0] Y-axis data 0x0 R
[3:0] Reserved Reserved 0x0 R
Z-AXIS DATA REGISTERS
These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement.
Address: 0x0E, Reset: 0x00, Name: ZDATA3
Table 30. Bit Descriptions for ZDATA3
Bits Bit Name Settings Description Reset Access
[7:0] ZDATA, Bits[19:12] Z-axis data 0x00 R
Address: 0x0F, Reset: 0x00, Name: ZDATA2
Table 31. Bit Descriptions for ZDATA2
Bits Bit Name Settings Description Reset Access
[7:0] ZDATA, Bits[11:4] Z-axis data 0x00 R
Address: 0x10, Reset: 0x00, Name: ZDATA1
Table 32. Bit Descriptions for ZDATA1
Bits Bit Name Settings Description Reset Access
[7:4] ZDATA, Bits[3:0] Z-axis data 0x0 R
[3:0] Reserved Reserved 0x0 R
ADXL356/ADXL357 Data Sheet
Rev. A | Page 36 of 42
FIFO ACCESS REGISTER
Address: 0x11, Reset: 0x00, Name: FIFO_DATA
Read this register to access data stored in the FIFO.
Table 33. Bit Descriptions for FIFO_DATA
Bits Bit Name Settings Description Reset Access
[7:0] FIFO_DATA FIFO data is formatted to 24 bits, three bytes, most significant byte first. A read to this
address pops an effective three equal byte words of axis data from the FIFO. Two
subsequent reads or a multibyte read completes the transaction of this data onto the
interface. Continued reading or a sustained multibyte read of this field continues to
pop the FIFO every third byte. Multibyte reads to this address do not increment the
address pointer. If this address is read due to an auto-increment from the previous
address, it does not pop the FIFO. Instead, it returns zeros and increments on to the
next address.
0x0 R
X-AXIS OFFSET TRIM REGISTERS
Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H
Table 34. Bit Descriptions for OFFSET_X_H
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_X,
Bits[15:8]
Offset added to x-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_X, Bits[15:0] matches the significance of XDATA,
Bits[19:4].
0x0 R/W
Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L
Table 35. Bit Descriptions for OFFSET_X_L
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_X,
Bits[7:0]
Offset added to x-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_X, Bits[15:0] matches the significance of XDATA,
Bits[19:4].
0x0 R/W
Y-AXIS OFFSET TRIM REGISTERS
Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H
Table 36. Bit Descriptions for OFFSET_Y_H
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Y,
Bits[15:8]
Offset added to y-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA,
Bits[19:4].
0x0 R/W
Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L
Table 37. Bit Descriptions for OFFSET_Y_L
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Y,
Bits[7:0]
Offset added to y-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA,
Bits[19:4].
0x0 R/W
Data Sheet ADXL356/ADXL357
Rev. A | Page 37 of 42
Z-AXIS OFFSET TRIM REGISTERS
Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H
Table 38. Bit Descriptions for OFFSET_Z_H
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Z,
Bits[15:8]
Offset added to z-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA,
Bits[19:4].
0x0 R/W
Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L
Table 39. Bit Descriptions for OFFSET_Z_L
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Z,
Bits[7:0]
Offset added to z-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA,
Bits[19:4].
0x0 R/W
ACTIVITY ENABLE REGISTER
Address: 0x24, Reset: 0x00, Name: ACT_EN
Table 40. Bit Descriptions for ACT_EN
Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R
2 ACT_Z Z-axis data is a component of the activity detection algorithm. 0x0 R/W
1 ACT_Y Y-axis data is a component of the activity detection algorithm. 0x0 R/W
0 ACT_X X-axis data is a component of the activity detection algorithm. 0x0 R/W
ACTIVITY THRESHOLD REGISTERS
Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H
Table 41. Bit Descriptions for ACT_THRESH_H
Bits Bit Name Settings Description Reset Access
[7:0] ACT_THRESH,
Bits[15:8]
Threshold for activity detection. Acceleration magnitude must be above
ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned
magnitude. The significance of ACT_THRESH, Bits[15:0] matches the
significance of Bits[18:3] of XDATA, YDATA, and ZDATA.
0x0 R/W
Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L
Table 42. Bit Descriptions for ACT_THRESH_L
Bits Bit Name Settings Description Reset Access
[7:0] ACT_THRESH,
Bits[7:0]
Threshold for activity detection. The acceleration magnitude must be greater
than the value in ACT_THRESH to trigger the activity counter. ACT_THRESH is
an unsigned magnitude. The significance of ACT_THRESH, Bits[15:0] matches
the significance of Bits[18:3] of XDATA, YDATA, and ZDATA.
0x0 R/W
ACTIVITY COUNT REGISTER
Address: 0x27, Reset: 0x01, Name: ACT_COUNT
Table 43. Bit Descriptions for ACT_COUNT
Bits Bit Name Settings Description Reset Access
[7:0] ACT_COUNT Number of consecutive events above threshold (from ACT_THRESH) required to
detect activity
0x1 R/W
ADXL356/ADXL357 Data Sheet
Rev. A | Page 38 of 42
FILTER SETTINGS REGISTER
Address: 0x28, Reset: 0x00, Name: Filter
Use this register to specify parameters for the internal high-pass and low-pass filters.
Table 44. Bit Descriptions for Filter
Bits Bit Name Settings Description Reset Access
7 Reserved Reserved 0x0 R
[6:4] HPF_CORNER −3 dB filter corner for the first-order, high-pass filter relative to the ODR 0x0 R/W
000 Not applicable, no high-pass filter enabled
001 24.7 × 10−4 × ODR
010 6.2084 × 10−4 × ODR
011 1.5545 × 10−4 × ODR
100 0.3862 × 10−4 × ODR
101 0.0954 × 10−4 × ODR
110 0.0238 × 10−4 × ODR
[3:0] ODR_LPF ODR and low-pass filter corner 0x0 R/W
0000 4000 Hz and 1000 Hz
0001 2000 Hz and 500 Hz
0010 1000 Hz and 250 Hz
0011 500 Hz and 125 Hz
0100 250 Hz and 62.5 Hz
0101 125 Hz and 31.25 Hz
0110 62.5 Hz and 15.625 Hz
0111 31.25 Hz and 7.813 Hz
1000 15.625 Hz and 3.906 Hz
1001 7.813 Hz and 1.953 Hz
1010 3.906 Hz and 0.977 Hz
FIFO SAMPLES REGISTER
Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES
Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid
triggering the FIFO watermark interrupt.
Table 45. Bit Descriptions for FIFO_SAMPLES
Bits Bit Name Settings Description Reset Access
7 Reserved Reserved. 0x0 R
[6:0] FIFO_SAMPLES Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition.
Values range from 1 to 96.
0x60 R/W
INTERRUPT PIN (INTx) FUNCTION MAP REGISTER
Address: 0x2A, Reset: 0x00, Name: INT_MAP
The INT_MAP register configures the interrupt pins. Bits[7:0] select which functions generate an interrupt on the INT1 and INT2 pins.
Multiple events can be configured. If the corresponding bit is set to 1, the function generates an interrupt on the interrupt pins.
Table 46. Bit Descriptions for INT_MAP
Bits Bit Name Settings Description Reset Access
7 ACT_EN2 Activity interrupt enable on INT2 0x0 R/W
6 OVR_EN2 FIFO_OVR interrupt enable on INT2 0x0 R/W
5 FULL_EN2 FIFO_FULL interrupt enable on INT2 0x0 R/W
4 RDY_EN2 DATA_RDY interrupt enable on INT2 0x0 R/W
3 ACT_EN1 Activity interrupt enable on INT1 0x0 R/W
2 OVR_EN1 FIFO_OVR interrupt enable on INT1 0x0 R/W
1 FULL_EN1 FIFO_FULL interrupt enable on INT1 0x0 R/W
0 RDY_EN1 DATA_RDY interrupt enable on INT1 0x0 R/W
Data Sheet ADXL356/ADXL357
Rev. A | Page 39 of 42
DATA SYNCHRONIZATION
Address: 0x2B, Reset: 0x00, Name: Sync
Use this register to control the external timing triggers.
Table 47. Bit Descriptions for Sync
Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R
2 EXT_CLK Enable external clock. See Table 14 for configuration details. 0x0 R/W
[1:0] EXT_SYNC Enable external synchronization control. 0x0 R/W
00 Internal synchronization.
01
External synchronization, no interpolation filter. After synchronization, and for
EXT_SYNC within specification, DATA_RDY occurs on EXT_SYNC.
10
External synchronization, interpolation filter, next available data indicated by
DATA_RDY 14 to 8204 oscillator cycles later (longer delay for higher ODR_LPF setting),
data represents a sample point group delay earlier in time.
11 Reserved.
I2C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER
Address: 0x2C, Reset: 0x81, Name: Range
Table 48. Bit Descriptions for Range
Bits Bit Name Settings Description Reset Access
7 I2C_HS I2C speed. 0x1 R/W
1 High speed mode.
0 Fast mode.
6 INT_POL Interrupt polarity. 0x0 R/W
0 INT1 and INT2 are active low.
1 INT1 and INT2 are active high.
[5:2] Reserved Reserved. 0x0 R
[1:0] Range Range. 0x1 R/W
01 ±10 g.
10 ±20 g.
11 ±40 g.
POWER CONTROL REGISTER
Address: 0x2D, Reset: 0x01, Name: POWER_CTL
Table 49. Bit Descriptions for POWER_CTL
Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R
2 DRDY_OFF Set to 1 to force the DRDY output to 0 in modes where it is normally signal data ready. 0x0 R/W
1 TEMP_OFF
Set to 1 to disable temperature processing. Temperature processing is also disabled
when standby = 1.
0x0 R/W
0 Standby Standby or measurement mode. 0x1 R/W
1
Standby mode. In standby mode, the device is in a low power state, and the
temperature and acceleration datapaths are not operating. In addition, digital
functions, including FIFO pointers, reset. Changes to the configuration setting of the
device must be made when standby = 1. An exception is a high-pass filter that can be
changed when the device is operating.
0 Measurement mode.
ADXL356/ADXL357 Data Sheet
Rev. A | Page 40 of 42
SELF TEST REGISTER
Address: 0x2E, Reset: 0x00, Name: SELF_TEST
Refer to the Self Test section for more information on the operation of the self test feature.
Table 50. Bit Descriptions for SELF_TEST
Bits Bit Name Settings Description Reset Access
[7:2] Reserved Reserved. 0x0 R
1 ST2 Set to 1 to enable self test force 0x0 R/W
0 ST1 Set to 1 to enable self test mode 0x0 R/W
RESET REGISTER
Address: 0x2F, Reset: 0x00, Name: Reset
Table 51. Bit Descriptions for Reset
Bits Bit Name Settings Description Reset Access
[7:0] Reset Write Code 0x52 to reset the device, similar to a power-on reset (POR) 0x0 W
In case of a software reset, an unlikely race condition may occur in products with REVID = 0x01 or earlier. If the race condition occurs,
some factory settings in the NVM load incorrectly to shadow registers (the registers from which the internal logic configures the sensor
and calculates the output after a power-on or a software reset). The incorrect loading of the NVM affects overall performance of the
sensor, such as an incorrect 0 g bias and other performance issues. The incorrect loading of NVM does not occur from a power-on or
after a power cycle. To guarantee reliable operation of the sensor after a software reset, the user can access the shadow registers after a
power-on, read and store the values on the host microprocessor, and compare the values read from the same shadow registers after a
software reset. This method guarantees proper operation in all devices and under all conditions. The recommended steps are as follows:
1. Read the shadow registers, Register 0x50 to Register 0x54 (five 8-bit registers) after power-up, but before any software reset.
2. Store these values in a host device (for example, a host microprocessor).
3. After each software reset, read the same five registers. If the values differ, perform a software reset again until they match.
Data Sheet ADXL356/ADXL357
Rev. A | Page 41 of 42
PCB FOOTPRINT PATTERN
Figure 77 shows the PCB footprint pattern and dimensions in millimeters.
3.80mm
3.22mm
3.80mm
0.68mm
0.70mm
0.70mm
14 PLCS
1.8mm × 0.68mm
TRIANGULAR MARKER, DETAIL A, POINTS TO PIN 1,
WHICH IS NOT ROUTED INTERNALLY AND DOES NOT
NEED TO BE GROUNDED
4.5mm
15429-076
Figure 77. PCB Footprint Pattern and Dimensions in Millimeters
ADXL356/ADXL357 Data Sheet
Rev. A | Page 42 of 42
OUTLINE DIMENSIONS
BOTTOM VIEW
SIDE VIEW
TOP VIEW
0.510 REF
2.20 REF
3.81
REF
2.54 REF
0.914
BSC
0.508
BSC
0.80
BSC
6.25
6.00 SQ
5.85
05-27-2016-
B
2.25
2.05
1.85
1
4
57
8
11
12 14
R 0.103
(14 PLCS)
R 0.203
(14 PLCS)
R 0.25
(4 PLCS) 0.10 BSC
5.60
SQ
0.15
BSC
0.30 SQ
(PIN 1 INDEX)
PKG-004554
1.674 BSC
DETAIL A
DETAIL A
Figure 78. 14-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-14-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Output
Mode
Measurement
Range (g)
Specified
Voltage (V) Temperature Range Package Description
Package
Option
ADXL356BEZ Analog ±10, ±20 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL356BEZ-RL Analog ±10, ±20 3.3 −40°C to +125°C 14-Terminal LCC, 13” Reel E-14-1
ADXL356BEZ-RL7 Analog ±10, ±20 3.3 −40°C to +125°C 14-Terminal LCC, 7” Reel E-14-1
ADXL356CEZ Analog ±10, ±40 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL356CEZ-RL Analog ±10, ±40 3.3 −40°C to +125°C 14-Terminal LCC, 13” Reel E-14-1
ADXL356CEZ-RL7 Analog ±10, ±40 3.3 −40°C to +125°C 14-Terminal LCC, 7” Reel E-14-1
ADXL357BEZ Digital ±10, ±20, ±40 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL357BEZ-RL Digital ±10, ±20, ±40 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL357BEZ-RL7 Digital ±10, ±20, ±40 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
EVAL-ADXL356BZ Evaluation Board for ADXL356B
EVAL-ADXL356CZ Evaluation Board for ADXL356C
EVAL-ADXL357Z Evaluation Board for ADXL357
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2017–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15429-6/20(A)