Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www.analog.com www.hittite.com THIS PAGE INTENTIONALLY LEFT BLANK HMCAD1063 Product Preview - 2.0214 Features * Cellular and Microwave Infrastructure Receivers * 14-bit Resolution * Communication Test Equipment * 50 to 500 MSPS Sampling Rate Range * Phased Array Radars * 83 dBc SFDR at 500 MSPS, Fin 187 MHz, BW= 100 MHz y Typical Applications * Magnetic Resonance Imaging * 71.1 dBFS SNR at 500 MSPS, Fin 70 MHz, 2.0Vpp * Spectrum Analyzers r * Adjustable Full Scale Range: 2.0Vpp and 1.4Vpp * Precision Digitizers * Dynamic Power Scaling vs. Sample Rate * 2-bit Fast Amplitude Detect (FAD) outputs Pin Compatibility a * 9 x 9 mm Package: QFN64 - 64 Lead Single Row in The HMCAD1063LP9 is pin compatible with HMCAD1073LP9 (QFN64 package). Functional Diagram General Description im The HMCAD1063 is a dual 14-bit wideband ADC, and achieves excellent linearity performance at high IF frequencies. P r e l Product Preview - ADC Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS The HMCAD1063 is based on a proprietary structure, and employs internal reference circuitry, a serial control interface, and parallel LVDS output data. Data synchronization clock is supplied for data capture at the receiver. Internal digital fine gain can be set separately for the ADC channels to calibrate for gain errors. HMCAD1063 provides a multiplexer inserted for each ADC output bit and the LVDS interface. This allows reducing the number of active LVDS pairs, as each LVDS pair will handle even and odd output bits. 2-bit Fast Amplitude Detect (FAD) outputs provide the amplitude of the input signal linear-in-dB at very low latency. Various modes and configuration settings can be applied to the ADCs through the serial control interface (SPI). Each channel can be powered down independently and output data format can be selected through this interface. A full chip power down mode can be set by a single external pin. Register settings determine the exact function of this pin. HMCAD1063 is designed to interface easily with Field Programmable Gate Arrays (FPGAs) from several vendors. 1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS in a r y Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Digital and Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC Electrical Specifications - 250 and 400 MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC Electrical Specifications - 500 MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LVDS Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Port Interface (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Startup Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Register 0x00 - Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Register 0x01 - Device Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Register 0x04 - Idle Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Register 0x05 - Recalibration by SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Register 0x10 - Full Scale Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Register 0x11 - Programmable Fine Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Register 0x20 - LVDS Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register 0x21 - Full Scale Range Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register 0x35 - Offset Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register 0x70 - Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Registers 0x71, 0x72 - Custom Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Register 0x73 - Custom Patterns for FAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Registers 0x7E and 0x7F - Vendor and Chip ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Recommended Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC-Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Clock Input and Jitter Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Fast Amplitude Detect (FAD) Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Evaluation Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 P r e l im Product Preview - ADC Table of Contents 2 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Specifications AVDD=DVDD=VDDIO= 1.8V, FS = 250 MSPS, Fin = 70 MHz, Ain = -1 dBFS, RSDS output data level, unless otherwise noted Parameter Description Min. Typ. Max. Units DC accuracy No missing codes guaranteed Offset error after internal digital offset correction GABS Gain error Grel Gain matching between channels DNL Differential nonlinearity 250 / 400 / 500 MSPS 0.6 / 0.5 / 0.5 LSB INL Integral nonlinearity (endpoint) 250 / 400 / 500 MSPS 1.6 / 1.3 / 2.4 LSB Vcm,out Common mode voltage output on VCM pin Analog input common mode voltage FSR HI Differential input voltage full scale range, high setting FSR LO Differential input voltage full scale range, low setting Cin Differential input capacitance Rin Differential input resistance at 250 / 400 / 500 MSPS AIBW The maximum analog input frequency where proper ADC performance is achieved for FSR HI / FSR LO Nin Input referred noise Operating free-air temperature Vcm,out + 0.1 V 2.0 Vpp 1.4 Vpp a in Gain Flatness im -3 dB bandwidth for the ADC input 0.5 dB Bandwidth 1.0 dB Bandwidth %FS 5/9 Vavdd Vcm,out - 0.1 Noise BW r Vcm,in Ta LSB %FS 0.5 Analog Input Temperature 2 6 y Offset 6.5 pF 2.5 / 1.4 / 1.26 k 900 MHz DC to 250 DC to 500 MHz 375 / 500 MHz 1.4 LSBrms -40 +85 Product Preview - ADC DC Electrical Specifications C l Digital and Switching Specifications Parameter Description Clock Inputs Duty Cycle FSmax Maximum sample rate FSmin Minimum sample rate Fclkmax Maximum input clock frequency r e DCclk Min Typ Max 45 55 250/400/500 % MSPS 50 MSPS 2000 Compliance Unit MHz LVDS, LVPECL, Sinewave Differential input voltage swing, Fclk 500 MHz 200 mVpp VCK,diff Differential input voltage swing, Fclk > 500 MHz 300 mVpp VCK,sine Differential input voltage swing, sine wave clock input 500 mVpp VCM,CK Input common mode voltage. Keep voltages within ground and voltage of VAVDD CCK Differential input capacitance RCK Differential input resistance P VCK,diff 0.3 VAVDD- 0.3 V 3 pF 100 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 3 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Digital and Switching Specifications, continued Description Min Typ Max Unit VHI High level input voltage. VVDDIO 3.0V VHI High level input voltage. VVDDIO= 1.7V- 3.0V VLI Low level input voltage. VVDDIO 3.0V 0 0.8 V VLI Low level input voltage. VVDDIO= 1.7V- 3.0V 0 0.2 *VVDDIO V 10 A High level input leakage current Low level input leakage current CI Input Capacitance 2 V 0.8 *VVDDIO V y IHI ILI 10 3 A pF VHO High level output voltage (IHO < 1 mA) VLO High level output voltage (ILO < 1 mA) r Logic Outputs (CMOS) 0.8 *VVDDIO V 0.2 *VVDDIO LVDS Data Outputs V LVDS / RSDS Differential output voltage, LVDS VOUT Differential output voltage, RSDS VCM Output common mode voltage Output coding Data output format Timing Characteristics in VOUT a Compliance Aperture delay Aperture jitter 0.79 TPDACT Startup time from Chip Power Down Mode to Active Mode TSLACT Startup time from Chip Sleep Mode to Active Mode TCAL Calibration time from ADC Enable to Active Mode TOVR im t AD Tjrms 350 mV 175 mV 1.2 V 2's complement 0.95 1.58 ns 75 fs rms 8000 clock cycles 1200 clock cycles 6.3510 6 clock cycles Out of range recovery time 1 clock cycles TLAT,DATA Data output latency 56 clock cycles TLAT,FAD Fast Amplitude Detect output latency 14 clock cycles l Product Preview - ADC Parameter Logic Inputs (CMOS) LVDS Output Timing Characteristics CLK input to data output delay (in addition to the pipeline delay) Tsk LCLK to Data output skew DClclk TEDGE 2.4 3.2 ns 0.1 +0.15 ns 55 % Data rise- and fall time 20% to 80% 0.12 0.2 ns Clock rise- and fall time 20% to 80% 0.12 0.2 ns LVDS LCLCK Duty-Cycle 45 r TCLKEDGE 1.8 -0.15 e Tod P "clock cycles" refers to ADC sample clock cycles. 4 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS AC Electrical Specifications - 250 and 400 MSPS AVDD=DVDD=VDDIO= 1.8V, FS = 250 MSPS, Fin = 70 MHz, Ain = -1 dBFS, RSDS output data level multiplexed, unless otherwise noted. Parameter 250 MSPS Description Min. Typ. 400 MSPS Max. Min. Typ. Max. Units Performance Parameters SNDR 71.9 FSR LO = 1.4Vpp, Fin = 70 MHz 69.1 FSR LO = 1.4Vpp, Fin = 150 MHz 68.9 FSR HI = 2.0Vpp, Fin = 350 MHz 70.1 FSR LO = 1.4Vpp, Fin = 350 MHz 67.9 FSR LO = 1.4Vpp, Fin = 440 MHz 66.3 Signal to noise and distortion ratio dBFS dBFS 66 dBFS 65 dBFS 69 dBFS dBFS 68.6 67.8 dBFS 67.7 64.5 dBFS 67.7 66 dBFS 65.6 64.5 dBFS FSR HI = 2.0Vpp, Fin = 70 MHz 79 75 dBc FSR LO = 1.4Vpp, Fin = 70 MHz 85 78 dBc FSR LO = 1.4Vpp, Fin = 150 MHz 81 75 dBc FSR LO = 1.4Vpp, Fin = 350 MHz FSR LO = 1.4Vpp, Fin = 440 MHz FSR HI = 2.0Vpp, Fin = 350 MHz 69 70 dBc FSR LO = 1.4Vpp, Fin = 350 MHz 77 70 dBc FSR LO = 1.4Vpp, Fin = 440 MHz 72 68 dBc l im Spurious free dynamic range in FSR HI = 2.0Vpp, Fin = 350 MHz FSR HI = 2.0Vpp, Fin = 70 MHz 88 86 dBc FSR LO = 1.4Vpp, Fin = 70 MHz 85 90 dBc e Second order harmonic spur 85 75 dBc FSR HI = 2.0Vpp, Fin = 350 MHz 72 90 dBc FSR LO = 1.4Vpp, Fin = 350 MHz 77 80 dBc 77 77 dBc FSR HI = 2.0Vpp, Fin = 70 MHz 79 75 dBc FSR LO = 1.4Vpp, Fin = 70 MHz 86 81 dBc FSR LO = 1.4Vpp, Fin = 150 MHz 81 84 dBc FSR HI = 2.0Vpp, Fin = 350 MHz 69 70 dBc FSR LO = 1.4Vpp, Fin = 350 MHz 78 80 dBc FSR LO = 1.4Vpp, Fin = 440 MHz 78 80 dBc r FSR LO = 1.4Vpp, Fin = 150 MHz FSR LO = 1.4Vpp, Fin = 440 MHz P 67 68.2 FSR LO = 1.4Vpp, Fin = 150 MHz HD3 67.9 71 FSR LO = 1.4Vpp, Fin = 70 MHz HD2 dBFS dBFS 69 FSR HI = 2.0Vpp, Fin = 70 MHz SFDR 70.5 68.4 r FSR HI = 2.0Vpp, Fin = 70 MHz y Signal to noise ratio a SNR Product Preview - ADC AC Electrical Specifications Third order harmonic spur For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 5 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Parameter 250 MSPS Description Typ. 400 MSPS Max. Min. Typ. Max. Units Effective number of bits 11.7 11.3 bit FSR LO = 1.4Vpp, Fin = 70 MHz 11.2 11.0 bit FSR LO = 1.4Vpp, Fin = 150 MHz 11.1 11.0 bit 10.6 FSR HI = 2.0Vpp, Fin = 350 MHz 11.0 FSR LO = 1.4Vpp, Fin = 350 MHz 11.0 FSR LO = 1.4Vpp, Fin = 440 MHz 10.6 bit 10.4 bit 90 80 dBc FSR HI = 2.0Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 91 88 dBFS FSR LO = 1.4Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 89 88 dBFS 90 88 dBFS Crosstalk IMD2 Second order intermodulation product FSR LO = 1.4Vpp, Fin = 440, 441 MHz, Ain = -7 dBFS Third order intermodulation product a FSR HI = 2.0Vpp, Fin 0 = 70 MHz, Fin1 = 71 MHz FSR HI = 2.0Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 89 82 dBFS FSR LO = 1.4Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 95 89 dBFS FSR LO = 1.4Vpp, Fin = 440, 441 MHz, Ain = -7 dBFS 91 88 dBFS FSR HI = 2.0Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 97 86 dBFS FSR LO = 1.4Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 100 97 dBFS FSR LO = 1.4Vpp, Fin = 440, 441 MHz, Ain = -7 dBFS 95 94 dBFS mA in In-Band IMD3 bit 10.7 Xtlk IMD3 y FSR HI = 2.0Vpp, Fin = 70 MHz r ENOB Min. In-Band Third order intermodulation product Power Supply im Product Preview - ADC AC Electrical Specifications - 250 and 400 MSPS, continued Analog supply current 320 505 Digital output driver supply current 170 235 mA Pavdd Analog power 575 910 mW Pdvdd Digital power 300 420 mW Ptot Total power dissipation 875 1330 mW Ppd Chip Power down Mode power dissipation <0.2 <0.35 mW Chip Sleep Mode power dissipation 320 475 mW Power saving per channel in channel-wise power down mode 365 535 mW Power saving per channel in channel-wise sleep mode 290 380 mW Ppdch _ sav e Pslp l Iavdd Idvdd P r Pslpch _ sav 6 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS AC Electrical Specifications - 500 MSPS AVDD=DVDD=VDDIO= 1.9V, FS = 500 MSPS, Fin = 70 MHz, Ain = -1 dBFS, RSDS output data level unless otherwise noted. Description Min. Typ. Max. Units SNR Signal to noise ratio FSR HI = 2.0Vpp, Fin = 70 MHz 71.1 dBFS FSR LO = 1.4Vpp, Fin = 70 MHz 68.3 dBFS 72 dBFS 72 dBFS FSR LO = 1.4Vpp, Fin = 70 MHz, BW= 100 MHz y FSR LO = 1.4Vpp, Fin = 187 MHz, BW= 100 MHz FSR LO = 1.4Vpp, Fin = 150 MHz FSR LO = 1.4Vpp, Fin = 320 MHz dBFS r FSR HI = 2.0Vpp, Fin = 70 MHz FSR LO = 1.4Vpp, Fin = 70 MHz FSR LO = 1.4Vpp, Fin = 320 MHz Spurious free dynamic range SFDR FSR HI = 2.0Vpp, Fin = 70 MHz a FSR LO = 1.4Vpp, Fin = 150 MHz 70.2 dBFS 68.1 dBFS 65.6 dBFS 67.5 dBFS dBc 83 dBc FSR LO = 1.4Vpp, Fin = 70 MHz, BW= 100 MHz 83 dBc FSR LO = 1.4Vpp, Fin = 187 MHz, BW= 100 MHz 83 dBc FSR LO = 1.4Vpp, Fin = 150 MHz 76 dBc FSR LO = 1.4Vpp, Fin = 320 MHz 71 dBc FSR HI = 2.0Vpp, Fin = 70 MHz 87 dBc FSR LO = 1.4Vpp, Fin = 70 MHz 92 dBc FSR LO = 1.4Vpp, Fin = 150 MHz 87 dBc FSR LO = 1.4Vpp, Fin = 187 MHz, BW= 100 MHz 90 dBc in 79 FSR LO = 1.4Vpp, Fin = 70 MHz Second order harmonic spur im HD2 Third order harmonic spur l HD3 79 dBc 83 dBc FSR LO = 1.4Vpp, Fin = 150 MHz 85 dBc 83 dBc e FSR HI = 2.0Vpp, Fin = 70 MHz FSR LO = 1.4Vpp, Fin = 70 MHz FSR LO = 1.4Vpp, Fin = 187 MHz, BW= 100 MHz r Effective number of bits FSR HI = 2.0Vpp, Fin = 70 MHz 11.5 bit FSR LO = 1.4Vpp, Fin = 70 MHz 11.0 bit FSR LO = 1.4Vpp, Fin = 150 MHz 10.6 bit FSR LO = 1.4Vpp, Fin = 187 MHz, BW= 100 MHz 10.7 bit 80 dBc FSR HI = 2.0Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 89 dBFS FSR LO = 1.4Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 86 dBFS FSR LO = 1.4Vpp, Fin = 370, 371 MHz, Ain = -7 dBFS 86 dBFS Xtlk Crosstalk IMD2 Second order intermodulation product P dBFS 66.2 Signal to noise and distortion ratio SNDR ENOB 65.6 Product Preview - ADC Parameter Performance Parameters FSR HI = 2.0Vpp, Fin 0 = 70 MHz, Fin1 = 71 MHz For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 7 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS AC Electrical Specifications - 500 MSPS, continued Description Min. Typ. Max. Units Third order intermodulation product In-Band IMD3 FSR HI = 2.0Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 85 dBFS FSR LO = 1.4Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 91 dBFS FSR LO = 1.4Vpp, Fin = 370, 371 MHz, Ain = -7 dBFS 87 dBFS 85 dBFS In-Band Third order intermodulation product y FSR HI = 2.0Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS FSR LO = 1.4Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS FSR LO = 1.4Vpp, Fin = 370, 371 MHz, Ain = -7 dBFS 94 dBFS 87 dBFS Analog supply current Idvdd Digital output driver supply current Pavdd Analog power Pdvdd Digital power a Iavdd r Power Supply 630 mA 270 mA 1130 mW 490 mW 1620 mW <0.5 mW Total power dissipation Chip Power down Mode power dissipation Pslp Chip Sleep Mode power dissipation 575 mW Ppdch _ sav Power saving per channel in channel-wise power down mode 635 mW Pslpch _ sav Power saving per channel in channel-wise sleep mode 435 mW in Ptot Ppd P r e l im Product Preview - ADC Parameter IMD3 8 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Operating Conditions 250 MSPS Description 400 MSPS 500 MSPS Min Typ Max Min Typ Max Min Typ Max Unit VAVDD Analog supply voltage range 1.7 1.8 2.0 1.7 1.8 2.0 1.8 1.9 2.0 VDVDD Digital and output driver voltage range 1.7 1.8 2.0 1.7 1.8 2.0 1.8 1.9 2.0 V V VOVDD Digital CMOS Inputs supply voltage range 1.7 1.8 3.6 1.7 1.8 3.6 1.7 1.9 3.6 V TA Ambient temperature -40 +85 -40 +85 -40 +85 C Absolute Maximum Ratings Parameter Description Min Junction temperature Tstorage Storage temperature AVDD Analog supply voltage in reference to AVSS DVDD Digital supply voltage in reference to DVSS OVDD Digital CMOS Inputs supply voltage in reference to AVSS AVSS-DVSS Supply difference Vanalog Analog inputs and outputs in reference to AVSS -0.3 Vclock Clock input pins voltage in reference to AVSS -0.3 VLVDS LVDS output pins voltage in reference to DVSS -0.3 Vdigital-in Digital input pins voltage in reference to DVSS -0.3 Unit C -65 +125 C -0.3 +2.3 V -0.3 +2.3 V -0.3 +3.9 V in im - Max +125 AVSS, DVSS are connected internally Human body model (JEDEC JS-001-2012) AVDD+0.3 or +2.3 OVDD+0.3 or 3.9 DVDD+0.2 or +2.3 OVDD+0.3 or 3.9 V V V V V passed 1000V (class 1C) l ESD Rating Typ a Tj r y Note: The conditions listed in this table must be observed for the device to be functional as specified in this document. These conditions do not guarantee specific performance levels - which are listed in the DC Electrical Specifications, AC Electrical Specifications, and Digital and Switching Specifications, and apply under the test conditions specified therein. Product Preview - ADC Parameter Charged device model (JESD-22-C101E) passed 1.5 kV (class IV) Soldering profile characteristics J-STD-020 e Note: Operating the device beyond the limits specified in this table may cause immediate damage to the device. Functional operation of the device is further limited by the Operating Conditions. Device functionality is not implied by the Absolute Maximum Ratings. r Thermal Information Parameter JA0 Description Standard1 Min Typ Max Unit JESD51-2 19.1 C/W JA1 Thermal resistance - junction-to-ambient, 1 m/s air flow JESD51-6 13.1 C/W JA2.5 Thermal resistance - junction-to-ambient, 2.5 m/s air flow JESD51-6 11.1 C/W JC Thermal resistance - junction-to-case, still air 2 MIL-STD883, 1012.1 0.6 C/W JB Thermal resistance - junction-to-board, still air JESD51-8 3.35 C/W P Thermal resistance - junction-to-ambient, still air2 2 Simulated environment according to JEDEC standards JESD51, JESD51-5 and JESD51-7. 2 "Still air" signifies natural convection in an enclosure according to JESD51-2. 1 Note: The thermal pad at the bottom of the device package (pin 0) must be attached to the PCB ground plane. It is also recommended that the thermal pad should be connected to a metal pad on the underside of the PCB through multiple vias for heat conduction purposes as this is the most optimal path for heat dissipation of this device. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 9 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS P r e l im in a r y Product Preview - ADC Outline Drawings, Top and Side View 10 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Product Preview - ADC l im in a r y Outline Drawings, Bottom View NOTES QFN64: r e 1. PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED. 2. LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY. 3. LEAD AND GROUND PADDLE PLATING: NiPdAu. 4. DIMENSIONS ARE IN INCHES [MILLIMETERS]. 5. LEAD SPACING TOLERANCE IS NON-CUMULATIVE. 6. CHARACTERS TO BE HELVETICA MEDIUM, .025 HIGH, WHITE INK, OR LASER MARK LOCATED APPROX. AS SHOWN. 7. PAD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL BE 0.25mm MAX. 8. PACKAGE WARP SHALL NOT EXCEED 0.05mm 9. ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND. 10. REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN. P 11. JEDEC STANDARD MO-220 APPLIES. Table 1. Package Information Part Number Package HMCAD1063LP9DE 9x9 mm QFN64 Package Body Material RoHS-compliant Low Stress Injection Molded Plastic Silica and silicon impregnated Lead Finish MSL Rating [2] Package Marking [1] NiPdAu MSL3 HAD6502 XXXX [1] Lot number XXXX [2] Max peak reflow temperature of 260 C For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 11 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Function 4, 7, 10, 13 AVDD 8, 61 AVDDCK 15 AVDDREF Interface Schematic Analog power supply, 1.8V 60 VDDCK 32, 41, 42, 49 DVDD 14 VDDIO 0 GND Thermal pad and main ground connection 16, 21, 64 GND Ground connections in addition to thermal pad (pin 0) 2 RN Resets SPI interface when low. After power is applied, a reset must be executed either by RN pin or SPI command reset to achieve proper ADC initialization. See also "Startup Sequence" on page 16 3 PD Sets chip Power Down when `high' Digital CMOS I/O supply voltage, 1.8 to 3.3V Chip select enable. Active low 18 SCLK Serial clock input 19 SDI Serial data input 20 SDO Serial data output DP1 LVDS channel 0, positive output DN1 LVDS channel 0, negative output DP2 LVDS channel 1, positive output DN2 LVDS channel 1, negative output FADP0 LVDS FAD channel 0, positive output FADN0 LVDS FAD channel 0, negative output FADP1 LVDS FAD channel 1, positive output FADN1 LVDS FAD channel 1, negative output LCLKP LVDS bit clock, positive output 40 LCLKN LVDS bit clock, negative output 62 CLKP Positive differential input clock 63 CLKN Negative differential input clock 5 IN1 Negative differential input signal, channel 1 r e l 39 P r Initiates Calibration when `high' a CAL CSN in 1 - -- Digital and LVDS power supply, 1.8V 17 See Table 2 12 Description y Pin Number im Product Preview - ADC Pin Descriptions 6 IP1 Positive differential input signal, channel 1 11 IN0 Negative differential input signal, channel 0 12 IP0 Positive differential input signal, channel 0 9 VCM Common mode output voltage For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS bit# n=0 DXn<1> DXn<2> DXn<3> DXn<4> DXn<5> DXn<6> DXn<7> 37 35 33 30 28 26 24 22 negative pin 38 36 34 31 29 27 25 23 positive pin 58 56 54 52 50 47 45 43 negative pin 59 57 55 53 51 48 46 44 a r y n=1 DXn<0> positive pin P r e l im in LVDS Timing Diagram Product Preview - ADC Table 2. Pins of LVDS Channels LVDS channel Figure 1. LVDS timing For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 13 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS CSN: Chip Select enabled when low * SDI: Serial Data Input * SDO: Serial Data Output * SCLK: Serial Clock When CSN is set low, the SDI pin is awaiting input on the rising edge of SCLK: First bit is a R/W bit (`0': Write to SPI on SDI, `1': Read from SDO) * For SPI input (R/W = `0') the last 16 bits are data, see Figure 2. Data are clocked in on the rising edge of SCLK and loaded into the register at the 24th rising SCLK edge. * For Serial Data Output (R/W = `1'), 16 bits are output on SDO during the last 16 SCLK periods, in sync with the falling edge of SCLK, see Figure 3. Acceptable SCLK frequencies are from a few Hertz to 20 MHz. Duty cycle is not considered critical. a * The next 7 bits are the register address to be written/read. y * * r The HMCAD1063 configuration registers can be accessed through SPI an interface formed by the pins Description in Table 3. SPI Timing Definitions Parameter Minimum value Maximum value Unit tcs Setup time between CSN and SCLK 8 ns tch Hold time between CSN and SCLK 8 ns thi SCLK high time 20 ns tlo SCLK low time tck ns SCLK period 50 ns im 20 ts SDI setup time 5 ns th SDI hold time 5 ns tchi CSN high time 100 td SDO delay ns 5 ns Figure 2. Serial Port Interface Timing during Write Operation See Table 3 for timing definitions. P r e l Product Preview - ADC Serial Port Interface (SPI) Figure 3. Serial Port Interface Timing during Read Operation 14 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Register Overview R/W adc_enable 5:4 R/W clock_div 2 R/W fgain_en 5:4 R/W vcm_drive_cfg 8 R/W pd_pin_cfg 0x01 0x05 0x10 0x11 0 11 4 mA 0 Configures Input clock division factor Enables the fine gain function Configures VCM output driving strength Configures the PD pin functionality. `0': PD pin invokes Chip Power Down Mode. `1': PD pin invokes Chip Sleep Mode R/W pd 0 Sets Chip power down Mode pd_ch 00 Sets Channel-wise power down Modes 8 R/W sleep 0 Sets Chip sleep Mode 13:12 R/W sleep_ch 00 Sets Channel-wise sleep Modes 0 AUTOCLR recal_by_spi 0 3:0 R/W fsr_ch0 11:8 R/W fsr_ch1 7:0 R/W fgain_ch0 15:8 R/W fgain_ch1 R/W lvdsterm_ctrl 4 R/W lvdscurr_ctrl 5 R/W scramble_en 8 R/W 0001 FSR= 2.0Vpp Initiates re-calibration Configures Full Scale Range for channel 0 0x00 factor 1x Configures Full Scale Range for channel 1 00 not terminated 0 Sets fine gain value for channel 0 Sets fine gain value for channel 1 Sets LVDS output (data and clock) termination resistance Selects RSDS (`0') or LVDS (`1') Mode 0 Enables scrambling of LVDS outputs by channel's LSB fad_en 0 Enables the Fast Amplitude Detect (FAD) output 0x00 no tuning 13:8 R/W fsrtune* 2:0 R/W offcomp_time_ch0 5 AUTOCLR offcomp_start_ch0 10:8 R/W offcomp_time_ch1 offcomp_start_ch1 000 0 000 0 Selects Full Scale Range Tuning factor Sets number of samples used for offset compensation for channel 0 Invokes offset compensation for channel 0 Sets number of samples used for offset compensation for channel 1 13 AUTOCLR 7:0 R temp_val 14 R temp_valid 0 Set when temperature measurement completed 15 R/W activate_tempm 0 Enables temperature measurement 0x000 Invokes offset compensation for channel 1 Temperature value P r 0x59 Enable ADC R/W l 0x35 1 00 division by 1 0 e 0x21 Self clearing software reset 5:4 1:0 0x20 Description 0 im 0x04 Default Product Preview - ADC 1 Name reset y AUTOCLR r Type 0 a 0x00 bit in Hex Address For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 15 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Register Overview, continued Type 0 R/W ramp_en Name Default 0 Enables a repeated full scale ramp data output pattern Description 1 R/W single_cust_pat_en 0 Enables custom_pattern0 on channel 0 and custom_pattern1 on channel 1 2 R/W dual_cust_pat_en 0 Enables toggling custom_pattern0 and custom_pattern1 on both channel 0 and channel 1 3 R/W prbs_en 0 Enables a pseudo random bit sequences on each LVDS output pair y 0x70 bit 15:0 R/W custom_pattern0 0x5555 Custom pattern 0 15:0 R/W custom_pattern1 0xAAAA Custom pattern 1 3:0 R/W custom_fad_pattern0 0x5 Custom pattern 0 for FAD outputs 7:4 R/W custom_fad_pattern1 0xA Custom pattern 1 for FAD outputs 15:0 R 0x713 0x7E vendor_id 0xADC Vendor ID 0x7F 15:0 R chip_id 400 MSPS: 0x03 500 MSPS: 0x04 a 250 MSPS: 0x01 r 0x71 0x72 Product ID in *When modifying registers marked with an asterisk, the ADC operation must be disabled first by setting adc_enable in register 0x00 to `0'. Afterwards, set adc_enable back to `1'. See also next section "Startup Sequence". Startup Sequence im Product Preview - ADC Hex Address The recommended startup sequence is: Purpose l Step SPI Write register value Power up chip 2. In register 0x00, set clock_div = `mn', adc_enable= `0' and reset = `1' 0x00 `00mn 0001' 3. Optional (if non-default values are desired): set fsrtune = `abcdef' in register 0x21 0x21 `00ab cdef 0000 0000' e 1. - Optional: write additional parameters Set adc_enable = `1' while maintaining clock_div = `mn' 0x00 `00mn 0010' 6. Optional: re-estimate Offset Compensation 0x35 see register description 7. Wait for Start-up (see also "Digital and Switching Specifications" on page 3) r 4. 5. - P Once the ADC is running, registers marked with an asterisk (*) in the Register Overview can be modified by 1. set adc_enable = 0 while maintaining the value of clock_div (register 0x00 = `00mn 0000') 2. follow steps 3. to 7. 16 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Register Description Register 0x00 - Software Reset Name Default Description bit Type Name Default 0 AUTOCLEAR reset 0 Self clearing software reset 2 R/W fgain_en 0 Enables the fine gain function 1 R/W adc_enable 1 Enable ADC 5:4 R/W vcm_drive_cfg 11 5:4 R/W clock_div 00 Input clock division factor Configures VCM output driving strength 8 R/W pd_pin_cfg 0 Configures the PD pin functionality r The register bit fgain_en enables the fine gain setting given by register 0x11, channel fine gain. If fgain_en is `0' the gain is set to 1. The vcm_drive_cfg register configures the Common Mode Voltage Output (VCM pin) driving strength. The driving strengths, as listed below, are the maximum currents from/to the VCM pin without exceeding 50 mV error voltage on the pin. in Setting adc_enable to `0' and later, back to `1' allows both to change register settings without generating data in an undesired intermediate state, and to initiate the ADC at a well-defined time. The HMCAD1063 has several configuration settings, controlling Digital Gain, Fast Amplitude Detect (FAD) Output, Common Mode output drive strength, PD pin functionality, and ADC resolution: a Setting the reset register bit to `1', restores the default value of all the internal registers including the reset register bit itself, but continues using the values of both clock_div and adc_enable that are being written to register 0x00 in the same SPI write command as reset. Using the reset register is equivalent to setting the RN pin low and then high, but RN always resets clock_div and adc_enable to their default values. The register bits clock_div allow the user to apply an input clock frequency higher than the sampling rate. The clock divider will divide the input clock frequency by a factor of 1, 2, 4, or 8, as in the following table. The maximum input clock frequency is 2000 MHz. im When changes are written to clock_div it is mandatory to invoke reset. See also section "Startup Sequence". Clock Divider Factor Sampling rate (Fs) 00 (default) 1 Input clock frequency / 1 01 2 Input clock frequency / 2 10 4 Input clock frequency / 4 11 8 vcm_drive_cfg<1:0> VCM output driving strength 00 OFF 01 0.1 mA 10 2 mA 11 (default) 4 mA The register bit pd_pin_cfg sets the function of the PD pin to either Power Down (`0' - default) or Sleep (`1'). l clock_div<1:0> Description y Type Product Preview - ADC Register 0x01 - Device Configuration bit P r e Input clock frequency / 8 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 17 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Default Description 0 R/W pd 0 Sets Chip to Power Down Mode 5:4 R/W pd_ch 00 Set Channel-wise Power Down Modes 8 R/W sleep 0 Invokes Chip Sleep Mode 13:12 R/W sleep_ch 00 Set Channel-wise Sleep Modes The HMCAD1063 includes power down and sleep idle modes for power management. The sleep modes offer short start up times while the power down modes offer extremely low power dissipation. Type Name Default Description 0 AUTOCLEAR recal_by_spi 0 Initiates re-calibration Setting the recal_by_spi register bit to `1', starts the calibration of HMCAD1063. ADC output data will be invalid during the calibration sequence. The register will be reset when the calibration is finished. During the calibration sequence the ADC input clock must be operated continuously at the frequency that will be used during operation. Analog input signals will not impact the calibration. The SPI interface must not be used during calibration. Recalibration by SPI is equivalent to using the CAL pin. This calibration is invoked during the Startup Sequence when setting adc_en = `1'. A re-calibration is recommended when external conditions changed considerably, such as sampling rate, supply voltage, or ambient temperature. in The register bit pd sets the Chip Power Down Mode, powering down the entire chip. All register values are maintained during Chip Power Down Mode, as long as reset in register 0x00 is not activated. All internal circuitry is turned off during Chip Power Down Mode, but SPI registers may still be written to and read from. bit y Name r Type a bit Register 0x05 - Recalibration by SPI pd_ch<1:0> Channel 1 00 (default) Active 01 Active 10 Power Down 11 Power Down im The register bits pd_ch set the Channel-wise Power Down Modes according to the table below. Setting both channels in power down (`11') is not equal to using Chip Power Down Mode, as LCLK and VCM outputs will be active. Channel 0 Active Power Down Active Power Down l Product Preview - ADC Register 0x04 - Idle Mode Control e The register bit sleep sets the Chip Sleep Mode, with short start up time. The LCLK and VCM outputs are active in sleep mode. r The register bits sleep_ch set Channel-wise Sleep Modes according to the following table. The Channelwise Sleep Modes are similar to the Channelwise Power Down Modes, but has higher power consumption and shorter start up time. Channel 1 Channel 0 00 (default) Active Active 01 Active Sleep 10 Sleep Active 11 Sleep Sleep P sleep_ch<1:0> 18 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Name Default Description 3:0 R/W fsr_ch0 0001 Configures Full Scale Range for channel 0 11:8 R/W fsr_ch1 0001 Configures Full Scale Range for channel 1 bit Table 4. Configuration of Full Scale Range (FSR) fsr_ ch0<3:0> fsr_ch1<11:8> Name 7:0 15:8 Name Default Description R/W fgain_ch0 0000 0000 factor 1x Programmable fine gain, channel 0 R/W fgain_ch1 0000 0000 factor 1x Programmable fine gain, channel 1 Digital fine gain can be set for each channel separately. fine_gain_en must be set to `1', see also "Register 0x01 - Device Configuration", and Table 5. y Full Scale Range can be set for each channel separately. The configuration is described in this table: Type Table 5. Fine Gain Factors fgain_ch0<7:0> Full Scale Range [Vpp] 0001 (default) FSR HI 2.0 0100 FSR LO 1.4 fgain_ch1<7:0> 0111 1111 Fine gain Arithmetic function r Type factor [x] out = in (1+2-4+2-5+2-6+2-7+2-8+2-9+2-10) out = in (1+2-4+2-5+2-6+2-7+2-8+2-9) 1.1230 0111 1101 out = in (1+2 +2 +2 +2 +2 +2 ) 1.1221 ... ... ... 0000 0010 out = in (1+2-9) 1.0020 0000 0001 out = in (1+2-10) 1.0010 0000 0000 out = in 1 1111 1111 out = in 1 1111 1110 out = in (1-2-10) 0.9990 1111 1101 out = in (1-2-9) 0.9980 ... ... ... 1000 0010 out = in (1-2-4-2-5-2-6-2-7-2-8-2-10) 0.8779 1000 0001 out = in (1-2-4-2-5-2-6-2-7-2-8-2-9) 0.8770 1000 0000 -4 -5 -6 -7 -8 out = in (1-2-4-2-5-2-6-2-7-2-8-2-9-2-10) -10 0.8760 P r e l im 1.1240 0111 1110 in In addition, the Full Scale Range of HMCAD1063 can be fine-tuned, see "Register 0x21 - Full Scale Range Tuning" on page 22. a bit Register 0x11 - Programmable Fine Gain Product Preview - ADC Register 0x10 - Full Scale Range For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 19 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Type Name Default 1:0 R/W lvdsterm_ctrl 00 Sets LVDS output (data and clock) termination resistance scramble_en, if set to `1', scrambles the data of both LVDS outputs by multiplication by each individual LSB. This can assist noise reduction within the LVDS part of the signal chain. 4 R/W lvdscurr_ctrl 0 Selects RSDS ('0') or LVDS ('1') Mode When fad_en is set to `1', 2-bit Fast Amplitude Detect (FAD) Outputs are available, see Table 6. 5 R/W scramble_en 0 Enable scrambling of LVDS output with each channel's LSB LCLK runs at the same frequency as the sampling rate (Fs). 8 R/W fad_en 0 Enable FAD output Channel 0 is output on the positive edge of LCLK and channel 1 on the negative edge of LCLK, as shown in the timing diagram in Figure 1. lvdsterm_ctrl sets the termination resistance of the LVDS outputs according to the following table: Nominal termination value 00 (default) Not terminated 01 200 10 200 11 100 The output pairs not used are powered down. The modes defined by fad_en are listed in Table 6. The corresponding LVDS pin-mappings are given in Table 7. in a lvdsterm_ctrl r Description y bit lvdscurr_ctrl LVDS output Mode 0 (default) RSDS 1 LVDS im lvdscurr_ctrl sets the LVDS signalling level. The LVDS output currents can be set to the RSDS (Reduced Swing Differential Signaling) or LVDS (Low Voltage Differential Signaling) currents: LVDS output current 1.75 mA 3.5 mA r e l Product Preview - ADC Register 0x20 - LVDS Control Table 6. Data Output Modes # Data bits per channel FAD output Mode LVDS data update rate 0 (default) 1 14 <15:2> Disabled 2 Fs 14 <15:2> 2-bit <1:0> 2 Fs P fad_en 20 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS FAD disabled LVDS pair first slice phi 0 FAD enabled second slice phi 1 first slice phi 0 second slice phi 1 DATA0<13> DATA0<12> DATA0<13> DATA0<12> DATA0<11> DATA0<10> DATA0<11> DATA0<10> DX0<5> DATA0<9> DATA0<8> DATA0<9> DATA0<8> DX0<4> DATA0<7> DATA0<6> DATA0<7> DATA0<6> y DX0<7> DX0<6> DATA0<5> DATA0<4> DATA0<5> DATA0<4> DATA0<3> DATA0<2> DATA0<3> DATA0<2> DX0<1> DATA0<1> DATA0<0> DATA0<1> DATA0<0> DX0<0> - - FAD0<1> r DX0<3> DX0<2> FAD0<0> DATA1<13> DATA1<12> DATA1<13> DATA0<11> DATA0<10> DATA1<11> DX1<5> DATA0<9> DATA0<8> DATA1<9> DATA1<8> DX1<4> DATA0<7> DATA0<6> DATA1<7> DATA1<6> a DX1<7> DX1<6> DATA1<12> DATA1<10> DATA0<5> DATA0<4> DATA1<5> DATA1<4> DATA0<3> DATA0<2> DATA1<3> DATA1<2> DX1<1> DATA0<1> DATA0<0> DATA1<1> DATA1<0> DX1<0> - - FAD1<1> FAD1<0> in DX1<3> DX1<2> l im Table 8 describes the Fast Amplitude Detect (FAD) outputs. The FAD will serve as a 2-bit low latency ADC, converting the analog input amplitude to a digital value. This allows the FAD outputs to be utilized as an Received Signal Strength Indicator, providing the signal strength at a lower latency compared to the Data output. The Input Amplitude column in the table shows the Amplitude in V peak-to-peak. Product Preview - ADC Table 7. LVDS Pin Mapping Table 8. FAD Output Pin Function Input Amplitude Vpp 2-bit FAD output Value FADx<1:0> > 0.94 3 11 0.44 to 0.94 2 10 0.19 to 0.44 1 01 < 0.19 0 00 e When 2-bit FAD is activated, the FAD0<1:0> and FAD1<1:0> outputs will provide a low latency 2-bit signal proportional with the Input Amplitude for channel 0 and channel 1, respectively. P r Table 6 lists the combinations of the data output modes and accompanying FAD modes. The usage of LVDS pin pairs in different data output modes is listed in Table 7. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 21 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS R/W Name Default fsrtune Selects Full Scale Range 00 0000 tuning factor Description bit HMCAD1063 Full Scale Range can be either FSRLO = 1.4Vpp or FSRHI = 2.0Vpp, see "Register 0x10 - Full Scale Range" on page 19. In addition, the Full Scale Range can be fine tuned by ca. 7%, by multiplying the Full Scale Range in Table 4 with the Full Scale Range tuning factor fsrtune according to this table: Full Scale Range Tuning factor 01 1111 +7.0% 01 1110 +6.8% ... ... 00 0001 +0.225% 00 0000 (default) +0% 11 1111 -0.225% ... ... 10 0001 -7.0% 10 0000 -7.2% im l e r 010 125 MSPS 500 MSPS 212 0.016 ms 0.004 ms 14 2 0.066 ms 0.017 ms 217 0.524 ms 0.131 ms 011 220 4 ms 1 ms 100 222 17 ms 4 ms 101 225 134 ms 34 ms 110 228 1074 ms 269 ms 111 231 8600 ms 2150 ms P 22 Compensation Time vs. Fs 001 R/W offcomp_ time_ch1 AUTO- offcomp_ CLR start_ch1 000 0 Invokes offset compensation for channel 0 000 Sets number of samples used for offset compensation for channel 1 0 Invokes offset compensation for channel 1 HMCAD1063 offset voltage may generate a non-zero DC value. Due to the HMCAD1063 architecture, Offset mismatch may give a tone in the Nyquist frequency Fs/2. 2.Disable the analog input signal or reduce the input amplitude level as much as possible. Table 9. Offset Compensation Times 000 (default) 13 AUTO- offcomp_ CLR start_ch0 Description Sets number of samples used for offset compensation for channel 0 1. Set adc_enable in register 0x00 to `1' (if applicable - see also "Startup Sequence" on page 16). It's mandatory to set adc_enable = `0' before writing to fsrtune, see also section "Startup Sequence" on page 16. # of samples 10:8 offcomp_ time_ch0 Default For Time Domain applications the Offset Compensation procedure described below is highly recommended to minimize unwanted signal energy in DC and Fs/2. The Full Scale Range tuning will apply equally to channel 0 and channel 1. offcomp_time_chx 5 R/W Name a fsrtune 2:0 Type r 13:8 Type in Product Preview - ADC bit Register 0x35 - Offset Compensation y Register 0x21 - Full Scale Range Tuning 3. Set offcomp_start_chx to `1'. This triggers an estimation of the offsets during a time periode determined by offcomp_time_chx, and adjusts the compensation accordingly. The bits offcomp_start_chx are auto-clearing: once the calibration is done, the bits D5 and D13 in register 0x35 will read out as `0' again. The default compensation time (offcomp_time_ chx = 000) is appropriate when the ADC analog input signal is shorted while offcomp_start_chx = 1. If there is a residual signal at the ADC input, longer compensation times may be necessary, see Table 9. In applications where DC and FS/2 are critical it is recommended to use offcomp_time_chx = `011' or higher, see Table 9. 4.When offcomp_start_chx is `0' again, the ADC will output data with compensated Offsets. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS 15 R temp_val 0x00 Temperature value 0 `1' after temperature measurement is completed 0 Triggers a temperature measurement temp_valid R/W activate_tempm Description bit Type HMCAD1063 includes a built-in temperature sensor. To perform a temperature measurement, the register activate_tempm must be set to `1'. The register bit temp_valid is set to `1' when the temperature measurement is completed, and subsequently, the temperature can be read from the register temp_val. Based on the value of the signed integer temp_val, the corresponding temperature T can be calculated in C: temp_val bit value temp_val signed integer Temperature in C + 255 + 309 C + 254 + 307 C ... ... ... 0 0000 0001 +1 + 1.2 C 0 0000 0000 0 1 1111 1111 -1 ... - 255 1 0000 0000 - 256 0 C - 1.2 C ... - 309 C - 310 C l ... 1 0000 0001 im 0 1111 1111 0 1111 1110 Note: The theoretical range of temp_val exceeds the Absolute Maximum Ratings. Be aware that the Absolute Maximum Ratings refer to enviromental conditions, whereas temp_val is rather the core temperature. Description 0 R/W ramp_en 0 Enable a repeating full scale ramp pattern out 1 R/W single_cust_ pat_en 0 Enable pattern 0 on ch0 and ch1 2 R/W dual_cust_ pat_en 0 Enable toggling patterns 0 and 1 on both ch0 and ch1 3 R/W prbs_en 0 Enables a pseudo random bit sequence on each LVDS output pair For LVDS data output debug purposes, a set of test patterns is available. Setting ramp_en to `1', outputs a ramp signal on both data channels. The ramp on channel 0 starts at code 0x0000 and steps up by one per clock cycle. When the ramp reaches value 0x3FFF it wraps to code 0x0000. The ramp on channel 1 starts at 0x3FFF and steps down by one per clock cycle and wraps around from 0x0000 to 0x3FFF. Setting single_cust_pat_en to `1' outputs custom_ pattern0 (given by register 0x71) on both channel 0 and channel 1. Setting dual_cust_pat_en to `1' toggles between custom_pattern0 on both channels simultaneously, and custom_pattern1 (content of register 0x72). Setting prbs_en to `1' outputs a pseudo random bit sequence on each of the LVDS output pairs. If the FAD output is activated (fad_en = `1' in Register 0x20 - LVDS Control), the content of register 0x73 will be output according to single_cust_pat_en and dual_ cust_pat_en. If both fad_en and ramp_en are activated, the concatenations of FAD and data on the LVDS channels will result in 16-bit counters. Note that only one test pattern must be enabled at a single time. P r e Default in T = temp_val 1.21C Name Product Preview - ADC 14 R Default r 8:0 Name a bit Type Register 0x70 - Test Patterns y Register 0x59 - Temperature Sensors For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 23 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Name Default Description 0x71 15:0 R/W custom_pattern0 0x5555 Custom pattern 0 0x72 15:0 R/W custom_pattern1 0xAAAA Custom pattern 1 The content of these registers is used if either single_ cust_pat_en or dual_cust_pat in register 0x70 is set to `1'. Register bit Type 0x7E 15:0 R Name vendor_id Default Description 0xADC Vendor ID 250 MSPS: 0x1 0x7F 15:0 R chip_id 400 MSPS: 0x3 Chip ID 500 MSPS: 0x4 y Register bit Type Registers 0x7E and 0x7F - Vendor and Chip ID Register vendor_id can be read to verify the vendor ID of the chip. Type Name Default Description 3:0 R/W 7:4 R/W custom_fad_pattern0 0x5 Custom pattern 0 custom_fad_pattern1 0xA Custom pattern 1 in The content of this register is used if either single_ cust_pat or dual_cust_pat in register 0x70 is set to `1', and FAD output is enabled according to Table 6. r bit Register chip_id can be read to verify the product variant identification code for the chip. a Register 0x73 - Custom Patterns for FAD If 2-bit FAD is activated, only the two LSB of custom_ fad_patternx are used. P r e l im Product Preview - ADC Registers 0x71, 0x72 - Custom Patterns 24 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Figure 2. Performance vs. Fin, 250 MSPS Ain = -1 dBFS, Fs = 250 MSPS, FSRLO = 1.4Vpp Ain = -1 dBFS, Fs = 250 MSPS, FSRHI = 2.0Vpp 95 95 90 90 85 80 75 85 80 75 y PERFORMANCE (dB) PERFORMANCE (dB) Figure 1. Performance vs. Fin, 250 MSPS 70 70 65 65 100 200 300 400 0 500 50 100 150 200 250 300 r 0 350 400 FREQUENCY (MHz) FREQUENCY (MHz) SNR (dBFS) SNDR (dBFS) SFDR (dBc) HD2 (dBc) HD3 (dBc) HD2 (dBc) HD3 (dBc) a SNR (dBFS) SNDR (dBFS) SFDR (dBc) Figure 3. Performance vs. Fin, 400 MSPS Figure 4. Performance vs. Fin, 400 MSPS Ain = -1 dBFS, Fs = 400 MSPS, FSRLO = 1.4Vpp Ain = -1 dBFS, Fs = 400 MSPS, FSRHI = 2.0Vpp 100 in 100 85 80 75 70 65 60 0 100 200 300 90 85 80 75 70 65 60 500 0 50 SNR (dBFS) SNDR (dBFS) SFDR (dBc) 100 150 200 250 300 350 400 FREQUENCY (MHz) l FREQUENCY (MHz) 400 PERFORMANCE (dB) 95 90 im PERFORMANCE (dB) 95 HD2 (dBc) HD3 (dBc) SNR (dBFS) SNDR (dBFS) SFDR (dBc) HD2 (dBc) HD3 (dBc) Figure 6. Performance vs. Fin, 500 MSPS Ain = -1 dBFS, Fs = 500 MSPS, FSRLO = 1.4Vpp Ain = -1 dBFS, Fs = 500 MSPS, FSRHI = 2.0Vpp e Figure 5. Performance vs. Fin, 500 MSPS 90 90 PERFORMANCE (dB) 95 95 85 P PERFORMANCE (dB) 100 r 105 Product Preview - ADC Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS 80 75 85 80 75 70 70 65 65 0 100 200 300 400 500 FREQUENCY (MHz) SNR (dBFS) SNDR (dBFS) SFDR (dBc) 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) HD2 (dBc) HD3 (dBc) SNR (dBFS) SNDR (dBFS) SFDR (dBc) HD2 (dBc) HD3 (dBc) For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 25 HMCAD1063 Product Preview - 2.0214 Figure 7. Performance vs. Input Amplitude Figure 8. Performance vs. Input Amplitude Fs = 250 MSPS, Fin = 141 MHz, FSRLO = 1.4V Fs = 250 MSPS, Fin = 141 MHz, FSRHI = 2.0V 100 90 80 70 80 70 60 -30 -25 -20 -15 -10 -5 50 -35 0 -30 -20 -15 -10 -5 0 INPUT SIGNAL LEVEL (dBFS) INPUT SIGNAL LEVEL (dBFS) SFDR (dBc) SNR (dBFS) SFDR (dBc) SFDR (dBFS) SNR (dBc) SFDR (dBFS) a SNR (dBFS) SNR (dBc) Figure 10. Performance vs. Input Amplitude Fs = 400 MSPS, Fin = 141 MHz, FSRLO = 1.4V Fs = 400 MSPS, Fin = 141 MHz, FSRHI = 2.0V in Figure 9. Performance vs. Input Amplitude 90 70 50 -35 -30 -25 -20 -15 im 80 -10 -5 PERFORMANCE (dB) 100 100 60 90 80 70 60 50 -35 0 -30 l SNR (dBFS) SNR (dBc) -25 -20 -15 -10 -5 0 INPUT SIGNAL LEVEL (dBFS) INPUT SIGNAL LEVEL (dBFS) SFDR (dBc) SNR (dBFS) SFDR (dBc) SFDR (dBFS) SNR (dBc) SFDR (dBFS) Figure 12. Performance vs. Input Amplitude Fs = 500 MSPS, Fin = 141 MHz, FSRLO = 1.4V Fs = 500 MSPS, Fin = 141 MHz, FSRHI = 2.0V e Figure 11. Performance vs. Input Amplitude 100 PERFORMANCE (dB) 90 80 P PERFORMANCE (dB) r 100 70 50 -35 90 80 70 60 60 -30 -25 -20 -15 -10 -5 0 50 -35 -30 -25 -20 -15 -10 -5 0 INPUT SIGNAL LEVEL (dBFS) INPUT SIGNAL LEVEL (dBFS) 26 -25 r 60 50 -35 90 y PERFORMANCE (dB) PERFORMANCE (dB) 100 PERFORMANCE (dB) Product Preview - ADC Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS SNR (dBFS) SFDR (dBc) SNR (dBFS) SFDR (dBc) SNR (dBc) SFDR (dBFS) SNR (dBc) SFDR (dBFS) For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS 250 MSPS, Fin = 71 MHz, Ain = -1 dBFS, FSRHI = 2.0V Figure 14. Integral Nonlinearity - INL 250 MSPS, Fin = 71 MHz, Ain = -1 dBFS, FSRHI = 2.0V 1 3 2 1 0 0 y INL (LSB) DNL (LSB) 0.5 -1 -0.5 -2 -1 r -3 CODE (bit) a CODE (bit) Figure 16. Integral Nonlinearity - INL 400 MSPS, Fin = 71 MHz, Ain = -1 dBFS, FSRHI = 2.0V 400 MSPS, Fin = 71 MHz, Ain = -1 dBFS, FSRHI = 2.0V in Figure 15. Differential Nonlinearity - DNL 3 1 2 0 -0.5 -1 INL (LSB) 1 im DNL (LSB) 0.5 Product Preview - ADC Figure 13. Differential Nonlinearity - DNL 0 -1 -2 -3 CODE (bit) l CODE (bit) Figure 18. Integral Nonlinearity - INL 500 MSPS, Fin = 70 MHz, Ain = -1 dBFS, FSRHI = 2.0V 500 MSPS, Fin = 70 MHz, Ain = -1 dBFS, FSRHI = 2.0V e Figure 17. Differential Nonlinearity - DNL 3 r 1 2 INL (LSB) 1 P DNL (LSB) 0.5 0 0 -1 -0.5 -2 -3 -1 CODE (bit) CODE (bit) For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 27 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Figure 19. Single Tone FFT - 250 MSPS 0 -40 -60 -80 y AMPLITUDE (dBFS) -20 -100 0 20 40 60 80 100 r -120 120 a FREQUENCY (MHz) Figure 20. Single Tone FFT - 400 MSPS in Fin = 80 MHz, Ain = -3 dBFS, FSRHI = 2.0V 0 -20 -40 -60 im AMPLITUDE (dBFS) Product Preview - ADC Fin = 80 MHz, Ain = -3 dBFS, FSRHI = 2.0V -80 -100 -120 50 100 150 200 l 0 FREQUENCY (MHz) e Figure 21. Single Tone FFT - 500 MSPS r Fin = 80 MHz, Ain = -3 dBFS, FSRHI = 2.0V 0 -40 P AMPLITUDE (dBFS) -20 -60 -80 -100 -120 0 50 100 150 200 250 FREQUENCY (MHz) 28 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Theory of Operation Recommended Usage HMCAD1063 is a Dual channel 14-bit A-to-D Converter (ADC). The ADC employs a Pipeline Converter architecture. Each Pipeline Stage feeds its output data into the digital error correction and calibration logic, ensuring excellent differential linearity and no missing codes. Analog Input y in Reduced Swing Differential Signalling (RSDS) is selected by default. The I/O current is set to 1.75 mA compared to 3.5 mA for LVDS. This will result in the best power dissipation and data integrity for most applications. Standard LVDS I/O current can be selected through the SPI interface if desired. r The timing of the LVDS interface is provided in the LVDS timing diagram on page 13. Operation at common mode voltages of 5/9 of the analog supply voltage (1V for 1.8V supply voltage) is recommended even if performance will be good for the ranges specified. The VCM pin provides a voltage suitable as common mode voltage reference. The internal buffer for the VCM voltage can be switched off, and driving capabilities can be changed programming the vcm_drive_cfg register. a HMCAD1063 utilizes a parallel LVDS output. 2:1 muxes are inserted between the ADC output and LVDS interface, so that even numbered bits are muxed with the according odd numbered bits of each channel before being applied to the LVDS interface. The analog input to the HMCAD1063 is a switched capacitor sample-and-hold circuit optimized for differential operation. im HMCAD1063 uses internally generated references. The default differential reference value is 1V. This results in a differential input of -1V to correspond to the minimum code of the ADC, and a differential input of +1V to correspond to the max code This gives a default Full Scale Range of 2Vpp. Section "Register 0x21 - Full Scale Range Tuning" on page 22 describes how to adjust the Full Scale Range. P r e l HMCAD1063 operates from two sets of supplies and grounds. The analog supply and ground set is identified as AVDD and AVSS, while the digital set is identified by DVDD and DVSS. Figure 4. HMCAD1063 switched capacitor input Product Preview - ADC Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Figure 4 shows a simplified drawing of the switched capacitor input of HMCAD1073. During the Sample phase (S) the analog input signal is sampled on the sampling capacitors (CS). During the Hold Phase (H) the sampled signal is held to the succeeding pipeline stage. CS contributes to the total ADC input capacitance (CIN). The charge sampled to CS at the Sampling rate will represent a resistive load (RIN) to the ADC driver. The total ADC input capacitance (CIN) value can be found in "Digital and Switching Specifications" on page 3. Figure 5 shows a model of the ADC input including RC shunt and RIN. The CIN parameter is equivalent to the total capacitance between the ADC analog inputs. Values for RIN can be found in the section "DC Electrical Specifications" on page 3. A small external resistor (e.g. 22 ) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 29 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS For DC coupling the common mode input voltage from the ADC driver must match the VCM,IN specification given in "DC Electrical Specifications" on page 3. Preferably, the ADC common mode output voltage (VCM pin) should be used as reference to set the common mode input voltage. Due to the switched nature of the ADC input stage, there will be some kick-back going from the ADC input and back into the driver. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. This could reduce the ADC performance. To avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. Component Value C1 1 nF C2 1 nF R1 28 C3 10 pF R2 20 r in Recommended Analog Input component values: Differential amplifiers are often suited to terminate the kick-back efficiently. It is of utmost importance that the amplifier is placed close to the ADC input to minimize any transmission line effects on the trace from the amplifier to the ADC input. The bandwidth in this node should also be maximized to allow the kick-back to settle within the available time. In Figure 5 the ADC common mode setup for AC-Coupling is shown. By connecting the termination resistors (R1) to the ADC VCM output, the ADC Common mode voltage will be set up correctly given an AC-coupling capacitor (C1) to control the lower passband frequency. a A double balun configuration is recommended for high performance AC-coupled input network. Figure 5 shows a recommended configuration utilizing a double balun configuration. The balun termination resistors (R1) define the impedance of the input network. A shunt RC (R2 and C3) to ground from each of the input signals eliminates both differential and single ended large signal effects from the ADC kick-back charges. y AC-Coupling im Product Preview - ADC DC-Coupling Note that Start Up Time from Sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. P r e l Make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. It is important to minimize second order distortion. This type of transformer coupled input is the preferred configuration to optimize Signal to Noise Ratio. A differential amplifier or differential Variable Gain Amplifier may result in higher linearity since they most often are less dependent on a pure resistive load. Magnetic coupling between the transformers and PCB traces may impact channel crosstalk, and must hence be taken into account during PCB layout. The value of C1 must be defined based on the requirement to the high-pass cut-off frequency. Figure 5. Double Balun based input network 30 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Clock Input and Jitter Considerations Using PLL/VCOs as Clock Generator In HMCAD1063 only the rising edge of the clock is used. When the direct ADC clock generation is not available, a high performance PLL/VCO should be utilized to generate a low jitter master clock. This should be applied to the ADC either directly or through a fan out buffer. SNRjitter = - 20 * log(2 * * IN * Tjrms) (1) y r Fast Amplitude Detect (FAD) Output Fast Amplitude Detect (FAD) output bits are indicating the amplitude of the input signal with a very low latency, see "Digital and Switching Specifications" on page 3. Depending on the LVDS output mode settings, Table 6, either 0, 2 or 4 FAD bits are available. in where IN is the signal frequency, and Tjrms is the rootmean-square (rms) ADC clock jitter measured in seconds. The recommended PLL/VCOs for HMCAD1063 are HMC1032LP6GE for excellent clock jitter, and HMC 1033LP6GE for an excellent combination of low clock jitter and low power consumption. The recommended fan out buffer is HMC987LP5E. a The input clock can be supplied in a variety of formats. The clock pins are AC-coupled internally, hence a wide common mode voltage range is accepted. Differential clock sources such as LVDS, LVPECL or differential sine wave can be utilized. The clock input has 100 differential termination. Additional termination, if required by the clock driver, must be placed as close to the ADC clock pins as possible. The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in equation 1. The FAD will serve as a 2- or 4-bit low latency ADC, converting the analog input amplitude to a digital value. This allows the FAD outputs to be utilized as an Received Signal Strength Indicator, providing the signal strength at a lower latency compared to the Data output. See "Register 0x20 - LVDS Control" on page 20 for a detailed description. l im It is of utmost importance to limit the clock jitter for applications where jitter may limit the obtainable performance. This can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. Product Preview - ADC Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS P r e The jitter performance is improved with reduced edge times of the input clock. Hence, optimum jitter performance is obtained with LVDS or LVPECL clock with low edge times. For sine wave clock inputs, the amplitude should be as high as possible to minimize the edge time. To avoid exceeding the clock input maximum levels, a clamping diode can be utilized. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 31 HMCAD1063 Product Preview - 2.0214 Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Analog Input Bandwidth (AIBW) The maximum analog input frequency where proper ADC performance is achieved. Above this frequency missing codes will be expected. code are different from the theoretical values. A Full Scale Range fundamental is a sine wave where the lowest value gives minimum output code and the highest value gives maximum output code. Aperture delay (t AD) The delay difference between Analog and Clock inputs to sampling. Noise Power Bandwidth (NoiseBW) The analog input frequency where the power of the fundamental is reduced by 3 dB compared to the low-frequency value. y tAD = Tsd -Tid, where Cross Talk (Xtlk) Crosstalk is the signal coupling between the ADC channels, and is measured by applying full scale signals to both an adjacent channel and to the channel of interest. The crosstalk is the ratio of power in between the signal applied to the adjacent channel and the signal power at the channel of interest that origin from the adjacent channel. im Decibel - carrier (dBc) A unit where the parameter is measured by comparing to the applied fundamental (or carrier) power in the given test. Decibel - Full Scale (dBFS) A unit where the parameter is measured by comparing to the theoretical maximum fundamental power based on Full Scale Range. e l Differential Non-Linearity (DNL) The DNL is the deviation from the ideal voltage that causes a change of one single code (1 LSB). The DNL plot is a diagram showing this deviation for all the codes in the ADC. The DNL parameter is the worst case value on this diagram. P r Effective Number of Bits (ENOB) Measures the converter performance in terms of number of bit resolution, based on a perfect ADC with quantization noise. ENOB = (SNDR- 1.76)/6.02. Full Scale Range (FSR) The voltage difference at the analog input of the ADC between the voltage that will generate the maximum digital output code, and the voltage that will generate the minimum digital output code. When referring to deviation in Full Scale Range this means that the analog voltages giving max/min output 32 r Aperture jitter (tjrms) The sample-to-sample variation in Aperture delay. Gain error (Gabs) The deviation from ideal Full Scale Range. This parameter is independent from Grel. Gain flatness The input frequency range where the Gain variation is within the specified number of dB. Gain matching (Grel) The mismatch in Full Scale Range between the ADC channels. This parameter is independent from Gabs. a Tsd delay from Clock input to sampling, and Tid delay from Analog input to sampling. Integral Non-Linearity (INL) The INL is the deviation of the ADC transfer function from an ideal straight line. The INL plot is this deviation generated with the best fit method for the ADC Full Scale range. The INL parameter is the worst case value on this line. in Product Preview - ADC Definition of Terms Intermodulation Distortion (IMD) IMDs are spectral spurs due to nonlinearities that occur when two frequencies f1 and f2 are processed simultaneously. IMD2 is the worst 2nd order spur, i.e. f1+f2 or f1-f2. In-Band IMD3 is the worst 3rd order spur close to the original frequencies, i.e. 2f1-f2 or 2f2-f1. IMD3 is the worst of all 3rd order spurs: 2f1-f2, 2f2-f1, 2f1+f2, and 2f1+f1. Signal to Noise Ratio (SNR) The ratio of the power of the fundamental to the power of the noise measured in dB. SNR excludes DC, harmonics and interleaving spurs. Signal to Noise and Distortion Ratio (SNDR) The ratio of the power of the fundamental to the power of the noise and distortion measured in dB. SNDR excludes DC. Spurious Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the power of the highest harmonic or spurious component. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com HMCAD1063 Product Preview - 2.0214 Item Contents HMCAD1063 Evaluation PCB Evaluation Kit HMCAD1063 Evaluation PCB Zynq 7020 evaluation board - Zedboard, USB memory stick containing users manual and software, Ethernet cable, attenuators. im Evaluation PCB Only Product Preview - ADC Evaluation Order Information in a r y Dual Channel 14-bit A-to-D Converter (ADC) 250/400/500 MSPS Part Number EV1HMCAD1063LP9DE [1] EK1HMCAD1063LP9DE [2] l [1] Reference this number when ordering Evaluation PCB Only [2] Reference this number when ordering an HMCAD1063 Evaluation KIt Version v0.0114 e Document Changes P r Product Preview - 2.0214 Comment Initial release Specifications completed, performance plots added, FSR adjusted The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50 Ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request. ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com Application Support: adcsupport@hittite.com 33