K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Document Title 512Kx36/x32 & 1Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History 1. Initial draft 1. Add JTAG Scan Order 1. Add x32 org and industrial temperature . 2. Add 165FBGA package Draft Date Feb. 23. 2001 May. 10. 2001 Aug. 30. 2001 Remark Preliminary Preliminary Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM 16Mb SB/SPB Synchronous SRAM Ordering Information Org. Mode VDD Speed SB ; Access Time(ns) SPB ; Cycle Time(MHz) K7B161825A-Q(H/F)C(I)65/75/85 SB 3.3 6.5/7.5/8.5ns K7A161880A-QC(I)25/22/20/16/14 Part Number PKG SPB(2E1D) 1.8 250/225/200/167/138MHz K7A161800A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D) 3.3 250/225/200/167/138MHz K7A161801A-QC(I)25/22/20/16/14 SPB(2E2D) 3.3 250/225/200/167/138MHz SB 3.3 6.5/7.5/8.5ns 512Kx32 K7A163280A-QC(I)25/22/20/16/14 SPB(2E1D) 1.8 K7A163200A-QC(I)25/22/20/16/14 SPB(2E1D) 3.3 Q :100TQFP 250/225/200/167/138MHz H : 119BGA F : 165FBGA 250/225/200/167/138MHz K7A163201A-QC(I)25/22/20/16/14 SPB(2E2D) 3.3 250/225/200/167/138MHz K7B163625A-Q(H/F)C(I)65/75/85 SB 3.3 6.5/7.5/8.5ns K7A163680A-QC(I)25/22/20/16/14 1Mx18 K7B163225A-QC(I)65/75/85 512Kx36 SPB(2E1D) 1.8 250/225/200/167/138MHz K7A163600A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D) 3.3 250/225/200/167/138MHz K7A163601A-QC(I)25/22/20/16/14 3.3 250/225/200/167/138MHz SPB(2E2D) -2- Temp C (Commercial Temperature Range) I (Industrial Temperature Range) Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM 512Kx36/32 & 1Mx18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION * Synchronous Operation. * On-Chip Address Counter. * Self-Timed Write Cycle. * On-Chip Address and Control Registers. * 3.3V+0.165V/-0.165V Power Supply. * I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O * 5V Tolerant Inputs Except I/O Pins. * Byte Writable Function. * Global Write Enable Controls a full bus-width write. * Power Down State via ZZ Signal. * LBO Pin allows a choice of either a interleaved burst or a linear burst. * Three Chip Enables for simple depth expansion with No Data Contention only for TQFP. * Asynchronous Output Enable Control. * ADSP, ADSC, ADV Burst Control Pins. * TTL-Level Three-State Output. * 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package) * 165FBGA(11x15 ball aray) with body size of 13mmx15mm. * Operating in commeical and industrial temperature range. The K7B163625A, K7B163225A and K7B161825A are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(32/18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7B163625A, K7B163225A and K7B161825A are fabricated using SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP, 119BGA and 165FBGA package. Multiple power and ground pins are utilized to minimize ground bounce. FAST ACCESS TIMES -75 -85 Unit Cycle Time PARAMETER Symbol -65 tCYC 7.5 8.5 10 ns Clock Access Time tCD 6.5 7.5 8.5 ns Output Enable Access Time tOE 3.5 3.5 4.0 ns LOGIC BLOCK DIAGRAM CLK LBO BURST CONTROL LOGIC CONTROL REGISTER ADV ADSC A0~A1 512Kx36/32 , 1Mx18 MEMORY ARRAY A0~A1 A0~A18 or A0~A19 ADSP ADDRESS REGISTER A2~A18 or A2~A19 DATA-IN REGISTER CONTROL REGISTER CS1 CS2 CS2 GW BW WEx (x=a,b,c,d or a,b) BURST ADDRESS COUNTER OUTPUT BUFFER CONTROL LOGIC OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb7 DQPa ~ DQPd DQPa,DQPb -3- Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM ADV A8 A9 82 81 49 50 A16 ADSP A15 ADSC 84 83 OE 85 48 BW 86 A14 GW 87 47 CLK 88 A13 VSS 89 46 VDD 90 A12 CS2 91 45 WEa 92 A11 WEb 93 44 WEc 94 A10 WEd 95 43 CS2 96 A17 CS1 97 42 A7 98 A18 A6 99 100 Pin TQFP (20mm x 14mm) 31 32 33 34 35 36 37 38 39 40 41 A4 A3 A2 A1 A0 N.C. N.C. VSS VDD K7B163625A(512Kx36) K7B163225A(512Kx32) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO NC/DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 NC/DQPd 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC PIN NAME SYMBOL A0 - A18 PIN NAME TQFP PIN NO. Address Inputs 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50,81,82,99,100 ADV Burst Address Advance 83 ADSP Address Status Processor 84 ADSC Address Status Controller 85 CLK Clock 89 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 WEx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 GW Global Write Enable 88 BW Byte Write Enable 87 ZZ Power Down Input 64 LBO Burst Mode Control 31 SYMBOL PIN NAME TQFP PIN NO. VDD VSS Power Supply(+3.3V) Ground 15,41,65,91 17,40,67,90 N.C. No Connect 14,16,38,39,66 DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd or NC Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 VDDQ Output Power Supply (2.5V or 3.3V) Output Ground 4,11,20,27,54,61,70,77 VSSQ 5,10,21,26,55,60,71,76 Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -4- Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM ADSP ADV A8 A9 83 82 81 49 50 A16 A17 ADSC 48 OE 85 A15 BW 86 84 GW 87 47 CLK 88 A14 VSS 89 46 VDD 90 A13 CS2 91 45 WEa 92 A12 WEb 93 44 N.C. 94 A11 N.C. 95 43 CS2 96 A18 CS1 97 42 A7 98 A19 A6 99 100 Pin TQFP (20mm x 14mm) 31 32 33 34 35 36 37 38 39 40 41 A4 A3 A2 A1 A0 N.C. N.C. VSS VDD K7B161825A(1Mx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 N.C. VDD N.C. VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb N.C. VSSQ VDDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 N.C. N.C. VDDQ VSSQ N.C. DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS N.C. VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A0 - A 19 Address Inputs ADV ADSP ADSC CLK CS1 CS2 CS2 WEx(x=a,b) OE GW BW ZZ LBO Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 PIN NAME TQFP PIN NO. VDD VSS N.C. Power Supply(+3.3V) Ground No Connect 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29, 30,38,39,51,52,53,56,57, 66,75,78,79,95,96 DQa0 ~ a 7 DQb0 ~ b 7 DQPa, Pb Data Inputs/Outputs 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 VDDQ Output Power Supply (2.5V or 3.3V) Output Ground 4,11,20,27,54,61,70,77 VSSQ 5,10,21,26,55,60,71,76 Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -5- Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM 119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7B163625A(512Kx36) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC A A ADSC A A NC C NC A A VDD A A NC D DQc DQPc VSS NC VSS DQPb DQb E DQc DQc VSS CS1 VSS DQb DQb F VDDQ DQc VSS OE VSS DQb VDDQ G DQc DQc WEc ADV WEb DQb DQb H DQc DQc VSS GW VSS DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS CLK VSS DQa DQa L DQd DQd WEd NC WEa DQa DQa M VDDQ DQd VSS BW VSS DQa VDDQ N DQd DQd VSS A1* VSS DQa DQa P DQd DQPd VSS A0* VSS DQPa DQa R NC A LBO VDD NC A NC T NC NC A A A NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME SYMBOL PIN NAME A A0, A1 Address Inputs Burst Count Address VDD VSS Power Supply(+3.3V) Ground ADV ADSP ADSC CLK CS1 WEx (x=a,b,c,d) Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Byte Write Inputs N.C. No Connect DQa DQb DQc DQd DQPa~Pd Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outpus OE GW BW ZZ LBO Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control VDDQ Output Power Supply (2.5V or 3.3V) TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output -6- Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM 119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7B161825A(1Mx18) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC A A ADSC A A NC C NC A A VDD A A NC D DQb NC VSS NC VSS DQPa NC E NC DQb VSS CS 1 VSS NC DQa F VDDQ NC VSS OE VSS DQa VDDQ G NC DQb WEb ADV VSS NC DQa H DQb NC VSS GW VSS DQa NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQb VSS CLK VSS NC DQa L DQb NC VSS NC WEa DQa NC M VDDQ DQb VSS BW VSS NC VDDQ N DQb NC VSS A1* VSS DQa NC P NC DQPb VSS A0* VSS NC DQa R NC A LBO VDD NC A NC T NC A A NC A A ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note : * A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME SYMBOL PIN NAME A A0,A1 Address Inputs Burst Count Address VDD VSS Power Supply(+3.3V) Ground ADV ADSP ADSC CLK CS1 WEx (x=a,b) Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Byte Write Inputs N.C. No Connect DQa DQb DQPa~Pb Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outpus VDDQ Output Power Supply (2.5V or 3.3V) OE GW BW ZZ LBO Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output -7- Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM 165-PIN FGBA PACKAGE CONFIGURATIONS(TOP VIEW) K7B163625A(512Kx36) 1 2 3 4 5 6 7 8 9 10 11 A NC A CS1 WEc WEb CS2 BW ADSC ADV A NC B NC A CS2 WEd WEa CLK GW OE ADSP A NC C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb H NC VSS NC VDD VSS VSS VSS VDD NC NC ZZ J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa N DQPd NC VDDQ VSS NC A VSS VSS VDDQ NC DQPa P NC NC A A TDI A 1* TDO A A A A R LBO NC A A TMS A 0* TCK A A A A Note : * A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME SYMBOL PIN NAME A A0, A1 Address Inputs Burst Count Address VDD VSS Power Supply(+3.3V) Ground ADV ADSP ADSC CLK CS1 WEx (x=a,b,c,d) Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Byte Write Inputs N.C. No Connect DQa DQb DQc DQd DQPa~Pd Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outpus OE GW BW ZZ LBO Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control VDDQ Output Power Supply (2.5V or 3.3V) TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output -8- Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM 165-PIN FGBA PACKAGE CONFIGURATIONS(TOP VIEW) K7B161825A(1Mx18) 1 2 3 4 5 6 7 8 9 10 11 A NC A CS1 WEb NC CS2 BW ADSC ADV A A B NC A CS2 NC WEa CLK GW OE ADSP A NC C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa D NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa E NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa F NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa G NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa H NC VSS NC VDD VSS VSS VSS VDD NC NC ZZ J DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC K DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC L DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC M DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC N DQPb NC VDDQ VSS NC A VSS VSS VDDQ NC NC P NC NC A A TDI A 1* TDO A A A A R LBO NC A A TMS A 0* TCK A A A A Note : * A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME SYMBOL PIN NAME A A0,A1 Address Inputs Burst Count Address VDD VSS Power Supply(+3.3V) Ground ADV ADSP ADSC CLK CS1 WEx (x=a,b) Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Byte Write Inputs N.C. No Connect DQa DQb DQPa~Pb Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outpus VDDQ Output Power Supply (2.5V or 3.3V) OE GW BW ZZ LBO Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output -9- Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM FUNCTION DESCRIPTION The K7B163625A, K7B163225A and K7B161825A are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the output pins. Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and individual byte write operation. All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high and BW is low. In K7B163625M, a 512Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd. CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded. ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address increases internally for the next access of the burst when ADV is sampled low. Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst) Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 1 0 0 BQ TABLE LBO PIN A0 1 0 1 0 (Linear Burst) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. - 10 - Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS1 CS2 CS2 ADV WRITE CLK ADDRESS ACCESSED OPERATION H X X ADSP ADSC X L X X N/A Not Selected L L X L X X X N/A Not Selected L X H L X X X N/A Not Selected L L X X L X X N/A Not Selected L X H X L X X N/A Not Selected L H L L X X X External Address Begin Burst Read Cycle L H L H L X L External Address Begin Burst Write Cycle L H L H L X H External Address Begin Burst Read Cycle X X X H H L H Next Address Continue Burst Read Cycle H X X X H L H Next Address Continue Burst Read Cycle X X X H H L L Next Address Continue Burst Write Cycle H X X X H L L Next Address Continue Burst Write Cycle X X X H H H H Current Address Suspend Burst Read Cycle H X X X H H H Current Address Suspend Burst Read Cycle X X X H H H L Current Address Suspend Burst Write Cycle H X X X H H L Current Address Suspend Burst Write Cycle Notes : 1. X means "Dont Care". 2. The rising edge of clock is symbolized by . 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE ( x36 / x32) GW BW WEa WEb H H X X H L H H H L L H H L H L H L H H L L L X X WEc WEd OPERATION X X READ H H READ H H WRITE BYTE a H H WRITE BYTE b H L L WRITE BYTE c and d L L L WRITE ALL BYTEs X X X WRITE ALL BYTEs Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(). WRITE TRUTH TABLE(x18) GW BW WEa WEb OPERATION H H X X READ H L H H READ H L L H WRITE BYTE a H L H L WRITE BYTE b H L L L WRITE ALL BYTEs L X X X WRITE ALL BYTEs Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ). - 11 - Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM ASYNCHRONOUS TRUTH TABLE Operation ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ Read L H High-Z Write L X Din, High-Z Deselected L X High-Z Notes 1. X means "Dont Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING VDD -0.3 to 4.6 V VDDQ VDD V Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to V SS UNIT Voltage on Input Pin Relative to VSS VIN -0.3 to VDD+0.3 V Voltage on I/O Pin Relative to V SS VIO -0.3 to VDDQ+0.3 V Power Dissipation Storage Temperature Operating Temperature PD 1.6 W TSTG -65 to 150 C Commercial TOPR 0 to 70 C Industrial TOPR -40 to 85 C TBIAS -10 to 85 C Storage Temperature Range Under Bias *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS at 3.3V I/O(0C TA 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT VDD 3.135 3.3 3.465 V VDDQ 3.135 3.3 3.465 V VSS 0 0 0 V * The above parameters are also guaranteed at industrial temperature range. OPERATING CONDITIONS at 2.5V I/O(0C TA 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT VDD 3.135 3.3 3.465 V VDDQ 2.375 2.5 2.9 V VSS 0 0 0 V * The above parameters are also guaranteed at industrial temperature range. CAPACITANCE*(TA=25C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION MIN MAX UNIT CIN VIN=0V - 5 pF COUT VOUT=0V - 7 pF *Note : Sampled not 100% tested. - 12 - Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0C to +70C) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD -2 +2 A Output Leakage Current IOL Output Disabled, Vout=VSS to V DDQ -2 +2 A -65 - 270 Operating Current ICC ZZVIL , Cycle Time tCYC Min -75 - 250 -85 - 230 Device deselected, IOUT=0mA, -65 - 100 ISB Standby Current ISB1 Device Selected, IOUT=0mA, mA ZZVIL, f=Max, All Inputs0.2V or -75 - 90 VDD-0.2V -85 - 80 - 70 mA Device deselected, I OUT=0mA, ZZ0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZVDD-0.2V, Notes 1,2 mA ISB2 f=Max, All InputsVIL or VIH - 60 mA Output Low Voltage(3.3V I/O) VOL IOL=8.0mA - 0.4 V Output High Voltage(3.3V I/O) VOH IOH=-4.0mA 2.4 - V Output Low Voltage(2.5V I/O) VOL IOL=1.0mA - 0.4 V Output High Voltage(2.5V I/O) VOH IOH=-1.0mA Input Low Voltage(3.3V I/O) VIL Input High Voltage(3.3V I/O) 2.0 - V -0.3* 0.8 V VIH 2.0 VDD+0.3** V Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.3** V 3 3 Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. Data states are all zero. 4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V VIH VSS VSS-1.0V 20% tCYC(MIN) TEST CONDITIONS (VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70C) PARAMETER VALUE Input Pulse Level(for 3.3V I/O) 0 to 3.0V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2 Output Load See Fig. 1 * The above parameters are also guaranteed at industrial temperature range. - 13 - Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Output Load(A) Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50 Dout Zo=50 30pF* VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O 319 / 1667 Dout 353 / 1538 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0C to +70C) PARAMETER SYMBOL -65 -75 -85 MIN MAX MIN MAX MIN MAX UNIT Cycle Time tCYC 7.5 - 8.5 - 10 - ns Clock Access Time tCD - 6.5 - 7.5 - 8.5 ns Output Enable to Data Valid tOE - 3.5 - 3.5 - 4.0 ns Clock High to Output Low-Z tLZC 2.5 - 2.5 - 2.5 - ns Output Hold from Clock High tOH 2.5 - 2.5 - 2.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 3.5 - 3.5 - 4.0 ns Clock High to Output High-Z tHZC - 3.8 - 4.0 - 5.0 ns Clock High Pulse Width tCH 2.2 - 2.5 - 3.0 - ns Clock Low Pulse Width tCL 2.2 - 2.5 - 3.0 - ns Address Setup to Clock High tAS 1.5 - 2.0 - 2.0 - ns Address Status Setup to Clock High tSS 1.5 - 2.0 - 2.0 - ns Data Setup to Clock High tDS 1.5 - 2.0 - 2.0 - ns tWS 1.5 - 2.0 - 2.0 - ns Address Advance Setup to Clock High tADVS 1.5 - 2.0 - 2.0 - ns Chip Select Setup to Clock High tCSS 1.5 - 2.0 - 2.0 - ns Address Hold from Clock High tAH 0.5 - 0.5 - 0.5 - ns Address Status Hold from Clock High tSH 0.5 - 0.5 - 0.5 - ns Write Setup to Clock High (GW, BW, WEX) Data Hold from Clock High tDH 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High (GW, BW, WEX) tWH 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - cycle Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. - 14 - Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to V DD through a resistor. TDO should be left unconnected. JTAG Instruction Coding JTAG Block Diagram IR2 IR1 IR0 Instruction SRAM CORE PI PI TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. Notes 0 0 0 SAMPLE-Z Boundary Scan Register 1 0 0 1 IDCODE 2 0 1 0 SAMPLE-Z Boundary Scan Register 1 0 1 1 BYPASS Bypass Register 3 1 0 0 SAMPLE Boundary Scan Register 4 1 0 1 BYPASS Bypass Register 3 1 1 0 BYPASS Bypass Register 3 1 1 1 BYPASS Bypass Register 3 Identification Register NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initiated to V SS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction dose not places DQs in Hi-Z. Control Signals TMS TCK TDO Output TAP Controller TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 Select DR 0 1 1 Exit2 DR 1 Update DR 0 - 15 - 1 Capture IR 0 0 1 Exit1 DR 0 Pause DR 1 Select IR 0 1 Capture DR 0 Shift DR 1 1 1 0 0 Shift IR 1 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register Boundary Scan 512Kx36 3 bits 1 bits 32 bits 75 bits 1Mx18 3 bits 1 bits 32 bits 75 bits ID REGISTER DEFINITION Part Revision Number (31:28) Part Configuration (27:18) Vendor Definition (17:12) Samsung JEDEC Code (11: 1) Start Bit(0) 512Kx36 0000 00111 00100 XXXXXX 00001001110 1 1Mx18 0000 01000 00011 XXXXXX 00001001110 1 119BGA BOUNDARY SCAN EXIT ORDER(x36) 119BGA BOUNDARY SCAN EXIT ORDER(x18) 1 2T NC CLK 4K 39 1 2T A CLK 4K 39 2 1R NC ADV 4G 40 2 1R NC ADV 4G 40 3 4T A ADSC 4B 41 3 6T A ADSC 4B 41 4 4H GW ADSP 4A 42 4 4H GW ADSP 4A 42 5 5R NC BW 4M 43 5 5R NC BW 4M 43 6 5T A WEc 3G 44 6 5T A WEb 3G 44 7 5L WEa A 3B 45 7 5L WEa A 3B 45 8 7R NC A 3A 46 8 7R NC A 3A 46 9 6R A A 2B 47 9 6R A A 2B 47 10 7T ZZ CS1 4E 48 10 7T ZZ CS1 4E 48 11 6P DQPa A 3C 49 11 6P NC A 3C 49 12 7N DQa A 2C 50 12 7N NC A 2C 50 13 6M DQa A 2A 51 13 6M NC A 2A 51 14 7L DQa DQPc 2D 52 14 7L NC NC 2D 52 15 6K DQa DQc 1E 53 15 6K NC NC 1E 53 16 7P DQa DQc 2F 54 16 7P DQa NC 2F 54 17 6N DQa DQc 1G 55 17 6N DQa NC 1G 55 18 6L DQa DQc 2H 56 18 6L DQa NC 2H 56 19 7K DQa DQc 1D 57 19 7K DQa DQb 1D 57 20 5J NC DQc 2E 58 20 5J NC DQb 2E 58 21 6H DQb DQc 2G 59 21 6H DQa DQb 2G 59 22 7G DQb DQc 1H 60 22 7G DQa DQb 1H 60 23 6F DQb DQd 2K 61 23 6F DQa DQb 2K 61 24 7E DQb DQd 1L 62 24 7E DQa DQb 1L 62 25 7D DQb DQd 2M 63 25 6D DQPa DQb 2M 63 26 7H DQb DQd 1N 64 26 7H NC DQb 1N 64 27 6G DQb DQd 1P 65 27 6G NC DQPb 2P 65 28 6E DQb DQd 1K 66 28 6E NC NC 1K 66 29 6D DQPb DQd 2L 67 29 7D NC NC 2L 67 30 7B NC DQd 2N 68 30 7B NC NC 2N 68 31 6C A DQPd 2P 69 31 6C A NC 1P 69 32 5C A WEd 3L 70 32 5C A NC 3L 70 33 6A A LBO 3R 71 33 6A A LBO 3R 71 34 5B A A 2R 72 34 5B A A 2R 72 35 5A A A 3T 73 35 5A A A 3T 73 36 4F OE A1 4N 74 36 4F OE A1 4N 74 37 5G WEb A0 4P 75 37 5G NC A0 4P 75 38 6B A 38 6B A NOTE, NC ; Dont Care - 16 - Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM 165FBGA BOUNDARY SCAN EXIT ORDER(x36) 165FBGA BOUNDARY SCAN EXIT ORDER(x18) 1 1R LBO CLK 6B 39 1 1R LBO CLK 6B 39 2 6N A NC 11B 40 2 6N A NC 11B 40 3 11P A NC 1A 41 3 11P A NC 1A 41 4 8P A CS2 6A 42 4 8P A CS2 6A 42 5 8R A WEa 5B 43 5 8R A WEa 5B 43 6 9R A WEb 5A 44 6 9R A NC 5A 44 7 9P A WEc 4A 45 7 9P A WEb 4A 45 8 10P A WEd 4B 46 8 10P A NC 4B 46 9 10R A CS2 3B 47 9 10R A CS2 3B 47 10 11R A CS1 3A 48 10 11R A CS1 3A 48 11 11H ZZ A 2A 49 11 11H ZZ A 2A 49 12 11N DQa A 2B 50 12 11N NC A 2B 50 13 11M DQa NC 1B 51 13 11M NC NC 1B 51 14 11L DQa DQc 1C 52 14 11L NC NC 1C 52 15 11K DQa DQc 1D 53 15 11K NC NC 1D 53 16 11J DQa DQc 1E 54 16 11J NC NC 1E 54 17 10M DQa DQc 1F 55 17 10M DQa NC 1F 55 18 10L DQa DQc 1G 56 18 10L DQa NC 1G 56 19 10K DQa DQc 2D 57 19 10K DQa DQb 2D 57 20 10J DQa DQc 2E 58 20 10J DQa DQb 2E 58 21 11G DQb DQc 2F 59 21 11G DQa DQb 2F 59 22 11F DQb DQc 2G 60 22 11F DQa DQb 2G 60 23 11E DQb DQd 1J 61 23 11E DQa DQb 1J 61 24 11D DQb DQd 1K 62 24 11D DQa DQb 1K 62 25 10G DQb DQd 1L 63 25 11C DQa DQb 1L 63 26 10F DQb DQd 1M 64 26 10F NC DQb 1M 64 27 10E DQb DQd 2J 65 27 10E NC DQb 1N 65 28 10D DQb DQd 2K 66 28 10D NC NC 2K 66 29 11C DQb DQd 2L 67 29 10G NC NC 2L 67 30 11A NC DQd 2M 68 30 11A A NC 2M 68 31 10A A DQd 1N 69 31 10A A NC 2J 69 32 10B A A 3P 70 32 10B A A 3P 70 33 9A ADV A 3R 71 33 9A ADV A 3R 71 34 9B ADSP A 4R 72 34 9B ADSP A 4R 72 35 8A ADSC A 4P 73 35 8A ADSC A 4P 73 36 8B OE A1 6P 74 36 8B OE A1 6P 74 37 7A BW A0 6R 75 37 7A BW A0 6R 75 38 7B GW 38 7B GW NOTE, NC ; Dont Care - 17 - Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM JTAG DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power Supply Voltage VDD 3.135 3.3 3.465 V Input High Level ( 3.3V I/O / 2.5V I/O ) VIH 2.0 / 1.7 - VDD+0.3 V Input Low Level ( 3.3V I/O / 2.5V I/O ) VIL -0.3 - 0.8 / 0.7 V Output High Voltage( 3.3V I/O / 2.5V I/O ) VOH 2.4 / 2.0 - - V Output Low Voltage( 3.3V I/O / 2.5V I/O ) VOL - - 0.4 / 0.4 V Note 1 NOTE : The input level of SRAM pin is to follow the SRAM DC specification. 1. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V. JTAG AC TEST CONDITIONS Symbol Min Unit Input High/Low Level( 3.3V I/O , 2.5V I/O ) Parameter VIH/VIL 3.0/0 , 2.5/0 V Input Rise/Fall Time( 3.3V I/O , 2.5V I/O ) TR/TF 1.0/1.0 , 1.0/1.0 ns VDDQ/2 V Input and Output Timing Reference Level Note JTAG AC Characteristics Symbol Min Max Unit TCK Cycle Time Parameter tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tCHCH tCHCL tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX t CLCH TMS TDI PI (SRAM) tCLQV TDO - 18 - Aug 2001 Rev 0.2 - 19 - Data Out OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS tOE Q1-1 tHZOE tADVH tWH tSS A2 tSH Q2-1 tCD tOH Q2-2 Q2-3 A3 Q2-4 (ADV INSERTS WAIT STATE) BURST CONTINUED WITH NEW BASE ADDRESS tCYC tCL NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx.= L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tADVS tCSH tWS tLZOE A1 tAH tSH tCH TIMING WAVEFORM OF READ CYCLE Q3-1 Q3-2 Q3-3 Undefined Dont Care Q3-4 tHZC K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Aug 2001 Rev 0.2 - 20 - Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK Q0-3 tCSS tAS tSS Q0-4 A1 tLZOE tCSH tAH tSH D1-1 tCL tCYC tCH A2 D2-1 D2-2 (ADV SUSPENDS BURST) D2-2 D2-3 (ADSC EXTENDED BURST) TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 A3 tDS tADVS tWS tSS D3-2 tDH tADVH tWH tSH D3-3 Undefined Dont Care D3-4 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Aug 2001 Rev 0.2 - 21 - Data Out Data In OE ADV CS WRITE ADDRESS ADSP CLOCK tHZC tSS A1 tLZC tCD tSH Q1-1 tHZOE tAS A2 tCL tCYC tDS tADVS tWS tAH tCH D2-1 tDH tADVH tWH A3 tLZOE tOE Q3-1 Q3-2 Q3-3 tOH Q3-4 TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH) Undefined Dont Care K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Aug 2001 Rev 0.2 - 22 - Data In Data Out OE ADV CS WRITE ADDRESS ADSC CLOCK tCSS tSS A1 tLZOE tOE tCSH tSH Q1-1 A2 Q2-1 A3 Q3-1 A4 Q4-1 tHZOE D5-1 A5 tDS tWS D6-1 A6 tDH tWH D7-1 A7 tWS tCD A8 A9 Q8-1 tCL tCYC tWH tCH TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH) Undefined Dont Care Q9-1 tOH K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Aug 2001 Rev 0.2 - 23 - Data In Data Out OE ADV CS WRITE ADDRESS ADSP CLOCK tCSS tSS tOE tCSH tLZOE A1 tSH Q1-1 A2 Q2-1 A3 tAS Q3-1 A4 tAH tCYC tCH A5 Q4-1 tCL tHZOE D5-1 A6 tDS D6-1 tDH A7 D7-1 tCD A8 Q8-1 A9 TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH) Q9-1 tOH Undefined Dont Care K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Aug 2001 Rev 0.2 - 24 - ZZ Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS A1 tLZOE tOE tCSH tAH tSH Q1-1 ZZ Setup Cycle tPDS tHZC Sleep State tPUS tCL ZZ Recovery Cycle tCYC tCH TIMING WAVEFORM OF POWER DOWN CYCLE tWS Normal Operation Mode tHZOE A2 D2-1 tWH Undefined Dont Care D2-2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 512Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. I/O[0:71] Data Address A[0:19] A[19] A[0:18] A[19] A[0:18] Address Data Address Data CLK CS2 CS2 CS2 CS2 CLK Microprocessor Address ADSC CLK WEx OE Cache Controller 512Kx36 SB SRAM ADSC WEx (Bank 0) OE 512Kx36 SB SRAM (Bank 1) CS1 CS1 ADV CLK ADSP ADV ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) CLOCK tSS tSH ADSP tAS ADDRESS [0:n] tAH A1 A2 tWS tWH WRITE tCSS tCSH CS1 Bank 0 is selected by CS2, and Bank 1 deselected by CS2 An+1 tADVS Bank 0 is deselected by CS2 , and Bank 1 selected by CS2 tADVH ADV OE tOE Data Out (Bank 0) Data Out (Bank 1) tLZOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 *Notes : n = 14 32K depth , 16 128K depth , 18 512K depth , 15 64K depth 17 256K depth 19 1M depth Q2-2 Q2-3 Q2-4 Dont Care - 25 - Undefined Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 1Mx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic. I/O[0:71] Data Address A[20] A[0:20] A[20] A[0:19] Address Data CLK Microprocessor CS2 CS2 CS2 ADSC CLK WEx OE Cache Controller Address Data CS2 CLK Address A[0:19] 1Mx18 SB SRAM CLK ADSC WEx (Bank 0) OE (Bank 1) CS1 CS1 ADV 1Mx18 SB SRAM ADV ADSP ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) CLOCK tSS tSH ADSP tAS ADDRESS [0:n] tAH A1 A2 tWS tWH WRITE tCSS tCSH CS1 Bank 0 is selected by CS2, and Bank 1 deselected by CS2 An+1 tADVS Bank 0 is deselected by CS2 , and Bank 1 selected by CS2 tADVH ADV OE tOE Data Out (Bank 0) Data Out (Bank 1) tLZOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 *Notes : n = 14 16 18 20 32K depth , 128K depth , 512K depth , 2M depth 15 64K depth 17 256K depth 19 1M depth Q2-2 Q2-3 Q2-4 Dont Care - 26 - Undefined Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 22.00 0.30 20.00 0.20 0~8 0.10 0.127 +- 0.05 16.00 0.30 14.00 0.20 0.10 MAX (0.83) 0.50 0.10 #1 0.65 (0.58) 0.30 0.10 0.10 MAX 1.40 0.50 0.10 - 27 - 0.10 1.60 MAX 0.05 MIN Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM 119BGA PACKAGE DIMENSIONS 14.000.10 1.27 1.27 22.000.10 Indicator of Ball(1A) Location 20.500.10 C0.70 C1.00 0.7500.15 1.50REF 0.600.10 0.600.10 12.500.10 NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX. - 28 - Aug 2001 Rev 0.2 K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM 165 FBGA PACKAGE DIMENSIONS 13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array A B Top View C Side View D A F E G B Bottom View H E Symbol Value Units Note Symbol Value Units A 15 0.1 mm E 1.0 mm B 13 0.1 mm F 14.0 mm C 1.3 0.1 mm G 10.0 mm D 0.35 0.05 mm H 0.45 0.05 mm - 29 - Note Aug 2001 Rev 0.2