AW9523B datasheet May 2016 V1.1.1 16 MULTI-FUNCTION LED DRIVER AND GPIO CONTROLLER WITH I2C INTERFACE FEATURES INTRODUCTION 16 multi-function I/O, each for LED drive (current-source dimming) or GPIO mode AW9523B is a 16 multi-function LED driver and GPIO controller. Any of the 16 I/O ports can be configured as LED drive mode or GPIO mode. Furthermore, any GPIO can be configured as an input or an output independently. 256 steps linear dimming in LED drive mode Any GPIO can be configured as an input or an output independently Support interrupt, 8us deglitch, low-level active 2 Standard I C interface, AD1/AD0 select 2 I C device address SDA, SCL, SHDN, and all GPIO can accept in 1.8V logic input ESD protection: 4000V HBM (MIL-STD-883H Method 3015.8 standard Latch-up 450mA JEDEC STANDARD NO.78C SEPTEMBER 2010 standard After power on, all the 16 I/O ports are configured as GPIO output as default, which 2 default states are set according to the I C device address selection inputs, AD0 and AD1. All I/O ports configured as inputs are continuously monitored for state changes. State changes are indicated by the INTN output. When AW9523B reads GPIO state 2 through the I C interface, the interrupt is cleared. Interrupt has 8us deglitch. APPLICATION RANGE When the I/O ports are configured as LED drive mode, AW9523B can set the current of LED drive between 0~IMAX by 2 I C interface, which is divided by 256 steps linear dimming. The default maximum current (IMAX) is 37mA, and IMAX can be changed in GCR register. Cell Phone PDA/MP3/MP4/CD/Minidiskplay AW9523B is available in TQFN4X4-24L package, and 2.5V~5.5V power supply. Supply shutdown function, low-level active 2.5V~5.5V power supply PIN CONFIGURATION AND MARKING AW9523B MARK 13 P0_7 14 P1_4 15 P1_5 16 P1_6 17 P1_7 18 AD0 AW9523B TOP VIEW SCL 19 12 P0_6 SDA 20 11 P0_5 25 GND VCC 21 INTN 22 10 P0_4 9 GND 4 5 6 P0_0 P0_1 3 P1_3 P0_2 P1_2 7 2 AD1 24 P1_1 P0_3 1 8 P1_0 RSTN 23 AW9523B XXXX AW9523B- AW9523BTQR XXXX-Manufactory trace No. Figure 1 AW9523B PIN CONFIGURATION AND MARKING Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page 1 of 21 AW9523B datasheet May 2016 V1.1.1 Typical Application 1: Drive 16 function LED, including 6 ports feasible for LED backlight VBAT VCCMCU 2 1uF VCC 4.7k (x2) VCC 6 LED Backlight or function LED P1_0 P1_1 GPO1 RSTN GPO2 SCL GPIO SDA P1_2 P1_3 MCU P0_0 P0_1 GPO3 AW9523B GND P0_2 P0_3 P0_4 P0_5 VBAT 1 AD1 P0_6 P0_7 P1_4 AD0 P1_5 INTN P1_6 GND P1_7 10 White or RGB LED 1. When LED anode is connected to VBAT, the AD1/AD0 PIN must be connected to VBAT to assure that the default value of GPIO after POWER ON is High or Hi-Z so that LED cannot be lighted falsely. The default value of GPIO after POWER ON is decided by AD1/AD0 PIN (refer to table 1). 2. The Dropout performance of the low 6 LED PortsP1_0~P1_3, P0_0~P0_1is optimized, so these ports are recommended if you want to use AW9523B to drive LED backlight. Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 2 - of 21 AW9523B datasheet May 2016 V1.1.1 Typical Application 2: function LED + keyboard/IO Extended VBAT VCCMCU VCCMCU 1F VCC 4.7k (x3) VCC INTN INTN P1_0 P1_1 MCU GPO1 SCL GPIO SDA GPO2 RSTN AW9523B GND 2 100k (x7) P0_0 Sub System EN P1_2 P1_3 P1_4 P1_5 VBAT P1_6 1 P1_7 P0_1 AD1 P0_2 AD0 P0_3 Keyboard P0_4 GND P0_5 P0_6 P0_7 1. When LED anode is connected to VBAT, the AD1/AD0 PIN must be connected to VBAT to assure that the default value of GPIO after POWER ON is High or Hi-Z so that LED cannot be lighted falsely. The default value of GPIO after POWER ON is decided by AD1/AD0 PIN (refer to table 1). 2. Any of the 16 I/O ports can be configured as LED drive mode or GPIO mode.In the application schematic, P1_0P1_1 are configured as LED mode, P0_0 is configured as GPIO output to control sub system, P1_2~P1_7 are configured as GPIO output to drive the row line of keyboard, P0_1~P0_7 are configured as GPIO input to drive the column line of keyboard. Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 3 - of 21 AW9523B datasheet May 2016 V1.1.1 Typical Application 3: 2 AW9523Bs drive 32 LEDs VCCMCU VCC 4.7k (x3) GPO1 GPO2 GPIO1 2 GPIO2 VBAT MCU 1uF VCC GND 1uF 6 LED Backlight or function LED VCC P1_0 P1_1 RSTN AW9523B P1_2 SCL P1_3 SDA P1_3 SDA P0_0 P0_0 P0_1 P0_1 AW9523B P0_2 P0_3 VBAT 1 AD1 P1_0 P1_1 RSTN P1_2 SCL 16 White or RGB LED P0_2 P0_3 P0_4 P0_4 P0_5 P0_5 P0_6 P0_6 VBAT P0_7 P0_7 P1_4 AD1 P1_4 AD0 P1_5 AD0 P1_5 INTN P1_6 INTN P1_6 GND P1_7 GND P1_7 10 White or RGB LED 1. When LED anode is connected to VBAT, the AD1/AD0 PIN must be connected to VBAT to assure that the default value of GPIO after POWER ON is High or Hi-Z so that LED cannot be lighted falsely. The default value of GPIO after POWER ON is decided by AD1/AD0 PIN (refer to table 1). 2. The 2 AW9523Bs can share reset line RSTN and clock line SCL, but the data line SDA need to separate. So the 2 AW9523Bs consume 4 GPIOs. Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 4 - of 21 AW9523B datasheet May 2016 V1.1.1 ORDER INFORMATION Part Number Temperature Package Mark AW9523BTQR -4085 TQFN4X4-24L AW9523B SPQ Tape and Reel 6000/Tape AW9523B RTape & Reel TQThin QFN ABSOLUTE MAXIMUM RATINGS (Note1) Parameter Range Supply voltage, VCC -0.3V to 6 V SCLSDAAD0AD1INTNRSTNP0_0~P0_7 -0.3V to VCC P1_0~P1_7 Max powerPDmaxpackage@ TA=25 3.2 W Package thermal impedance, JA 31/W Max junction temperature, TJmax 125 Storage temperature range -65 to 150 Solder temperature (10s) 260 ESD range (Note2) 4000V HBM Latch-up Standard JEDEC SEPTEMBER 2010 STANDARD NO.78C +IT450mA -IT-450mA Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Note2: HBM standard: MIL-STD-883H Method 3015.8. Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 5 - of 21 AW9523B datasheet May 2016 V1.1.1 ELECTRICAL CHARACTERISTICS TA=25VCC=3.8V (unless otherwise noted) Parameter Test Condition Min. Typ. Max. Unit 5.5 V Supply voltage and current VCC Supply voltage 2.5 Ishutdown Shutdown current SHDN=GND 0.1 A IMAX Max current of LED drive Configure DIMx Reg. as FFH 37 mA Vdrop1 Dropout voltage on low 6 portsP1-0~P1_3 P0_0~P0_1 IOUT=20mA 60 mV Vdrop2 Dropout voltage on high 10 portsP0-2~P0_7 P1_4~P1_7 IOUT=20mA 80 mV VCC=2.5VISOURCE=10mA VCC-170 mV VCC=3.6VISOURCE=20mA VCC-250 mV VCC=5VISOURCE=20mA VCC-200 mV VCC=2.5VISINK=20mA 90 mV VCC=3.6VISINK=20mA 70 mV VCC=5VISINK=20mA 60 mV VCC=2.5VISINK=6mA 150 mV VCC=3.6VISINK=6mA 100 mV VCC=5VISINK=6mA 75 mV LED Drive Digital pin output VOH VOL VOL High-level output voltageP0_7~P0_0 P1_7~P1_0 Low-level output voltageP0_7~P0_0 P1_7~P1_0 Low-level output voltageSDA,INTN Digital pin input High-level input voltage VIH SCLSDARSTN AD0AD1P0_7~P0_0 P1_7~P1_0 1.4 V Low-level input voltage VIL SCLSDARSTN AD0AD1P0_7~P0_0 P1_7~P1_0 IIHIIL Input currentSCL SDAAD0AD1 P0_7~P0_0 P1_7~P1_0 R_RSTN internal pull-low resistor in RSTN PIN CI Input capacitance SCLSDARSTN AD0AD1P0_7~P0_0 P1_7~P1_0 tSP_RSTN Pulse width that RSTN PIN can filter VI=VCC or GND -0.2 0.4 V +0.2 A 100k VI=VCC or GND 3 pF RSTN=VCC 10 s Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 6 - of 21 AW9523B datasheet May 2016 V1.1.1 I2C INTERFACE TIMING REQUIREMENTS Parameter Symbol 2 Min. Typ. fSCL SCL I C clock frequency I2C Start or repeated Start condition hold time Max. Unit 400 kHz tHD:STA 0.6 S SCL I C clock low time tLOW 1.3 S SCL I2C clock high time 2 tHIGH 0.6 S 2 tSU:STA 0.6 S 2 I C serial-data hold time tHD:DAT 0 S I2C serial-data setup time tSU:DAT 0.1 S I C Start or repeated Start condition setup time 2 I C rise time tR 0.3 S I2C fall time tF 0.3 S 2 tSU:STO 0.6 I2C spike time tBUF 1.3 Valid-data time tSP 0 I2C bus capacitive load Cb I C Stop condition setup time S 140 240 nS 400 pF VIH SDA VIL tBUF tLOW tHIGH tR tSP tF VIH SCL VIL Stop Start tHD:STA tHD:DAT tSU:DAT tSU:STA Start 2 Figure 2 I C Interface Timing Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 7 - of 21 tSU:STO Stop AW9523B datasheet May 2016 V1.1.1 TYPICAL CHARACTERISTIC CURVES GPIO SINK CURRENT vs OUTPUT LOW VOLTAGE 80 80 70 70 60 TA=25 50 TA=-40 40 30 TA=85 20 10 ISINK - I/O Sink Current - mA ISINK - I/O Sink Current - mA GPIO SINK CURRENT vs OUTPUT LOW VOLTAGE TA=25 60 TA=-40 50 TA=85 40 30 20 10 VCC=2.5V VCC=3.6V 0 0 0 0 0.04 0.08 0.12 0.16 0.2 0.24 0.28 0.32 0.36 GPIO SINK CURRENT vs OUTPUT LOW VOLTAGE GPIO SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 80 40 70 35 TA=-40 60 50 TA=85 40 TA=25 30 20 10 VCC=5V ISOURCE - I/O Source Current - mA ISINK - I/O Sink Current - mA 0.04 0.08 0.12 0.16 0.2 0.24 0.28 0.32 0.36 VOL - Output Low Voltage - V VOL - Output Low Voltage - V 0 30 25 TA=85 20 TA=25 15 TA=-40 10 5 VCC=2.5V 0 0 0.04 0.08 0.12 0.16 0.2 0.24 0.28 0.32 0.36 0 0.04 0.08 0.12 0.16 0.2 0.24 0.28 0.32 0.36 (VCC - VOH) - V VOL - Output Low Voltage - V GPIO SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 40 40 35 35 30 25 TA=25 20 TA=-40 15 10 TA=85 5 VCC=3.6V 0 ISOURCE - I/O Source Current - mA ISOURCE - I/O Source Current - mA GPIO SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 30 TA=25 25 20 TA=-40 15 TA=85 10 5 VCC=5V 0 0 0.04 0.08 0.12 0.16 0.2 0.24 0.28 0.32 0.36 (VCC - VOH) - V 0 0.04 0.08 0.12 0.16 0.2 0.24 0.28 0.32 0.36 (VCC - VOH) - V Figure 3 TYPICAL CHARACTERISTIC CURVES Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 8 - of 21 AW9523B datasheet May 2016 V1.1.1 PIN DEFINATION Pin No. Name Description 1 P1_0 GPIO mode default, input or output, push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 2 P1_1 GPIO mode default, input or output, push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 3 P1_2 GPIO mode default, input or output, push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 4 P1_3 GPIO mode default, input or output, push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 5 P0_0 GPIO mode default, input or output, open-drain (default) or push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 6 P0_1 GPIO mode default, input or output, open-drain (default) or push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 7 P0_2 GPIO mode default, input or output, open-drain (default) or push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 8 P0_3 GPIO mode default, input or output, open-drain (default) or push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 9 GND Ground supply 10 P0_4 GPIO mode default, input or output, open-drain (default) or push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 11 P0_5 GPIO mode default, input or output, open-drain (default) or push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 12 P0_6 GPIO mode default, input or output, open-drain (default) or push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 13 P0_7 GPIO mode default, input or output, open-drain (default) or push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 14 P1_4 GPIO mode default, input or output, push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 15 P1_5 GPIO mode default, input or output, push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 16 P1_6 GPIO mode default, input or output, push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 17 P1_7 GPIO mode default, input or output, push-pull mode. Can be configured as LED drive mode. The default state after power on is related to AD1/AD0 PIN. 18 AD0 I2C interface device addressconnect to VBAT or GNDand control the default state of output pin (refer to table 1). 19 SCL I2C interface clock bus 20 SDA I2C interface data bus 21 VCC Power supply 22 INTN Interrupt output pin, open-drain mode, need external pull-up resistor; interrupt low active. 23 RSTN Hardware reset pin, low reset; it has an internal 100 k(typical) pull-low resistor. 24 AD1 I2C interface device addressconnect to VBAT or GNDand control the default state of output pin (refer to table 1). 25 GND Ground supply Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 9 - of 21 AW9523B datasheet May 2016 V1.1.1 SYSTEM BLOCK INTN Interrupt Logic RSTN Reset Filter LP Filter P1_3P1_0 AD1 AD0 Control Register SCL SDA LP Filter GPIO Control /LED Driver P0_7P0_0 I2C Controller P1_7P1_4 GND POR VCC Figure 4 AW9523B system block FUNCTION DESCRIPTION AW9523B is a 16 multi-function IO controller, which is applied for LED drive or GPIO. Any of the 16 I/O ports can be configured as LED drive mode or GPIO mode. Furthermore, any GPIO can be configured as an input or an output independently. When configured as GPIO mode, all I/O ports configured as inputs are continuously monitored for state changes. State changes are indicated by the INTN output. When AW9523B read 2 GPIO state through the I C interface, the interrupt is cleared. When configured as LED drive, drive current range is 0 ~IMAX, which 256 steps is divided. Default IMAX is 37mA, and it can be changed in GCR register. GPIO OUTPUT After power on, all the 16 I/O ports are configured as GPIO output as default, which default 2 states are set according to the I C slave address selection inputs, AD0 and AD1, refer to table 1 for detail. The P1 port is Push-Pull mode; P0 port is Open-Drain mode (default) and can be configured as Push-Pull mode. When P0 port is Open-Drain mode, it need pull-up resistor. Table 1. Default state of IO ports , AD1/AD0 and P0_x/P1_x AD1 AD0 GND GND P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 0 0 0 0 0 0 0 0 0 0 0 0 Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 10 - of 21 0 0 0 0 AW9523B datasheet May 2016 V1.1.1 GND VBAT 0 0 0 0 1 1 1 1 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z VBAT GND 1 1 1 1 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z 0 0 0 0 VBAT VBAT 1 1 1 1 1 1 1 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z GPIO INPUT/OUTPUT DIRECTION SELECT The register Config_Port0 and Config_Port1 can configure a port as input or output. Each bit of the register is corresponding to each port, the bit set 1 as input, 0 as output. The default value is 0 as output. GPIO INPUT User can get the current state of GPIO through reading the register Input_Port0 and In2 put_Port1 by I C Interface. AW9523B GPIO support 1.8V logic input. INTERRUPUT AW9523B can monitor IO state to generate interrupt when configure port as GPI and GPIO interrupt enabled. External MCU is required acknowledge by INTN pin. INTN is open-drain output, low-level active, and need external pull-up resistor. When AW9523B detect port change, any input state from high-level to low-level or from low-level to high-level will generate interrupt after 8us internal deglitch. External MCU read GPIO_INPUT_A/B register to clear interrupt. P1 port state change must clear interrupt by read GPIO_INPUT_B register; P0 port state change must clear interrupt by read GPIO_INPUT_A register. 8us deglitch P0/P1 INTN Data readout SDA S 1 0 1 1 0 AD1AD0 0 A 0 0 0 0 0 0 0 0/1 A S 1 0 1 1 0 AD1AD0 1 A MSB LSB N A P 0 : read P0 Port 1 : read P1 Port Figure 5 Interrupt generation and clear LED DRIVE AW9523B is co-anode current source LED drive. LED drive IMAX is configured by GCR (ISEL) register, to select 4 grades. The default IMAX is 37mA. In LED drive mode, LED dim step can be manually controlled by external MCU. Drive current is from 0~IMAX divided by 256 steps. Table-2. 256 step dimming 7 0 0 0 6 0 0 0 5 0 0 0 4 0 0 0 DIMx bit 3 0 0 0 2 0 0 0 1 0 0 1 0 0 1 0 D OFF 1/255xIMAX 2/255xIMAX Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page 11 of 21 AW9523B datasheet May 2016 V1.1.1 1 1 1 1 1 1 1 1 1 ...... 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 ...... 253/255xIMAX 254/255xIMAX 255/255xIMAX I2C INTERFACE 2 2 AW9523B support I C interface. The bidirectional I C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 2 I C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high. After the Start condition, the device address byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (AD1/AD0) of the slave device must not be changed between the Start and Stop conditions. 2 On the I C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master. SDA SCL S/Sr S: start condition Srrepeat start condition Pstop condition Figure 6 Start and stop condition SDA SCL SDA stable Change of Data avalible data allowed Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page 12 of 21 AW9523B datasheet May 2016 V1.1.1 Figure 7 Bit Transfer Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. Data output by transmitter NACK Data output by receiver ACK 2 1 SCL from mater 8 9 Clock pulse for acknowledgment Start Condition 2 Figure 8 Acknowledgment On I C Bus DEVICE ADDRESS Below is the device address of AW9523B. AD1/AD0 bit in device address match with AD1/AD0 pin respectively. 1 0 1 1 0 AD1 AD0 R/W AD1/AD0 value match with AW9523B pin AD1/AD0 respectively Figure 9 AW9523B Device Address WRITE Data is transmitted to the AW9523B by sending the device address and setting the least-significant bit to a logic 0. The register address byte is sent after the device address and determines which register receives the data that follows the command byte. After sending data to one register, the next data byte is sent to the other register. There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 13 - of 21 AW9523B datasheet May 2016 V1.1.1 SCL 1 2 3 4 5 6 7 8 9 1 2 3 Device address SDA 1 1 0 5 6 7 8 9 1 2 3 Register address 0 1 4 AD1 AD0 0 5 6 7 8 9 Register data LSB MSB A Ack R/W S A 4 LSB MSB Ack Ack A P Figure 10 AW9523B Write Operation READ The bus master first must send the AW9523B address with the least-significant bit set to a logic 0. The register address byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data from the register defined by the register address byte then is sent by the AW9523B. After a restart, the value of the register defined by the register address byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflect the information in the other register. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. SCL 1 2 3 4 5 6 7 8 9 Device address SDA 1 0 1 1 S 1 AD1 AD0 A 0 3 4 5 6 7 8 Register address Ack 0 2 MSB 9 1 3 LSB A 4 5 6 7 8 9 1 A Device address Ack 1 S 1 0 0 1 AD1 AD0 R/W Sr R/W At this moment, master transmitter becomes master receiver, and slave receiver becomes slave transmitter. 2 1 2 3 4 5 6 7 8 Ack 9 Read out data MSB LSB NA Nack P Figure 11 AW9523B Read Operation RESET FUNCTION AW9523B support 3 reset mode: power on reset, hardware reset, software reset. Each reset mode can reset registers to default value. Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page 14 of 21 AW9523B datasheet May 2016 V1.1.1 Hardware Reset Hardware reset timing is as the following figure. tSP_RSTN Less than 10s tRW RSTN tRT AW9523B state Normal Opration Reset Initial Conditon Figure 12 Hardware Reset Timing Table 3. Hardware Reset Parameter Parameter tRW Reset pulse low level width tRT Reset recovery time Condition min VSS=0VVCC=2.4V~5.5V 20 s 1 s T=-40~85 typ max unit Note: 1. The hardware reset PINRSTNhas a built-in deglitch blockSpike due to an electrostatic discharge on RSTN line does not cause irregular system reset according to the table below Reset pulseRSTN AW9523B action Shorter than 10stypical Reset Rejected Longer than 20s Reset 2. After reset, AW9523B is in default state. All GPIO are configured as output, which value is decided by 2 device address (AD1/AD0) (refer to table 1). The interrupt (INTN) is cleared and pulled up by external pull-up resistor. 3. Spike Rejection also applies during a valid reset pulse as shown below: Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page 15 of 21 AW9523B datasheet May 2016 V1.1.1 20s Reset is accepted 20s Reset is accepted 10ns (Less than 10ns width positive spike will be rejected) Figure 13 Operation When RSTN SLOW Software Reset AW9523B support software reset mode. Writing 00H to the software register(7FH) will generate a reset pulse. After software reset, AW9523B is in default state, which is the same as hardware reset. The software reset timing is as below. SCL 1 2 3 4 5 6 7 8 9 1 1 0 Start condition 1 1 0 3 4 5 6 7 8 9 1 Software reset register address 7FH 7 bit slave device address SDA 2 AD1 AD0 0 A 0 1 R/W AW9523B ack 1 1 1 1 1 2 3 4 5 6 7 8 9 0 A Software reset register data 00H 1 A 0 0 0 0 AW9523B ack Reset_int (internal reset pulse) Figure 14 Software Reset Timing Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 16 - of 21 0 0 0 AW9523B ack Stop condition AW9523B datasheet May 2016 V1.1.1 REGISTERS Table-4. AW9523B register list Address W/R Default Value Function Description 00H R Equal to P0 Input_Port0 P0 port input state 01H R Equal to P1 Input_Port1 P1 port input state 02H W/R Refer to table 1 Output_Port0 P0 port output state 03H W/R Refer to table 1 Output_Port1 P1 port output state 04H W/R 00H Config_Port0 P0 port direction configure 05H W/R 00H Config_Port1 P1 port direction configure 06H W/R 00H Int_Port0 P0 port interrupt enable 07H W/R 00H Int_Port1 P1 port interrupt enable 10H R 23H ID ID register (read only) 11H W/R 00H CTL Global control register 12H W/R FFH LED Mode Switch P0 port mode configure 13H W/R FFH LED Mode Switch P1 port mode configure 20H W 00H DIM0 P1_0 LED current control 21H W 00H DIM1 P1_1 LED current control 22H W 00H DIM2 P1_2 LED current control 23H W 00H DIM3 P1_3 LED current control 24H W 00H DIM4 P0_0 LED current control 25H W 00H DIM5 P0_1 LED current control 26H W 00H DIM6 P0_2 LED current control 27H W 00H DIM7 P0_3 LED current control 28H W 00H DIM8 P0_4 LED current control 29H W 00H DIM9 P0_5 LED current control 2AH W 00H DIM10 P0_6 LED current control 2BH W 00H DIM11 P0_7 LED current control 2CH W 00H DIM12 P1_4 LED current control 2DH W 00H DIM13 P1_5 LED current control 2EH W 00H DIM14 P1_6 LED current control 2FH W 00H DIM15 P1_7 LED current control 7FH W 00H SW_RSTN Soft reset Other - - - Reserved Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page 17 of 21 AW9523B datasheet May 2016 V1.1.1 REGISTER DETAIL DESCRIPTION Table 5. Input state register00H01H Address 00H 01H Name Input_Port0 Input_Port1 Description P0 port current logic state, 0-low level1-high level P1 port current logic state, 0-low level1-high level Default X X The Input state registers (00H,01H) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration Register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to let the 2 I C device know that the Input Port registers will be accessed next. Table 6. Output state register02H03H Address Name Description 02H Output_Port0 Set P0 port output value. 0-low level; 1-high level 03H Output_Port1 Set P1 port output value. 0-low level; 1-high level Default Refer to table1 Refer to table1 The Output state register02H03Hshow the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 7. Configuration register04H05H Address 04H 05H Name Config_Port0 Config_Port1 Description P0 port input/output mode select. 0-output; 1-input P1 port input/output mode select. 0-output; 1-input Default 00H 00H The Configuration registers (04H05H) configure the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 8. Interrupt enable register06H07H Address 06H 07H Name Int_Port0 Int_Port1 Description P0 port interrupt enable. 0-enable; 1-disable P1 port interrupt enable. 0-enable; 1-disable Default 00H 00H The Interrupt enable register (06H07H) are used to configure the interrupt enable or disable of GPIO. If a bit in this register is set to 1, the interrupt function of the corresponding port pin is disabled. If a bit in this register is cleared to 0, the interrupt function of corresponding port pin is enabled. Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page 18 of 21 AW9523B datasheet May 2016 V1.1.1 Table 9. ID register10H Address 10H Name ID Description ID register, read only, the readout value is 23H Default 23H ID register10His a read only register which stores the device IDThe ID read value of AW9523B is 23H. Table 10. GCR ,Global control register11H Address D[7:5] Name reserved D[4] GPOMD D[3:2] D[1:0] reserved ISEL Description Set P0 port GPIO output drive modeif D[4]=0, P0 port is Open-Drain mode; if D[4]=1, P0 port is Push-Pull mode. 256 step dimming range select 000~IMAX 010~(IMAXx3/4) 100~(IMAXx2/4) 110~(IMAXx1/4) Default 0 00 D[4] is used to configure P0 port output drive as Open-Drain or Push-Pull modeWhen P0 port use as output with Open-Drain mode, it needs pull-up resistor. If in Push-pull mode, it needs no pull-up resistor. D[1:0] is used to configure the max drive current of LEDAW9523B set max current IMAX to 37mA(typical) default, and through register ISEL[1:0] can set to IMAXx1/4,IMAXx2/4, IMAXx 3/4,IMAX,so the 256 step dimming range changes. Except D4, D[1:0], other bits (D[7:5]\D[3:2]) are used for test purpose and the default value is 0. If user needs to configure register 11H, then the bits D[7:5]\D[3:2] must configure to 0, or system function error may occur. Table 11. LED mode switch register12H Address Name Description Default Configure P0_7~P0_0 as LED or GPIO mode 12H LED Mode Switch 1GPIO mode FFH 0LED mode LED mode switch register12Hcan configure P0 port as LED or GPIO mode. After reset, it is GPIO mode as default. Set a bit of 12H[7:0] to 0 so the corresponding port is LED mode, and set to 1 so the corresponding port is GPIO mode. Table 12. LED mode switch register13H Address 13H Name Description Configure P1_7~P1_0 as LED or GPIO mode LED Mode Switch 1GPIO mode 0LED mode Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page 19 of 21 Default FFH AW9523B datasheet May 2016 V1.1.1 LED mode switch register13Hcan configure P1 port as LED or GPIO mode. After reset, it is GPIO mode as default. Set a bit of 13H[7:0] to 0 so the corresponding port is LED mode, and set to 1 so the corresponding port is GPIO mode. Table 13. 256 step dimming control register (20H~2FH) Address Name Description Default 20H DIM0 P1_0 port LED current control 00H 21H DIM1 P1_1 port LED current control 00H 22H DIM2 P1_2 port LED current control 00H 23H DIM3 P1_3 port LED current control 00H 24H DIM4 P0_0 port LED current control 00H 25H DIM5 P0_1 port LED current control 00H 26H DIM6 P0_2 port LED current control 00H 27H DIM7 P0_3 port LED current control 00H 28H DIM8 P0_4 port LED current control 00H 29H DIM9 P0_5 port LED current control 00H 2AH DIM10 P0_6 port LED current control 00H 2BH DIM11 P0_7 port LED current control 00H 2CH DIM12 P1_4 port LED current control 00H 2DH DIM13 P1_5 port LED current control 00H 2EH DIM14 P1_6 port LED current control 00H 2FH DIM15 P1_7 port LED current control 00H The dimming control register (20H~2FH) are used to configure P0 port and P1 port LED current. Each port supports 256 step dimming. For the detailed configuration, refer to table 2. Table 13.Soft reset register7FH Address 7FH Name Software Reset Description Write 00H to generate a reset pulse Default X The soft reset register (7FH) support software reset function, which brings convenience to software engineer. Every time write 00H to this register, it generate a reset pulse. The software reset timing, please refer to figure 14. Table 14. Reserve register Address 08H~0FH 14H~1FH 30H~7EH 80H~FFH Name Reserve register, for test purpose or not defined. Description X Reserve register08H~10H14H~1FH30H~7EH80H~FFHare for test purpose or not defined, user should not write these registers, or may cause function error. Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page 20 of 21 AW9523B datasheet May 2016 V1.1.1 PACKAGE DESCRIPTION D2 Unit:mm b D c 24L TQFN (4X4mm) E E2 e D1 Top View Bottom View Min Typ Max A 0.700 0.750 0.800 A1 0.000 A2 A2 0.050 0.203 (Ref.) b 0.200 0.250 0.300 c 0.350 0.400 0.450 D 3.950 4.000 4.050 D1 D2 e A TQFN-24L Symbol 2.500(Ref.) 2.650 2.700 2.750 0.500(BSC) E 3.950 4.000 4.050 E2 2.650 2.700 2.750 A1 Side View Copyright (c) 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD Page - 21 - of 21