Serial FIR Filter April 2003 IP Data Sheet Features General Description Serial Arithmetic for Reduced Resource Utilization Many digital systems use filters to remove noise, provide spectral shaping, or perform signal detection. Two types of common filters that provide these functions are Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filters. IIR filters are used in systems that can tolerate phase distortion. FIR filters have an inherently stable structure, and are used in systems that require linear phase. This benefit makes FIR filters attractive enough that they are designed into a large number of systems. However, for a given frequency response specification, FIR filters are of higher order than IIR, making them computationally expensive. Variable Number of Taps up to 64 Data and Coefficients up to 32 Bits Output Size Consistent with Data Size Signed or Unsigned Data and Coefficients Full Arithmetic Precision Fixed or Loadable Coefficients Decimation and Interpolation Real or Complex Data The Lattice Serial FIR filter uses serial arithmetic elements to achieve a compact size. Due to the serial nature of the arithmetic, the data rate is slower than the clock rate and dependant on the data width. The effective throughput is defined as: Selectable Rounding Scaleable Outputs Multi-cycle Modes for Area/Time Tradeoffs Supports Symmetric or Anti-Symmetric Filters Data rate = (f/(ofw +1) where ofw is the Output Full Width and f is the clock frequency. Optimization Based on Symmetry of Filter Fully Synchronous Design Block Diagram Figure 1. Serial FIR Filter Core Block Diagram real_in irdy din Tap Tap Array Array Symmetry Optimizer Data Scheduler coeff loadc Multiplier Bank Adder Tree Output Control Unit ordy dout real_out Coefficient Registers clk (c) 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. The product described herein is subject to continuing development, and applicable specifications and information are subject to change without notice. Such specifications and information are provided in good faith; actual performance is not guaranteed, as it is dependent on many factors, including the user's system design. www.latticesemi.com 1 ip1019_01 Lattice Semiconductor Serial FIR Filter The Lattice Serial FIR Filter IP core is based on a generic parameterizable model. This model generates a customized core with optimal architecture based on user parameters set at the time of core generation. The core supports a wide range of user-defined taps, data lengths and architectures. The core supports a variable number of taps, from 4 to 64, which is sufficient for most applications. The core can also be used to implement decimation and interpolation filters. Additionally, the core can operate with complex or real data types. The coefficients can either be fixed at the time of core generation or dynamically loaded during runtime, thus allowing use in adaptive filtering. The architecture is optimized depending on the symmetry type of the filter. Symmetric odd and symmetric even types are recognized in addition to non-symmetric type. Functional Description The Serial FIR Filter core is comprised of a number of interconnected functional blocks (Figure 1). Descriptions of these functional blocks are given below. Tap Array The Tap Array module stores delayed versions or taps of input data. The number of taps of the FIR filter and the data width are user parameters and they are fixed at the time of core generation. The array consists of n taps each of width w, which are organized as shift registers. All data registers are reset when the reset_n input is asserted. At the end of each processing cycle, the data values are shifted into the next sequential shift register inside the Tap Array, with the first register getting the value from the input data port din. Symmetry Optimizer The Symmetry Optimizer block is used for optimizing symmetric or anti-symmetric filter implementations. Symmetric filter implementations incorporate adders, while anti-symmetric filter implementations incorporate subtractors. For anti-symmetric filters, the output of this block has an additional latency of one clock cycle. Coefficient Registers The Coefficient Registers module holds the coefficient data for the filter. The Serial FIR Filter coefficients can either be loaded at run time or set during IP core generation. This module supports real as well as complex coefficients. The serial FIR core can operate as fixed or loadable coefficients filter. For a fixed-coefficient filter, this module supplies the fixed coefficient value. For a loadable-coefficient filter, this module implements a series of word shift registers equal to the number of taps, (or equal to half the number of taps for symmetric or anti-symmetric filters). Data Scheduler The Data Scheduler synchronizes the tap and coefficient data with the multiplier bank for multi-cycle filter implementations. In these implementations, the number of taps and the number of clock cycles determine the number of multipliers used. The Data Scheduler is also used to multiplex data for optimizing decimation and interpolation filters. This block is not present in single-cycle filter implementations. Multiplier Bank The Multiplier Bank receives data from the data scheduler and delivers output to the Adder Tree. The maximum delay through the Multiplier Bank is equal to the delay of a single multiplier. The number of multipliers is equal to the number of taps for single-cycle implementations. Adder Tree and Output Processor The Adder Tree contains serial adders instantiated in a binary tree fashion. The Adder Tree receives input from the multiplier bank, and delivers output to the Output Processor. The Output Processor may contain an adder to support the following operations: 1. Accumulating the intermediate computation results in multi-cycle filter implementations. 2. Rounding to the nearest value, when output-scaling option is enabled. 2 Lattice Semiconductor Serial FIR Filter In both cases, output latency increases by one clock cycle. Parameter Descriptions Table 1 shows the parameter definitions for the Serial FIR Filter core. Table 1. Serial FIR Filter Parameter Definitions Default Value Value Description Filter Type Parameter Single-Cycle Single-Cycle, Multi-Cycle, Decimation or Interpolation Type of filter selected by the user. This determines the rest of the parameter options. Data Width 8 bits Real: 4 to 32 bits Width of input data (w) in bits. The width of the coefficients Complex: 4 to 16 is also equal to this parameter. For complex data types, the bits Data Width is equal to the width of the real part and the range is from 4 to 16 bits. Number of Taps 16 4 to 64 Number of taps (n) in the filter. Computational Cycles 2 2 to 32 Number of cycles (c) for multi-cycle filters. Number of processing cycles (PP) to perform the filtering process. The output is computed once in c PPs. Decimation Ratio 2 2 to 32 Decimation is down sampling of the bit stream. In a decimation filter with decimation ratio `d', the output data rate is 1/d of the input rate. Interpolation Ratio 2 2 to 32 For interpolation filters. Interpolation is the reverse of decimation. The input rate is 1/u of the output rate. Rounding Method Nearest Truncation or Nearest Arithmetic Type Signed Signed or Unsigned Specifies the type of arithmetic modules for the core. If the symmetry of the core is even or odd, then the arithmetic type is always signed. Real Real or Complex Specifies the data type of the inputs (din and coeff) and the output (dout) of the Serial FIR core. When complex data type mode is selected, the arithmetic type is always signed. Parallel Parallel or Serial In the parallel I/O mode, real and imaginary parts are applied on the data bus in the same clock cycle. In the serial mode, real data is applied in the first PP cycles, followed by the imaginary data in the next PP cycles. Full Precision 4 to 96 Width of output data (w) in bits. If the width is less than the maximum output width determined by the core generator, the outputs are scaled. Data Type Complex I/O Mode Output Width Coeffs Loadable Coefficients Format Symmetricity Run-time Loadable Types of rounding available. Fixed or Run-time Determines if the coefficients are run-time loadable. If the Loadable coefficients are run-time loadable, the core has two additional input ports, coeff and loadc, for loading purposes. If the coefficients are fixed during core configuration, no additional input ports are used. Hexadecimal Hexadecimal or Decimal The coefficient values can be entered in either in hexadecimal or decimal format. Even None, Even, or Odd Specifies the impulse response of the filter. Even Symmetricity applies to symmetric impulse response, while Odd Symmetricity applies to anti-symmetric impulse response. Decimation and Interpolation filters do not have Symmetricity (the value None should be selected). If the Symmetricity of the core is even or odd, then the arithmetic type is always signed. 3 Lattice Semiconductor Serial FIR Filter Signal Descriptions Table 2 shows the definitions of the I/O ports. Table 2. Input/Output Signal Descriptions Name clk Size I/O 1 Input Clock. Description 1 Input Reset. din 4 to 32 bits Input Data Input. Data to be filtered. irdy 1 Input Input Ready. This signal indicates that the din port contains valid data to be filtered. dout 4 to 128 bits Output Data Output. Data output after filtering. ordy 1 Output Output Ready. Filtered data is ready. coeff 4 to 32 bits Input Coefficient Data. Coefficients loaded into the Serial FIR core for the filtering process. This signal is present only when the Coeffs Loadable parameter is set during core configuration. loadc 1 Input Load Coefficient. This signal indicates that the input coefficient data is valid. This signal is present only when the Coeffs Loadable parameter is set during core configuration. real_in 1 Input Real Data Input. This signal indicates that the real part of the input complex data is being applied. This is used only if the Complex I/O mode is serial. real_out 1 Output Real Data Output. This signal indicates that the real part of the output complex data is being output. This is used only if the Complex I/O mode is serial. reset_n Custom Core Configurations For Serial FIR configurations not available in the Evaluation Package, please contact your Lattice sales office. Related Information For more information regarding usage of the core, please refer to the Serial FIR User's Guide, available on the Lattice web site at www.latticesemi.com. 4 Lattice Semiconductor Serial FIR Filter Appendix for ispXPGATM FPGAs Table 3. Performance and Resource Utilization Parameter fir_ser_xp_1_002.lpc LUT4s2 PFUs3 Registers 260 115 382 4 External Pins System EBRs 41 None fMAX1 185 1. Performance and utilization characteristics using LFX1200B-04FE680C in Lattice's ispLEVERTM v.3.0 design tool. Synthesized using Synplicity's Synplify Pro v.7.2.1. When using this IP core in a different density, package, speed, or grade within the ispXPGA family, performance may vary slightly. 2. Look-Up Table (LUT) is a standard logic block of Lattice devices. LUT4 is a 4-input LUT. For more information check the data sheet of the device. 3. Programmable Function Unit (PFU) is a standard logic block of some Lattice devices. For more information, check the data sheet of the device. 4. Configuration fir_ser_xp_1_002.lpc has the following settings: Number of Taps (n) = 16, Data Width(w) = 8, Coeff Width = 8, Output Width = 20, Signed, Single-Cycle, Real, Symmetric Coeff, Loadable Coeff (8 Coeffs). Supplied Netlist Configurations The Ordering Part Number (OPN) for the Lattice Serial FIR Filter IP Core is FIR-SER-XP-N1. Table 4 lists the Lattice-specific netlists that are available in the Evaluation Package, which can be downloaded from the Lattice web site at www.latticesemi.com. Table 4. Parameter Values for Evaluation Configuration(s) Parameter File Name fir_ser_xp_1_002.lpc1 Input Data Width (Bits) Number of Taps FIR Type 8 16 Single cycle Symmetry Arithmetic Type Data Type Output Data Width (Full Data Width)2 Symmetric Signed Real Full (20) 1. The latency for the fir_ser_xp_1_002 configuration is (6 + Output_Full_Width + 1) or 27. 2. The Output Data Width is the same as the Full Data Width. 5