Features * Organization: 8,192 words x 8 bits * High speed - 8/10/12/15/20 ns address access time - 3/3/3/4/5 ns output enable access time Low power consumption - Active: 633 mW max (10 ns cycle) - Standby: 11 mW max, CMOS I/O * Very low DC component in active power Logic block diagram ral SN Vcc > . GND > : Input buffer re) 5 i V/o7 A} & 128 64%8 E A4 g Array LA : weer] assy [RT| Al2 me rp 0 foe - WE Column decoder rr Control - OE circuit, CET AAAAAA k CE2 056789 Selection guide *2.0V data retention * Equal access and cycle times * Very fast 3 ns output enable access time * Easy memory expansion with CEI, CE2, OF inputs * TTL-compatible, three-state I/O * 28-pin JEDEC standard packages * 300 mil PDIP and SO] * ESD protection 2 2000 volts * Latch-up current 2 200 mA Pin arrangement DIP SO} WON RUN AwWDH AIMCO 7C164-8 7C164-10 7C164-12 7C164-15 = 7C164-20 Unit Maximum address access time 8 10 12 i$ 20 ns Maximum output enable access time 3 3 3 4 5 ns Maximum operating current 120 115 110 100 90 mA Maximum CMOS standby current 2.0 2.0 2.0 2.0 2.0 mA DID t1-20008-A. 998 Alliance Semiconductor. AN) rights reserved.AS7C164 dw: The AS7C164 is a high performance CMOS 65,536-bit Static Random Access Memory (SRAM) organized as 8,192 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Functional description Equal address access and cycle times (tay, inc two) of 8/10/12/15/20 ns with output enable access times (tog) of 3/3/3/4/ 5 ns are ideal for high performance applications. Active high and low chip enables (CET, CE2) permit easy memory expansion with multiple-bank memory systems. When CEI is High or CE2 is Low the device enters standby mode. The standard AS7C164 is guaranteed not to exceed 11.0 mW power consumption in standby mode, and typically requires only 250 wW, it offers 2.0V data retention with maximum power of 120 pW. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CEI, CE2). Data on the input pins 1/00- 1/07 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CEI or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CEI, CE2), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-irapedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C1 64 is packaged in all high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on any pin relative to GND Vv, 0.5 +7.0 Vv Power dissipation Ph - 1.0 Ww Storage temperature (plastic) Typ 55 +150 C Temperature under bias Thias 10 +85 C DC output current Tour - 20 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this spedfication is not implied. Exposure 10 absolute maximum rating conditions for extended periods may affect reliability. Truth table CET CE2 WE OE Data Made H X X X High Z Standby (Isp, Isp1) X L X X High Z Standby (gp, Igp1) L H H H High Z Output disable L H H L Dou Read L H L x D Write in. Key: X = Dont Care, L = Low, H = High 22 DID 13-20008-A. Copyright 1998 Alliance Semiconductor. All rights reserved.Recommended operating conditions ae: Applicable to all portions of this specification unless otherwise noted. AS7C164 Parameter Symbol Min pp Max Unit Vv 4.5 5.0 5.5 v Supply voltage ce Ppiy wom= GND 0.0 0.0 0.0 V Vv 2.2 - Vectl v Input voltage i oe iL 0.5 - 0.8 Vv Ambient operating temperature T, 0 > 70 * Vy, min = ~3.0V for pulse width less than tp-/2. DC operating characteristics -8 -10 -12 -15 -20 Parameter Symbol Test Conditions Min Max| Min Max| Min Max| Min Max | Min Max | Unit Input leakage Voc = Max, current Nl Vin = GND to Vee ~ ! ~ ~ ' ~ | ~ TBA Output CEI = Vy, or CE2 = Vy, leakage tol = Vec = Max, ~ FPP- P_- PP tyr Fs | pa current Vour = GND to Voc Operating a=a7 _ power supply Ice ee Vie CE omit 120} - 115} 110] ~ 100; ~ 90} mA current ~ max, Tout Igg CEL = Wan or CE2 = Vi, - 40/- 35] - 30] - 25] - 25 |ma f = fnax Standby Ghi>v ay power supply ce : ao or current 7 ~ - ~ ~ - Isp1 V,<0.2V oF 2.0 2.0 2.0 2.0 2.0 | mA Vin 2 Vec-0.2V, f= 0 Output Vo. lo =8mA, Vec = Min ~ 0.4 ~ 0.4 _ 0.4 - 0.4 - 0.4 v voltage Vou lon = 74+ MA, Vec = Min 24 - 124 \- [24 ~ [24 - 124 -|] 9 Capacitance = 1 MHz, T, = room temperature Parameter Symbol Signals Test conditions Max Unit Input capacitance Cy A, CEI, CE2, WE, OE = -V,, = 0V 5 pF 1/O capacitance Cro 1/O Vin = Vour = OV 7 pF Key to switching waveforms E77 Rising input RQ Falling input DID 11-20008-A. Undefined output/dont care 23 Copyright 1998 Alliance Semiconductor. Ail rights reserved.AS7C164 Read cycle -8 -10 -12 -15 -20 Parameter Symbol | Min Max | Min Max} Min Max | Min Max | Min Max | Unit Notes Read cycle time tec 8 - {10 - ]12 -]15 - | 20 - | ns Address access time taa - 8] - 10} - 12} - 15] - 20] ns 3 Chip enable (CET) access time tacer | - 8 | - 10] 12] - 15] - 20] ns 3,12 Chip enable (CE2) access time tac? - 8] - 0] - 12} = 15] - 20] ns 3,12 Output enable (OE) access time tog - 3}]- 347+ #3 }]- 44]- #5 | ns Output hold from address change toy 3 ~}|]3 --]73 -]3 +-]3 +- J] ns 5 CET Low to output in low Z terz1 3 - {13 -|]3 -|{3 +-|3 - | ns 4,5,12 CE2 High to output in low Z torz2 3 -}|3 -|3 -|{|3 -|3 - |] ns 4,5,12 CET High to output in high Z tyz1 | 3 | - 3 | - 3} - 41] - 5 | ns 4,5,12 CE2 Low to output in high Z teyz2 | - 3 | - 3 J - 3 | - 44]- 5 | ms 4,5,12 OE Low to output in low Z toiz oO -|/0 j-|]0 -|]0 -]0 -J] ns 4,5 OE High to output in high Z toxwz | - 3 | - 3 | - 3 | - 4]- 5 |] os 4,5 Power up time tpy 0 - 0 - 0 - 0 - 0 - ns 4,5, 12 Power down time tpp - 8 | = 10} - 12] - 15] - 20] ns 4,5, 12 Read waveform 17% 7% ?2 Address controlled tre Address K ou Data valid Read waveform 27 & % #2 CET and CE2 controlled CET a "Re # CE2 x OE RUM LIL oz i ouzZ Dos [*_ ACE] ," ACE2 _. CHZ1,CHZ2 t terz1,cLz2> tep I cupery id + 50% 50% is 24 DED 11-20008-A. Copyright 1998 Alliance Semiconductor. All rights reserved.AS7C164 a: Write cycle -8 -10 -12 -15 -20 Parameter Symbol | Min Max | Min Max| Min Max| Min Max| Min Max| Unit Notes Write cycle time twe 8 - {10 -] 12 -]15 - |]20 - | ns Chip enable (CE1) to write end twi | 7 - | 8 -]| 9 -|10 -~]12 ~ 4} ns 12 Chip enable (CE2) to write end tew? 7 -~ |] 8 - | 9 -]10 -]12 - 1] ns 12 Address setup to write end taw 7 -~- | 8 -~|] 9 -~}] 10 -]12 ~ |] ns Address setup time tas o -~}]O -~J]o -]0 -]0 +1] ns 12 Write pulse width twe 4 ~] 7 =~] 8 - | 9 =] 12 = | os Address hold from write end tan o -/]0 -~|]0 -|/0 -|]o0 -1] as Data valid to write end tow 5 - {6 -|]6 + ]7 -~]8 =] ns Data hold time toy 0 -|]|90 -+~]o -]/0 -/]0 +1] ns 4,5 Write enable to output in high Z tw - S{[- 5]7)- 5 ]- SJ] 5S |ns 4,5 Output active from write end tow 2 -]2 -|]3 -=-/]3 -+]3 - |] as 4,5 Write waveform 1/8 #4 2 WE controlled Address "pw Din Data valid Dou Write waveform 224 4 42 CET and CE? controlled twe | Taw "aH Address 4 lK tag tew1,tcw2 -4] v CEL A CE2 * WE Din Data valid l B 25 DID 11-20008-A. , Copyright 1998 Alliance Semiconductor. AH rights reserved.AS7C164 ae: Data retention characteristics Parameter Symbol Test conditions Min Max Unit Vcc for data retention Vopr 2.0 - v . Vec = 2.0V Data retention current Iecpr __ - 60 HA ; _ CET > Voc-0.2V or Chip enable to data retention time cpr CE? <0.2 0 - ns Operation recovery time te tac - ns Data retention waveform Data retention mode Veo OO~OCS SW Vp 2 2.0V AAN UU CDR 'R CET Vin DR Vi AC test conditions - Output load: see Figure B, except for toyz and tcq3z7 see Figure C. Thevenin equivalent: 168Q. - Input pulse level: GND to 3.0V. See Figure A. PourViwe + 1.728 - Input rise and fall times: 5 ns. See Figure A. - Input and output timing reference levels: 1.5V. +8V $V 480Q 480Q +3.0V Pout Dour 90% 90% 2550 30 pF* 255 5 pF* _*including scope 10% 10% and jig capacitance GND GND GND Figure A: Input waveform Figure B: Output load Figure C: Output load for tory tqy7 Notes 1 During Vec power-up, a pull-up resistor to Vcc on CEI is required to meet Isp specification. 2 This parameter is sampled and not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B, C. 4 toyz and toyz are specified with CL = SpF as in Figure C. Transition is measured 500mV from steady-state voltage. 5 This parameter is guaranteed but not tested. 6 WEis High for read cycle. 7 CET and OF are Low and CE? is High for read cycle. 8 Address valid prior to or coincident with CET transition Low and CE2 transition High. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 CEI or WE must be High or CE2 Low during address transitions. 11 All write cycle timings are referenced from the last valid address to the first wansitioning address. 12 CET and CE2 have identical timing. 26 DID 11-20008-A. Copyright 1998 Alliance Semiconductor. All rights reserved.Typical DC and AC characteristics Normalized supply current Ing Ign vs. supply voltage Voc mop loc fawn Q Normalized Inc, Isp eso eo 9 oOo RP Fe RK OH a o 4.5 8.0 5.5 Supply voltage (V) 6.0 Normalized access time t vs. supply voltage Voc T, = 25C Normalized access time 4.5 5.0 S55 Supply voltage V) 6.0 Output source current Io; vs. output voltage Voz; _ ow =} 120 Veo = 5.6V T=25 - DB BS OS oO 2 82 co Output source current (mA) Nt oO of o 1.25 Output voltage (V) 25 3.75 5.0 DID 11-20008-A. Normalized supply current lee Isp a ys. ambient temperature AS7C164 Normalized supply current dss a vs. ambient temperature 1.4 1.2 Bb25 a Tec 3 Voc= 5.0 = 1.0 w 25 2 = ~ 0.8 a E a 43 06 Bo B q 5 04 Jog 8 0.2 5 0.2 20.04 0.0 55-10 35 80 125 $5 -10 35 80 125 Ambient temperature (C) Ambient temperature (C) Normalized access time ty 4 Normalized supply current Ice vs, ambient temperature * vs, cycle frequency 1/tge, 1/tyce 1S L4 wy 14 12 g Veo = 5.0V Veo = 5.0V a 1.3 3 1.0 25 1; zy g 1.2 g 0.8 gu 2 0.6 a bw 1.0 Z 04 3 409 0.2 0.8 0.0 -55 -10 35 80 125 25 50 78 100 Ambient temperature (C) Cycle frequency (MHz) Output sink current Ip; Typical access time change At, , vs. output voltage Voy vs. Output capacitive loading 140 35 giro 5 Vor = 5.0V > Voc = 45V wy 00h T= 25 = . E 80 2 5 a 4 60 y, | & 2 g 40 A & UG & 20 0 9.0 1.25 2.5 3.75 5.0 Go 250 $00 750 1000 Output voltage (V) Capacitance (pF) 27 Copyright 1998 Alliance Semiconductor. All rights reserved.AS7C164 a: AS7C 164 ordering codes Package \ Access time 8 ns 10 ns 12 ns 15 ns 20 ns Plastic DIP, 300 mil - AS7C164-10PC AS7C164-12PC AS7C164-15PC AS7C1L64-20PC Plastic SOJ, 300 mil AS7C164-8JC AS7C164-10JC AS7C164-12JC AS7C164-15JC AS7C164-20JC AS7C 164 part numbering system ASTC 164 x XX x Cc Package code: c ecialt F SRAM prefix Device number Blank = Standard power Access time P = PDIP 300 mil ~oramen vantemp ranure _ : range, 0C to 70 C J = SOJ 300 mil 28 DID 11-20008-A. Copyright 1998 Alliance Semiconductor. All rights reserved.