12 AT49LD3200(B) 1940B–FLASH–11/01
and all the address inputs are ignored. In addition, entering a Mode Register Set com-
mand in the middle of a normal operation results in an illegal state in the
AT49LD3200(B).
Power-up The following power-up sequence is recommended.
1. Apply power and start clock. Hold the MR, CKE and DQM inputs high; all other
pins are a NOP condition at the inputs before or along with VCC (and VCCQ)
supply.
2. Set WORD to the desired state (prior to any device operation).
3. To change the default Mode Register Set values, perf orm a Mode Register Set
cycle to program the RAS latency, CAS latency, burst length and burst type.
4. At the end of three clock cycles after the mode register set cycle, the device is
ready for operation.
When the above sequence is used for power-up, all outputs will be in high impedance
state. The high impedance of outputs is not guaranteed in any other power-up
sequence.
For AT49LD3200B, Asynchronous Boot Block will be selected after power-up.
Mode Selection Control Mode selection is controlled by the polarity of WORD pin. WORD should be set to the
desired state during power-up and prior to any device operation. The AT49LD3200(B)
can be organized as either double word wide (x32) or word wide (x16). The organization
is selected via the WORD pin. W hen WORD is asserted high (VIH) , the double wo rd-
wide organization is selected. When WORD is asser t e d low (VIL), the word-wid e or gan i-
zation is selected.
Address Decoding The address bits required to decode one of the available cell locations out of the total
depth are multiplexed onto the address select pi ns and latched by ex ternally applying
two commands. The first command, RAS asserted low, latches the row address into the
device. A second command, CAS asserted low, subsequently latches the column
address.
Mode Register Set (MRS ) The mode register stores the data for controlling the various operating modes of
AT49L D3200(B). It prog rams the RAS la tency, CAS late ncy, burst lengt h, burst type,
selects product ID Read or activates the Asynchronous Boot Block. For
AT49LD3200(B), the default value of the mode register is defined as array read with
RAS l atenc y = 2, CAS la tency = 5, bu rst l engt h = 4, s equ entia l b urs t type . Wh en and if
the user wants to change its values, the user must exit from power-down mode and start
Mode Regis ter S et before e ntering n ormal operatio n mode. T he mo de regis ter is r epro-
grammed by asserting low on CS, RAS, CAS and MR (the AT49LD3200(B) should be in
active mode with CKE already high prior to writing the mode register). The state of
addres s pins A0 ~ A7 in the same c ycl e as CS, RAS, CA S and M R going low is the da ta
written in the mode re gist e r. Three cl oc k cycle s are re qui red t o comple te the pr ogr am in
the mode regi ster, t herefo re a fter a M ode Re giste r Se t com mand is com pleted, no n ew
comma nds can be issued fo r 3 clock c ycles and CS or MR must be high within 3 clock
cycles. The mode regis ter is div ided i nto v arious fiel ds, dep ending o n functi onali ty. Th e
burst length fiel d uses A0 ~ A1, bu rst t ype use s A2, C AS late ncy (re ad l atenc y from co l-
umn ad dress) uses A 3 ~ A5, RAS latenc y uses A6 (RA S to C AS delay) , array r ead or
product ID read uses A7. Refer to Mode Reg ister Control T able for s pecific cod es for
various burst lengths, burst types, CAS latencies, RAS latencies, and read modes.