Features * 3.0V to 3.6V Read/Write * Burst Read Performance * * * * * * * * * * - <100 MHz (RAS Latency = 2, CAS Latency = 6), 10 ns Cycle Time tSAC = 7 ns - <75 MHz (RAS Latency = 2, CAS Latency = 5), 13 ns Cycle Time tSAC = 8 ns - <50 MHz (RAS Latency = 1, CAS Latency = 4), 20 ns Cycle Time tSAC = 9 ns MRS Cycle with Address Key Programs - RAS Latency (1 and 2) - CAS Latency (2 ~ 8) - Burst Length: 4, 8 - Burst Type: Sequential and Interleaved Word Selectable Organization - 16 (Word Mode)/x 32 (Double Word Mode) Sector Erase Architecture - Eight 256K Word or 128K Double Word (4-Mbit) Sectors Independent Asynchronous Boot Block - 8K x 16 Bits with Hardware Lockout Fast Program Time - 3-volt, 100 s per Word/Double Word Typical - 12-volt, 30 s per Word/Double Word Typical Fast Sector Erase Time - 2.5 Seconds at 3 Volts - 1.6 Seconds at 12 Volts Low-power Operation - ICC Read = 75 mA Typical Input and Output Pin Continuity Test Mode Optimizes Off-board Programming Package: - 86-pin TSOP Type II with Off-center Parting Line (OCPL) for Improved Reliability LVTTL-compatible Inputs and Outputs 32-megabit (1M x 32 or 2M x 16) High-speed Synchronous Flash Memory AT49LD3200 AT49LD3200B SFlashTM Description The AT49LD3200 or AT49LD3200B SFlashTM is a synchronous, high-bandwidth Flash memory fabricated with Atmel's high-performance CMOS process technology and is organized either as 2,097,152 x 16 bits (word mode) or as 1,048,576 x 32 bits (double word mode), depending on the polarity of the WORD pin (see Pin Function Description Table). Synchronous design allows precise cycle control. I/O transactions are possible on every clock cycle. All operations are synchronized to the rising edge of the system clock. The range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high-bandwidth, high-performance memory system applications. The AT49LD3200B will automatically activate the Asynchronous Boot Block after power-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be activated through Mode Register Set. The synchronous DRAM interface allows designers to maximize system performance while eliminating the need to shadow slow asynchronous Flash memory into highspeed RAM. The 32-megabit SFlash device is designed to sit on the synchronous memory bus and operate alongside SDRAM. Rev. 1940B-FLASH-11/01 1 To maximize system manufacturing throughput the AT49LD3200(B) features highspeed 12-volt program and erase options. Additionally, stand-alone programming cycle time of individual devices or modules is optimized with Atmel's unique input and output pin continuity test mode. Pin Configuration TSOP (Type II) Top View VCC DQ0 VCCQ DQ16 DQ1 VSSQ DQ17 DQ2 VCCQ DQ18 DQ3 VSSQ DQ19 MR VCC DQM NC CAS RAS CS WORD A12 A11 A10 A0 A1 A2 NC VCC NC DQ4 VSSQ DQ20 DQ5 VCCQ DQ21 DQ6 VSSQ DQ22 DQ7 VCCQ DQ23 VCC 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ31 VSSQ DQ15 DQ30 VCCQ DQ14 DQ29 VSSQ DQ13 DQ28 VCCQ DQ12 NC VSS NC VPP WE CLK CKE A9 A8 A7 A6 A5 A4 A3 NC VSS NC DQ27 VCCQ DQ11 DQ26 VSSQ DQ10 DQ25 VCCQ DQ9 DQ24 VSSQ DQ8 VSS AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Pin Function Description Pin Name Input Function CLK System Clock Active on the rising edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK and CKE. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for powerdown in standby mode. A0 - A12 Address Row/column addresses are multiplexed on the same pins. Row address: RA0 ~ RA12, Column address: CA0 ~ CA6 (x32), CA0 ~ CA7 (x16) RAS Row Address Strobe Latches row addresses on the rising edge of the CLK with RAS low. Enables row access. CAS Column Address Strobe Latches column addresses on the rising edge of the CLK with CAS low. Enables column access. MR Mode Register Set Enables mode register set with MR low. (Simultaneously CS, RAS and CAS are low). DQ0 - DQ31 Data Input/Output Data input for program/erase. Data output for read. VCC/VSS Power Supply/Ground Power and ground for the input buffers and the core logic. VCCQ/VSSQ Data Output Power/Ground Power and ground for the output buffers. WORD x32/x16 Mode Selection Double word mode/word mode, depending on polarity of WORD pin (WORD = high, double word mode; WORD = low, word mode). Should be set to the desired state during power-up and prior to any device operation. DQM Data-out Masking Masks output operation when a complete burst is not required. NC No Connection Not connected WE Write Enable Enables the chip to be written. VPP Program/Erase Pin Supply Program/Erase power supply. 3 1940B-FLASH-11/01 Absolute Maximum Ratings* *NOTICE: Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground .....................................-0.6V to +4.6V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on VPP with Respect to Ground ...................................-0.6V to +13.5V Power Dissipation .............................................................. 1 W Functional Block Diagram DQ0 WE VPP DQ16 DQ15 DQ31 IO Buffer Program/ Erase Logic ADD 1M x 32 Cell Array LRAS Column Decoder Column Buffer LCKE LRAS Sense AMP Row Decoder Row Buffer ADD Address Register CLK 8K x 16 Boot Block Latency & Burst Length Programming Register LMR LCAS Timing Register CLK 4 CKE MR RAS CAS CS DQM AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) DC and AC Operating Range Operating Temperature (Case) Commercial Industrial VCC, VCCQ Power Supply AT49LD3200(B)-10 AT49LD3200(B)-13 AT49LD3200(B)-20 0C - 70C 0C - 70C 0C - 70C -40C - 85C -40C - 85C -40C - 85C 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V DC Characteristics Symbol Parameter Condition ISB1 VCC Standby Current CMOS ISB2 Max Units CKE = 0, tCC = Min 20 mA VCC Standby Current TTL CKE VIL (Max), tCC = Min 20 mA ISB3 VCC Active Standby Current CS VIH (Min), tCC = Min 50 mA ICC VCC Active Current tCC = Min, All Outputs Open 150 mA IIL Input Leakage Current 0V VIN VDD + 0.3V Pins not under test = 0V -10 10 A IOL Output Leakage Current (IOOUT Disabled) (0V VOUT VDD Max) All Outputs in High-Z -10 10 A VIH Input High Voltage, All Inputs Note(1) 2.0 VDD + 0.3 V VIL Input Low Voltage, All Inputs Note(2) -0.3 0.8 V VOH Output High Voltage Level (Logic 1) IOH = -2 mA 2.4 VOL Output Low Voltage Level (Logic 0) IOL = 2 mA Notes: Min V 0.4 V 1. VIH (max) = 4.6V for pulse width <10 ns acceptable, pulse width measured at 50% of pulse amplitude. 2. VIL (min) = -1.5V for pulse width <10 ns acceptable, pulse width measured at 50% of pulse amplitude. AC Operating Test Conditions TA = 0 to 70C, VCC = 3.3V 0.3V, unless otherwise noted. Parameter(1) Value Timing Reference Levels of Input/Output Signals 1.4V Input Signal Levels Transition Time (Rise & Fall) of Input Signals Output Load Note: VIH/VIL = 2.4V/0.4V tr/tf = 1 ns/1 ns LVTTL 1. If CLK transition time is longer than 1 ns, timing parameters should be compensated. Add [(tr + tf)/2-1] ns for transition time longer than 1 ns. Transition time is measured between VIL (max) and VIH (min). 5 1940B-FLASH-11/01 Figure 1. DC Output Load Circuit 3.3V 1200 V OH (DC) = 2.4V, I OH= -2 mA V OL (DC) = 0.4V, I OL= 2 mA Output 870 50 pF Figure 2. AC Output Load Circuit Vtt = 1.4V 50 Output Z0 = 50 50pF Pin Capacitance(1) f = 1 MHz, T = 25C Symbol CIN COUT (2) Notes: 6 Typ Max Units Conditions 4 6 pF VIN = 0V 8 12 pF VOUT = 0V 1. This parameter is characterized and is not 100% tested. 2. VPP behaves as an output pin. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) AC Read Characteristics AC operating conditions unless otherwise noted. <100 MHz Min Max <75 MHz Min Max <50 MHz Min Max Units Symbol Parameter tCC CLK Cycle Time tSAC CLK to Valid Output Delay tOH Data Output Hold Time 3 4 4 ns tCH CLK High Pulse Width 3 4 6.5 ns tCL CLK Low Pulse Width 3 4 6.5 ns 11 10 9 clks 10 (1) 13 7 20 8 ns 9 ns tRC Row-active to Row-active tSS Input Setup Time 2 4 4 ns tSH Input Hold Time 1 2 2 ns tSLZ CLK to Output in Low-Z 0 0 0 ns tSHZ CLK to Output in High-Z tT Transition Time tVCVC Valid CAS Enable to Valid CAS Enable(2) Notes: 7 0.1 9 10 10 0.1 8 10 0.1 7 15 ns 10 ns clks 1. These tRC values are for BL = 8. For BL = 4, tRC = 7 CLKs for up to 100 MHz, tRC = 6 CLKs for up to 75 MHz, tRC = 5 CLKs for up to 50 MHz. RAS latency increase means a simultaneous tRC increase in the same number of cycles. (If RAS latency is 3 CLKs, tRC is 12 CLKs for BL = 8.) Refer to page 27 for gapless operation. 2. These tVCVC values are for BL = 8. For BL = 4, tVCVC = 5 CLKs for up to 100 MHz, tVCVC = 4 CLKs for up to 75 MHz, tVCVC = 3 CLKs for up to 50 MHz. Refer to page 27 for gapless operation. 7 1940B-FLASH-11/01 Function Truth Table (V = Valid, X = Don't Care, H = Logic High, L = Logic Low) Abbreviations (RA: Row Address, CA: Column Address, NOP: No Operation Command, DWM: Double Word Mode, WM: Word Mode) CKEn-1 CKEn CS RAS CAS MR(9) DQM Add. WORD VPP WE Mode Register Set H X L L L L X Code X X X Row Active Row Access & Latch H X L L H H X RA X X X Read Column Access & Latch H X L H L H X CA X X H H X L H H L X X X X X H X L L H L X X X X X Entry H L X X X X X X X X X Exit L H X X X X X X X X X H X X X X X V X X X X H X H X X X X X X X X H X L H H H X X X X X H X L H L H X CA X H Command Register (1) Burst Stop Power-down and Clock Suspend(2) (Precharge on Synch. DRAM) Two Standby Mode DQM(3) No Operation Command(4) H Organization Control(5) L Program/Erase(6) H X L H L X X CA X X L (6) H X L H L X X CA X 12V L Program/Erase Inhibit H X H X X X X X X X X Mode Register Set H X L L L L X A7 = H X X X Read H X L H L H X L X X H H X L H L X X CA X X L X X X Fast Program/Erase Product Identification(7) Entry Continuity Test Mode Exit Notes: 8 X X X X X X X Code (8) 1. A0 ~ A6: Program keys (@MRS). After power-up, mode register set can be set before issuing other input command. After the Mode Register Set command is completed, no new commands can be issued for 3 CLK Cycles, and CS or MR state must be defined "H" within 3 CLK cycles. Refer to the Mode Register Control Table. 2. In the case CKE is low, two standby modes are possible. Those are standby mode in power-down, and active standby mode in clock suspend (non-power-down). Power-down: CKE = "L" (after no command is issued for 60 s) Clock Suspend: CKE = "L" (at the range of Row Active, Read and Data Out) 3. DQM sampled at rising edge of a CLK makes a high-Z state the data-out state, delayed by 2 CLK cycles. 4. Precharge command on Synch. DRAM can be used for Burst Stop operation during burst read operation only. 5. Mode selection is controlled by the polarity of WORD pin, "H" state is DWM, "L" state is WM. WORD should be set to the desired state during power-up and prior to any device operation. 6. Data is provided through DQ0 ~ DQ31. Refer to AC programming and erasing waveforms. 7. DQ0 ~ DQ31 will output Manufacturer Code/Device Code. 8. A0 = A2 = A11 = "H", A1 = A10 = A12 = "L" 9. The user can tie MR and WE together to simplify the interface of the AT49LD3200(B) onto the standard SDRAM bus. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Asynchronous Boot Block Function Truth Table Command Read Output Disable CLK(2) CKE(2) CS RAS CAS MR DQM Add. WORD VPP WE X X L X X X L Add X X X X X L X X X H X X X X (1) Program/Erase H L H L X X Add X X L (1) H L H L X X Add X 12V L Program/Erase Inhibit H H X X X X X X X X Fast Program/Erase Notes: 1. Program/Erase is performed through the synchronous bus cycle operation after the boot block is activated through either power-up or Mode Register Set. 2. It is recommended to hold CKE Low if CLK is running during asynchronous boot block mode except for synchronous command cycle and MRS operations. Mode Register Control Table(1) Register Programmed with MRS Address A7 A6 Function Product ID RAS Latency Product ID A5 RAS Latency A4 A3 A2 CAS Latency A1 Burst Type CAS Latency A0 Burst Length Burst Type Burst Length A7 "Read" A6 Type A5 A4 A3 Length A2 Type A1 A0 Length 0 Array 0 1 0 0 0 Reserved 0 Sequential 0 0 Reserved 1 ID 1 2 0 0 1 2 1 Interleave 0 1 4 0 1 0 3 1 0 8 0 1 1 4 1 1 Boot Block 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 Note: 1. After power-up, when the user wants to change Mode Register Set, the user must exit from power-down mode and start Mode Register Set before entering normal operation mode. Reserved modes are not to be used; device function in these modes is not guaranteed. 9 1940B-FLASH-11/01 Addressing Map WORD = "H": x32 Organization(1) Function A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Row Address RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 X X X X X X Column Address Note: CA0 CA1 CA2 CA3 CA4 CA5 CA6 (1) 1. Column Address MSB (at x32 organization) (X = Don't Care) WORD = "L": x16 Organization(1) Function A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Row Address RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 X X X X X Column Address Note: CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 (1) 1. Column Address MSB (at x16 organization) (X = Don't Care) Each Address is Arranged as Follows(1)(2) For X32 operation, MSB LSB Address Register AR19 AR18 AR17 ... AR8 AR7 AR6 ... AR3 AR2 AR1 AR0 Address RA12 RA11 RA10 ... RA1 RA0 CA6 ... CA3 CA2 CA1 CA0 BL = 4 * Initial Address Notes: 10 BL = 8 1. For X16 operation, when CA0 is set to Low, data belonging to 0 ~ 15th registers are output to DQ0 ~ DQ15 pins, and when CA0 is set to High, data belonging to 16 ~ 31th registers are output to DQ0 ~ DQ15 pins. 2. Asynchronous Boot Block uses x16 operation and A0 ~ A12 as address inputs. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Burst Sequence (Burst Length = 4) Initial Address A1 A0 Sequential Interleave 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 Burst Sequence (Burst Length = 8) Initial Address A2 A1 A0 Sequential Interleave 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 Device Operations Clock (CLK) A square wave signal (CLK) must be applied externally at cycle time tCC. All operations are synchronized to the rising edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high, all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around the positive edge of the clock for proper functionality and ICC specifications. Clock Enable (CKE) The clock enable (CKE) gates the clock into the AT49LD3200(B) and is asserted high during all cycles, except for power-down, standby and clock suspend mode. If CKE goes low synchronously with clock (setup and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen for as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. The AT49LD3200(B) remains in the power-down mode, ignoring other inputs for as long as CKE remains low. The power-down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1 CLK + tSS" before the rising edge of the clock, then the AT49LD3200 becomes active from the same clock edge accepting all the input commands. NOP and Device Deselect When RAS, CAS and MR are high, the AT49LD3200(B) performs no operation (NOP). NOP does not initiate any new operation. Device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR 11 1940B-FLASH-11/01 and all the address inputs are ignored. In addition, entering a Mode Register Set command in the middle of a normal operation results in an illegal state in the AT49LD3200(B). Power-up The following power-up sequence is recommended. 1. Apply power and start clock. Hold the MR, CKE and DQM inputs high; all other pins are a NOP condition at the inputs before or along with VCC (and VCCQ) supply. 2. Set WORD to the desired state (prior to any device operation). 3. To change the default Mode Register Set values, perform a Mode Register Set cycle to program the RAS latency, CAS latency, burst length and burst type. 4. At the end of three clock cycles after the mode register set cycle, the device is ready for operation. When the above sequence is used for power-up, all outputs will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence. For AT49LD3200B, Asynchronous Boot Block will be selected after power-up. Mode Selection Control Mode selection is controlled by the polarity of WORD pin. WORD should be set to the desired state during power-up and prior to any device operation. The AT49LD3200(B) can be organized as either double word wide (x32) or word wide (x16). The organization is selected via the WORD pin. When WORD is asserted high (VIH), the double wordwide organization is selected. When WORD is asserted low (VIL), the word-wide organization is selected. Address Decoding The address bits required to decode one of the available cell locations out of the total depth are multiplexed onto the address select pins and latched by externally applying two commands. The first command, RAS asserted low, latches the row address into the device. A second command, CAS asserted low, subsequently latches the column address. Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of AT49LD3200(B). It programs the RAS latency, CAS latency, burst length, burst type, s e l e c t s p r o d u c t ID R e a d o r ac ti v a te s t h e A s y n c h r on o u s B o o t B l o c k . Fo r AT49LD3200(B), the default value of the mode register is defined as array read with RAS latency = 2, CAS latency = 5, burst length = 4, sequential burst type. When and if the user wants to change its values, the user must exit from power-down mode and start Mode Register Set before entering normal operation mode. The mode register is reprogrammed by asserting low on CS, RAS, CAS and MR (the AT49LD3200(B) should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ A7 in the same cycle as CS, RAS, CAS and MR going low is the data written in the mode register. Three clock cycles are required to complete the program in the mode register, therefore after a Mode Register Set command is completed, no new commands can be issued for 3 clock cycles and CS or MR must be high within 3 clock cycles. The mode register is divided into various fields, depending on functionality. The burst length field uses A0 ~ A1, burst type uses A2, CAS latency (read latency from column address) uses A3 ~ A5, RAS latency uses A6 (RAS to CAS delay), array read or product ID read uses A7. Refer to Mode Register Control Table for specific codes for various burst lengths, burst types, CAS latencies, RAS latencies, and read modes. 12 AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Latency There are latencies between the issuance of a Row Active command and when data is available on the I/O buffers. The RAS to CAS delay is defined as the RAS latency. The CAS to data out delay is the CAS latency. The CAS and RAS latencies are programmable through the mode register. RAS latencies of 1 and 2, and CAS latencies of 2 through 6 are supported. It is understood that some RAS and CAS latency values are reserved for future use, and are not available in this generation of synchronous Flash. The following are the supported minimum values: RAS latency = 2, and CAS latency = 6 for 100 MHz operation, and RAS latency = 2, and CAS latency = 5 for 66 MHz operation, and RAS latency = 1, and CAS latency = 4 for 50 MHz operation, and RAS latency = 1, and CAS latency = 3 for 33 MHz operation. DQM Operation The DQM is used to mask output operations when a complete burst read is not required. It works similar to OE during a read operation. The read latency is two cycles from DQM, which means DQM masking occurs two cycles later in the read cycle. DQM operation is synchronous with the clock. The masking occurs for a complete cycle. (Also refer to the DQM timing diagram.) Burst Read The Burst Read command is used to access a burst of data on consecutive clock cycles from an active row state. The Burst Read command is issued by asserting low CS and CAS with MR being high on the rising edge of the clock. The first output appears in CAS latency number of clock cycles after the issuance of the Burst Read command. The burst length, burst sequence and latency from the Burst Read command are determined by the mode register, which is already programmed. Burst read can be initiated on any column address of the active row. The output goes into high-impedance at the end of the burst, unless a new burst read is initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read. Sector Erase Before a word/double word can be reprogrammed, it must be erased. The erased state of the memory bits is a logical "1". The AT49LD3200(B) is organized into eight uniform four megabit sectors (SA0 - SA7) that can be individually erased. The Sector Erase command is a synchronous six-bus cycle operation (refer to the Command Definition table and Program Cycle and Erase Cycle waveforms). The erase code consists of 6byte (DQ8 - DQ31 are Don't Care inputs for the command) load commands to specific address locations with a specific data pattern. The sector address and 30H data input are latched in the sixth cycle. The sector erase starts at the following rising edge of CLK after the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. Any commands written to the device during the erase cycle will be ignored. The maximum time needed to erase one sector is tEC. Word/Double Word Programming Once a sector is erased, it is programmed (to a logical "0") on a word-by-word/doubleword-by-double-word basis. Programming is accomplished via the internal device command register and is synchronous four-bus cycle operation (refer to the Command Definition table and Program Cycle and Erase Cycle waveforms). The programming operation starts at the following rising edge of CLK after the fourth cycle. The device will automatically generate the required internal program pulses. Any commands written to the device during the embedded programming cycle will be ignored. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tPGM cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. 13 1940B-FLASH-11/01 Product Identification The product identification mode identifies the device and manufacturer as Atmel. This mode can be used by an on-board controller or external programmer to identify the correct programming algorithm for the Atmel product. DATA Polling The AT49LD3200(B) features DATA polling to indicate the end of a program or sector erase cycle. DATA polling may begin at any time during the program or sector erase cycle. During a program cycle, an attempted read of the last word/double word loaded will result in the complement of the loaded data in DQ7. Once the program cycle has completed, true valid data can be read on all outputs and the next cycle may begin. During a sector erase operation, an attempt to read the device will give a "0" on DQ7. Once the sector erase cycle has completed, logical "1" data can be read on all outputs from the device. Hardware Data Protection Hardware features protect against inadvertent programming or erasure to the AT49LD3200(B) in the following way: VCC sense: if VCC is below 2.3V (typical), the program or erase function is inhibited; but if VCC dips below 2.3V during program or erase cycle, the respective function will be interrupted and the data at the location being programmed may be corrupted. Continuity Test Mode The AT49LD3200(B) has built-in circuitries to make input and output pin continuity check simple and easy. This mode can be activated via the internal device command register and is a synchronous five-bus cycle operation (refer to the Command Definition Table and Continuity Test Mode Entry Waveforms). After the bus cycle operation, keep DQM high (VIH) and allow 5 sec for circuit setup time or until data is no longer asserted at DQ0 - DQ7, whichever takes longer. This will keep DQ0 - DQ7 from contention since data is asserted at DQ0 - DQ7 during the mode entry sequence. Then DQM can be asserted low (VIL) to enable DQ0 - DQ7 for test. Once in this asynchronous mode, input pins are virtually tied to output pins internally forming input - output pin pairs. The output pin of the pair will follow the logic state of the input pin of the pair (refer to the Input Output Pin Pairs table). To exit the mode, A0, A2 and AII are asserted high (VIH) and A1, A10 and A12 are asserted low (VIL), allow 5 sec for circuit recovery time before returning the device for normal operation. 14 AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Input - Output Pin Pairs Asynchronous Boot Block Input Output MR DQ0, DQ16 RAS DQ1, DQ17 CAS DQ2 DQM DQ18 CS DQ3 WORD DQ19 A12 DQ4 A11 DQ20 A10 DQ5 A0 DQ21 A1 DQ6, DQ22 A2 DQ7, DQ23 A3 DQ8, DQ24 A4 DQ9, DQ25 A5 DQ10 A6 DQ26 A7 DQ11 A8 DQ27 A9 DQ12 CKE DQ28 CLK DQ13, DQ29 WE DQ14, DQ30 VPP DQ15, DQ31 The AT49LD3200B will automatically activate the Asynchronous Boot Block after power-up and the AT49LD3200 can activate the Asynchronous Boot Block through the Mode Register Set. The size of the boot block is 8K x 16 bits with addresses A0 ~ A12 and outputs DQ0 ~ DQ15. The contents of the boot block are accessed asynchronously, meaning the data at outputs will change according to the address inputs after tACC, without any external clocking signals. Programs and erases are performed using the synchronous bus cycle operation (refer to Command Definitions table and Program Cycle and Erase Cycle waveforms) after the boot block is activated either through power-up or Mode Register Set. Programming of the boot block is set up for x16 mode. This Asynchronous Boot Block has a lockout feature that prevents programming or erasing of data in this boot block once the feature has been enabled. This feature does not have to be activated; the boot block's usage as a protected region is optional to the user. Once this feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 3.6V or less are used. To activate the lockout feature, 15 1940B-FLASH-11/01 Boot Block Lockout command, which is a synchronous five-bus cycle operation, must be performed (refer to Command Definitions table and Program Cycle Waveforms). A software method is available to determine if programming or erasing of the boot block is locked out. Issue Boot Block Lockout Verify command and observe DQ0 ~ DQ7. If the data show 00H/02H, the boot block can be programmed or erased; if the data show 01H/03H, the lockout feature has been enabled and the boot block cannot be programmed or erased. The Boot Block Lockout Verify Exit command should be used to return to standard operation (refer to Command Definition table and Boot Block Lockout Verify Waveforms). The user can override the boot block lockout by taking the MR pin to 12 volts after the boot block is activated. When the MR pin is brought back to TTL levels, the boot block lockout feature is again active. 16 AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Command Definition in Hex(1) Command Sequence 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle Bus Cycles RA CA Data RA CA Data RA CA Data RA CA Data Word/ Double Word Program 4 AA 55 AA 55 2A 55 AA 55 A0 RA CA DIN Sector Erase 6 AA 55 AA 55 2A 55 AA 55 80 AA 55 Continuity Test Mode Entry 5 AA 55 AA 55 2A 55 AA 55 80 AA Boot Block Lockout 5 AA 55 AA 55 2A 55 AA 55 80 Boot Block Lockout Verify 5 AA 55 AA 55 2A 55 AA 55 Boot Block Lockout Verify Exit 5 AA 55 AA 55 2A 55 AA 55 Notes: 5th Bus Cycle 6th Bus Cycle RA CA Data RA CA Data AA 55 2A 55 SA(2) X 30 55 AA AA 55 70 AA 55 AA AA 55 40 80 AA 55 AA AA 55 90 80 AA 55 AA AA 55 F0 1. The DATA FORMAT in each bus cycle is as follows: DQ31 - DQ8 (Don't Care); DQ7 - DQ0 (Hex). 2. SA = Sector Addresses: Any word/double word address within a sector can be used to designate the sector address. See Sector Address Mapping table below. 3. Allow minimum 200 ns after Boot Block Lockout Verify command and before Read. 4. Allow minimum 10 s after Boot Block Lockout Verify Exit command for the device to return to standard operation. Sector Address Mapping x16 Address Range x32 Address Range Sector Size (Word/Double Word) CA7-0 RA12-0 CA6-0 RA12-0 SA0 256K/128K X 00XX 03XX X 00XX 03XX SA1 256K/128K X 04XX 07XX X 04XX 07XX SA2 256K/128K X 08XX 0BXX X 08XX 0BXX SA3 256K/128K X 0CXX 0FXX X 0CXX 0FXX SA4 256K/128K X 10XX 13XX X 10XX 13XX SA5 256K/128K X 14XX 17XX X 14XX 17XX SA6 256K/128K X 18XX 1BXX X 18XX 1BXX SA7 256K/128K X 1CXX 1FXX X 1CXX 1FXX 17 1940B-FLASH-11/01 Basic Feature and Function Descriptions MRS Mode Register Set CLK CMD MRS ACT (1) 3CLK Clock Suspend Clock Suspended During Burst Read (BL=4) CLK CMD RD CKE Masked by CKE Internal CLK Data DQ0 D0 1 DQ DQ 2 DQ 3 : This command cannot be activated. Suspended Dout Clock Suspend Exit and Power-down Exit 1) Clock Suspend Exit 2) Power Down CLK CKE CLK tSS CKE Internal CLK CMD Note: 18 t SS Internal CLK RD CMD NOP ACT After Mode Register Set command is completed, no new commands can be issued for 3 clock cycles, and MR or CS should be fixed "H" within a minimum of 3 clock cycles. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) DQM Operation 1) Read Mask (BL=4) CLK CMD RD DQM Data(CL2) DQ0 DQ1 DQ0 Data(CL3) Masked by DQM High-Z DQ3 High-Z High-Z Data(CL4) DQ2 DQ 3 DQ1 DQ2 DQ3 DQM to Data-out Mask = 2CLKs 2) DQM with Clock Suspended (BL=8) CLK CMD RD CKE DQM (1) Data(CL2) Data(CL3) Data(CL4) Note: DQ0 D1DQ1 DQ0 High-Z High-Z High-Z DQ 3 DQ2 DQ 1 High-Z High-Z High-Z DQ 5 DQ4 DQ 3 High-Z High-Z High-Z DQ7 DQ 6 DQ7 DQ 5 DQ 6 DQ7 DQM makes data out high-Z after 2 CLKs, which should be masked by CKE "L". 19 1940B-FLASH-11/01 Read Cycle I: Normal @RAS Latency = 2, CAS Latency = 5, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCL tCC HIGH CKE tRC tSH CS tSS RAS Latency tSH RAS tSS CAS tSH ADDR RAa CAa RAb CAb tSS tRC=6 clocks at BL=4 (1) tOH DQa0 DQa1 DQa2 DQa3 Data tSAC DQb0 DQb1 DQb2 DQb3 tSHZ MR Row Active Note: 20 Read Row Active Read : Don't Care When the burst length is 4 at 66 MHz, tRC is equal to 6 clock cycles. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Read Cycle II: Consecutive Column Access @RAS Latency = 2, CAS Latency = 5, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCL tCC HIGH CKE tSH CS t SS RAS Latency tSH RAS tSS CAS tSH ADDR RAa CAa CAb tSS t VCVC=4 clocks at BL=4 tOH Burst Length=4 Data DQa0 DQa1 DQa2 DQa3 DQb0 DQb1 DQb2 DQb3 tSAC tSHZ MR Row Active Read Read : Don't Care Note: When column access is initiated beyond tVCVC, at BL = 4, CAa access read is completed, CAb access read begins. 21 1940B-FLASH-11/01 Read Cycle III: Clock Suspend @RAS Latency = 2, CAS Latency = 5, Burst Length = 4 0 1 2 3 tCH 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCL t CC CKE (1) Internal CLK CS RAS Latency tSH RAS t SS CAS t SH ADDR RAa t SS CAa tVCVC= 4 clocks at BL=4 (2) Data Burst Length=4 DQa0 DQa1 DQa2 DQa3 MR Row Active Read Clock Suspend Resume : Don't Care Notes: 22 1. From next clock after CKE goes low, clock suspension begins. 2. For clock suspension, data output state is held and maintained. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Read Interrupted by Precharge Command and Burst Read Stop Cycle @Burst Length = 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK HIGH CKE CS RAS CAS RAa ADDR CAa CAb (1) (1) CL=2 DQa0 DQa1 DQa2 DQa3 DQa4 Data DQb0 DQb1 DQb2 DQb3 DQb4 DQb5 (2) (2) CL=3 DQa0 DQa1 DQa2 DQa3 DQa4 DQb0 DQb1 DQb2 DQb3 DQb4 DQb5 MR DQM (1)(2) Row Active Read Burst Stop Read Precharge : Don't Care Notes: 1. The Burst Stop command is valid at every page burst length. The data bus goes to high-Z after the CAS latency from the Burst Stop command is issued. 2. The interval between Read command (column address presented) and Burst Stop command is 1 cycle (min). 23 1940B-FLASH-11/01 Power-down and Clock Suspend Cycle: @RAS Latency = 2, CAS Latency = 5, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tSS CKE (1) (1) Power Down Clock Suspend (3) CLK (internal) CS RAS CAS (2) ADDR t SH NOP RAa CAa tSS Data MR Data High-Z State DQa0 DQa1 DQa2 DQa3 (High) Row Active Power-down Entry Power-down Exit Read Clock Suspend Entry Clock Suspend Exit : Don't Care Notes: 24 1. From next clock after CKE goes low, clock suspend and power-down begins. 2. After power-down exit, NOP should be issued and new command can be issued after 1 clock. 3. Clock suspend is in active standby mode. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Mode Register Set: @RAS Latency = 2, CAS Latency = 5, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCC tCL HIGH CKE tSH CS t SS RAS CAS ADDR Code RAa CAa Data High-Z State Data DQa0 DQa1 DQa2 DQa3 MR MRS Row Active : Don't Care Notes: 1. After the Mode Register Set is completed, no new commands can be issued for 3 CLK cycles. 2. After power-up, necessarily Mode Register Set should be completed at least one time and CS or MR must be fixed "H" within 3 clock cycles, and when user wants to change Mode Register Set, user must exit from power-down mode and start Mode Register Set before chip enters normal operation mode. 25 1940B-FLASH-11/01 Detailed Functional Truth Table Input Signal Current State After Power-up(1) Row Active CKE CS RAS CAS MR Add. L X X X X X H L L H H RA H L L L L Code H L L H H RA If consecutive row access is issued within tRC (min.) without CAS enabling, only the final RA is valid. H L H L H CA Begin READ; latch CA H L L L L Code L X X X X X H L L H H Next State Operation Power-down Row Active; latch RA Mode Register Set Illegal(1) Clock Suspend RA Row Access in Read State, within the tRC, previous read is ignored and new row is activated. Beyond the tRC, previous read is completed and new read begins. Consecutive Column Access, within the tVCVC, only the final CA is valid and the previous burst read is ignored. Beyond the tVCVC, the previous read is completed and new read begins. H L H L H CA H L L H L X NOP (after Burst Read)/Read Interrupt H L H H L X NOP (after Burst Read)/Read Interrupt H L L L L Code L X X X X X Clock Suspend/Power-down Any State L L L L H X Low Power Consumption Mode Any State H L H H H X NOP H L L L H X Illegal H L H L L CA Illegal READ Illegal(1) Any State Note: 26 1. After the power-up, when user wants to change MR Set, user must exit from power-down mode and start MR Set before chip enters normal operation mode. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Technical Notes Frequency vs. AC Parameter Relationship Table(1) <100 MHz Burst Length RAS Latency 4 2 8 CAS Latency tRC (min) tVCVC (min) 6 7 5(2) 7 8 6 6 11 9(2) 7 12 10 CAS Latency tRC (min) tVCVC (min) 5 6 4(2) 6 7 5 5 10 8(2) 6 11 9 CAS Latency tRC (min) tVCVC (min) 2 <75 MHz Burst Length RAS Latency 4 2 8 2 <50 MHz Burst Length RAS Latency 4 4 8 Notes: 1 1 (2) 4 3/4(2) 5 5 4(2) 6 6 5 4 8(2) 7/8(2) 5 9 8(2) 6 10 9 1. Above tables are not specifications values, but rather the actual number of clock cycles. There are no gapless operations for CAS latency 7 and 8. 2. Minimum clocks for gapless operation. 3. tRC (max) = tVCVC (max) = 50 s. If tRC (max) or tVCVC (max) has been reached, a new "ACTIVE" command is necessary for new access. 27 1940B-FLASH-11/01 CAS Interrupt Read interrupted by Read (BL=4) (1) CLK CMD RD RD ADD A B Data(CL2) DQB0 DQB1 DQB2 DQB3 Data(CL3) DQB0 DQB1 DQB2 DQB3 Data(CL4) DQB 0 DQB1 DQB2 DQB3 (2) Notes: 1. By "Interrupt", it is meant to stop Burst Read by external command before the end of burst. By "CAS Interrupt", to stop Burst Read by CAS access. 2. CAS to CAS delay (=1 CLK). Read Interrupt Operation by Issuing the Precharge of Burst Stop Command CASE I ) Issued read Interrupt command during burst read operation period. CLK CMD CLK RD PRE CMD RD STOP (1) Data(CL2) DQ 0 DQ1 DQ 0 Data(CL3) (1) Data(CL4) DQ 0 Data(CL2) DQ1 DQ0 DQ 0 Data(CL3) DQ1 DQ1 DQ1 DQ0 DQ1 Data(CL4) CASE II ) Issued read Interrupt command between read command and data out. CLK CMD CLK RD PRE CMD (2) Data(CL2) Data(CL3) 28 STOP (2) DQ 0 Data(CL2) DQ 0 Data(CL4) Notes: RD Data(CL3) DQ0 Data(CL4) DQ 0 DQ 0 DQ0 1. The data bus goes to high-Z after CAS latency from the Burst Stop (or precharge) command. 2. Valid output data will last up to CL-1 clock cycle from PRE command. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Read Cycle Depending on tRC @RL = 2, CL = 6, BL = 4; 100 MHz CLK tRC(min)=7 CMD ACT tCC=10ns RDa ACT RDb ACT CASE I ) RDb ACT CASE II ) RDb CASE III ) High-Z CASE I ) DQb0 DQb1 DQb2 DQb3 CASE II ) DQa 0 DQa1 DQa 2 DQa 3 CASE III ) DQa0 DQa1 DQa 2 DQa 3 DQb0 DQb1 DQb2 DQb3 DQb0 DQb1 DQb2 DQb3 @RL = 2, CL = 5, BL = 4; 75 MHz CLK tRC(min)=6 CMD ACT tCC=15ns RDa ACT RDb ACT CASE I ) RDb ACT CASE II ) RDb CASE III ) High-Z CASE I ) DQb0 DQb1 DQb2 DQb3 CASE II ) DQa 0 DQa1 DQa 2 DQa 3 CASE III ) DQa0 DQa1 DQa 2 DQa 3 DQb0 DQb1 DQb2 DQb3 DQb0 DQb1 DQb2 DQb3 @RL = 1, CL = 4, BL = 4; 50 MHz CLK tRC(min)=4 CMD ACT RDa tCC=20ns ACT RDb CASE I ) ACT RDb CASE II) ACT RDb CASE I ) CASE III) DQb0 DQb1 DQb2 DQb3 CASE II ) DQa0 DQa1 DQa 2 DQa3 DQb0 DQb1 DQb2 DQb3 CASE III ) DQa0 DQa1 DQa 2 DQa3 (Gapless Operation) DQb0 DQb1 DQb2 DQb3 29 1940B-FLASH-11/01 Read Cycle Depending on tVCVC @RL = 2, CL = 6, BL = 4; 100 MHz CLK tVCVC=5 CMD tCC=10ns RDa ACT RDb CASE I) RDb CASE II) RDb CASE III) CASE I ) DQb0 DQb1 DQb2 DQb3 (Gapless Operation) CASE II ) DQa0 DQa1 DQa 2 DQa3 DQb0 DQb1 DQb2 DQb3 CASE III ) DQa0 DQa1 DQa 2 DQa3 DQb0 DQb1 DQb2 DQb3 @RL = 2, CL = 5, BL = 4; 75 MHz CLK tVCVC=4 CMD RDa ACT tCC=15ns RDb CASE I) RDb CASE II) RDb CASE I ) CASE III) DQb0 DQb1 DQb2 DQb3 (Gapless Operation) CASE II ) DQa0 DQa1 DQa 2 DQa3 DQb0 DQb1 DQb2 DQb3 CASE III ) DQa0 DQa1 DQa 2 DQa3 DQb0 DQb1 DQb2 DQb3 @RL = 1, CL = 4, BL = 4; 50 MHz CLK tVCVC=3 CMD ACT RDa RDb tCC=20ns CASE I) RDb CASE II) RDb CASE I ) CASE III) DQb0 DQb1 DQb2 DQb3 CASE II ) DQa0 DQa1 DQa 2 CASE III ) DQa0 DQa1 DQa 2 DQa 3 DQb0 DQb1 DQb2 DQb3 DQb1 DQb2 DQb3 (Gapless Operation) : Invalid Data 30 AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) AC Characteristics for Boot Block Read Operation Symbol Parameter Condition tACC Address to Output Delay tOE DQM to Output Delay tDF DQM High to Output Float tOH Output Hold from Address Min Max Units CS = DQM = VIL 170 ns CS = VIL 60 ns 40 ns 0 ns AC Waveforms for Boot Block Read Operation ADDRESS ADDRESS VALID CS tOE DQM tDF tACC OUTPUT HIGH-Z tOH OUTPUT VALID 31 1940B-FLASH-11/01 l 3-volt Program and Erase Cycle Characteristics Symbol Parameter Typ Max Units tPGM Word/Double Word Programming Time 50 600 s tEC Sector/Boot Block Erase Cycle Time 2.0/300 seconds/ms tBBL Boot Block Lockout Enable Time 10 ms ICC2 VCC Current during Program and Erase Cycle 150 mA High-speed 12-volt Program and Erase Cycle Characteristics Symbol Parameter Typ Max Units tPGM Word/Double Word Programming Time 15 200 s tEC Sector/Boot Block Erase Cycle Time 1.2/200 seconds/ms ICC3 VCC Current During Program and Erase Cycle 75 mA IPP3 VPP Current During Program and Erase Cycle 75 mA Program Cycle Waveforms PROGRAM CYCLE CLK CS tPGM WE RAS CAS ADDR AA 55 AA DATA 55 PRECHARGE COMMAND AA 2A 55 PRECHARGE COMMAND RA 55 A0 PRECHARGE COMMAND CA DIN PRECHARGE COMMAND Sector Erase Cycle Waveforms SECTOR ERASE CYCLE CLK CS tEC WE RAS CAS ADDR DATA Notes: 32 AA 55 AA 55 PRECHARGE COMMAND 2A 55 AA PRECHARGE COMMAND 55 80 AA PRECHARGE COMMAND 55 AA 55 PRECHARGE COMMAND 2A 55 SA PRECHARGE COMMAND X 30 PRECHARGE COMMAND 1. The Precharge command is optional. A Precharge command (CS, RAS, MR = L) during Program and Sector Erase cycles (WE = L) will be treated as NOP, and the number of clock cycles between the bus cycle and the Precharge command or vice versa should be "Don't Care". 2. For boot block programming, RA = CA = A0 ~ A12 and be held valid throughout program cycle; DQM should be held "H" during the four-bus cycle command operation. 3. For boot block erasing, SA = X; DQM should be held "H" during the six-bus cycle command operation. AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Data Polling Waveforms tPGM/tEC CLK DQM CS WE RAS CAS ADDR DQ7 (RL2, CL5, BL4) Note: RA RA CA READ (DATA POLLING) DATA CA READ DATA During Program cycle, DATA = complement of loaded DQ7. After Program cycle, DATA = same state as loaded DQ7. During Sector Erase cycle, DATA = "0"; after Sector Erase cycle, DATA = "1". Data Polling Waveforms for Boot Block tPGM/tEC CLK DQM CS WE RAS CAS ADDR DQ7 (RL2, CL5, BL4) Note: VALID ADDRESS READ (DATA POLLING) DATA READ DATA During Program cycle, DATA = complement of loaded DQ7. After Program cycle, DATA = same state as loaded DQ7. During Sector Erase cycle, DATA = "0"; after Sector Erase cycle, DATA = "1". 33 1940B-FLASH-11/01 Product ID Cycle Waveforms PRODUCT ID CYCLE CLK DQM CS WE RAS CAS ADDR A7 DATA (CL5, BL4, X16) MC DC DATA (CL5, BL4, X32) C MR READ MRS Note: For x16 Mode, Manufacturer Code, MC = 001F(HEX), Device Code, DC = 32C2 (HEX). For x32 Mode, Code, C = 32C2001F (HEX). Continuity Test Mode Entry Waveforms CLK DQM CS WE RAS CAS ADDR DATA 34 AA 55 AA 55 PRECHARGE COMMAND 2A 55 AA PRECHARGE COMMAND 55 80 AA PRECHARGE COMMAND 55 AA AA PRECHARGE COMMAND 55 70 AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Boot Block Lockout Cycle Waveforms BOOT BLOCK LOCKOUT CYCLE CLK CS tBBL WE RAS CAS AA ADDR 55 AA DATA 55 PRECHARGE COMMAND AA 2A 55 PRECHARGE COMMAND AA 55 80 PRECHARGE COMMAND AA 55 AA PRECHARGE COMMAND 55 40 PRECHARGE COMMAND Boot Block Lockout Verify Cycle Waveforms BOOT BLOCK LOCKOUT VERIFY CYCLE CLK 200 ns CS WE RAS CAS ADDR AA DATA (CL5, BL4) Note: 55 AA 55 PRECHARGE COMMAND 2A 55 AA PRECHARGE COMMAND 55 80 AA PRECHARGE COMMAND 55 AA AA PRECHARGE COMMAND 55 90 PRECHARGE COMMAND READ DQ DQ = XX00 (Hex) implies Boot Block not activated and Lockout not enabled. DQ = XX01 (Hex) implies Boot Block not activated and Lockout enabled. DQ = XX02 (Hex) implies Boot Block activated and Lockout not enabled. DQ = XX03 (Hex) implies Boot Block activated and Lockout enabled. 35 1940B-FLASH-11/01 Boot Block Lockout Verify Exit Cycle Waveforms BOOT BLOCK LOCKOUT VERIFY EXIT CYCLE CLK CS 10 s WE RAS CAS ADDR DATA 36 AA 55 AA 55 PRECHARGE COMMAND 2A 55 AA PRECHARGE COMMAND 55 80 AA PRECHARGE COMMAND 55 AA AA PRECHARGE COMMAND 55 F0 PRECHARGE COMMAND AT49LD3200(B) 1940B-FLASH-11/01 AT49LD3200(B) Ordering Information ICC (mA) Max Freq (MHz) Active Standby 100 150 0.05 150 75 50 Ordering Code Package Operation Range AT49LD3200-10TC 86T Commercial (0 to 70C) 0.05 AT49LD3200-10TI 86T Industrial (-40 to 85C) 150 0.05 AT49LD3200-13TC 86T Commercial (0 to 70C) 150 0.05 AT49LD3200-13TI 86T Industrial (-40 to 85C) 150 0.05 AT49LD3200-20TC 86T Commercial (0 to 70C) 150 0.05 AT49LD3200-20TI 86T Industrial (-40 to 85C) Package Type 86T 86-lead, Thin Small Outline Package (TSOP Type II) 37 1940B-FLASH-11/01 Packaging Information 86T - TSOP Type II 0 ~ 8 c E1 E L PIN 1 Identifier L1 b PIN 1 GAGE PLANE SEATING PLANE D A e A1 A2 COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MO-142, Variation EC. 2. Dimensions D and E1 do not include mold protrusion. Allowable protrusion on E1 is 0.25 mm per side and on D is 0.15 mm per side. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 D 22.12 22.22 22.32 E 11.56 11.76 11.96 E1 10.06 10.16 10.26 L 0.40 0.50 0.60 L1 Note 2 Note 2 0.25 BASIC b 0.17 c 0.12 e NOTE 0.22 0.27 - 0.21 0.50 BASIC 10/18/01 R 38 2325 Orchard Parkway San Jose, CA 95131 TITLE 86T, 86-lead (10.16 mm Body Width) Thin Small Outline Package (TSOP Type ll) DRAWING NO. REV. 86T B AT49LD3200(B) 1940B-FLASH-11/01 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 USA TEL 1(408) 441-0311 FAX 1(408) 487-2600 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Microcontrollers Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. SFlash TM is a trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1940B-FLASH-11/01 /xM