1
Features
•3.0V to 3 .6V Read/Write
•Burst Read Performance
–<
100 MHz (RAS Latency = 2, CAS Latency = 6), 10 ns Cycle Time
tSAC = 7 ns
–<
75 MHz (RAS Latency = 2, CAS Lat ency = 5), 13 ns Cycle Time
tSAC = 8 ns
–<
50 MHz (RAS Latency = 1, CAS Lat ency = 4), 20 ns Cycle Time
tSAC = 9 ns
•MRS Cycle with Address Key Programs
– RAS Late ncy (1 and 2)
– CAS Latency (2 ~ 8)
– Burst Length: 4, 8
– Burst Type: Sequentia l and Interleaved
•Word Selectable Organization
– 16 (Word Mode)/x 32 (Double Word Mode)
•Sector Erase Architecture
– Eight 256K Word or 128K Double Word (4-Mbit) Sectors
•Independent Asynchronous Boot Block
– 8K x 16 Bits with Hardware Lockout
•Fast Program Time
– 3-volt, 100 µs per Word/Double Word Typical
– 12-volt, 30 µs per Word/Double Word Typical
•Fast Sector Erase Time
– 2.5 Seconds at 3 Volts
– 1.6 Seconds at 12 Volts
•Low-p ower Operation
–I
CC Read = 75 mA Typical
•Input and Output Pin Continuity Test Mode Optimizes Off-board Programming
•Package:
– 86-pin TSOP Type II wi th Off-center Parting Line (OCPL) for Improved Reliability
•LVTTL-compatib le Inputs and Outputs
Description
The AT49LD3200 or AT49LD3200B SFlas h™ is a s ynchr onous, high- bandw idth F lash
memory fabricated with Atmel’s high-perfor mance CMOS process technology and is
organized either as 2,097,152 x 16 bits (word mode) or as 1,048,576 x 32 bits (double
word mode), depending on the polarity of the WORD pin (see Pin Function Descrip-
tion Tabl e). Synchronous design allows precise cycl e control. I/O transactions are
possible on ev ery clock cycle. All operations are synchronized to the rising edge of the
system clock. The range of operating frequencies, programmable burst length and
programmable latencie s al low the same device to be useful for a var ie ty of hi gh- ba nd-
width, high-performance memory system applications.
The AT49 LD3200B will auto matically activate the Asynchronou s Boot Block after
power-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be acti-
va ted throug h Mode Regi s ter Set.
The synchr onous DRAM interface al lows designers to maximize system per for ma nce
while eliminating the need to shadow slow asynchronous Flash memory into high-
speed RAM.
The 32-megabit SFlash de vice is designed to sit on the synchronous memory bus and
operate alongs id e SDRAM.
32-megabit
(1M x 32 or
2M x 16)
High-speed
Synchronous
Flash Memory
AT49LD3200
AT49LD3200B
SFlash™
Rev. 1940B–FLASH–11/01
2AT49LD3200(B) 1940B–FLASH–11/01
To maximize system manufacturing throughput the AT49LD3200(B) features high-
speed 12- volt prog ram and eras e options. Add itional ly, stand- alone pro gramming c ycle
time o f in divi dual dev ice s o r modu les is o ptimi zed with Atm el’ s un ique inp ut an d ou tput
pin continuity test mode.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VCC
DQ0
VCCQ
DQ16
DQ1
VSSQ
DQ17
DQ2
VCCQ
DQ18
DQ3
VSSQ
DQ19
MR
VCC
DQM
NC
CAS
RAS
CS
WORD
A12
A11
A10
A0
A1
A2
NC
VCC
NC
DQ4
VSSQ
DQ20
DQ5
VCCQ
DQ21
DQ6
VSSQ
DQ22
DQ7
VCCQ
DQ23
VCC
VSS
DQ31
VSSQ
DQ15
DQ30
VCCQ
DQ14
DQ29
VSSQ
DQ13
DQ28
VCCQ
DQ12
NC
VSS
NC
VPP
WE
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
NC
VSS
NC
DQ27
VCCQ
DQ11
DQ26
VSSQ
DQ10
DQ25
VCCQ
DQ9
DQ24
VSSQ
DQ8
VSS
TSOP (Type II)
Top View
3
AT49LD3200(B)
1940B–FLASH–11/01
Pin Function Description
Pin Name Input Function
CLK System Clock Active on the ri sing edge to sample all inputs.
CS Chip Select Disables or enables device operation by masking or enabling all inputs except
CLK and CKE.
CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be
enabled at least one cycle prior to new command. Disables input buffers for power-
down in standby mode.
A0 - A12 Address Row/column addresses are multiplexed on the same pins.
Row address: RA0 ~ RA12, Column address: CA0 ~ CA6 (x32), CA0 ~ CA7 (x16)
RAS Row Address Strobe Latches row addresses on the rising edge of the CLK with RAS low.
Enables row access.
CAS Column Address Strobe Latches column addresses on the ri sing edge of the CLK with CAS low.
Enables column access.
MR Mode Register Set Enables mode register set with MR low. (Simultaneously CS, RAS and CAS are low).
DQ0 - DQ31 Data Input/Output Data input for program/erase. Data output for read.
VCC/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.
VCCQ/VSSQ Data Output Power/Ground Power and ground for the output buffers.
WORD x32/x16 Mode Selection Double word mode/word mode, depending on polarity of WORD pin (WORD = high,
double word mode; WORD = low, word mode).
Should be set to the desired state during power-up and prior to any device operation.
DQM Data-out Masking Masks output operation when a complete burst is not required.
NC No Connec tion Not connected
WE Write Enable Enables the chip to be written.
VPP Program/Erase Pin Supply Program/Erase power supply.
4AT49LD3200(B) 1940B–FLASH–11/01
Functional Blo ck D iagram
Absolute Maxim u m Ratings*
Temperature under Bias ................................ -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This i s a stres s rat ing onl y and
funct ional ope rati on of the de vic e at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditi ons for e xtended periods may affe ct device
reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground.....................................-0.6V to +4.6V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on VPP
with Respect to Ground...................................-0.6V to +13.5V
Power Dissipation.............................................................. 1 W
Timing Register
Programming Register
Latency & Burst Length
Column Decoder
1M x 32
Cell Array
IO Buffer
Program/
Erase
Logic
WE
VPP
CLK
CLK
ADD
DQ15
CS
CASRASMR
DQ16DQ0
CKE
LRAS
LRAS
LCKE
LCAS
LMR
DQ31
DQM
Address Register
Row Buffer
Row Decoder
Sense AMP
Column Buffer
8K x 16 Boot Block
ADD
5
AT49LD3200(B)
1940B–FLASH–11/01
Notes: 1. VIH (max) = 4.6V for pulse width <10 ns acceptable, pulse width measured at 50% of pulse amplitude.
2. VIL (min) = -1.5V for pulse width <10 ns acceptable, pulse width measured at 50% of pulse amplitude.
Note: 1. If CLK transition time is longer than 1 ns, timing parameters should be compensated. Add [(tr + tf)/2-1] ns for transition time
longer than 1 ns. Transition time is measured between VIL (max) and VIH (min).
DC and AC Operating Range
AT49LD3200(B)-10 AT49LD3200(B)-13 AT49LD3200(B)-20
Operating Temperature
(Case) Commercial 0°C - 70°C0°C - 70°C0°C - 70°C
Industrial -40°C - 85°C-40°C - 85°C-40°C - 85°C
VCC, VCCQ Power Supply 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V
DC Characteristics
Symbol Parameter Condition Min Max Units
ISB1 VCC Standby Current CMOS CKE = 0, tCC = Min 20 m A
ISB2 VCC Standby Current TTL CKE £ VIL (Max), tCC = Min 20 mA
ISB3 VCC Active Standby Current CS ³ VIH (Min), tCC = Min 50 mA
ICC VCC Active Current tCC = Min, All Ou tputs Open 150 mA
IIL Input Leakage Current 0V £ VIN £ VDD + 0.3V
Pins not under test = 0V -10 10 µA
IOL Output Leakage Current (IOOUT
Disabled) (0V £ VOUT £ VDD Max)
All Outputs in High-Z -10 10 µA
VIH Input High Voltage, All Inputs Note(1) 2.0 VDD + 0.3 V
VIL Input Low Voltage, All Inputs Note(2) -0.3 0.8 V
VOH Output High Voltage Level (Logic 1) IOH = -2 mA 2.4 V
VOL Output Low Volt age Level (Logic 0) IOL = 2 mA 0.4 V
AC Operating Test Conditions
TA = 0 to 70°C, VCC = 3.3V ± 0.3V, unless otherwise noted.
Parameter(1) Value
Timing Reference Levels of Input/Output Signals 1.4V
Input Signal Levels VIH/VIL = 2.4V/0.4V
Transition Time (Rise & Fall) of Input Signals tr/tf = 1 ns/1 ns
Output Loa d LVTTL
6AT49LD3200(B) 1940B–FLASH–11/01
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
Notes: 1. This parameter is characterized and is not 100% tested.
2. VPP behaves as an output pin.
Pin Capacitance(1)
f = 1 MHz, T = 25°C
Symbol Typ Max Units Conditions
CIN 46pFV
IN = 0V
COUT(2) 812pFV
OUT = 0V
3.3V
1200Ω
870Ω
Out
p
ut
50
p
F
V
OH
(
DC
)
= 2.4V, I
OH
= -2 mA
V
OL
(
DC
)
= 0.4V, I
OL
= 2 mA
Vtt = 1.4V
50Ω
Out
ut
50
p
F
Z0 = 50Ω
7
AT49LD3200(B)
1940B–FLASH–11/01
Notes: 1. These tRC v alues are f or BL = 8. F or BL = 4, tRC = 7 CLKs for up to 1 00 MH z , tRC = 6 CLKs for up to 75 MHz, tRC = 5 CLKs f or
up to 50 MHz. RAS latency increase means a simultaneous tRC increase in the same number of cycles. (If RAS latency is
3CLKs, t
RC is 12 CLKs for BL = 8.) Refer to page 27 for gapless operation.
2. These tVCVC values are for BL = 8. For BL = 4, tVCVC = 5 CLKs for up to 100 MHz, tVCVC = 4 CLKs for up to 75 MHz,
tVCVC = 3 CLKs for up to 50 MHz. Refer to page 27 for gapless operation.
AC Read Characteristi cs
AC operating conditions unless otherwise noted.
Symbol Parameter
<100 MHz <75 MHz <50 MHz
UnitsMin Max Min Max Min Max
tCC CLK Cycle Time 10 13 20 ns
tSAC CLK to Valid Output Delay 7 8 9 ns
tOH Data Output Hold Time 3 4 4 ns
tCH CLK High Pulse Width 3 4 6.5 ns
tCL CLK Low Pulse Width 3 4 6.5 ns
tRC Row-active to Row-active(1) 11 10 9 clks
tSS Input Setup Time 2 4 4 ns
tSH Input Hold Time 1 2 2 ns
tSLZ CLK to Output in Low-Z 0 0 0 ns
tSHZ CLK to Output in High-Z 7 10 15 ns
tTTransition Time 0.1 10 0.1 10 0.1 10 ns
tVCVC Valid CAS Enable to Valid CAS Enable(2) 9 8 7 clks
8AT49LD3200(B) 1940B–FLASH–11/01
Notes: 1. A0 ~ A6: Progr am keys (@ M RS). After power-up, mo de regi ster set can b e set bef or e i ss uin g othe r i npu t c om mand. After the
Mode Register Set command is completed, no new commands can be issued for 3 CLK Cycles, and CS or MR state must
be defined “H” withi n 3 CLK cycles . Re fer to the Mode Registe r Cont rol Table.
2. In t he cas e C KE is lo w, two st andby mode s are pos si ble . Thos e a re st andby mode in power-down, and acti ve standby mode
in clock suspend (non-power-down).
Power-down: CKE = “L” (after no command is issued for 60 µs)
Clock Suspend: CKE = “L” (at the range of Row Active, Read and Data Out)
3. DQM sampled at rising edge of a CLK makes a high-Z state the data-out state, delayed by 2 CLK cycles.
4. Precharge command on Synch. DRAM can be used for Burst Stop operation during burst read operation only.
5. Mode selection is controlled by the polarity of WORD pin, “H” state is DWM, “L” state is WM. WORD should be set to the
desired state during power-up and prior to any device operation.
6. Data is provided through DQ0 ~ DQ31. Refer to AC programming and erasing waveforms.
7. DQ0 ~ DQ31 will output Manufacturer Code/Device Code.
8. A0 = A2 = A11 = “H”, A1 = A10 = A12 = “L”
9. The user can tie MR and WE together to simplify the interface of the AT49LD3200(B) onto the standard SDRAM bus.
Function Truth Table
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Abbre viation s (RA: Row A ddress , CA: Colum n Addres s, NOP: No Ope ratio n Comman d, DWM: Do uble Word Mode, WM :
Word Mode)
Command CKEn-1 CKEn CS RAS CAS MR(9) DQM Add. WORD VPP WE
Register(1) Mode Register Set H X L L L L X Code X X X
Row Activ e Row Access
& Latch HXLLHHXRAXXX
Read Column A ccess
& Latch HXLHLHXCAXXH
Burst Stop HXLHHLXXXXX
(Precharge on
Synch. DR AM) HXLLHLXXXXX
Power-down
and Clock
Suspend(2)
Two
Standby
Mode
Entry H L X X X X X X X X X
Exit L H X X X X X X X X X
DQM(3) HXXXXXVXXXX
No Operation Comma nd(4) HXHXXXXXXXX
HXLHHHXXXXX
Organization Control(5) HXLHLHXCA
HXH
L
Program/Erase(6) HXLHLXXCAXXL
Fast Program/Erase(6) HXLHLXXCAX12VL
Program/Erase Inhibit H X H X X X X X X X X
Product
Identification(7) Mo de R egi ste r Set H X L L L L X A 7 = H X X X
Read H X L H L H X L X X H
Continuity Test Mode Entry H X L H L X X CA X X L
Exit X X X X X X X Code(8) XXX
9
AT49LD3200(B)
1940B–FLASH–11/01
Notes: 1. Program/Erase is performed through the synchronous bus cycle operation after the boot block is activated through either
power-up or Mode Register Set.
2. It is recommended to hold CKE Low if CLK is running during asynchronous boot block mode except for synchronous com-
mand cycle and MRS operations.
Note: 1. After power-up, when the user wants to change Mode Register Set, the user must exit from power-down mode and start
Mode Register Set before entering normal operation mode. Reserved modes are not to be used; device function in these
mod es is not guarante ed.
Asynchronous Boot Block Function Truth Table
Command CLK(2) CKE(2) CS RAS CAS MR DQM Add. WORD VPP WE
Read X X L X X X L Add X X X
Output Disable XXLXXXHXXXX
Program/Erase(1) HLHLXXAddXXL
Fast Program/Erase(1) HLHLXXAddX12VL
Program/Erase Inhibit H H X X X X X X X X
Mode Register Control Table(1)
Register Programmed with MRS
Address A7 A6 A5 A4 A3 A2 A1 A0
Function Product ID RAS Latency CAS Latency Burst Type Burst Length
Product ID RAS Latency CAS Latency Burst Type Burst Length
A7 “Read” A6 Type A5 A4 A3 Length A2 Type A1 A0 Length
0 Array 0 1 0 0 0 Reserved 0 Sequential 0 0 Reserved
1 ID 1 2 001 2 1 Interleave 0 1 4
010 3 1 0 8
011 4 1 1Boot Block
100 5
101 6
110 7
111 8
10 AT49LD3200(B) 1940B–FLASH–11/01
Addressing Map
Note: 1. Column Address MSB (at x32 organization) (X = Don’t Care)
Note: 1. Column Address MSB (at x16 organization) (X = Don’t Care)
Notes: 1. For X16 operation, when CA0 is set to Low, data belonging to 0 ~ 15th registers are output to DQ0 ~ DQ15 pins, and when
CA0 is set to High, data belonging to 16 ~ 31th registers are output to DQ0 ~ DQ15 pins.
2. Asynchronous Boot Block uses x16 operation and A0 ~ A12 as address inputs.
WORD = “H”: x32 Organization(1)
Function A0A1A2A3A4A5A6A7A8A9A10 A11 A12
Row Address RA0RA1RA2RA3RA4RA5RA6RA7RA8RA9RA10 RA11 RA12
Column Address CA0CA1CA2CA3CA4CA5CA6(1) XXXXXX
WORD = “L”: x16 Organization(1)
Function A0A1A2A3A4A5A6A7A8A9A10 A11 A12
Row Address RA0RA1RA2RA3RA4RA5RA6RA7RA8RA9RA10 RA11 RA12
Column Address CA0CA1CA2CA3CA4CA5CA6CA7(1) XXXXX
Each Address is Arranged as Follows(1)(2)
For X32 operation,
MSB LSB
Address Register AR19 AR18 AR17 ... AR8AR7AR6... AR3AR2AR1AR0
Address RA12 RA11 RA10 ... RA1RA0CA6... CA3CA2CA1CA0
BL = 8
BL = 4
* Initial Address
11
AT49LD3200(B)
1940B–FLASH–11/01
Device Operations
Clock (CLK) A square wave signal (CL K) must be ap plied exte rnally at cycl e time tCC. Al l operations
are synchroni zed to the rising edge of the cloc k. The clock transitions mus t be mono-
toni c be t we en VIL and VIH. During operation with CKE high, all inputs are assumed to be
in valid sta te (low or high) for t he duration of setup and hold time arou nd the positive
edge of the clock for proper functionality and ICC specifications.
Clock Enable (CKE) The clock enable (CKE) gates the clock into the AT49LD3200(B) and is asserted high
during all cycles, except for power-down, standby and clock suspend mode. If CKE goes
low synchr onously with clock (setup and hold time sam e as other i nputs), the interna l
clock is suspe nded from the next cl ock cycle and the stat e of outp ut and burst ad dress
is frozen for as lon g as the CKE remains low. All other inputs are ig nored from the next
clock cycle after CKE goes low. The AT49LD3200(B) remains in the power-down mode,
ignor ing other inputs for as lon g as CKE rema ins low. The power- down exit is synchro-
nous as the intern al clock is s uspended . When CKE go es high at l east “1 CLK + t SS”
before the rising edge of the clock, then t he AT49LD3200 becomes activ e from the
same clock edge accepting all the input commands.
NOP and Device
Deselect When RAS, CAS and MR are high, the AT49LD3200(B) performs no operation (NOP).
NOP does not ini tiate any new oper ation. Device deselec t is also a NOP and is entered
by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR
Burst Sequence (Burst Length = 4)
Initial Address
Sequential InterleaveA1 A0
0001230123
0112301032
1023012301
1130123210
Burst Sequence (Burst Length = 8)
Initial Address
Sequential InterleaveA2 A1 A0
0 0 0 0123456701234567
0 0 1 1234567010325476
0 1 0 2345670123016745
0 1 1 3456701232107654
1 0 0 4567012345670123
1 0 1 5670123454761032
1 1 0 6701234567452301
1 1 1 7012345676543210
12 AT49LD3200(B) 1940B–FLASH–11/01
and all the address inputs are ignored. In addition, entering a Mode Register Set com-
mand in the middle of a normal operation results in an illegal state in the
AT49LD3200(B).
Power-up The following power-up sequence is recommended.
1. Apply power and start clock. Hold the MR, CKE and DQM inputs high; all other
pins are a NOP condition at the inputs before or along with VCC (and VCCQ)
supply.
2. Set WORD to the desired state (prior to any device operation).
3. To change the default Mode Register Set values, perf orm a Mode Register Set
cycle to program the RAS latency, CAS latency, burst length and burst type.
4. At the end of three clock cycles after the mode register set cycle, the device is
ready for operation.
When the above sequence is used for power-up, all outputs will be in high impedance
state. The high impedance of outputs is not guaranteed in any other power-up
sequence.
For AT49LD3200B, Asynchronous Boot Block will be selected after power-up.
Mode Selection Control Mode selection is controlled by the polarity of WORD pin. WORD should be set to the
desired state during power-up and prior to any device operation. The AT49LD3200(B)
can be organized as either double word wide (x32) or word wide (x16). The organization
is selected via the WORD pin. W hen WORD is asserted high (VIH) , the double wo rd-
wide organization is selected. When WORD is asser t e d low (VIL), the word-wid e or gan i-
zation is selected.
Address Decoding The address bits required to decode one of the available cell locations out of the total
depth are multiplexed onto the address select pi ns and latched by ex ternally applying
two commands. The first command, RAS asserted low, latches the row address into the
device. A second command, CAS asserted low, subsequently latches the column
address.
Mode Register Set (MRS ) The mode register stores the data for controlling the various operating modes of
AT49L D3200(B). It prog rams the RAS la tency, CAS late ncy, burst lengt h, burst type,
selects product ID Read or activates the Asynchronous Boot Block. For
AT49LD3200(B), the default value of the mode register is defined as array read with
RAS l atenc y = 2, CAS la tency = 5, bu rst l engt h = 4, s equ entia l b urs t type . Wh en and if
the user wants to change its values, the user must exit from power-down mode and start
Mode Regis ter S et before e ntering n ormal operatio n mode. T he mo de regis ter is r epro-
grammed by asserting low on CS, RAS, CAS and MR (the AT49LD3200(B) should be in
active mode with CKE already high prior to writing the mode register). The state of
addres s pins A0 ~ A7 in the same c ycl e as CS, RAS, CA S and M R going low is the da ta
written in the mode re gist e r. Three cl oc k cycle s are re qui red t o comple te the pr ogr am in
the mode regi ster, t herefo re a fter a M ode Re giste r Se t com mand is com pleted, no n ew
comma nds can be issued fo r 3 clock c ycles and CS or MR must be high within 3 clock
cycles. The mode regis ter is div ided i nto v arious fiel ds, dep ending o n functi onali ty. Th e
burst length fiel d uses A0 ~ A1, bu rst t ype use s A2, C AS late ncy (re ad l atenc y from co l-
umn ad dress) uses A 3 ~ A5, RAS latenc y uses A6 (RA S to C AS delay) , array r ead or
product ID read uses A7. Refer to Mode Reg ister Control T able for s pecific cod es for
various burst lengths, burst types, CAS latencies, RAS latencies, and read modes.
13
AT49LD3200(B)
1940B–FLASH–11/01
Latency The re are laten cies betwee n the issuan ce of a Row Ac tive comma nd and when da ta is
availab le on the I/O buffers. The RAS to CA S del ay is d efined as t he RAS latency . The
CAS to data out delay is the CAS latency. The CAS and RAS latencies are programma-
ble through the mode register. RAS latencies of 1 and 2, and CAS latencies of 2 through
6 are su pporte d. It is und ersto od th at s ome RAS and CAS la tenc y va lues are res erve d
for future use, and are not available in this generation of synchronous Flash. The follow-
ing are the s upported minimum values: RAS latency = 2, and CAS latency = 6 for 100
MHz operation, and RAS latency = 2, and CAS latency = 5 for 66 MHz operation, and
RAS latenc y = 1, and CAS l atency = 4 for 50 MHz opera tion, and RAS latency = 1, and
CAS latency = 3 for 33 MHz operation.
DQM Operation The DQM is used to mask output operations when a complete burst read is not required.
It works similar to OE during a read operation. The read latency is two cycles from DQM,
which means DQM masking occurs two cycles later in the read cycle. DQM operation is
synchron ous wi th th e c lock . The masking oc cu rs fo r a co mpl ete cyc le. (A lso r ef er to th e
DQM timing diagram.)
Burst Read The Burst Read command is used to access a burst of data on consecutive clock cycles
from a n active row st ate. The B urst Read comm and is issued by asser ting low CS and
CAS with MR being high on the rising edge of the clock. The first output appears in CAS
latency number of clock c ycles after the issuance of the Burst Read command. T he
burst length, burst sequence and latency from the Burst Read command are determined
by the mo de regist er, whic h is alre ady progr ammed . Burst re ad can be ini tiated on any
column addr ess of the active row. The output goes into high-imp edance at the end of
the burst, unless a new burst read is initiated to keep the data output gapless. The burst
read can be terminated by issuing another burst read.
Sector Erase Before a word/d ouble word c an be reprogramme d, it must be erased . The erased sta te
of the memory bits is a logical “1”. The AT49LD3200(B) is organized into eight uniform
four megabit sectors (SA0 - SA7) that can be indi vidually erased. The Sector Erase
comman d is a synchrono us six- bus cy cle oper ation (refer to the Command Defini tion
table and Program Cycle and Erase Cycle waveforms). The erase code co nsists of 6-
byte (DQ8 - DQ31 are Don’t Care inputs for the command) load commands to specific
address locations with a specific data pattern. The sector address and 30H data input
are latched in the sixth cycle. The sector erase starts at the following rising edge of CLK
after the sixth cycle. The erase operation is internally controlled; it will automatically time
to completion.
Any commands written to the device during the erase cycle will be ignored. The maxi-
mum time needed to erase one sector is tEC.
Word/Double Word
Programming Once a sector is erased, it is programmed (to a logical “0”) on a word-by-word/double-
word-b y-dou ble-word ba sis. Pr ogramm ing is ac compli shed via the intern al device c om-
mand register and is synchronous four-bus cycle operation (refer to the Command
Definition table and Program Cycle and Erase Cycle wav eforms). The programming
operation starts at the following rising edge of CLK after the fourth cycle. The device will
automatically generate the required internal program pulses.
Any comma nds written to the device dur ing the embed ded programming cycle will be
ignored . P lease note that a data “0 ” cannot be program med back to a “1”; only er ase
operations can convert “0”s to “1”s. Programming is completed after the specified tPGM
cycle time. The DATA pol ling feat ure may also be us ed to indic ate the end of a program
cycle.
14 AT49LD3200(B) 1940B–FLASH–11/01
Product Identification The product identification mode identifies the devi ce and manufacturer as Atmel. This
mode can be u sed by an o n- boa rd co ntr ol le r or e xt ernal pr ogrammer to id enti fy the co r-
rect progra mmi ng alg orith m for the Atm el produ ct.
DATA Polling The AT49LD3200(B) features DATA polling to indicate the end of a program or sector
erase cycle. DATA polling may begin at any time during the program or sector erase
cycle.
During a program cycle, an attempted read of the last word/double word loaded will
resu lt in the com pleme nt of the loaded data in DQ 7. Once th e progr am cycl e has com-
pleted, true valid data can be read on all outputs and the next cycle may begin.
During a sector erase operation, an attempt to read the device will give a “0” on DQ7.
Once the sector erase cycle has completed, logical “1” data can be read on all outputs
from the device.
Hardware Data
Protection Hardware features protect against inadvertent programming or erasure to the
AT49LD3 200(B ) in the follo win g way: VCC se nse: if VCC i s bel ow 2.3V (typ ical), the pr o-
gram or erase function is inhibited; but if VCC dips b elow 2. 3V duri ng pro gram or erase
cycle, the respective function will be interrupted and the data at the location being pro-
grammed may be corrup ted.
Continuity Test Mode The AT49LD3200(B) has built-in circuitries to make input and ou tput pin continuity
check s imple and e asy. This m ode can be a ctivated via the internal device comma nd
regist er and i s a s ynchronous fi ve - bus cy c le op erati on ( refer to th e Com man d Defi ni tio n
Table and Con tinuity Test Mo de Entry Wavefo rms). After the bus cycle opera tion, keep
DQM high (VIH) and allow 5 µsec for circuit setup time or until data is no longer asserted
at DQ0 - DQ7 , whi c hev er ta ke s lon ger . This will k eep DQ0 - DQ7 from c onte nti on si nce
data is asserted at DQ0 - DQ7 during the mode entry sequence. Then DQM can be
asser ted lo w (V IL) to enable DQ0 - DQ7 for test. Once in this asynchronous mode, input
pins are virtually tied to output pins internally forming input - output pin pairs. The output
pin of the pair will follow the l ogic state of the in put pin of t he pair (refer to the Inp ut -
Output P i n Pai rs tabl e) . To e xit the mod e, A 0, A2 an d AII are assert ed high (V IH) a nd A 1,
A10 and A12 are as se rt ed l ow ( VIL), allow 5 µsec for circuit recovery time before returning
the device for normal operation.
15
AT49LD3200(B)
1940B–FLASH–11/01
Asynchronous Boot
Block The AT49LD3200B will automatically activate the Asynchronous Boot Block after
power -up and the AT49L D3200 ca n activa te the As ynchro nous Bo ot Block through th e
Mode Register Set. The size of the boot block is 8K x 16 bits with addresses A0 ~ A12
and outp uts DQ0 ~ D Q15. The contents of the bo ot bloc k are acce ssed async hronous ly,
meaning the data at outputs will change according to the address inputs after tACC, with-
out any external clocking signals.
Programs and erases are performed using the synchronous bus cycle operation (refer
to Command Definitions table and Program Cycle and Erase Cycle waveforms) after the
boot block is activated either through power-up or Mode Register Set. Programming of
the boot block is set up for x16 mode.
This Asynchronous Boo t Block has a lockout feature that prevents programming or
erasin g of dat a in th is boo t block once t he featu re ha s been enable d. Th is featur e does
not have to be act ivate d; the bo ot block’ s us age as a pr otect ed region is op tional to the
user. Once this feature is enabled, the data in the boot block can no longer be erased or
programmed when input levels of 3.6V or less are used. To activate the lockout feature,
Input - Output Pin Pairs
Input Output
MR DQ0, DQ16
RAS DQ1, DQ17
CAS DQ2
DQM DQ18
CS DQ3
WORD DQ19
A12 DQ4
A11 DQ20
A10 DQ5
A0 DQ21
A1 DQ6, DQ22
A2 DQ7, DQ23
A3 DQ8, DQ24
A4 DQ9, DQ25
A5 DQ10
A6 DQ26
A7 DQ11
A8 DQ27
A9 DQ12
CKE DQ28
CLK DQ13, DQ29
WE DQ14, DQ30
VPP DQ15, DQ31
16 AT49LD3200(B) 1940B–FLASH–11/01
Boot Block Lockout command, which is a synchronous five-bus cycle operation, must be
performed (refer to Command Definitions table and Program Cycle Waveforms).
A software method is available to determine if programming or erasing of the boot block
is lock ed out. Is sue B oot B lo ck Loc k out V erify c omm and and ob se rve DQ 0 ~ DQ7. If the
data show 00H/02H, the boot block can be programmed or erased; if the data show
01H/03H, the lockout feature has been enabled and the boot block cannot be pro-
grammed or erased . The Boot Block L ockout Verify Exit com mand should be used to
return to standard operation (refer to Command Definition table and Boot Block Lockout
Verify Waveforms).
The user can override the boot block lockout by taking the MR pin to 12 vo lts a fter th e
boot block is activated. When the MR pin is brou ght bac k to TTL level s, the b oot bl ock
lockout feature is again active.
17
AT49LD3200(B)
1940B–FLASH–11/01
Notes: 1. The DATA FORMAT in each bus cycle is as follows: DQ31 - DQ8 (Don’t Care); DQ7 - DQ0 (Hex).
2. SA = Sector Addresses: Any word/double word address within a sector can be used to designate the sector address.
See Sector Address Mapping table below.
3. Allow minimum 200 ns after Boot Block Lockout Verify command and before Read.
4. Allow minimum 10 µs after Boot Block Lockout Verify Exit command for the device to return to standard operation.
Command Definition in Hex(1)
Command
Sequence Bus
Cycles
1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cy cle 5th Bus Cycle 6t h Bus Cycle
RA CA Data RA CA Data RA CA Data RA CA Data RA CA Data RA CA Data
Word/
Double
Word
Program
4 AA55AA552A55AA55A0RACAD
IN
Sector
Erase 6 AA55AA552A55AA5580AA55AA552A55SA
(2) X30
Continuity
Tes t Mode
Entry 5 AA55AA552A55AA5580AA55AAAA5570
Boot Block
Lockout 5 AA55AA552A55AA5580AA55AAAA5540
Boot Block
Lockout
Verify 5 AA55AA552A55AA5580AA55AAAA5590
Boot Block
Lockout
Verify Exit 5 AA55AA552A55AA5580AA55AAAA55F0
Sector Ad dress Mapping
Sector Size (Word/Double Word)
x16
Address Range x32
Address Range
CA7-0 RA12-0 CA6-0 RA12-0
SA0 256K/128K X 00XX
03XX X00XX
03XX
SA1 256K/128K X 04XX
07XX X04XX
07XX
SA2 256K/128K X 08XX
0BXX X08XX
0BXX
SA3 256K/128K X 0CXX
0FXX X0CXX
0FXX
SA4 256K/128K X 10XX
13XX X10XX
13XX
SA5 256K/128K X 14XX
17XX X14XX
17XX
SA6 256K/128K X 18XX
1BXX X18XX
1BXX
SA7 256K/128K X 1CXX
1FXX X1CXX
1FXX
18 AT49LD3200(B) 1940B–FLASH–11/01
Basic Feature and Function Descriptions
MRS
Clock Suspend
Clock Suspend Exit and Power-down Exit
Note: After Mode Register Set command is completed, no new commands can be issued for 3 clock cycles, and MR or CS should be
fixed “H” within a minimum of 3 clock cycles.
Mode Re
g
ister Set
CLK
CMD MRS ACT
(
1
)
3CLK
D0
Internal
CLK
Clock Sus
p
ended Durin
g
Burst Read
(
BL=4
)
Masked by CKE
DQ0DQ1DQ2DQ3
Sus
p
ended Dout
CLK
CMD RD
CKE
Data
: This command cannot be activated.
Internal
CLK
CKE
Internal
CLK
1
)
Clock Sus
p
end Exit
CLK
CKE
CMD RD
2
)
Power Down
CLK
CMD NOP ACT
tSStSS
19
AT49LD3200(B)
1940B–FLASH–11/01
DQM Operation
Note: DQM makes data out high-Z after 2 CLKs, which should be masked by CKE “L”.
DQ0DQ1DQ3
DQ0DQ2DQ3
DQ1DQ2DQ3
Masked by DQM
DQ0D1DQ1DQ3
DQ0DQ7
DQ2
DQ6DQ7
DQ1
DQ7
DQ6
DQ5
CLK
CMD
DQM
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
RD
CLK
CMD
DQM
CKE
RD
1
)
Read Mask
(
BL=4
)
2
)
DQM with Clock Sus
p
ended
(
BL=8
)
High-Z
High-Z
High-Z
DQ5
DQ4
DQ3
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQM to Data-out Mask = 2CLKs
High-Z
High-Z
High-Z
(
1
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
20 AT49LD3200(B) 1940B–FLASH–11/01
Read Cycle I: Normal @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
Note: When the burst length is 4 at 66 MHz, tRC is equ al to 6 clock cycles .
0 1 2 3 4 5 6 7 8 9 10111213141516171819
tSS
tSH
CKE
CS
RAS
CAS
ADDR
Data
tCH
tCC tCL
tRC
HIGH
tSH
tSS
tSHZtSAC
tOH
DQa0 DQa1 DQa2 DQa3
CAbRAb
RAS
Latenc
y
MR
(
1
)
tRC=6 clocks at BL=4
Row Active Read Row Active Read : Don't Care
tSS
tSH
DQb0 DQb1 DQb2 DQb3
CAaRAa
CLK
21
AT49LD3200(B)
1940B–FLASH–11/01
Read Cycle II: Consecutive Column Access @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
Note: When column access is initiated beyond tVCVC, at BL = 4, CAa access read is completed, CAb access read begins.
0 1 2 3 4 5 6 7 8 9 10111213141516171819
t
SS
t
SH
t
SS
t
SH
CKE
CS
RAS
CAS
ADDR
Data
t
CH
t
CC
t
CL
HIGH
t
SH
t
SS
CAaRAa
t
SHZ
t
SAC
t
OH
DQb1 DQb2 DQb3
CAb
DQb0
RAS
Latenc
y
t
VCVC
=4 clocks at BL=4
Burst Len
g
th=4 DQa1 DQa2 DQa3DQa0
MR
Row Active Read Read : Don't Care
CLK
22 AT49LD3200(B) 1940B–FLASH–11/01
Read Cycle III: Clock Suspend @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
Notes: 1. From next clock after CKE goes low, clock suspension begins.
2. For clock suspension, data output state is held and maintained.
012345678910111213141516171819
t
SS
t
SH
CKE
CS
RAS
CAS
ADDR
Data
t
CH
t
CC
t
CL
t
SH
t
SS
CAaRAa
RAS
Latenc
y
t
VCVC
= 4 clocks at BL=4
(
2
)
Burst Len
g
th=4 DQa2 DQa3
DQa0
(
1
)
MR
Row Active Read Clock Sus
p
end Resume : Don't Care
DQa1
CLK
Internal
CLK
23
AT49LD3200(B)
1940B–FLASH–11/01
Read Interrupted by Precharge Command and Burst Read Stop Cycle @Burst Length = 8
Notes: 1. The Burst Stop command is valid at ever y page burst length. The data bus goes to high-Z after the CAS latency from the
Burst Stop command is issued.
2. The interval between Read command (column address presented) and Burst Stop command is 1 cycle (min).
0 1 2 3 4 5 6 7 8 9 10111213141516171819
HIGH
CL=3
ADDR
CAS
RAS
CS
CKE
CLK
MR
DQM
DQa0 DQa1 DQa2 DQa4 DQb0 DQb1 DQb2 DQb3 DQb4 DQb5
RAa CAa CAb
Row Active Prechar
g
eBurst Sto
p
Read Read
: Don't Care
(1)
CL=2
Data
DQa0 DQa1 DQa2 DQa4 DQb0 DQb1 DQb2 DQb3 DQb4 DQb5DQa3
DQa3
(1)(2)
(1)
(2) (2)
24 AT49LD3200(B) 1940B–FLASH–11/01
Power -down and Clock Suspend Cycle: @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
Notes: 1. From next clock after CKE goes low, clock suspend and power-down begins.
2. After power-down exit, NOP should be issued and new command can be issued after 1 clock.
3. Clock suspend is in active standby mode.
012345678910111213141516171819
CKE
CS
RAS
CAS
ADDR
Data
Read
CAaRAa
DQa1 DQa2DQa0
MR
DQa3
Row Active
(
Hi
g
h
)
CLK
(internal)
NOP
Power-down Clock Sus
p
end
Entr
y
Entr
y
Power-down
Exit Clock Sus
p
end
Exit
: Don't Care
t
SS
t
SH
(
2
)
(
1
)
t
SS
(
1
)
(
3
)
Clock Sus
p
endPower Down
Data Hi
g
h-Z State
25
AT49LD3200(B)
1940B–FLASH–11/01
Mode Register Set: @RAS Latency = 2, CAS Late ncy = 5, Burst Length = 4
Notes: 1. After the Mode Register Set is completed, no new commands can be issued for 3 CLK cycles.
2. Afte r po we r-up , neces sarily M ode Reg ister Se t shou ld be c ompl eted a t least one ti me and CS or MR must be fix ed “H ” withi n
3 clock cycles, and when user wants to change Mode Register Set, user must exit from power-down mode and start Mode
Register Set before chip enters normal operation mode.
012345678910111213141516171819
t
SS
t
SH
CKE
CS
RAS
CAS
ADDR
Data
MR
t
CH
t
CC
t
CL
HIGH
Code RAa
Data High-Z State
MRS Row Active
: Don' t Care
CAa
DQa0 DQa1 DQa2 DQa3
CLK
26 AT49LD3200(B) 1940B–FLASH–11/01
Note: 1. Afte r the po w er-up, when user wa nts to chan ge MR Set, use r must e xit from pow er -down mode a nd start MR Set before chip
enters normal operation mode.
Detailed Functional Truth Table
Current
State
Input Signal
Next State OperationCKE CS RAS CAS MR Add.
After
Power-up(1)
LXXXXXPower-down
H L L H H RA Row Active; latch RA
HLLLLCodeMode Register Set
Row Activ e
HLLHHRA
If consecutive row access is issued within tRC (min.)
without CAS enabling, only the final RA is valid.
H L H L H CA Begin READ; latch CA
HLLLLCodeIllegal
(1)
L XXXXXClock Suspend
READ
HLLHHRA
Row Access in Read State, within the tRC, previous
read is ignored and new row is activated. Beyond the
tRC, previous read is completed and new read
begins.
HLHLHCA
Consecutive Column Access, within the tVCVC, only
the final CA is valid and the previous burst read is
ignored. Be yond the tVCVC, the previous read is
completed and new read begins.
H L L H L X NOP (after Burst Read)/Read Interrupt
H L H H L X NOP (after Burst Read)/Read Interrupt
HLLLLCodeIllegal
(1)
LXXXXXClock Suspend/Power-down
Any StateLLLLHXLow Power Consumption Mode
Any State H L H H H X NOP
Any State HLLLHXIllegal
H L H L L CA Illegal
27
AT49LD3200(B)
1940B–FLASH–11/01
Technical Notes
Frequency vs. AC Parameter Relationship Table(1)
Notes : 1. Abo ve tab le s are not s pec if ica t io ns values, but rath er th e ac tua l n um ber of cl ock cycles . There are no gap les s operations for
CAS latency 7 and 8.
2. Minimum clocks for gapless operation.
3. tRC (max) = tVCVC (max) = 50 µs. If tRC (max) or tVCVC (max) has been reached, a new “ACTIVE” command is necessary for
new access.
<100 MHz
Burst Length RAS Latency CAS Latency tRC (min) tVCVC (min)
42675
(2)
786
826119
(2)
71210
<75 MHz
Burst Length RAS Latency CAS Latency tRC (min) tVCVC (min)
42564
(2)
675
825108
(2)
6119
<50 MHz
Burst Length RAS Latency CAS Latency tRC (min) tVCVC (min)
41
44
(2) 3/4(2)
554
(2)
665
81
48
(2) 7/8(2)
598
(2)
6109
28 AT49LD3200(B) 1940B–FLASH–11/01
CAS Interrupt
Notes: 1. By “Interrupt”, it is meant to stop Burst Read by external command before the end of burst. By “CAS Interrupt”, to stop Burst
Read by CAS access.
2. CAS to CAS delay (=1 CLK).
Read Interrupt Operation by Issuing the Precharge of Burst Stop Command
Notes: 1. The data bus goes to high-Z after CAS latency from the Burst Stop (or precharge) command.
2. Valid output data will last up to CL-1 clock cycle from PRE command.
DQB1DQB2
RD
DQB3
RD
A B
DQB0
DQB1DQB2DQB3
DQB0
DQB1DQB2DQB3DQB0
(
2
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
Read interru
p
ted b
y
Read
(
BL=4
)
(1)
CLK
CMD
ADD
RD PRE
DQ0
DQ0DQ1
DQ0DQ1
RD
STOP
DQ0DQ1
DQ0DQ1
DQ0DQ1
DQ1
CLK
CMD
CLK
CMD
CASE I
)
Issued read Interru
p
t command durin
g
burst read o
p
eration
p
eriod.
RD PRE
DQ0
DQ0
DQ0
(
2
)
RD
STOP
DQ0
DQ0
DQ0
CLK
CMD
CLK
CMD
CASE II
)
Issued read Interru
p
t command between read command and data out.
(
2
)
(
1
)
(
1
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
29
AT49LD3200(B)
1940B–FLASH–11/01
Read Cycle Depending on tRC
@RL = 2, CL = 6, BL = 4; 100 MHz
@RL = 2, CL = 5, BL = 4; 75 MHz
@RL = 1, CL = 4, BL = 4; 50 MHz
RDa
tRC(min)=7
ACT
tCC=10ns
CLK
CMD
CASE I )
CASE II )
CASE III )
RDbACT
RDb
DQb
1
DQb
2
DQb
0
DQb
1
DQb
2
DQb
3
DQb
0
DQa
1
DQa
2
DQa
0
DQa
3
DQa
1
DQa
2
DQa
0
DQa
3
High-Z
CASE I )
RDbACT
CASE II )
CASE III )
ACT
DQb
1
DQb
2
DQb
3
DQb
0
DQb
3
RDa
tRC(min)=6
ACT
tCC=15ns
RDbACT
RDb
DQb1DQb2DQb3DQb0
DQb1DQb2DQb3DQb0DQa1DQa2DQa0DQa3
DQa1DQa2DQa0DQa3
High-Z
CASE I )
RDbACT
CASE II )
CASE III )
ACT
DQb1DQb2DQb3DQb0
CLK
CMD
CASE I )
CASE II )
CASE III )
tRC(min)=4
ACT
tCC=20ns
ACT
DQb
1
DQb
2
DQb
3
DQb
0
DQb
1
DQb
2
DQb
3
DQb
0
DQa
1
DQa
2
DQa
0
DQa
3
DQa
1
DQa
2
DQa
0
DQa
3
CASE I )
ACT
CASE II)
CASE III)
ACT
DQb
1
DQb
2
DQb
3
DQb
0
CLK
CMD
CASE I )
CASE II )
CASE III )
RDa RDb
RDb
RDb
(Gapless Operation)
30 AT49LD3200(B) 1940B–FLASH–11/01
Read Cycle Depending on tVCVC
@RL = 2, CL = 6, BL = 4; 100 MHz
@RL = 2, CL = 5, BL = 4; 75 MHz
@RL = 1, CL = 4, BL = 4; 50 MHz
tVCVC=5
ACT
CLK
CMD
CASE I )
CASE II )
CASE III )
RDa
DQb
1
DQb
2
DQb
3
DQb
0
CASE I)
CASE II)
CASE III)
DQb
1
DQb
2
DQb
3
DQb
0
DQb
1
DQb
2
DQb
3
DQb
0
DQa
0
DQa
1
DQa
0
RDb
RDb
RDb
DQa
2
DQa
3
DQa
1
(Gapless Operation)
DQa
3
DQa
2
tCC=10ns
tVCVC=4
ACT
DQb
1
DQb
2
DQb
3
DQb
0
CASE I)
CASE II)
CASE III)
CLK
CMD
CASE I )
CASE II )
CASE III )
DQb
1
DQb
2
DQb
3
DQb
0
DQb
1
DQb
2
DQb
3
DQb
0
DQa
0
DQa
1
DQa
0
RDa RDb
RDb
RDb
DQa
2
DQa
3
DQa
1
(Gapless Operation)
DQa
3
DQa
2
tCC=15ns
tVCVC=3
ACT
DQb
1
DQb
2
DQb
3
DQb
0
CASE I)
CASE II)
CASE III)
CLK
CMD
CASE I )
CASE II )
CASE III )
DQb
1
DQb
2
DQb
3
DQb
1
DQb
2
DQb
3
DQb
0
DQa
0
DQa
1
DQa
0
RDa RDb
RDb
RDb
DQa
3
DQa
2
(Gapless Operation)
: Invalid Data
DQa
2
DQa
1
tCC=20ns
31
AT49LD3200(B)
1940B–FLASH–11/01
AC Waveforms for Boot Block Read Operation
AC Characteristics for Boot Block Read Operation
Symbol Parameter Condition Min Max Units
tACC Address to Output Delay CS = DQM
= VIL 170 ns
tOE DQM to Output Delay CS = VIL 60 ns
tDF DQM High to Output Float 40 ns
tOH Output Hold from Address 0 ns
ADDRESS VALID
tACC
tDF
tOH
HIGH-Z
OUTPUT VALID
tOE
ADDRESS
DQM
OUTPUT
CS
32 AT49LD3200(B) 1940B–FLASH–11/01
l
Program Cycle Waveforms
Sector Erase Cycle Waveforms
Notes: 1. The Precharge command is optional. A Precharge command (CS, RAS, MR = L) during Program and Sector Erase cycles
(WE = L) will be trea ted as N OP, and the n u mb er o f cl ock cycles b etween the bus cycle an d th e Pre ch arge c omma nd or v ic e
versa should be “Don’t Care”.
2. For boot block programming, RA = CA = A0 ~ A12 and be held valid throughout program cycle; DQM should be held “H” dur-
ing the four-bus cycle command operation.
3. For boot block erasing, SA = X; DQM should be held “H” during the six-bus cycle command operation.
3-volt Program and Erase Cycle Characteristics
Symbol Parameter Typ Max Units
tPGM Word/Double Word Programming Time 50 600 µs
tEC Sector/Boot Block Erase Cycle Time 2.0/300 seconds/ms
tBBL Boot Block Lockout Enable Time 10 ms
ICC2 VCC Current during Program and Erase Cycle 150 mA
High-speed 12-volt Program and Erase Cyc le Characteristics
Symbol Parameter Typ Max Units
tPGM Word/Double Wor d Progr amming Time 15 200 µs
tEC Sector/Boot Block Erase Cycle Time 1.2/200 seconds/ms
ICC3 VCC Current During Program and Erase Cycle 75 mA
IPP3 VPP Current D uring Program and Erase Cycle 75 mA
CS
PROGRAM CYCLE
CLK
WE
RAS
CAS
AA 55 55 2A AA 55 RA CA
DATA AA 55 A0 DIN
ADDR
PRECHARGE COMMAND
tPGM
PRECHARGE COMMAND PRECHARGE COMMAND PRECHARGE COMMAND
CS
SECTOR ERASE CYCLE
CLK
WE
RAS
CAS
AA 55 55 2A AA 55
DATA AA 55 80 AA
ADDR
tEC
PRECHARGE
COMMAND
AA 55 55 2A SA X
55 30
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
33
AT49LD3200(B)
1940B–FLASH–11/01
Data Polling Waveforms
Note: During Program cycle, DATA = complement of loaded DQ7.
After Program cycle, DATA = same state as loaded DQ7.
During Sector Erase cycle, DATA = “0”; after Sector Erase cycle, DATA = “1”.
Data Polling Waveforms for Boot Block
Note: During Program cycle, DATA = complement of loaded DQ7.
After Program cycle, DATA = same state as loaded DQ7.
During Sector Erase cycle, DATA = “0”; after Sector Erase cycle, DATA = “1”.
DQM
CS
tPGM/tEC
CLK
WE
RAS
CAS
DQ7
(RL2, CL5, BL4) DATA
ADDR
READ
READ
(DATA POLLING)
RA CA
DATA
RA CA
DQM
CS
t
PGM
/t
EC
CLK
WE
RAS
CAS
DQ7
(RL2, CL5, BL4) DATA
ADDR
READ
READ
(DATA POLLING) DATA
VALID ADDRESS
34 AT49LD3200(B) 1940B–FLASH–11/01
Product ID Cycle Waveforms
Note: For x16 Mode, Manufacturer Code, MC = 001F(HEX), Device Code, DC = 32C2 (HEX).
For x32 Mode, Code, C = 32C2001F (HEX).
Continuity Test Mode Entr y Waveforms
DQM
CS
PRODUCT ID CYCLE
CLK
WE
RAS
CAS
DATA
(CL5, BL4, X16)
ADDR
READ
A7
MR MRS
DC
MC
DATA
(CL5, BL4, X32) C
CLK
CS
WE
RAS
CAS
ADDR
AA 55 55 2A AA 55 AA 55 55
AA
DATA
AA 55 80 AA 70
PRECHARGE
COMMAND PRECHARGE
COMMAND PRECHARGE
COMMAND PRECHARGE
COMMAND
DQM
35
AT49LD3200(B)
1940B–FLASH–11/01
Boot Block Lo ckou t Cycle Waveforms
Boot Block Lockou t Verify Cycle Waveforms
Note: DQ = XX00 (Hex) implies Boot Block not activated and Lockout not enabled.
DQ = XX01 (Hex) implies Boot Block not activated and Lockout enabled.
DQ = XX02 (Hex) implies Boot Block activated and Lockout not enabled.
DQ = XX03 (Hex) implies Boot Block activated and Lockout enabled.
CS
BOOT BLOCK LOCKOUT CYCLE
CLK
WE
RAS
CAS
AA 55 55 2A AA 55
DATA AA 55 80 AA
ADDR
tBBL
AA 55 AA 55
40
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
CS
BOOT BLOCK LOCKOUT VERIFY CYCLE
CLK
WE
RAS
CAS
AA 55 55 2A AA 55
DATA
(CL5, BL4) AA 55 80 AA
ADDR
200 ns
AA 55 55AA
90
PRECHARGE
COMMAND READ
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND DQ
36 AT49LD3200(B) 1940B–FLASH–11/01
Boot Block Lockout Verify Ex it Cycle Waveform s
CS
BOOT BLOCK LOCKOUT VERIFY EXIT CYCLE
CLK
WE
RAS
CAS
AA 55 55 2A AA 55
DATA AA 55 80 AA
ADDR AA 55 AA 55
F0
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
10 µs
37
AT49LD3200(B)
1940B–FLASH–11/01
Ordering Information
Max Freq
(MHz)
ICC (mA)
Ord ering Code Pac kage Operation RangeActive Standby
100 150 0.05 AT49LD3200-10TC 86T Commercial
(0° to 70°C)
150 0.05 AT49LD3200-10TI 86T Industrial
(-40° to 85°C)
75 150 0.05 AT49LD3200-13TC 86T Commercial
(0° to 70°C)
150 0.05 AT49LD3200-13TI 86T Industrial
(-40° to 85°C)
50 150 0.05 AT49LD3200-20TC 86T Commercial
(0° to 70°C)
150 0.05 AT49LD3200-20TI 86T Industrial
(-40° to 85°C)
Package Type
86T 86-lead, Thin Small Outline Package (TSOP Type II)
38 AT49LD3200(B) 1940B–FLASH–11/01
Packaging Information
86T – TSOP Type II
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
86T, 86-lead (10.16 mm Body Width) Thin Small Outline Package
(TSOP Type ll) B
86T
10/18/01
0˚ ~ 8˚
PIN 1 Identifier
PIN 1
c
GAGE PLANE
L1
SEATING PLANE
L
A
A1 A2
E1 E
D
b
e
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation EC.
2. Dimensions D and E1 do not include mold protrusion. Allowable
protrusion on E1 is 0.25 mm per side and on D is 0.15 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 22.12 22.22 22.32 Note 2
E 11.56 11.76 11.96
E1 10.06 10.16 10.26 Note 2
L 0.40 0.50 0.60
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.12 – 0.21
e 0.50 BASIC
Printed on recycled paper.
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Other terms and product names may be the trademarks of others.
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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1940B–FLASH–11/01 /xM