©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
HUF76407DK8
3.5A, 60V, 0.105 Ohm, Dual N-Channel,
Logic Level UltraFET® Po wer MOSFET
Packaging
Symbol
Features
• Ultra Low On-Resistance
-r
DS(ON) = 0.090Ω, VGS = 10V
-r
DS(ON) = 0.105Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- SPICE and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pu lse Width Curve
• UIS Rating Curve
• Transient Thermal Impedance Cu rve vs Board Mounting
Area
• Switching Time vs RGS Curves
Ordering Information
Absolute Maximum Ratings TA = 25oC, Unless Other wise Specified
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Autom otive HUFA series.
All Fairchild semiconductor products are manuf actured, assembled and tested under ISO9000 and QS9000 quality systems c ertification.
JEDEC MS-012AA
BRANDING DASH
1234
5
DRAIN 1 (8)
SOURCE1 (1)
DRAIN 1 (7)
DRAIN 2 (6)
DRAIN 2 (5)
SOURCE2 (3)
GATE2 (4)
GATE1 (2)
PART NUMBER PACKAGE BRAND
HUF76407DK8 MS-012AA 76407DK8
NOT E: When ord ering, use the entire part number. Add the s uff ix T
to obtain the variant in tape and reel, e.g., HUF76407DK8T.
HUF76407DK8 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 60 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 60 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±16 V
Drain Current
Continuous (TA = 25oC, VGS = 5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 100oC, VGS = 4.5V) (Figure 2) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
3.5
3.8
1.0
1.0
Figure 4
A
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 17, 18
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5
20 W
mW/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.76 in2 (490.3 mm2) copper pad at 1 second.
3. 228oC/W measured using FR-4 board with 0.006 in 2 (3.87 mm2) copper pad at 1000 seconds.
CAUTION: Stresses ab ove th ose listed in “ Absolute M aximum Ratin gs” may cause perm anent damage to the device. This is a stress on ly rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet December 2001
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source B reakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 12) 60 - - V
ID = 250µA, V GS = 0V , TA = -40oC (Figure 12) 55 - - V
Zero Gate Vo ltage Drain C urrent IDSS VDS = 55V, VGS = 0V - - 1 µA
VDS = 50V, VGS = 0V, TA = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±16V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V
Drain to Source On Resist ance rDS(ON) ID = 3.8A, VGS = 10V (Figures 9, 10) - 0.075 0.090 Ω
ID = 1.0A, VGS = 5V (Figure 9) - 0.088 0.105 Ω
ID = 1.0A, VGS = 4.5V (Figure 9) - 0.092 0.110 Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to
Ambient RθJA Pad Area = 0.76 in2 (490.3 mm2) (Note 2) - - 50 oC/W
Pad Area = 0.027 in2 (17.4 mm2) (Figure 23) - - 191 oC/W
Pad Area = 0.006 in2 (3.87 mm2) (Figure 23) - - 228 oC/W
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time tON VDD = 30V, ID = 1.0A
VGS = 4.5V, RGS = 27Ω
(Figures 15, 21, 22)
- - 57 ns
Turn-On De lay Time td(ON) -8-ns
Rise Time tr-30-ns
Turn-Off De lay Time td(OFF) -25-ns
Fall Time tf-25-ns
Turn-Off T ime tOFF - - 75 ns
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 30V, ID = 3.8A
VGS = 10V,
RGS = 30Ω
(Figures 16, 21, 22)
- - 24 ns
Turn-On De lay Time td(ON) -5-ns
Rise Time tr-11-ns
Turn-Off De lay Time td(OFF) -46-ns
Fall Time tf-31-ns
Turn-Off T ime tOFF - - 116 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 30V,
ID = 1.0A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
- 9.4 11.2 nC
Gate Charge at 5V Qg(5) VGS = 0V to 5V - 5.3 6.4 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 1V - 0.42 0.5 nC
Gate to Source Gate C harge Qgs -1.05- nC
Gate to Drain “Miller” Charge Qgd -2.4-nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
- 330 - pF
Output Capacitance COSS - 100 - pF
Reverse Transfer Capacitance CRSS -18-pF
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to D rain Diode Volt age VSD ISD = 3.8A - - 1.25 V
ISD = 1.0A - - 1.00 V
Reverse Recovery Time trr ISD = 1.0A, dISD/dt = 100A/µs--48ns
Reverse Recovered Charge QRR ISD = 1.0A, dISD/dt = 100A/µs--89nC
HUF76407DK8
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
Typical Performance Curves
FIGURE 1. NORMALIZED PO WER DISSIPA TION vs AMBIENT
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AM BIENT TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00255075100 15
0
0.2
0.4
0.6
0.8
1.0
1.2
125
1
2
3
4
50 75 100 125 15
0
025
I
D
, DRAIN CURRENT (A)
TA, AMBIENT TEMPERATURE (oC)
VGS = 4.5V, R
θ
JA = 228oC/W
VGS = 10V, R
θ
JA = 50oC/W
0.01
0.1
1
2
10-4 10-3 10-2 10-1 100101102103
0.00110-5
t, RECTANGULAR PULSE DURATION (s)
ZθJA, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
RθJA = 228oC/W
10
100
200
1
10-4 10-3 10-2 10-1 100101102103
10-5
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
VGS = 5V
RθJA = 228oC/W
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
I = I25 150 - TA
125
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
HUF76407DK8
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
1
10
10 20
0
500
0.1 1
100µs
10ms
1ms
VDS, DRAIN TO SOURCE VOLTAG E (V)
ID, DRAIN CURRENT (A)
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TJ = MAX RATED
TA = 25oC
SINGLE PULSE
100
RθJA = 228oC/W
100
1
10
50
0.01 0.1 1 1
0
I
AS
, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R
≠
0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
0
5
10
15
20
2.0 2.5 3.0 3.5 4.5 5
.0
I
D,
DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% M AX
VDD = 15V TJ = 25oC
TJ = 150oC
TJ = -55oC
4.0
5
10
15
20
0123
4
0
VGS = 4V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 3V
VGS = 5V
VGS = 10V
TA = 25oC
VGS = 4.5V
VGS = 3.5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 1A
60
90
120
150
246810
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 3.8A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
3579 0.5
1.0
1.5
2.0
-80 -40 0 40 80 120 16
0
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATUR E (oC)
ON RESISTANCE
VGS = 10V, ID = 3.8A
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
0.5
HUF76407DK8
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
FIGURE 11. NORMALIZED GATE THRESHOLD V OLTA GE vs
JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDO WN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE W AVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Typical Performance Curves (Continued)
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 16
0
NORMALIZED GATE
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250
µ
A
THRESH OLD VOLTAGE
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 16
0
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250
µ
A
5
10
100
1000
0.1 1.0 10 6
0
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS
=
CGS + CGD
COSS
≅
CDS + CGD
CRSS
=
CGD 0
2
4
6
8
10
024681
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 30V
Qg, GATE CHARGE (nC)
ID = 3.8A
ID = 1.0A
WAVEFORMS IN
DESCENDING ORDER:
20
30
40
50
0 102030405
0
0
SWITCHING TIM E (ns)
RGS, GATE TO SOURCE RESISTANCE (
Ω
)
VGS = 4.5V, VDD = 30V, ID = 1.0A
td(OFF)
tr
tf
td(ON)
10 20
40
60
80
0 102030405
0
0
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (
Ω
)
VGS = 10V, VDD = 30V, ID = 3.8A td(OFF)
trtd(ON)
tf
HUF76407DK8
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10
V
VDS
VGS
I
g(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF76407DK8
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maxi mum allo wab le de vice pow er dissipati on, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and ther mal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equat ion 1 math em atically represents the rela tionship and
serves as the basis for estab l is hing the rat ing of the part.
In usin g surface moun t devices su ch as the SO P-8 pac k age ,
the environment in which it is applied will have a significant
influence on the part’s current and maxim um power
dissip ation ratin gs. Preci se determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whethe r there is cop pe r on one side or both sides of the
board.
2. The number o f copp er la y e rs and the th ic knes s of t he
board.
3. The use of exter nal heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non st eady state ap plication s, the pul se width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’ s preliminary application eval uation. Figure 23
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board wi th 1oz co pper after 1000 seco nd s
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power di ssipation. Pulse applications
can be ev aluated using the Fairchild device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict t he compromise between the copper board area, the
thermal resis tance and ultimately the po w e r dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a cofficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
While Equation 2 describes the thermal resistance of a
single die, se veral of the new UltraFETs are offered with two
die in the SOP-8 package. The dual die SOP-8 package
introduces an additi ona l thermal component, the rmal
coupling resistance, Rθβ. Equation 3 desc ribes Rθβ as a
function of the top coppe r moun ting pad area .
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
thermal resistance (RθJA) and thermal coupling resi st anc e
(Rθβ) are equivalent for both die. For example at 0.1 square
inches of copper:
RθJA1 = RθJA2 = 159oC/W
Rθβ1 = Rθβ2 = 97oC/W
TJ1 and TJ2 define the junction temerature of the respective
die. Sim il arly, P 1 and P2 defi ne the po wer dissipated i n each
die. The steady sta te junction temperatu re can be ca lculated
using Equation 4 for die 1and Equation 5 for di e 2.
Example : To calcula te the junction temper a ture of each die
when di e 2 is dis si pat ing 0.5 Wa tts and die 1 is d is si pating 0
Watts. The am bi ent tem perature is 70oC and the pac k age is
mounted to a top copp er ar ea of 0.1 squ are inches per die.
Use Equation 4 to c alulate TJ1 and and Equation 5 to
calulate TJ2.
.
TJ1 = (0 Watts)(159oC/W) + (0.5 Watts)(97oC/W) + 70oC
TJ1 = 119oC
TJ2 = (0.5 Watts)(159oC/W) + (0 Watts)(97oC/W) + 70°C
TJ2 = 150oC
(EQ.
1)
PDM TJM TA
–()
RθJA
-------------------------------=
(EQ. 2
)
R
θJA 103.2 24.3 Area()
ln
×–=
0
50
100
150
200
250
300
0.001 0.01 0.1
1
Rθβ, RθJA (oC/W)
AREA, TOP COPPER AREA (in2) PER DIE
191 oC/W - 0.027in2
228 oC/W - 0.006in2
F
IGURE 23. THERMAL RESISTANCE vs MOUNTING PAD ARE
A
RθJA = 103.2 - 24.3 * ln(AREA)
Rθβ = 46.4 - 21.7 * ln(AREA)
(EQ. 3
)
R
θβ 46.4 21.7 Area()
ln
×–=
(EQ. 4
)
T
J1 P1RθJA P2Rθβ TA
++=
(EQ. 5
)
T
J2 P2RθJA P1Rθβ TA
++=
HUF76407DK8
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
The tra nsien t thermal imped anc e (ZθJA) is also effected by
varied top copper board area. Figure 24 shows the effect of
copper pad area on sing le pul se tr ans ient thermal
impedance. Each trace represents a copper pad area in
squar e inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths les s than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
R THERM5 remain constant f or each of the thermal models. A
listing of the model component values is available in Table 1.
0
40
80
120
160
10-1 100101102103
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
t, RECTANGUL AR PULSE DURATION (s)
ZθJA, THERMAL
IMPEDANCE (oC/W)
COPPER BOARD AREA - DESCENDING ORDER
0.020 in2
0.140 in2
0.257 in2
0.380 in2
0.493 in2
HUF76407DK8
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
PSPICE Ele ctrical Model
.SUBCKT HUF76407DK8 2 1 3 ; REV 28 May 1999
CA 12 8 4.55e-10
CB 15 14 5.20e-10
CIN 6 8 3.11e-10
DBODY 7 5 DBODYMOD
DBRE AK 5 11 DB REAK MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 67.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTH R ES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRA IN 2 5 1.0e - 9
LGATE 1 9 1.5e-9
LSOURCE 3 7 4.86e-10
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.00e-2
RGATE 9 20 3.37
RLDRAIN 2 5 10
RLGATE 1 9 15
RLSOURCE 3 7 4.86
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.80e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTE M P 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 1 9 DC 1
ESL C 51 50 VALUE={(V(5,5 1)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*105),2))}
.MODEL DBOD YMOD D (IS = 3.17e-13 RS = 2.21e-2 TRS1 = 6.25e-4 TRS2 = -1.11e-6 CJO = 6.82e-10 T T = 7 .98e-8 M = 0.65)
.MODEL DBREAKMOD D (RS = 3.36e- 1TRS1 = 1.25e- 4TRS2 = 1.34e-6)
.MODEL DPLCAPMOD D (CJO = 2.91e-1 0IS = 1e-3 0 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 2.00 KP = 1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37)
.MODEL MSTRO M OD NMOS (V TO = 2.33 KP = 19 IS = 1e-30 N = 10 TO X = 1 L = 1u W = 1u)
.MODEL MWEA KM OD NMOS (VTO = 1.71 KP = 0.02 IS = 1 e-30 N = 10 TO X = 1 L = 1u W = 1u RG = 33.7 RS = 0 .1)
.MODEL RBREAK MOD R ES (TC1 = 1.06e - 3TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5)
.MODEL RSLCMOD RES (TC1 = 1.0e-3 TC2 = 1.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6)
.MODEL RVTEMPMO D RE S (TC1 = -1.11e- 3TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.0 VOFF= -2.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -7.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= 0)
.MODEL S2BMOD VSWIT CH (RON = 1e-5 ROFF = 0.1 VON = 0 V OFF= -1.0)
.ENDS
NOTE: For further disc ussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MO SFET Feat uring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J . Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF76407DK8
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
SABER Electrical Model
REV 28May 1999
template huf76407dk8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.17e-13, cjo = 6.82e-10, tt = 7.98e-8, m = 0.65)
d..model dbreakmod = ()
d..model dplc apmod = (cjo = 2 .91e-10, is = 1e-30, m = 0.85)
m..model mmedmod = (type=_n, vto = 2 .00, kp = 1, is = 1e-30, tox = 1)
m..model mstrongmod = (type= _n, vto = 2.33, kp = 19, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.71, kp = 0.02, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7, voff = -2.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -7)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -1)
c.ca n12 n8 = 4.55e-10
c.cb n15 n14 = 5.20e-10
c.cin n6 n8 = 3.11e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dpl capmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.5e-9
l.lsourc e n3 n7 = 4.86e-10
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res. rb r ea k n17 n18 = 1, t c1 = 1.06e-3, tc2 = 0
res.rdbody n71 n5 = 2.21e-2, tc1 = -6 .25e-4, tc2 = -1.11e-6
res.rdbreak n72 n5 = 3.36e-1, tc1 = 1.25e-4, tc2 = 1.34e-6
res.rdrain n50 n16 = 3.00e-2, tc1 = 1.23e-2, tc2 = 2.58e-5
res.rgate n9 n20 = 3.37
res.r ldrain n2 n5 = 10
res. rl g ate n1 n9 = 15
res.rlsource n3 n7 = 4.86
res.rs lc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.r slc2 n5 n50 = 1e3
res.rs ource n8 n7 = 3.80e-2, tc1 = 0, tc2 = 0
res.rv temp n18 n19 = 1, tc1 = -1.11e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -2.19e-3, tc2 = -4.97e-6
spe.ebreak n11 n7 n17 n18 = 67.8
spe.e ds n14 n8 n5 n8 = 1
spe.e gs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5 ,n51))))*((abs(v(n5,n51)*1e6/105))** 2))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76407DK8
©2001 Fairch ild Semicond uctor C orpo ration HUF76407DK8 Rev. B
SPICE Thermal Model
REV 1June 1999
HUF76407DK8
Copper Area = 0.02 in2
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1 .8e-3
CTHERM3 7 6 5 .0e-3
CTHERM4 6 5 1 .3e-2
CTHERM5 5 4 4 .0e-2
CTHERM6 4 3 9 .0e-2
CTHERM7 3 2 4 .0e-1
CTHERM8 2 tl 1.4
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6 .0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
RTHERM5 5 4 18
RTHERM6 4 3 39
RTHERM7 3 2 42
RTHERM8 2 tl 48
SABER Thermal Model
Copper Area = 0.02 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm 1 t h 8 = 8.5e-4
ctherm.ctherm 2 8 7 = 1.8e- 3
ctherm.ctherm 3 7 6 = 5.0e- 3
ctherm.ctherm 4 6 5 = 1.3e- 2
ctherm.ctherm 5 5 4 = 4.0e- 2
ctherm.ctherm 6 4 3 = 9.0e- 2
ctherm.ctherm 7 3 2 = 4.0e- 1
ctherm.ctherm8 2 tl = 1.4
rtherm.rtherm1 th 8 = 3.5e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 2
rtherm.rtherm4 6 5 = 8
rtherm.rtherm5 5 4 = 18
rtherm.rtherm6 4 3 = 39
rtherm.rtherm7 3 2 = 42
rtherm.rtherm8 2 tl = 48
}
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
7
JUNCTION
AMBIENT
8
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
TABLE 1. THERMAL MODELS
COMPONENT 0.02 in20.14 in20.257 in20.38 in20.493 in2
CTHERM6 9.0e-2 1.3e-1 1.5e-1 1.5e-1 1.5e-1
CTHERM7 4.0e-1 6.0e-1 4.5e-1 6.5e-1 7.5e-1
CTHERM8 1.4 2.5 2.2 3 3
RTHERM6 39 26 20 20 20
RTHERM7 42 32 31 29 23
RTHERM8 48 35 38 31 25
HUF76407DK8
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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
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that has been discontinued by Fairchild semiconductor.
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FASTr™
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Rev. H4
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STAR*POWER is used under license
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