Direct-Rambus-Clock-Generator- - Rambus, Inc.

Document DL-0097 Version 1.1 Preliminary Information Page 1

RAMBUS Direct RambusTM Clock Generator-Lite

Overview

The Direct RambusTM Clock Generator-Lite (DRCG-

Lite) provides the necessary clock signals to support a

Direct Rambus mem ory subsystem using a low cost

crystal input. Contained in a 16-pin TSSOP package,

the DRCG-Li te provides an off-the-shelf solution for a

broad range of Direct Rambus® memory applications,

such as PC and workstation main memory, graphics

frame buffe rs, and commun ication s buffer memor y.

Features

■High speed clock support

300-400 MHz clock source for Direct Rambus

memory syste ms supports up to a 1.6 GB /sec data

transfer rate

■Single differential output driver with less than

50ps short term jitt er

■18.75 MHz crystal input

■Supports frequency multipliers: 16 and 64/3.

■Second LVCMOS output (LCLK) which runs at 1/2

the crystal frequency

■Supports independent channel clocking

Supports syst ems not requiring s ynchronization of

the Rambus clock to another system clock

■Act ive po wer < 350mW; Vdd = 3.3 V ± 10%

■Output edge rate control to minimize EMI

Figure 1: Direct Rambus Clock Generator-Lite Package

Related Documentation

Data sheets for the Rambus memory system compo-

nents, including the Rambus DRAMs, RIMMTM-

Module, RIMM connector a r e available on the Rambus

web site at http://www.rambus.com.

The DRCG-Lite is packaged in a 16-p in 225mil TSS OP.

Figure 2 shows the pin assignments. Table 1 describes

the function and connection of each pin.

Figure 2: DRCG-Lite Pin-out

CLK

VDD

LCLK

VDDL

VSSL

XIN

VSS

VDDP

VSSP

XOUT

CLK

VSS

Page 2 Preliminary Information Document DL-0097 Version 1.1

Direct RambusTM Clock Generator-Lite Data Sheet

a. Test pins S1 and S2 should be left floating during normal operation.

Table 1. DRCG-Lite Pin-Out

Pin# Signal Type Function Notes

1 VDDP Pwr Power Supply for PLL 3.3V Supply

2 VSSP Pwr Ground for PLL Ground

3 XOUT - Reference Crystal Feedback

4 XIN - Reference Crystal Input

5 VDDL Pwr Power Supply for LCLK 1.8V Supply

6 LCLK Out LVCMOS Output 1/2 of Crystal Frequency

7 VSSL Pwr Ground for LCLK Ground

8 S1 I/O Test Vendor Specifica

9 S2 I/O Test Vendor Specifica

10 VDD Pwr Power Supply 3.3V Supply

11 VSS Pwr Ground Ground

12 CLKB Out Output Clock (compl ement) Connect to Rambus Channel

13 CLK Out Output Clock Connect to Rambus Channel

14 VSS Pwr Ground Ground

15 VDD Pwr Power Supply 3.3V Supply

16 S0 In PLL Multiplier Select Pull-up Resi stor Inside

Document DL-0097 Version 1.1 Preliminary Info rmation Page 3

Direct RambusTM Clock Generator-Lite Data Sheet

Figure 3: Direct Rambus Clock Generator-Lite Block Diagram

General Description

Figure 3 shows the block diagram of the DRCG-Lite.

The major blocks of the DRCG-Lite include a Phase

Lock Loop, a Differential Output Buffer, and an

LVCMOS outpu t buffer.

The DRCG-Lite receives its reference from an external

crystal. Pin XIN is the reference crystal input, and pin

XOUT is the reference crystal feedback. As the capac-

itor is external, please contact crystal manufacturer for

the specific capacitor value. The S0 pi n controls the

multiply ratio for the PL L . The multiply ratio va lues

for S0 are shown in Table 2 and described in the PLL

Multiplier section.

The Differential Output Buffer (CLK and CLKB)

supplies the 300-400 MHz clock for the Rambus system

and is impedance ma tched to the Rambus Channel

transmission line.

The LVCMOS output buffer ( LCLK) is a refer ence clock

that operates at 1/2 the crystal input frequency and

can be used by other parts of the system. It is not used

in the Rambus memory system.

The S1 and S2 input pins are used for test mode

purposes only. Please contact the specific DRCG-Lite

manufacturer for further information on how the S1

and S2 pins should be used.

PLL CLK

OSC

CLK

Differential

Output Buffer

Multiplier

LCLK

XTAL Xin

Xout

Page 4 Preliminary Information Document DL-0097 Version 1.1

Direct RambusTM Clock Generator-Lite Data Sheet

Figure 4: System Clock Architecture

Example System Clock Configuration

Figure 4 shows the clocking config uration for an

example single channel Direct Rambus DRAM

subsystem . T he configuration shows the in terconnec-

tion of the system clock source, the Direct Rambus

Clock Generator-Lite (DRCG-Lite), an d the clock

signals of a memory controller. The controller contains

the Rambus ASIC Cell (RAC) and the Rambus

Memory Controller (RMC). (The diagram represents

the differential clock outputs. CLK and CLKB, as a

single Bus Clock wire.)

A crystal is used as the input reference frequency. A

PLL inside the DRCG-Lite generates the desired

frequency for Bus Clock. Bus Clo c k is driven on the

Rambus Channel through a terminated transmission

line. At the mid-point of the Channel, the RAC senses

Bus Clock using its own DL L for clock al ignment,

followed by a fixed divide-by-4 circuit that generates

SynClk. SynClk is the clock used at the ASIC interface

of the RAC.

The DRCG-Li te also contai n s an addit i on al LVCMOS

output, Lclk, which provides a reference clock at 1/2 of

the crystal frequency. This clock can be used by other

blocks in a system, but is not used in the memory

subsystem.

PLL Multiplier

Table 2 shows the frequency mul tipliers in the PLL,

selected via the S0 input. The S0 pin is a standard 3.3v

LVCMOS input with a n internal pullup resistor.

Test Modes

The select bits, S1 and S2, control the selection of test

modes. These modes are vendor specific. Please

contact vendor for information. S1 and S2 are left

floating during normal opera t ion.

Bus Clock

Direct RambusTM

Clock Generator-

Lite

(DRCG-Lite)

Controller

...

3.3V

DLL

SynClk

RAC

RMC

XTAL

Lclk

RDRAM® devices

Table 2. PLL Multiplier Selection

S0 M (PLL Multiplier)

016

1 or

open 64/3

Document DL-0097 Version 1.1 Preliminary Info rmation Page 5

Direct RambusTM Clock Generator-Lite Data Sheet

State Transition Latency

Table 3 specifies the maxim um settling time of the

CLK, CLKB and LCLK o utputs from device power - up.

For VDD, VDDP and VDDL, any sequence is a llowed

to power-up and power-down the DRCG-Lite.

Device Parameters

This section specifies the numerical values of the phys-

ical parameters described earlier in this data sheet.

The DRCG clock source meets the device characteris-

tics listed in Table 7 and Table 10 when characterized

under the operati ng conditions lis ted i n Table 6 and

Table 8, and when using the components shown in

Figure 5, and the corresponding component values

given in Table 11.

Only the DC specifications of Table 7 apply while in

Test mode. The AC specifications of Table 10 (see

Logical Specification Section for mode descriptions) do

not apply while in Test mode unless specified .

Absolute Maximums

Table 4 represents stres s ratings only, and functional

operation at the maximum settings is not gu aranteed.

Supply Current Characteristics

The current drawn through the VDD pins i s specif ied in

Table 5. This includes the total curr ent through all VDD,

VDDP, and VDDL pins.

Table 3. State Transition Latency

From To Transition

Laten c y Description

VDD/V

DDL/V

DDP

CLK/C

LKB/LC

LK No r-

mal

3 mS Time from

VDD/VDDL/VDDP is

applied and settled to

CLK/CLKB/LCLK ou t-

puts settled.

Table 4. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

VDD,ABS Max voltage on VDD

with respect to

ground

-0.5 4.0 V

VI,ABS Max voltage on an y

pin with respect to

ground

-0.5 VDD+

0.5 V

ViL,ABS Max voltag e on LCLK

with respect to

ground

-0.5 VDD+

0.5 V

Table 5. Supply Current Characteristics

Symbol Parameter Min Max Unit

INORMAL Current in Normal

state 100 mA

Page 6 Preliminary Information Document DL-0097 Version 1.1

Direct RambusTM Clock Generator-Lite Data Sheet

DC Operating Conditions

This section specifies input conditions for operating

the device. When operated outside these limits, device

characteristics are undefined.

a VDD L shou ld be tie d to grou n d if LCL K is not us ed

DC Characteristics

This section specifies the device characteristics when

using the external circuits as shown in Figure 5 wit h

component va lues listed in Table 11.

a. VCOS = VOH - VOL . Measured on external divider shown in Figure 5.

b. rOUT = DVO/DIO. This is defined at the output pins.

Table 6. DC Operating Conditions

Symbol Parameter Min Max Unit

VDD Supply vol tage 3.04 3.5 6 V

VDDL LCLK Supply voltagea1.7 2.1 V

TAAmbient operating temperature 0 70 °C

VIL Input s ignal lo w volt age at pi n S - 0.35 VDD

VIH Input signal high voltage at pin S 0.65 - VDD

RPUP Internal pull- up resistance 10 100 kΩ

Table 7. DC Device Characteristics

Symbol Parameter Min Max Unit

VXDifferential output crossing-point voltage 1.3 1.8 V

VCOS Out put volt a ge swing (p-p single-ended) a0.4 0.7 V

VOH Output high voltage - 2.1 V

VOL Output low voltage 1.0 - V

rOUT Output dynamic resistance (at pins)b12 50 Ω

VLOH LCL K Outp ut high voltage at IOH = -10mA VDD L -

0.45V VDDL V

VLOL LCLK Output low voltage at IOL = 10mA 0 0.45V V

Document DL-0097 Version 1.1 Preliminary Info rmation Page 7

Direct RambusTM Clock Generator-Lite Data Sheet

AC Operating Conditions

This section specifies input AC conditi ons for oper-

ating the device. When operated outside these limits,

device characteristics are undefined.

a. Nomina l co ndi t i on with 18 .7 5 MHz crystal

b. Capacitance measured at Frequency= 1MHz, DC bias = 0.9V, and VAC < 100mV

Crystal Requirements

Table 9 Gives the specifications of the recommended

crystal to be used with the DRCG-Lite clock source.

The mode of oscillation is fundamental.

a. At 25oC +/- 3oC

b. CL = 10pF

c. -10oC to 75oC

d. At XF +/- 500 kHz

Table 8. AC Operating Conditions

Symbol Parameter Min Max Unit

fXTAL,IN Input frequency at crystal inputa14.0625 18.75 MHz

CIN,CMOS Input capacitance at S0 pinb-10pF

Table 9. Crystal Specifications

Symbol Parameter Min Max Unit

XFFrequency 14.0625 18.75 MHz

XFTOL Frequency Tolerancea-100 100 ppm

XEQRES Equivalent Resi st anc eb100 Ω

XTEMP Temperature Driftc10 ppm

XDRIVE Drive Level 0.01 1500 uW

XMI Motional Inductance 20.7 25.3 mH

XIR Insulation Resistance 500 MΩ

XSAR Spurious Attenuation Ratiod3dB

XOS Overtone Spurious 8 dB

Page 8 Preliminary Information Document DL-0097 Version 1.1

Direct RambusTM Clock Generator-Lite Data Sheet

AC Characteristics

Table 10 gives the AC characteristics for device opera-

tion using the external circuits as shown in Figure 5

with component values listed in Table 11.

a. Output s ho rt -t erm ji tter spec is the a bs olu te v al ue o f the worst case +/- deviation and i s def i ned in the Jitter s ecti on.

b. LCLK cycle jitter is defined as the difference between the measured period and the no minal period as defined in the

Jitter section.

Table 10. AC Device Characteristics

Symbol Parameter Min Max Unit

tCYCLE Clock cycle time 2.5 3.33 ns

tJJitter over 1-6 clock cycles at 400MHza-50ps

Jitter over 1-6 clock cycles at 300MHza-70ps

tJL Long-term Jitter at 400MHz - 300 ps

Long-term Jitter at 300MHz - 400 ps

DC Long-term average output duty cycle 40% 60% tCYCLE

tDC,ERR Cycle-to-cycle duty cycle error at 400MHz - 50 ps

Cycle-to-cycle duty cycle error at 300MHz - 70 ps

tCR, tCF Output rise and fall times (measured at

20% - 80% of output voltage) 120 400 ps

tCR,CF Difference between output rise and fall times

on the same pin of a single device (20% - 80%) - 100 ps

BWLOOP PLL Loop Bandwidth 50 kHz

(-3dB) 8 MHz

(-20dB)

tCYCLE,L LCLK Clock cycle time 106.6 142.2 ns

tLR, tLF LCLK output ri se and fall time - 1 ns

tJC,L LCLK cycle jitter b-0.8 0.8 ns

DCLLCLK output duty cycle 40% 60% tCYCLE,L

Document DL-0097 Version 1.1 Preliminary Info rmation Page 9

Direct RambusTM Clock Generator-Lite Data Sheet

Clock Output Driver

Figure 5: Example System Cloc k Drive r Equi vale nt Circuit

Figure 5 shows the clock driver equivalent circuit. The

differential output clock driver of the DRCG has a low

output impedance in the range of about 20 ohms. The

driver produces the specified voltage swing on the

channel, and also mat ches the chan nel im pedance. The

nominal value of the channel impedance, ZCH, is

expected to be 28-40 ohms for a Rambus memory

subsystem. External series resistors RS an d para llel

resistors RP are used to set the voltage swing on the

channel. The driver output characteristics are defined

together with the external components, and the output

clock is specified at the mea surement point indicated

in Figure 5. The complete set of external components

for the output driver circuit, including edge-rate filter

capacitors is also shown in the figure and example

values for the external components are shown in

Table 11.

The clock driver is specified as a black-box at the

package pins. The output characteristics are measured

after the series resistance, RS. The outputs are termi-

nated differentially at the end of the transmission line,

with no appl ied termination voltage.

The clock driver’s output impedance, rOUT, is in series

with RS, and the combination is in parallel with RP

. The

resulting effective impedance must mat ch the channel

impedance in or der to minimize secondary reflections.

To accomplish this, each of the four CMOS output

devices is designed to have an rOUT of abou t 20 ohms

when fully turned on. rOUT is the dynamic output resis-

tance. Since rOUT is in series with RS, and that co mbina -

tion is in parallel with RP, the effective output

impedance is given by:

RP (RS + rOUT) / (RP + RS + rOUT)

This calculation results in an effective output imped-

ance of about 27 ohms for the example values listed in

Table 1 1. Since the total impedance is dominated by the

external resistors, a large variation in the on-chip value

of rOUT is allowed. When the output is tran sitioning,

the impedance of the CMOS devices incr eases dramati -

cally. The purpose of RP is to limit the maximum

output impedance during output transitions.

In order to control signal attenuation and EMI, clock

signal rise/fall times are tightly controlled. External

filter capacitors CF could be used to control the output

slew rate. In addition, the capacitor CMID is used to

provide AC ground at the mid-point of the RP and the

RT resistors.

Table 11 gives the nominal values of the externa l

components and th eir maximum acceptable tolerance,

assuming ZCH = 28 ohms for the example Rambus

memory subsystem. These values apply to DRCG test-

boards. For motherboard values, see the system phys-

ical design guide.

a: CF is optional and can be used to control output slew rate

and EMI if necessary. For the DRCG-Lite characterization

board, no discrete capacitor filter is used.

Measurement Point

RPZCH

ZCH

CFCMID

Measurement Point

CMID

Differential Driver

Table 11. Example External Component Values

Symbol Parameter Value Tolerance Unit

RTTermi nation resistor 28 ± 1% Ω

RSSeries resi stor 68 ± 5% Ω

RPP arallel resistor 39 ± 5% Ω

CFEdge-Rate

Filter Capacitora4-10 ± 10% pF

CMID AC Ground Capacitor 100 ± 20% pF

Page 10 Preliminary Information Document DL-0097 Version 1.1

Direct RambusTM Clock Generator-Lite Data Sheet

Output Driver Characteristics

Table 12 gives example V/I characteristics for the

differential clock output drivers at the pins of the

DRCG-Lite. The sign on all current parameters (direc-

tion of current flow) is referenced to a ground inside

the component; i.e. positive currents flow into the

component. These example V/I characteristics can be

used for generating simulation models of the DRCG-

Lite (such as IBIS models). Table 12 provides examples

values and does not represent additional specifica-

tions.

Table 12 . Output Buffer V/I Characteristics

Voltage

(V)

Pull-Down Pull-Up

I (mA) I (mA) I (mA) I (mA) I (mA) I (mA)

Min Typ Max Min Typ Max

0000-35-55-91

0.2 8.3 11.9 17.6 -34 -55 -90

0.4 15.8 22.8 33.6 -34 -54 -89

0.6 22.5 32.5 47.9 -33 -53 -87

0.8 28.3 41.0 60.3 -33 -52 -86

1.0 33 48 71 -32 -51 -84

1.2 37 54 79 -31 -50 -82

1.4 41 59 85 -30 -48 -79

1.6 43 62 90 -28 -46 -77

1.8 44 64 92 -27 -43 -73

2.0 45 65 93 -24 -40 -68

2.2 45 66 94 -21 -36 -62

2.4 46 66 95 -17.7 -31.1 -55.0

2.6 46 67 95 -13.6 -25.4 -46.7

2.8 46 67 95 -8.9 -19.0 -37.6

3.0 46 67 96 -3.7 -11.9 -27.4

3.135 46 67 96 0 -6.7 -19.9

3.3 67 96 0 -10.3

3.465 96 0

Document DL-0097 Version 1.1 Preliminary Information Page 11

Direct RambusTM Clock Generator-Lite Data Sheet

Signal Waveforms

A physical signal which appears at the pins of a device

is deemed valid or invalid depending on its voltage

and timing relations with other signals. Input and

output voltage waveforms are defined as shown in

Figure 6. Both rise and fall times are defined between

the 20% and 80% points of the voltage swing, wi th the

swing defined as VH - VL. For example, the output

voltage swin g VCOS = VOH - VOL

Figure 6: Input a nd Output Voltage Waveforms

Figu re 7 shows th e def in i ti on of output crossing p oi n t.

The nominal crossing point between the complemen-

tary outputs is defined to be at the 50% point of the DC

voltage levels. There are two crossing points defined,

Vx+ at the rising edge of CLK and Vx- at the falling

edge of CLK. For some clock waveforms, both Vx+ and

Vx- might be below Vx,nom (for example, if tCR is

larger than tCF).

Figure 7: Crossing-p oint Voltage

Figure 8 shows the definition of long-term duty cycle,

which is sim p ly the waveform hi gh- time divided by

the cycle time (defined at the crossing point). Long-

term duty cycle is the average over many (>10,000)

cycles. Short-term duty cycle is defined in Figure 10.

Figure 8: Duty Cycle

80%

V(t) 20%

CLK

CLKB

Vx,nom

Vx+

Vx-

CLK

CLKB

tPW+

tCYCLE

DC = (tPW+ / tCYCLE)

tPW-

Page 12 Preliminary Information Document DL-0097 Version 1.1

Direct RambusTM Clock Generator-Lite Data Sheet

Jitter

This section de fines the specifications that relate to

timing uncertainty (or jitter) of the input and output

waveforms. Figure 9 shows the definition of cycle-to-

cycle jitter with respect to the falling edge of the CLK

signal. Cycle-to-cycle j itter ( als o called 1-cycle short

term jitter) is the difference between cycle times of

adjacent cycles. Equal requirements apply for rising

edges of the CLK signal.

Figure 9: Cycle-to-cycle Jitter

Figure 10 shows the definition of 4-cycle short-term

jitter. Short-term jitter is defined with respect to the

falling edge of the CLK signal. 4-cycle short-term jitter

is the differ ence between the cumulative cycle times of

adjacent 4-cycles. Equal requirements apply for rising

edges of the CLK signal. Equal requirements also

apply for 2-cycle, 3-cycle, 5-cycle, and 6-cycle short-

term jitter.

Figure 10: Short-term Jitter

The purpose of this definition of short-term jitter is to

define errors in the measured time (for example,

t4CYCLE, i) vs. the expected time. The purpose for

measuring the adjacent time t4CYCLE, i+1 is only to help

determine the expected time for t4CYCLE , i. Alternate

methods of determini ng tJ are possible. However,

measuring long-term average jitter instead of short-

term jitter would normally give more pessimistic

results.

Figure 11 sho ws the definition of cycle-to-cycle duty

cycle error (tDC,ERR). Cycle-to-cycle duty cycle error is

defined as the difference between tPW+ (high-times) of

adjacent differential clock cycles. Equal requirements

apply to tPW- , low-times of the differential clock

cycles.

Figure 11: Cycle-to-cycle Duty Cycle Error

CLK

CLKB tCYCLE,i

tJ = tCYCLE,i - tCYCLE, i+1 ov er 10,000 consecutive cycles

tCYCLE,i+1

CLK

CLKB t4CYCLE, i

tJ = t4CYCLE, i - t4CYCLE, i+1 over 10,000 consecutive cycles

t4CYCLE, i+1

CLK

CLKB

Cycle (i) Cycle (i+1 )

tPW+ (i)

tCYCLE (i)

tPW+ (i+1)

tCYCLE (i+1)

tDC,ERR = tPW+(i) - tPW+(i+1) and tPW-(i) - tPW-(i+1)

tPW- (i) tPW- (i+1)

Document DL-0097 Version 1.1 Preliminary Information Page 13

Direct RambusTM Clock Generator-Lite Data Sheet

Figure 12 shows the definition of LCLK cycle jitter and

LCLK 10-cycle jitter. These parameters apply to th e

LCLK output, and not to the Rambus channel clock

outputs.

LCLK cycle jitter is the variation in the clock period, T,

over a continuous set of clock cycles. The difference

between the maximum period and the nominal period

in the set of clock cycles measured would be compared

to the max spec in Table 10. LCLK cycle jitter is

measured between rising edges at 50% of the output

voltage, and is measured continuously over 30 ,00 0

cycles.

Figure 11 sho ws the definition of cycle-to-cycle duty

cycle error (tDC,ERR). Cycle-to-cycle duty cycle error is

defined as the difference between tPW+ (high-times) of

adjacent differential clock cycles. Equal requirements

apply to tPW- , low-times of the differential clock

cycles.

Figure 12: LCLK Jitter

LCLK

Page 14 Preliminary Information Document DL-0097 Version 1.1

Direct RambusTM Clock Generator-Lite Data Sheet

Package Drawing .

Fig ure 13: 16-Pin 225mil TSSOP Pack age Drawing

Table 13. Package Dimensions

Symbol Parameter Min Max Unit

e Pin Pitch 0.6 5 0.65 mm

b Pin width 0.1 9 0.30 mm

A Packa ge tota l length 6.20 6.60 mm

A1 Packa ge bod y leng th 4.30 4.50 mm

D Packa ge tota l width 4.90 5.10 mm

D1 Package o verhang 0.175 0.2 75 mm

E Packa ge total thickness - 1.20 mm

E1 Space under package 0.0 5 0.15 mm

Document DL-0097 Version 1.1 Preliminary Information Page 15

Direct RambusTM Clock Generator-Lite Data Sheet

Table Of Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

DRCG-Lite Pin-out Diagram . . . . . . . . . . . . . . . . . . . . . 1

DRCG-Lite Pin-out Table. . . . . . . . . . . . . . . . . . . . . . . . . 2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Example System Clock Configuration . . . . . . . . . . . . . 4

Transition Ti ming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute Maximums . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 6

AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 7

Crystal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Clock Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

Signal Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Dir ect Rambus , Dire ct RDRAM, SO- RIMM, and RIMM

are trademarks of Rambus Inc. Rambus, RDRAM and

the Rambus Logo are register ed trademarks of Rambus

Inc. All other trademarks re ferenced are property of

their re spective owners.

This document contains information that is subject to

change by Rambus Inc. without notice. Rambus Inc.

assumes no responsibility or liability for any use of the

information contained herein.

This Rambus d ocument is for design evaluation

purposes only. Rambus devices and modules are

manufactured and sold by Rambus partners . Rambus

partners provide data sheets specific to their products.

For a list of companies who are providing Rambus

prod ucts, visit the internet address listed below.

Document DL-009 7, Version 1 .0

Rambus Inc.

2465 Latham Stree t

Mountain View, California USA

94040

Telephone: 650-944-8000

Fax: 650-944-8080

Internet: http://ww w.rambus.com