CY62127BV MoBL(R) 1M (64K x 16) Static RAM Features significantly reduces power consumption when addresses are not toggling, or when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). * High Speed: 55 ns and 70 ns * Wide voltage range: 2.7V-3.6V * Low active power -- 54 mW (max.) (15 mA) * Low standby power (70 ns) -- 54 W (max.) (15 A) * Easy memory expansion with CE and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Package available in a 44-pin TSOP Type II (forward pinout) and a 48-ball fBGA package Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. Functional Description[1] The CY62127BV MoBL(R) MoBL(R) is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that Logic Block Diagram A6 A5 A4 A3 A2 A1 A0 64K x 16 RAM Array 2048 X 512 SENSE AMPS A10 A9 A8 A7 ROW DECODER DATA IN DRIVERS I/O0-I/O7 I/O8-I/O15 BHE WE CE OE BLE A15 A13 Power -Down Circuit A14 A12 A11 COLUMN DECODER CE BHE BLE Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05155 Rev. *B * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised August 27, 2002 CY62127BV MoBL(R) Pin Configurations[2] FBGA (Top View) 4 5 3 6 A1 A2 NC A A3 A4 CE I/O0 B I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 DNU NC I/O4 VSS E 1 2 BLE OE A0 I/O8 BHE I/O9 TSOP II (Forward) Top View A15 I/O5 I/O6 F I/O7 G I/O14 I/O13 A14 I/O15 NC A12 A13 WE NC A8 A9 A10 A11 NC A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC H 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 37 36 35 34 33 32 31 30 29 28 27 13 14 15 16 17 18 19 20 21 22 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC DC Input Voltage[3].................................... -0.5V to VCC + 0.5V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................-65C to +150C Latch-up Current..................................................... >200 mA Ambient Temperature with Power Applied............................................. -55C to +125C Operating Range Supply Voltage to Ground Potential ................. -0.5V to 4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V Range Ambient Temperature VCC Industrial -40C to +85C 2.7V to 3.6V Product Portfolio Power Dissipation (Industrial) Operating, ICC (mA) f = fmax VCC Range (V) Product CY62127BV MoBL(R) Standby, ISB2 (A) VCC(min.) VCC(typ.)[4] VCC(max.) Speed (ns) Max. Typ.[4] Max. 2.7 3.0 3.6 55 20 0.5 15 70 15 Notes: 2. NC pins are not connected to the die. 3. VIL(min.) = -2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. Document #: 38-05155 Rev. *B Page 2 of 11 CY62127BV MoBL(R) Electrical Characteristics Over the Operating Range CY62127BV MoBL(R)-55 Parameter Description Test Conditions Min. Typ.[4] CY62127BV MoBL(R)-70 Max. VOH Output HIGH Voltage IOH = -1.0 mA VCC = 2.7V VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V VIH Input HIGH Voltage 2.0 VCC + 0.3V VIL Input LOW Voltage -0.3 IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VI< VCC, Output Disabled ICC VCC Operating Supply Current f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current-- TTL Inputs Max. VCC, CE VIH VIN VIH or VIN VIL, f = fMAX ISB2 Automatic CE Power-Down Current-- CMOS Inputs Max. VCC, CE VCC - 0.3V, VIN VCC - 0.3V, or VIN 0.3V, f=0 Min. 2.2 Typ.[4] Max. Unit 2.2 V 0.4 0.4 V 2.0 VCC + 0.3V V 0.4 -0.3 0.4 V -1 +1 -1 +1 A -1 +1 -1 +1 A 20 15 mA 2 2 mA VCC = 3.6V IOUT = 0 mA CMOS Levels 0.5 15 0.5 15 A Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 9 pF 9 pF TA = 25C, f = 1 MHz, VCC = 3.3V Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Test Conditions Symbol BGA Unit Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board JA 55 C/W JC 16 C/W Thermal Resistance (Junction to Case)[5] AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC Typ OUTPUT 10% 30 pF R2 INCLUDING JIG AND SCOPE 90% 10% 90% GND Rise TIme: 1 V/ns Fall Time: 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT Note: 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05155 Rev. *B VTH Page 3 of 11 CY62127BV MoBL(R) Parameters 3.0V Unit R1 1.076 K Ohms R2 1.262 K Ohms RTH 0.581 K Ohms VTH 1.620 Volts Data Retention Characteristics (Over the Operating Range) Parameter Description Min. Typ.[4] Max. Unit Conditions VDR VCC for Data Retention 2.0 ICCDR Data Retention Current tCDR[5] Chip Deselect to Data Retention Time tR[6] Operation Recovery Time VCC= VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0.5 3.6 V 15 A 0 ns tRC ns Data Retention Waveform[7] DATA RETENTION MODE VCC 3.0 V 3.0 V VDR > 2.0 V tR tCDR CE or BHE.BLE Switching Characteristics Over the Operating Range [8] 55 ns Parameter Description Min. 70 ns Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 55 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns 55 Z[9] tLZOE OE LOW to Low tHZOE OE HIGH to High Z[9, 11] CE LOW to Low tHZCE CE HIGH to High Z[9, 11] tPU CE LOW to Power-Up tPD CE HIGH to Power-Down tDBE BHE / BLE LOW to Data Valid tLZBE[10] BHE / BLE LOW to Low Z[9] 70 ns 25 10 20 0 0 55 5 ns ns 70 ns 70 ns 5 20 ns ns 25 55 ns ns 5 10 Z[9, 11] ns 10 20 Z[9] BHE / BLE HIGH to High 10 5 tLZCE tHZBE 70 ns 25 ns Write Cycle[12] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 60 ns Notes: 6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together this value is 10 ns. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05155 Rev. *B Page 4 of 11 CY62127BV MoBL(R) Switching Characteristics Over the Operating Range (continued)[8] 55 ns Parameter Description Min. 70 ns Max. Min. Max. Unit tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 40 50 ns tBW BHE / BLE Pulse Width 45 60 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns [9, 11] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z[9] 25 5 25 5 ns ns Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13, 14] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled) DATA VALID [14, 15] ADDRESS tRC CE tPD tHZCE tACE OE BHE/BLE ttLZOE LZOE tHZOE tDOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB Notes: 13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #: 38-05155 Rev. *B Page 5 of 11 CY62127BV MoBL(R) Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [12, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Write Cycle No. 2 (CE Controlled) [12, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05155 Rev. *B Page 6 of 11 CY62127BV MoBL(R) Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [17] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD NOTE 18 DATAI/O tHD DATAIN VALID tLZWE tHZWE [17] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O tHD DATAIN VALID NOTE 18 Truth Table CE WE OE BHE BLE H X X X X High Z Deselect/Power-Down Standby (ISB) X X X H H High Z Deselect/Power-Down Standby (ISB) L H L L L Data Out (I/OO-I/O15) Read Active (ICC) L H L H L Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8-I/O15); I/O0-I/O7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) Document #: 38-05155 Rev. *B Inputs/Outputs Mode Power Page 7 of 11 CY62127BV MoBL(R) Truth Table (continued) CE WE OE BHE BLE L H H L H Inputs/Outputs L L X L L L L X H L L L X L H Data In (I/O8-I/O15) Mode Power Output Disabled Active (ICC) Data In (I/OO-I/O15) Write Active (ICC) Data In (I/OO-I/O7) Write Lower Byte Only Active (ICC) Write Upper Byte Only Active (ICC) High Z Ordering Information Speed (ns) Package Name Ordering Code 55 CY62127BVLL-55ZI 70 CY62127BVLL-70ZI Z44 Operating Range Package Type 44-lead TSOP II Industrial CY62127BVLL-70BAI BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) CY62127BVLL-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Package Diagrams 48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A 51 -850 96-* E Document #: 38-05155 Rev. *B Page 8 of 11 CY62127BV MoBL(R) Package Diagrams (continued) 44-pin TSOP II Z44 51-85087-A Document #: 38-05155 Rev. *B Page 9 of 11 CY62127BV MoBL(R) Package Diagrams (continued) . 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-** MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be trademarks of their respective holders. Document #: 38-05155 Rev. *B Page 10 of 11 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62127BV MoBL(R) Document Title: CY62127BV MoBL(R) 1M (64K x 16) Static RAM Document Number: 38-05155 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109899 10/02/01 SZV Change from Spec number: 38-01018 to 38-05155 *A 113307 03/01/02 MGN Format standardization & update ordering information *B 116362 09/04/02 GBI Document #: 38-05155 Rev. *B Add footnote 1 and BV Package. Page 11 of 11