FINAL
Publication# 15652 Rev: DAmendment/+1
Issue Date: M arch 5, 1999
Am27X020
2 Me gabit (2 56 K x 8 -B i t ) CMO S Express ROM Devi ce
DISTINCTIVE CHARACTERISTICS
■As an OTP EPROM alternative:
— Factory optimized programming
— Fully tested an d guaranteed
■As a Mask ROM alternative:
— Shorter leadtime
— L ower volu me per code
■Fast acce ss tim e
— 75 ns
■Single +5 V power supply
■Compatible with JEDEC-approved EPROM
pinout
■±10% p ower supply tolerance
■Hig h noise immunity
■Low power dissipation
— 1 00 µA max imu m C MO S standby current
■Available in Plastic Dual-In-line Package (PDIP)
and Plastic Leaded Chip Carr ier (PLCC)
■Latch-up protected to 100 mA from – 1 V to
VCC + 1 V
■Versatile features for simple inter facing
— Both CMOS and TTL in put/output comp atibility
— Two line control functions
GENERAL DESCRIPTION
The Am27X020 is a factory programmed and tested
O TP EPR OM. I t is pro gr amme d af ter pac kagi ng pri or to
final test. Every device is rigorously tested under AC
and DC ope rating c onditions to your stable code. It is
organized as 256 Kwords by 8 bits per word and is
available in plastic dual in-line packages (PDIP), as
well as plastic leaded chip carrier (PLCC) packages.
ExpressROM devices provide a board-ready memor y
solution for medium to high volume codes with short
leadtimes. This offers manufacturers a cost-effective
and f le xi ble alt ernati v e to O TP EPRO Ms an d mas k pro-
grammed ROMs.
Data can be accessed as fast as 75 ns, allowing
high-performance microprocessors to operate with re-
duced WAIT states. The device offers separate Output
Enable (OE#) and Chip Enable (CE#) controls, thus
eliminating bus c ontention in a multiple bus microp ro-
cessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 100 mW in active mode,
and 100 µW in standby mode.
BLOCK DIAGRAM
15652D-1
A0–A17
Address
Inputs
CE#
OE#
VCC
VSS
Data Outputs DQ0–DQ7
Output
Buffers
Y
Gating
2,097,152
Bit Cell
Matrix
X
Decoder
Y
Decoder
Output Enable
Chip Enable
and
Prog Logic
2Am27X020
PR ODUCT SELECTOR GUIDE
CONNECTION DIAGRAMS
Top View
DIP PLCC
Notes:.
1. JEDEC nomenclature is in parenthesis.
2. Don’t use (DU) for PLCC.
PIN DESIGNATIONS
A0–A17 = Address Inputs
CE# (E#) = Chip Enable Input
DQ 0– DQ7 = Da ta Inp ut/ Ou tpu ts
OE# (G#) = Output Enable Input
PGM# (P#) = Program Enable Input
VCC =V
CC Supply Voltage
VPP = Program Voltage Input
VSS =Ground
NC = No Internal Connection
LOGIC SYMBOL
Family Part Number Am27X020
Speed Options VCC = 5.0 V ± 5% -255
VCC = 5.0 V ± 10% -75 -90 -120 -150 -200
Max Access Time (ns) 70 90 120 150 200 250
CE# (E#) Access (ns) 70 90 120 150 200 250
OE# (G#) Access (ns) 40 50 50 65 75 100
3
4
5
2
1
9
10
11
12
13
27
26
25
24
23
7
8
22
21
6
32
31
20
14
30
29
28
15
16
19
18
17
A6
A5
A4
A3
A2
A1
A0
A16
DQ0
A15
A12
A7
DQ1
DQ2
VSS
A8
A9
A11
OE# (G#)
A10
CE# (E#)
DQ7
VCC
PGM# (P#)
DQ6
A17
A14
A13
DQ5
DQ4
DQ3
VPP
15652D-2
DQ6
VPP
DQ5
DQ4
DQ3
13130234
5
6
7
8
9
10
11
12
13 17 18 19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE# (G#)
A10
CE# (E#)
DQ7
A12
A15
A16
VCC
PGM# (P#)
A17
DQ1
DQ2
VSS
15652D-3
18
8
DQ0–DQ7
A0–A17
CE# (E#)
OE# (G#)
15652D-4
Am27X020 3
ORDERING INFORMATION
Standard Products
AMD standard products are available in sev eral pac kages and operating ranges. The order number (Valid Combination) is f ormed
by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am27X020
2 Megabit (256 K x 8-Bit) CMOS ExpressR OM Device
AM27X020 -70 J C
CODE DESIGNATION
Assigned by AMD
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I=Industrial (–40°C to +85°C)
PACKAGE TYPE
P = 32-Pin Plastic Dual In-Line Package (PD 032)
J = 32-Pin Plastic Leaded Chip Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
XXXXX
Valid Combinations
AM27X020-70
PC, JC, PI, JI
AM27X020-90
AM27X020-120
AM27X020-150
AM27X020-200
AM27X020-255
VCC = 5.0 V ± 5%
4Am27X020
FUNCTIONAL DESCRIPTIO N
Rea d Mode
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low . CE# con-
trols the power to the device and is typically used to se-
le ct th e de v i c e. OE # en ab l es th e de v i c e to ou tp u t da t a,
independent of device selection. Addresses must be
stable for at least tACC–tOE. Refer to the Switching
Waveforms section for the timing diagram.
Stand by Mode
The device enters the CMOS standby mode when CE#
is at VCC ± 0.3 V. Ma ximu m VCC curr ent is re duc ed t o
100 µA. The device enters the TTL-standby mode
when CE# is at VIH. Maxi mum V CC current is r educe d
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
Output OR-Ti e ing
To accommodate multiple memory connections, a
two-line control function provides:
■Low memory power dissipation, and
■Assurance th at output b us contention will not occur .
CE# should be decoded and u sed as the prim ary de-
vice-selecting function, while OE# be made a common
connection to all devices in the array and connected to
the READ line from the system control bus. This as-
sures that all deselected memor y devices are in their
low-p ower st an dby mo de a nd th at th e o utput pins ar e
onl y a ct iv e w hen d ata i s de sire d fr om a particu lar mem-
ory device.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the r is-
in g a nd f al l in g ed ge s of C hip E n ab l e . The ma gn i t ud e of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to m ini m ize tran si e nt e ffects. In a dd iti on ,
to ove rcome the vol tage dro p cau sed by th e i nduct ive
effects of the printed cir cuit board traces on Express-
ROM device arra ys, a 4.7 µF bulk electrolytic capacitor
should be used between VCC and VSS for each eight
devices. The loca tion of the capacitor should be close
to where the power supply is connected to the array.
MODE SELECT TABLE
Note:
X = Either V
IH
or V
IL
.
Mode CE# OE# PGM# VPP Outputs
Read VIL VIL XXD
OUT
Output Disable X VIH X X High Z
Standby (TTL) VIH X X X High Z
Standby (CMOS) VCC ± 0.3 V X X X High Z
Am27X020 5
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to VSS
All pins except VCC . . . . . . . . . –0.6 V to VCC + 0.6 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V
Note:
1. Minimum DC voltage on input o r I/O pins –0.5 V. Dur ing
voltage transitions, the input may o vershoot V
SS
to –2.0 V
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is V
CC
+ 5 V. During voltage transitions, input
and I/O pins may overshoot to V
CC
+ 2.0 V f or periods up
to 20 ns.
Stresses a bove those liste d under “Abs olute Maximum R at-
ings” may cause p er mane nt dam age t o the d evice. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for e xtended periods
may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Tem perature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Ambient Tem perature (TA) . . . . . . . . .–40°C to +85°C
Supply Read Voltages
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
6Am27X020
DC CHARACTERISTICS o ver op erat in g range (unless otherwise specified )
Caution: The device must not be removed from (or inserted into) a socket when V
CC
or V
PP
is applied.
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
..
2. I
CC1
is tested with OE# = V
IH
to simulate open outputs.
3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods less than 20 ns.
F igure 1. Typ ical Supply Current vs. Frequency
VCC = 5.5 V, T = 25°CFigure 2 . Typi c al Sup pl y Curr en t vs . Temp er ature
VCC = 5.5 V, f = 10 MHz
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –400 µA 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA 0.45 V
VIH Input HIGH Voltage 2.0 VCC + 0.5 V
VIL Input LOW Voltage –0.5 +0.8 V
ILI Input Load Current VIN = 0 V to VCC 1.0 µA
ILO Output Leakage Current VOUT = 0 V to VCC 5.0 µA
ICC1 VCC Active Current (Note 2) CE# = VIL, f = 10 MHz,
IOUT = 0 mA 30 mA
ICC2 VCC TTL Standby Current CE# = VIH 1.0 mA
ICC3 VCC CMOS Standby Current CE# = VCC ± 0.3 V 100 µA
15652D-5
12345678910
30
25
20
15
10
Frequency in MHz
Supply Current
in mA
15652D-6
–75 –50 –55 0 25 50 75 100 125 150
30
25
20
15
10
Temperature in °C
Supply Current
in mA
Am27X020 7
TES T CONDITIONS
Table 1. Test Specifications
SWITCHING TEST WAVE FORM
KEY TO SWITCHIN G WAVE FORMS
2.7 kΩ
CL6.2 kΩ
5.0 V
Device
Under
Test
15652D-7
Figure 3. Test Setup
Note:
Diodes are IN3064 or equivalents.
Test Condition All Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 100 pF
Input Rise and Fall Times ≤ 20 ns
Input Pulse Levels 0.45–2.4 V
Input timing measurement reference
levels 0.8, 2.0 V
Output timing measurement
reference levels 0.8, 2.0 V
2.4 V
0.45 V Input Output
Test Points
2.0 V 2.0 V
0.8 V0.8 V
15652D-8
Note: For C
L
= 100 pF.
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
8Am27X020
AC CHARACTERISTICS
Caution: Do not remove the device from (or insert it into) a socket or board that has V
PP
or V
CC
applied.
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WA VEF ORMS
Notes:
1. OE# may be delayed up to t
ACC
– t
OE
after the falling edge of the addresses without impact on t
ACC
.
2. t
DF
is specified from OE# or CE#, whichever occurs first.
P ACKAGE CAPACITANCE
Notes:
1. This parameter is only sampled and not 100% tested.
2. T
A
= +25
°
C, f = 1 MHz.
Parameter Symbols
Description Test Setup
Am27X020
UnitJEDEC Standard -75 -90 -120 -150 -200 -255
tAVQV tACC Address to Output Delay CE#,
OE# = VIL Max 70 90 120 150 200 250 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 150 200 250 ns
tGLQV tOE Output Enable to Output
Delay CE# = VIL Max 40 50 50 65 75 100 ns
tEHQZ
tGHQZ
tDF
(Note 2)
Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First Max253030304060ns
t
AXQX tOH
Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First Min000000ns
Addresses
CE#
OE#
Output 15652D-9
Addresses Valid
High Z High Z
tCE
Valid Output
2.4
0.45
2.0
0.8 2.0
0.8
tACC
(Note 1)
tOE tDF (Note 2)
tOH
Parameter
Symbol Parameter Description Test Conditions
PD 032 PL 032
UnitTyp Max Typ Max
CIN Input Capacitance VIN = 0 10 12 8 10 pF
COUT Output Capacitance VOUT = 0 12 15 9 12 pF
Am27X020 9
PHY SICAL DIMENSIONS
PD 032—32-Pin Plastic Dual In-Line Packag e (measured in inches)
PL 032—32-Pin Plastic L eaded Chip Carrier (measured in inches)
Pin 1 I.D.
1.640
1.680
.530
.580
.005 MIN
.045
.065
.090
.110
.140
.225
.120
.160 .014
.022
SEATING PLANE
.015
.060
16-038-SB_AG
PD 032
DG75
2-28-95 ae
32 17
16 .630
.700
0˚
10˚
.600
.625
.008
.015
.050 REF.
.026
.032 TOP VIEW
Pin 1 I.D.
.485
.495
.447
.453
.585
.595
.547
.553
16-038FPO-5
PL 032
DA79
6-28-94 ae
SIDE VIEW
SEATING
PLANE
.125
.140
.009
.015
.080
.095
.042
.056
.013
.021
.400
REF. .490
.530
10 Am27X020
REVIS ION SUMMARY FOR AM27X020
Revisio n D
Global
Changed formatting to match current data sheets.
Absolute Maximum Ratings
Storage Temperature
: Removed “All Other Products ...
–65°C to +150°C”.
Revisio n D+1 (March 5, 1999)
Ordering Informati on
The 70 ns speed option now has VCC = 5.0V±10% de-
vice and is indicated in the OPN b y a -70.
Trademarks
Copyright © 1999 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Ad vanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
