REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD10465
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Dual Channel, 14-Bit, 65 MSPS A/D Converter
with Analog Input Signal Conditioning
FEATURES
Dual, 65 MSPS Minimum Sample Rate
Channel-to-Channel Matching, ⴞ0.5% Gain Error
Channel-to-Channel Isolation, >90 dB
DC-Coupled Signal Conditioning Included
Selectable Bipolar Input Voltage Range
(ⴞ0.5 V, ⴞ1.0 V, ⴞ2.0 V)
Gain Flatness up to 25 MHz: < 0.2 dB
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
1.75 W per Channel
Industrial and Military Grade
APPLICATIONS
Phased Array Receivers
Communications Receivers
FLIR Processing
Secure Communications
GPS Antijamming Receivers
Multichannel, Multimode Receivers
FUNCTIONAL BLOCK DIAGRAM
VREF
DROUT
OUTPUT BUFFERING
TIMING
A
IN
A3 A
IN
A2 A
IN
A1 REF A
3
11
14
VREF
DROUT
A
IN
B2 A
IN
B1
14
A
IN
B3
ENC
ENC D11A D12A D13A (MSB)
OUTPUT BUFFERING
D0B (LSB) D1B D3BD2B D4B D5B D6B D7B D8B
TIMING
D9B
9
5
ENC
ENC
DRBOUT
D10B
D11B
D12B
D13B
REF B
D0A (LSB)
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
AD10465
DRAOUT
PRODUCT DESCRIPTION
The AD10465 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and fully
matched channel-to-channel performance. The module includes
two wide dynamic range AD6644 ADCs. Each AD6644 has a dc-
coupled amplifier front end including an AD8037 low distortion,
high bandwidth amplifier, providing a high input impedance
and gain, and driving the AD8138 single-to-differential ampli-
fier. The AD6644s have on-chip track-and-hold circuitry and
utilize an innovative multipass architecture to achieve 14-bit,
65 MSPS performance. The AD10465 uses innovative high-
density circuit design and laser-trimmed thin-film resistor networks
to achieve exceptional matching and performance, while still
maintaining excellent isolation and providing for significant
board area savings.
The AD10465 operates with ±5.0 V for the analog signal condi-
tioning with a separate 5.0 V supply for the analog-to-digital
conversion and 3.3 V digital supply for the output stage. Each
channel is completely independent, allowing operation with
independent encode and analog inputs. The AD10465 also
offers the user a choice of analog input signal ranges to fur-
ther minimize additional external signal conditioning, while
still remaining general-purpose.
The AD10465 is packaged in a 68-lead Ceramic Gull Wing
package, footprint-compatible with the earlier generation AD10242
(12-bit, 40 MSPS) and AD10265 (12-bit, 65 MSPS). Manufac-
turing is done on Analog Devices, Inc. Mil-38534 Qualified
Manufacturers Line (QML) and components are available up to
Class-H (–40°C to +85°C). The AD6644 internal components
are manufactured on Analog Devices, Inc. high-speed comple-
mentary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 65 MSPS.
2. Input amplitude options, user configurable.
3. Input signal conditioning included; both channels matched
for gain.
4. Fully tested/characterized performance.
5. Footprint compatible family; 68-lead LCC.
REV. 0
–2–
AD10465–SPECIFICATIONS
Test Mil AD10465AZ/BZ/QML-H
Parameter Temp Level Subgroup Min Typ Max Unit
RESOLUTION 14 Bits
DC ACCURACY
No Missing Codes Full VI 1, 2, 3 Guaranteed
Offset Error 25°C I 1 –2.2 ±0.02 +2.2 % FS
Full VI 2, 3 –2.2 ±1.0 +2.2 % FS
Offset Error Channel Match Full V –1 ±1.0 +1 %
Gain Error
1
25°C I 1 –3 –1.0 +1 % FS
Full VI 2, 3 –5 ±2.0 +5 % FS
Gain Error Channel Match 25°C I 1 –1.5 ±0.5 +1.5 %
Max I 2 –3 ±1.0 +3 %
Min I 3 –5 +5 %
ANALOG INPUT (A
IN
)
Input Voltage Range
A
IN
1 Full V ±0.5 V
A
IN
2 Full V ±1.0 V
A
IN
3 Full V ±2V
Input Resistance
A
IN
1 Full IV 12 99 100 101 Ω
A
IN
2 Full IV 12 198 200 202 Ω
A
IN
3 Full IV 12 396 400 404 Ω
Input Capacitance
2
25°C IV 12 0 4.0 7.0 pF
Analog Input Bandwidth
3
Full V 100 MHz
ENCODE INPUT (ENC, ENC)
4
Differential Input Voltage
17
Full IV 0.4 V p-p
Differential Input Resistance 25°CV 10 kΩ
Differential Input Capacitance 25°C V 2.5 pF
SWITCHING PERFORMANCE
Maximum Conversion Rate
5
Full VI 4, 5, 6 65 MSPS
Minimum Conversion Rate
5
Full V 12 20 MSPS
Aperture Delay (t
A
)25°C V 1.5 ns
Aperture Delay Matching 25°C IV 12 250 500 ps
Aperture Uncertainty (Jitter) 25°C V 0.3 ps rms
ENCODE Pulsewidth High 25°C IV 12 6.2 7.7 9.2 ns
ENCODE Pulsewidth Low 25°C IV 12 6.2 7.7 9.2 ns
Output Delay (t
OD
) Full V 6.8 ns
Encode, Rising to Data Ready, Rising Delay (T
E_DR
) Full 11.5 ns
SNR
6
Analog Input @ 4.98 MHz 25°C V 70 dBFS
Analog Input @ 9.9 MHz 25°C I 4 69 70 dBFS
Full II 5, 6 68 70 dBFS
Analog Input @ 19.5 MHz 25°C I 4 68 70 dBFS
Full II 5, 6 67 70 dBFS
Analog Input @ 32.1 MHz 25°C I 4 67 69 dBFS
Full II 5, 6 67 69 dBFS
SINAD
7
Analog Input @ 4.98 MHz 25°CV 70 dB
Analog Input @ 9.9 MHz 25°C I 4 67.5 69 dB
Full II 5, 6 67.5 69 dB
Analog Input @ 19.5 MHz 25°CI 4 65 68 dB
Full II 5, 6 65 68 dB
Analog Input @ 32.1 MHz 25°CI 4 60 63 dB
Full II 5, 6 58 61 dB
(AVCC = +5 V; AVEE = –5 V; DVCC = 3.3 V applies to each ADC unless otherwise noted.)
REV. 0 –3–
AD10465
Test Mil AD10465AZ/BZ/QML-H
Parameter Temp Level Subgroup Min Typ Max Unit
SPURIOUS-FREE DYNAMIC RANGE
8
Analog Input @ 4.98 MHz 25°C V 85 dBFS
Analog Input @ 9.9 MHz 25°C I 4 73 82 dBFS
Full II 5, 6 70 82 dBFS
Analog Input @ 19.5 MHz 25°C I 4 72 78 dBFS
Full II 5, 6 70 78 dBFS
Analog Input @ 32.1 MHz 25°C I 4 62 68 dBFS
Full II 5, 6 60 66 dBFS
TWO-TONE IMD REJECTION
9
f
IN
= 10 MHz and 11 MHz 25°C I 4 78 87 dBFS
f
1
and f
2
are –7 dB II 5, 6 78
f
IN
= 31 MHz and 32 MHz 25°C I 4 68 70 dBFS
f
1
and f
2
Are –7 dB Full II 5, 6 60
CHANNEL-TO-CHANNEL ISOLATION
10
25°CIV 12 90 dB
TRANSIENT RESPONSE 25°C V 15.3 ns
OVERVOLTAGE RECOVERY TIME
11
VIN = 2.0 × f
S
Full IV 12 40 100 ns
VIN = 4.0 × f
S
Full IV 12 150 200 ns
DIGITAL OUTPUTS
12
Logic Compatibility CMOS
DV
CC
= 3.3 V
Logic “1” Voltage Full I 1, 2, 3 2.5 DV
CC
– 0.2 V
Logic “0” Voltage Full I 1, 2, 3 0.2 0.5 V
DV
CC
= 5 V
Logic “1” Voltage Full V DV
CC
– 0.3 V
Logic “0” Voltage Full V 0.35 V
Output Coding Two’s Complement
POWER SUPPLY
AV
CC
Supply Voltage
13
Full VI 4.85 5.0 5.25 V
I (AV
CC
) Current Full I 270 308 mA
AV
EE
Supply Voltage
13
Full VI –5.25 –5.0 –4.75 V
I (AV
EE
) Current Full V 38 49 mA
DV
CC
Supply Voltage
13
Full VI 3.135 3.3 3.465 V
I (DV
CC
) Current Full V 30 46 mA
I
CC
(Total) Supply Current per Channel Full I 1, 2, 3 338 403 mA
Power Dissipation (Total) Full I 1, 2, 3 3.5 3.9 W
Power Supply Rejection Ratio (PSRR) Full V 0.02 % FSR/% V
S
Passband Ripple to 10 MHz V 0.1 dB
Passband Ripple to 25 MHz V 0.2 dB
NOTES
1
Gain tests are performed on A
IN
1 input voltage range.
2
Input Capacitance spec. combines AD8037 die capacitance and ceramic package capacitance.
3
Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
All ac specifications tested by driving ENCODE and ENCODE differentially.
5
Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.
6
Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR
is reported in dBFS, related back to converter full power.
7
Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.
8
Analog input signal power swept from –1 dBFS to –60 dBFS; SFDR is ratio of converter full scale to worst spur.
9
Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.
10
Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.
11
Input driven to 2× and 4× A
IN
1 range for > four clock cycles. Output recovers inband in specified time with Encode = 65 MSPS.
12
Digital output logic levels: DV
CC
= 3.3 V, C
LOAD
= 10 pF. Capacitive loads > 10 pF will degrade performance.
13
Supply voltage recommended operating range. AV
CC
may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AV
CC
= 5.0 V to 5.25 V.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
REV. 0
AD10465
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10465 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Parameter Min Max Units
ELECTRICAL
V
CC
Voltage 0 7 V
V
EE
Voltage –7 0 V
Analog Input Voltage V
EE
V
CC
V
Analog Input Current –10 +10 mA
Digital Input Voltage (ENCODE) 0 V
CC
V
ENCODE, ENCODE Differential Voltage 4 V
Digital Output Current –10 +10 mA
ENVIRONMENTAL
2
Operating Temperature (Case) –40 +85 °C
Maximum Junction Temperature 174 °C
Lead Temperature (Soldering, 10 sec) 300 °C
Storage Temperature Range (Ambient) –65 +150 °C
NOTES
1
Absolute maximum ratings are limiting values applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.
2
Typical thermal impedance for “ES” package: θ
JC
= 2.2°C/W; θ
JA
= 24.3°C/W.
TEST LEVEL
I. 100% Production Tested.
II. 100% Production Tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III. Sample Tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at temperature at 25°C, sample
tested at temperature extremes.
ORDERING GUIDE
Model Temperature Range Package Description
AD10465AZ –25°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier
AD10465BZ –40°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier
5962-9961601HXA –40°C to +85°C (Case) 68-Lead Ceramic Leaded Chip Carrier
AD10465/PCB 25°C Evaluation Board with AD10465AZ
REV. 0
AD10465
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
1 SHIELD Internal Ground Shield between channels.
2, 4, 5, 9–11 AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device
as possible.
3 REF_A A Channel Internal Voltage Reference.
6A
IN
A1 Analog Input for A side ADC (nominally ±0.5 V).
7A
IN
A2 Analog Input for A side ADC (nominally ±1.0 V).
8A
IN
A3 Analog Input for A side ADC (nominally ±2.0 V).
12 DRAOUT Data Ready A Output.
13 AV
EE
Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V).
14 AV
CC
Analog Positive Supply Voltage (nominally 5.0 V).
26, 27 DGNDA A Channel Digital Ground.
15–25, 31–33 D0A–D13A Digital Outputs for ADC A. D0 (LSB).
28 ENCODEA ENCODE is complement of ENCODE.
29 ENCODEA Data conversion initiated on rising edge of ENCODE input.
30 DV
CC
Digital Positive Supply Voltage (nominally 5.0 V/3.3 V).
43, 44 DGNDB B Channel Digital Ground.
34–42, 45–49 D0B-D13B Digital Outputs for ADC B. D0 (LSB).
53–54, 57–61, 65, 68 AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device
as possible.
50 DV
CC
Digital Positive Supply Voltage (nominally 5.0 V/3.3 V).
51 ENCODEB Data conversion initiated on rising edge of ENCODE input.
52 ENCODEB ENCODE is complement of ENCODE.
55 DRBOUT Data Ready B Output.
56 REF_B B Channel Internal Voltage Reference.
62 A
IN
B1 Analog Input for B side ADC (nominally ±0.5 V).
63 A
IN
B2 Analog Input for B side ADC (nominally ±1.0 V).
64 A
IN
B3 Analog Input for B side ADC (nominally ±2.0 V).
66 AV
CC
Analog Positive Supply Voltage (nominally –5.0 V).
67 AV
EE
Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V). .
PIN CONFIGURATION
68-Lead Ceramic Leaded Chip Carrier
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
21
27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42
9618765 686766656463624321
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD10465
AGNDB
AGNDB
AGNDB
AGNDB
REF B
DRBOUT
AGNDB
D12A
DGNDA
ENCODEA
ENCODEA
DV
CC
D11A
D13A(MSBA)
AGNDA
AGNDA
DRAOUT
AV
EE
D0A(LSBA)
D1A
D2A
D3A
D4A
D5A
AGNDB
ENCODEB
ENCODEB
DV
CC
D0B(LSBB)
D1B
D2B
D3B
AGNDA
AGNDA
A
IN
A3
AGNDA
AGNDA
REF A
AV
EE
A
IN
B3
AV
CC
AGNDB
AGNDB
A
IN
A1
A
IN
A2
AGNDB
SHIELD
A
IN
B1
A
IN
B2
D4B
D5B
D6B
D7B
D8B
DGNDB
D6A
D7A
D8A
D9A
D10A
DGNDA
D13B(MSBB)
D12B
D11B
D10B
D9B
DGNDB
AV
CC
REV. 0
FREQUENCY – MHz
–130 02.5
dB
ENCODE = 65MSPS
A
IN
= 5MHz (–1dBFS)
SNR = 71.02
SFDR = 92.11dBc
5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
6
23
45
TPC 1. Single Tone @ 5 MHz
FREQUENCY – MHz
–130 02.5
dB
ENCODE = 65MSPS
AIN = 20MHz (–1dBFS)
SNR = 70.71
SFDR = 79.73dBc
5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
6
2
3
4
5
TPC 2. Single Tone @ 20 MHz
FREQUENCY – MHz
–130 02.5
dB
ENCODE = 65MSPS
AIN = 32MHz (–1dBFS)
SNR = 70.22
SFDR = 66.40dBc
5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
6
23
4
5
TPC 3. Single Tone @ 32 MHz
AD10465–Typical Performance Characteristics
–6–
FREQUENCY – MHz
–130 02.5
dB
ENCODE = 65MSPS
AIN = 10MHz (–1dBFS)
SNR = 70.79
SFDR = 86.06dBc
5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
6
23
4
5
TPC 4. Single Tone @ 10 MHz
FREQUENCY – MHz
–130 02.5
dB
ENCODE = 65MSPS
AIN = 25MHz (–1dBFS)
SNR = 70.36
SFDR = 74.58dBc
5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
6
2
3
4
5
TPC 5. Single Tone @ 25 MHz
INPUT FREQUENCY – MHz
4.989
–dBc
0
10
20
30
40
50
60
70
80
90
100
SFDR
SINAD
9.989 19.000 32.000
TPC 6. SFDR and SINAD vs. Frequency
REV. 0
AD10465
–7–
FREQUENCY – MHz
–130 02.5
dB
ENCODE = 65MSPS
AIN = 9MHz AND
10MHz (–7dBFS)
SFDR = 82.83dBc
5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
F2–
F1
F1+
F2
2F1–
F2
2F2–
F1
2F1+
F2
2F2+
F1
TPC 7. Two Tone @ 9/10 MHz
–1.0
02048
LSB
ENCODE = 65MSPS
DNL MAX = +0.549 CODES
DNL MIN = –0.549 CODES
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
4096 6144 8192 10240 12288 14336 16384
TPC 8. Differential Nonlinearity
FREQUENCY – MHz
1.0 4.2
dBFS
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
7.4 10.6 13.8 17.0 20.2 23.4 26.6 29.8 33.0
TPC 9. Gain Flatness
FREQUENCY – MHz
–130 02.5
dB
ENCODE = 65MSPS
AIN = 17MHz AND
18MHz (–7dBFS)
SFDR = 77.68dBc
5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
F2–
F1
F1+
F2
2F1+
F2
2F2+
F1 2F1–
F2 2F2–
F1
TPC 10. Two Tone @ 17/18 MHz
–3.0
02048
LSB
ENCODE = 65MSPS
INL MAX = +1.173 CODES
INL MIN = –1.332 CODES
–2.0
0
2.0
3.0
4096 6144 8192 10240 12288 14336 16384
1.0
–1.0
TPC 11. Integral Nonlinearity
A
IN
– MHz
5
SNRFS
67.5
68.0
68.5
69.0
69.5
70.0
70.5
71.0
71.5
72.0
+25
ⴗ
C
10 19 32
–40
ⴗ
C
+85
ⴗ
C
TPC 12. SNR vs. A
IN
Frequency
REV. 0
AD10465
–8–
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable Encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed,
above which converter performance may degrade.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power
supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc. May be reported
in dB (i.e., relative to signal level) or in dBFS (always related
back to converter full scale).
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc. May be reported
in dB (i.e., relative to signal level) or in dBFS (always related
back to converter full scale).
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic.
Transient Response
The time required for the converter to achieve 0.03% accu-
racy when a one-half full-scale step function is applied to the
analog input.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBFS.
t
A
AIN
ENC, ENC
D[13:0]
DRY
N
N+1
N+2
N+3
N+4
NN+1 N+2 N+3 N+4
N–3N–2N–1N
t
ENCL
t
ENCH
t
ENC
t
E, DR
t
OD
Figure 1. Timing Diagram
REV. 0
AD10465
–9–
CURRENT MIRROR
DR OUT
DVCC
VREF
CURRENT MIRROR
DVCC
Figure 4. Digital Output Stage
CURRENT MIRROR
D0–D13
DV
CC
V
REF
CURRENT MIRROR
DV
CC
100⍀
Figure 5. Digital Output Stage
AV
IN
3
AV
IN
2
AV
IN
1
200⍀
100⍀
100⍀
TO AD8037
Figure 2. Analog Input Stage
LOADS
LOADS
10k⍀
10k⍀
ENCODE
AV CC
AV CC
10k⍀
10k⍀
ENCODE
AV CC
AV CC
Figure 3. ENCODE Inputs
THEORY OF OPERATION
The AD10465 is a high dynamic range 14-bit, 65 MHz pipeline
delay (three pipelines) analog-to-digital converter. The custom
analog input section maintains the same input ranges (1 V p-p,
2 V p-p, and 4 V p-p) and input impedance (100 Ω, 200 Ω, and
400 Ω) as the AD10242.
The AD10465 employs four monolithic ADI components per
channel (AD8037, AD8138, AD8031, and AD6644), along with
multiple passive resistor networks and decoupling capacitors to
fully integrate a complete 14-bit analog-to-digital converter.
The input signal is passed through a precision laser-trimmed
resistor divider allowing the user to externally select operation
with a full-scale signal of ±0.5 V, ±1.0 V or ±2.0 V by choosing
the proper input terminal for the application.
The AD10465 analog input includes an AD8037 amplifier
featuring an innovative architecture that maximizes the dynamic
range capability on the amplifiers inputs and outputs. The AD8037
amplifier provides a high input impedance and gain for driving
the AD8138 in a single-ended to differential amplifier configu-
ration. The AD8138 has a –3 dB bandwidth at 300 MHz and
delivers a differential signal with the lowest harmonic distortion
available in a differential amplifier. The AD8138 differential
outputs help balance the differential inputs to the AD6644,
maximizing the performance of the ADC.
The AD8031 provides the buffer for the internal reference of
the AD6644. The internal reference voltage of the AD6644 is
designed to track the offsets and drifts of the ADC and is used
to ensure matching over an extended temperature range of
operation. The reference voltage is connected to the output
common mode input on the AD8138. The AD6644 reference
voltage sets the output common-mode on the AD8138 at 2.4 V,
which is the midsupply level for the AD6644.
The AD6644 has complementary analog input pins, AIN and AIN.
Each analog input is centered at 2.4 V and should swing ±0.55 V
around this reference. Since AIN and AIN are 180 degrees out
of phase, the differential analog input signal is 2.2 V peak-to-peak.
Both analog inputs are buffered prior to the first track-and-hold,
TH1. The high state of the ENCODE pulse places TH1 in hold
mode. The held value of TH1 is applied to the input of a 5-bit
coarse ADC1. The digital output of ADC1 drives 14 bits of
precision which is achieved through laser trimming. The output
of DAC1 is subtracted from the delayed analog signal at the
input of TH3 to generate a first residue signal. TH2 provides an
analog pipeline delay to compensate for the digital delay of ADC1.
The first residue signal is applied to a second conversion stage
consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4.
The second DAC requires 10 bits of precision which is met by
the process with no trim. The input to TH5 is a second residue
signal generated by subtracting the quantized output of DAC2
from the first residue signal held by TH4. TH5 drives a final
6-bit ADC3.
The digital outputs from ADC1, ADC2, and ADC3 are added
together and corrected in the digital error correction logic to
generate the final output data. The result is a 14-bit parallel
digital CMOS-compatible word, coded as two’s complement.
USING THE FLEXIBLE INPUT
The AD10465 has been designed with the user’s ease of opera-
tion in mind. Multiple input configurations have been included
on board to allow the user a choice of input signal levels and
input impedance. While the standard inputs are ±0.5 V, ±1.0 V
and ±2.0 V, the user can select the input impedance of the
REV. 0
AD10465
–10–
AD10465 on any input by using the other inputs as alternate
locations for GND or an external resistor. The following chart
summarizes the impedance options available at each input
location:
A
IN
1 = 100 Ω when A
IN
2 and A
IN
3 are open.
A
IN
1 = 75 Ω when A
IN
3 is shorted to GND.
A
IN
1 = 50 Ω when A
IN
2 is shorted to GND.
A
IN
2 = 200 Ω when A
IN
3 is open.
A
IN
2 = 100 Ω when A
IN
3 is shorted to GND.
A
IN
2 = 75 Ω when A
IN
2 to A
IN
3 has an external resistor of
300 Ω, with A
IN
3 shorted to GND.
A
IN
2 = 50 Ω when A
IN
2 to A
IN
3 has an external resistor of
100 Ω, with A
IN
3 shorted to GND.
A
IN
3 = 400 Ω.
A
IN
3 = 100 Ω when A
IN
3 has an external resistor of 133 Ω to
GND.
A
IN
3 = 75 Ω when A
IN
3 has an external resistor of 92 Ω to
GND.
A
IN
3 = 50 Ω when A
IN
3 has an external resistor of 57 Ω to
GND.
APPLYING THE AD10465
Encoding the AD10465
The AD10465 encode signal must be a high quality, extremely
low phase noise source, to prevent degradation of performance.
Maintaining 14-bit accuracy places a premium on encode clock
phase noise. SNR performance can easily degrade by 3 dB to
4 dB with 32 MHz input signals when using a high-jitter clock
source. See Analog Devices’ Application Note AN-501, “Aper-
ture Uncertainty and ADC System Performance” for complete
details. For optimum performance, the AD10465 must be clocked
differentially. The encode signal is usually ac-coupled into the
ENCODE and ENCODE pins via a transformer or capacitors.
These pins are biased internally and require no additional bias.
Shown below is one preferred method for clocking the AD10465.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD10465 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD10465, and limits the
noise presented to the ENCODE inputs. A crystal clock oscillator
can also be used to drive the RF transformer if an appropriate
limiting resistor (typically 100 Ω) is placed in the series with
the primary.
T1-4T100⍀
0.1nF
ENCODE
ENCODE
AD10465
HSMS2812
DIODES
CLOCK
SOURCE
Figure 6. Crystal Clock Oscillator, Differential Encode
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter perfor-
mance is the MC100LVEL16 (or same family) from Motorola.
ENCODE
ENCODE
AD10465
0.1␮F
ECL/
PECL
VT
VT
0.1␮F
Figure 7. Differential ECL for Encode
Jitter Considerations
The signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, Equation 1 accurately predicts
the SNR based on three terms. These are jitter, average DNL
error, and thermal noise. Each of these terms contributes to the
noise within the converter.
SNR f t rms
V
N
ANALOG
NOISE RMS
N
=− ×
+
+
×× ×
()
+
20
1
2
2
2
2
2
12
log
/
ε
π
J
(1)
f
ANALOG
=analog input frequency.
t
J RMS
= rms jitter of the encode (rms sum of encode
source and internal encode circuitry).
ε= average DNL of the ADC (typically 0.50 LSB).
N= Number of bits in the ADC.
V
NOISE RMS
= V rms noise referred to the analog input of the
ADC (typically 5 LSB).
For a 14-bit analog-to-digital converter like the AD10465, aper-
ture jitter can greatly affect the SNR performance as the analog
frequency is increased. The chart below shows a family of curves
that demonstrates the expected SNR performance of the AD10465
as jitter increases. The chart is derived from the above equation.
For a complete discussion of aperture jitter, please consult
Analog Devices’ Application Note AN-501, “Aperture Uncer-
tainty and ADC System Performance.”
RMS CLOCK JITTER – ps
0.1
SNR – dBFS
60
AIN = 5MHz
AIN = 10MHz
AIN = 20MHz
AIN = 32MHz
0.3
0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7
0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 3.9
61
62
63
64
65
66
67
68
69
70
71
Figure 8. SNR vs. Jitter
REV. 0
AD10465
–11–
Power Supplies
Care should be taken when selecting a power source. Linear
supplies are strongly recommended. Switching supplies tend
to have radiated components that may be “received” by the
AD10465. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 µF chip capacitors.
The AD10465 has separate digital and analog power supply
pins. The analog supplies are denoted AV
CC
and the digital
supply pins are denoted DV
CC
. AV
CC
and DV
CC
should be
separate power supplies. This is because the fast digital output
swings can couple switching current back into the analog sup-
plies. Note that AV
CC
must be held within 5% of 5 V. The
AD10465 is specified for DV
CC
= 3.3 V as this is a common
supply for digital ASICs.
Output Loading
Care must be taken when designing the data receivers for the
AD10465. The digital outputs drive an internal series resistor
(e.g., 100 Ω) followed by a gate like 75LCX574. To minimize
capacitive loading, there should only be one gate on each output
pin. An example of this is shown in the evaluation board sche-
matic shown in Figure 10. The digital outputs of the AD10465
have a constant output slew rate of 1 V/ns. A typical CMOS
gate combined with a PCB trace will have a load of approxi-
mately 10 pF. Therefore, as each bit switches, 10 mA (10 pF ×
1V, ÷ 1 ns) of dynamic current per bit will flow in or out of the
device. A full-scale transition can cause up to 140 mA (14 bits ×
10 mA/bit) of current flow through the output stages. These
switching currents are confined between ground and the DV
CC
pin. Standard TTL gates should be avoided since they can
appreciably add to the dynamic switching currents of the AD10465.
It should also be noted that extra capacitive loading will increase
output timing and invalidate timing specifications. Digital out-
put timing is guaranteed with 10 pF loads.
LAYOUT INFORMATION
The schematic of the evaluation board (Figure 10) represents a
typical implementation of the AD10465. The pinout of the
AD10465 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design
practices. It is recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high quality ceramic
chip capacitors.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.
EVALUATION BOARD
The AD10465 evaluation board (Figure 9) is designed to pro-
vide optimal performance for evaluation of the AD10465 analog-
to-digital converter. The board encompasses everything needed
to insure the highest level of performance for evaluating the
AD10465. The board requires an analog input signal, encode
clock and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and clocks
are available at the standard 40-pin connectors J1 and J2.
Power to the analog supply pins is connected via banana jacks. The
analog supply powers the associated components and the analog
section of the AD10465. The digital outputs of the AD10465
are powered via banana jacks with 3.3 V. Contact the factory if
additional layout or applications assistance is required.
Figure 9a. Evaluation Board Mechanical Layout
REV. 0
AD10465
–12–
U1
AD10465
DRAOUT
AGNDA
DGNDA DGNDB
L10
47
L7
47
C22
10␮F
–5.2VAA
C53
10␮F
+5VAA
AGNDB
DRBOUT
C61
0.1␮F
AGNDB
+3.3VDB
C58
10␮F
L6
47
C64
0.1␮F
DGNDB
L9
47
C59
10␮F
–5.2VAB
C57
0.1␮F
AGNDA
AGNDA
AGNDB
C52
10␮F
AGNDB
L8
47
47⍀
AT 100MHz
C63
0.1␮F
L11
47
C62
10␮F
DGNDA
DGNDA
+3.3VDA
47⍀
AT 100MHz
47⍀
AT 100MHz
AGNDA
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
AGNDB
AGNDB
AGNDB
AGNDB
REFB
DRBOUT
AGNDB
AGNDB
ENCBB
ENCB
+3.3VDB
D13B(MSB)
D12B
D11B
D10B
D9B
DGNDB
ENCBB
ENCB
DUT 3.3VDB
D13B(MSB)
D12B
D11B
D10B
D9B
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
AGNDA
AINA3
AINA2
AINA1
AGNDA
AGNDA
REFA
AGNDA
SHIELD
AGNDB
–5.2VAB
+5VAB
AGNDB
AINB3
AINB2
AINB1
AGNDB
+5VAB
AINB3
AINB2
AINB1
AINA3
AINA2
AINA1
AGNDA
AGNDA
DRAOUT
–5.2VAA
+5VAA
D0A(LSB)
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8B
D9A
D10A
DGNDA
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DGNDA
ENCAB
ENCA
+3.3VDA
D11A
D12A
D13A(MSB)
D0B(LSB)
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
DGNDB
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
ENCAB
ENCA
DUT 3.3VDA
D11A
D12A
D13A
DB0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
+5VAA
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8B
D9A
D10A
+5VAB
AINB3
J1
AGNDB
AINB2
J2
AGNDB
AINB1
J22
AGNDB
AINA3
J7
AGNDA
AINA2
J8
AGNDA
AINA1
J20
AGNDA
DUT 3.3VDB
C26
0.1␮F
DGNDB
DGNDB
SPARE
GATE
U2:C
DUT 3.3VDA
C27
0.1␮F
DGNDA
DGNDA
SPARE
GATE
U4:C
10
9
10
9
88
74LCX00M74LCX00M
U2:A
1
2
JP5
3
U2:D
13
12
11
U2:B
4
56
JP1 BUFLATB
LATCHB
JP3
JP4
U4:A
1
23
U4:D
12 11
U4:B
4
56
13
74LCX00M 74LCX00M 74LCX00M
74LCX00M 74LCX00M 74LCX00M JP2 BUFLATA
CLKLATCHB2
CLKLATCHB1
DRBOUT
DRAOUT
CLKLATCHA2
CLKLATCHA1
JP6
LATCHA
Figure 9b. Evaluation Board
REV. 0
AD10465
–13–
J18
AGNDA
R83
51⍀
C40
0.1␮F
AGNDA
J6
AGNDA
R82
51⍀
C42
0.1␮F
AGNDA
JP8
JP11
OPEN
ENCODEA
E
NCODEA
NC = NO CONNECT
VCC
Q
Q
VEE
NC
D
D
VBB
U7
MC10EP16D
AGNDA
1
2
3
4
8
7
6
5
OUT
NR
IN
SD
U6
AGNDA
2
6
1
8
ERR 3
+5VAA
C45
100pF
GND
AGNDA
JP7
R140
33k⍀
4
+5VAA
C41
0.47␮F
AGNDA
R89
100⍀
AGNDA
R94
100⍀
C49
0.1␮F
C44
0.1␮F
ENCAB
ENCA
ADP3330
J17
AGNDB
R79
51⍀
C39
0.1␮F
AGNDB
J16
AGNDB
R76
51⍀
C37
0.1␮F
AGNDB
JP10
JP12
OPEN
ENCODEB
E
NCODEB
NC = NO CONNECT
VCC
Q
Q
VEE
NC
D
D
VBB
U9
MC10EP16D
AGNDB
1
2
3
4
8
7
6
5
OUT
NR
IN
SD
U8
AGNDB
2
6
1
8
ERR 3
+5VAA
C43
100pF
GND
AGNDB
JP9
R141
33k⍀
4
+5VAA
C38
0.47␮F
AGNDB
R95
100⍀
AGNDAB
R97
100⍀
C46
0.1␮F
C48
0.1␮F
ENCB
ENCBB
ADP3330
Figure 9c. Evaluation Board
REV. 0
AD10465
–14–
OUT 3.3VDA
C20
0.1␮F
C15
0.1␮F
C14
0.1␮F
C13
0.1␮F
DGNDA
E1
E2
E3
E4
E5
E6
E7
E8
E9
+5VAA
+5VAB
+3.3VDA
+3.3VDB
–5.2VAB
AGNDB
AGNDA
DGNDA
DGNDB
–5.2VAA
E10
U21
25
24
26
27
42
31
7
16
29
30
32
33
23
22
20
19
35
36
48
17
16
14
13
1
37
38
40
12
11
41
43
44
9
8
6
5
46
47
28
3
2
21
15
34
39 18
4
CP2
OE2
I15
I14
I10
I4
I0
45
I11
I12
I8
I13
I7
I6
I5
I1
I3
I2
GND
I9
O10
O7
O3
O0
GND
O6
O5
O4
O2
O1
GND
GND
GND
O9
O11
O12
O13
O14
O15
VCC
VCC
VCC
VCC
O8
CP1
OE1
GND
GND
GND
74LCX163743MTD
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D12A
(MSB) D13A
D11A
D10A
D9A
D8A
D7A
D6A
R99
0⍀
DGNDA
R100
0⍀
R98
51⍀
DGNDA
OUT 3.3VDA
21
22
23
24
25
26
27
28
29
30
31
32
35
36
37
38
39
40
33
34
21
22
23
24
25
26
27
28
29
30
31
32
35
36
37
38
39
40
33
34
20
19
18
17
16
15
14
13
12
11
10
9
6
5
4
3
2
1
8
7
20
19
18
17
16
15
14
13
12
11
10
9
6
5
4
3
2
1
8
7
R113
100⍀
R105
100⍀
R104
100⍀
R106
100⍀
R117
100⍀
R115
100⍀
R116
100⍀
R114
100⍀
DGNDA
R108
100⍀
R107
100⍀
R110
100⍀
R111
100⍀
R102
100⍀
R101
100⍀
R109
100⍀
R103
100⍀
J3
R118
51⍀
BUFLATA
LATCHA
MSB
OUT 3.3VDA
C24
0.1␮F
C23
0.1␮F
C21
0.1␮F
C25
0.1␮F
DGNDB
U22
25
24
26
27
42
31
7
16
29
30
32
33
23
22
20
19
35
36
48
17
16
14
13
1
37
38
40
12
11
41
43
44
9
8
6
5
46
47
28
3
2
21
1534
39 18
4
CP2
OE2
I15
I14
I10
I4
I0
45
I11
I12
I8
I13
I7
I6
I5
I1
I3
I2
GND
I9
O10
O7
O3
O0
GND
O6
O5
O4
O2
O1
GND
GND
GND
O9
O11
O12
O13
O14
O15
VCC
VCC
VCC
VCC
O8
CP1
OE1
GND
GND
GND
74LCX163743MTD
(LSB) D0B
D1B
D2B
D3B
D4B
D5B
D12B
(MSB) D13B
D11B
D10B
D9B
D8B
D7B
D6B
R124
0⍀
DGNDB
R123
0⍀
R119
51⍀
DGNDB
OUT 3.3VDB
21
22
23
24
25
26
27
28
29
30
31
32
35
36
37
38
39
40
33
34
21
22
23
24
25
26
27
28
29
30
31
32
35
36
37
38
39
40
33
34
20
19
18
17
16
15
14
13
12
11
10
9
6
5
4
3
2
1
8
7
20
19
18
17
16
15
14
13
12
11
10
9
6
5
4
3
2
1
8
7
R130
100⍀
R129
100⍀
R128
100⍀
R134
100⍀
R112
100⍀
R127
100⍀
R126
100⍀
R125
100⍀
DGNDB
R133
100⍀
R120
100⍀
R121
100⍀
R122
100⍀
R136
100⍀
R131
100⍀
R132
100⍀
R135
100⍀
J4
R137
51⍀
BUFLATB
LATCHB
MSB
E162
E163
E164
E165
E166
E171
E172
E177
E179
E181
E186
E187
E207
E209
E211
E213
E215
E217
E219
E221
E227
E229
E231
E233
E159
E160
E161
E167
E168
E169
E170
E178
E180
E182
E183
E191
E192
E193
E208
E210
E212
E214
E216
E218
E220
E222
E228
E230
E232
E234
DGNDB
AGNDB
E89
E139
E143
E146
E148
E149
E152
E153
E184
E188
E189
E190
E195
E197
E199
E201
E203
E205
E224
E226
E87
E88
E72
E140
E141
E142
E144
E145
E147
E150
E151
E154
E185
E194
E196
E198
E200
E202
E204
E206
E223
E225
DGNDA AGNDA
BANANA JACKS FOR GNDS AND PWRS
Figure 9d. Evaluation Board
REV. 0
AD10465
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Bill of Materials List for AD10465 Evaluation Board
Reference Manufacturer and Component
Qty Designator Value Description Part Number Name
2 U2, U4 IC, Low-Voltage Quad 2-Input Nand, SOIC-14 Toshiba/TC74LCX00FN 74LCX00M
2 U21, U22 IC, 16-Bit Transparent Latch with Three-State Fairchild/74LCX163743MTD 74LCX163743MTD
Outputs, TSSOP-48
1 U1 DUT, IC 14-Bit Analog-to-Digital Converter ADI/AD10465AZ ADI/AD10465AZ
2 U6, U8 IC, Voltage Regulator 3.3 V, RT-6 Analog Devices/ADP3330ART-3, ADP3330
3-RLT
10 E1–E10 Banana Jack, Socket Johnson Components/08-0740-001 Banana Hole
22 C13–C15, 0.1 µF Capacitor, 0.1 µF, 20%, 12 V dc, 0805 Mena/GRM40X7R104K025BL CAP 0805
C20, C21,
C23–C27,
C37, C39, C40,
C42, C44, C46,
C48, C49, C57,
C61, C63, C64
2 C38, C41 0.47 µF Capacitor, 0.47 µF, 5%, 12 V dc, 1206 Vitramon/VJ1206U474MFXMB CAP 1206
2 C43, C45 100 pF Capacitor, 100 pF, 10%, 12 V dc, 0805 Johansen/500R15N101JV4 CAP 0805
2 J3, J4 Connector, 40-pin Header Male St. Samtec/TSW-120-08-G-D HD40M
6 L6–L11 47 µH Inductor, 47 µH @ 100 MHz, 20%, IND2 Fair-Rite/2743019447 IND2
2 U7, U9 IC, Differential Receiver, SOIC-8 Motorola/MC10EP16D MC10EP16D
6 C22, C50, C52,
C53, C59, C62 10 µF Capacitor, 10 µF, 20%, 16 V dc, 1812POL Kemet/T491C106M016A57280 POLCAP 1812
4 R99, R100,
R123, R124 0.0 ΩResistor, 0.0 Ω, 0805 Panasonic/ERJ-6GEY0R00V RES2 0805
2 R140, R141 33,000 ΩResistor, 33,000 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ333V RES2 0805
8 R76, R79, R82, 51 ΩResistor, 51 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ510V RES2 0805, RES 0805
R83, R98, R118,
R119, R137
36 R89, R94, R95, 100 ΩResistor, 100 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ101V RES2 0805, RES 0805
R97, R101–R117,
R120–R122,
R125–R136
8 J1, J2, J6–J8, Connector, SMA Female St. Johnson Components/142-0701-201 SMA
J16–J18, J20, J22
REV. 0
AD10465
–16–
Figure 10a. Top Layer Copper
Figure 10b. Second Layer Copper
REV. 0
AD10465
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Figure 10c. Third Layer Copper
Figure 10d. Fourth Layer Copper
REV. 0
AD10465
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Figure 10e. Fifth Layer Copper
Figure 10f. Bottom Layer Copper
REV. 0
AD10465
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Figure 10g. Bottom Silkscreen
Figure 10h. Bottom Assembly
REV. 0
–20–
C02356–4.5–1/01 (rev. 0)
PRINTED IN U.S.A.
AD10465
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Lead Ceramic Leaded Chip Carrier
(ES-68A)
0.950 (24.13) SQ
TOP VIEW
(PINS DOWN)
PIN 1
10
26
961
60
44
43
27
0.050 (1.27) 0.018 (0.457)
0.800
(20.32)
1.180 (29.97) SQ
0.060
(1.52)
0.240 (6.096)