© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 1 of 42
3.3 Volt Synchronous x36 First-In/First-Out Queue
Memory Organization Device Memory Organization Device
131,072 x 36 FQV36110 8,192 x 36 FQV3670
65,536 x 36 FQV36100 4,096 x 36 FQV3660
32,768 x 36 FQV3690 2,048 x 36 FQV3650
16,384 x 36 FQV3680 1,024 x 36 FQV3640
Key Features
• Industry leading First-In/First-Out Queues (up to 166MHz)
• Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)
• Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)
• User selectable input and output port bus-sizing
• Big Endian/Little Endian user selectable byte representation
• 3.3V power supply
• 5V input tolerant on all control and data input pins
• 5V output tolerant on all flags and data output pins
• Master Reset clears all previously programmed configurations including Write and Read pointers
• Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
• First Word Fall Through (FWFT) and Standard Timing modes
• Presets for eight different Almost Full and Almost Empty offset values
• Parallel/Serial programming of PRAF and PRAE offset values
• Programmable 8-bit or 9-bit parallel programming modes for offset values
• Full, Empty, Almost Full, Almost Empty, and Half Full indicators
• PRAF and PRAE operates in either synchronous or asynchronous modes
• Asynchronous output enable tri-state data output drivers
• Data retransmission with programmable zero or normal latency modes
• Available package: 128 - pin Plastic Thin Quad Flat Pack (TQFP)
• (0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above
• (-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
HBA’s FlexQ™ III offers industry leading FIFO queuing bandwidth (up to 6.0 Gbps), with a wide range of memory
configurations (from 1,024 x 36 to 131,072 x 36). System designer has full flexibility of implementing deeper and wider queues
using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between
transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation
of virtual queue depths.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching
capability.
Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will
initialize Write and Read pointers to zero.
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high
transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing
depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.
In Standard mode, always assert REN for read operation. FULL and EMPTY are used instead of DRDY and
QRDY respectively.
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 2 of 42
Product Description (Continued)
Bus matching feature is available with the following memory configurations:
Input Bus Width Output Bus Width
x9 x36
x18 x36
x36 x36
x36 x18
x36 x9
In addition, Endian Select is available for implementing byte re-ordering on data outputs.
Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 9-bit
parallel programming modes for offset values can be selected for convenience.
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. PRAF and PRAE can operate in either
synchronous or asynchronous modes.
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the
physical 0th (Read pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit
operation.
These FlexQ™ III devices have low power consumption, hence minimizing system power requirements. In addition, industry
standard 128 - pin Plastic TQFP is offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 3 of 42
FQV36110
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
FQV3650
FQV3640
WRITE CLOCK (WCLK)
WRITE ENABLE ( )
LOAD ( )
x36, x18, x9 DATA IN (D35 - 0)
FIRST WORD FALL THROUGH/
SERIAL DATA INPUT (FWFT/SDI)
READ CLOCK (RCLK)
x36, x18, x9 DATA OUT (Q35 - 0)
PROGRAMMABLE ALMOST-
EMPTY ( )
HALF-FULL FLAG ( )
PARTIAL RESET ( ) MASTER RESET ( )
Block Diagram of Single Synchronous Queue
131,072 x 36 / 65,536 x 36 / 32,768 x 36 / 16,384 x 36 / 8,192 x 36 / 4,096 x 36 / 2,048 x 36 / 1,024 x 36
BIG-ENDIAN / LITTLE-ENDIAN (ES)
INTERSPERSED/NON-INTERSPERSED
PARITY (IPAR)
BUS
MATCHING 0
(BM0)
BUS
MATCHING 2
(BM2)
BUS
MATCHING 1
(BM1)
PRST MRST
WEN
LOAD
PRAE
HALF
SERIAL DATA ENABLE ( )
SDEN
RETRANSMIT ( )
RET
OUTPUT ENABLE ( )
OE
READ ENABLE ( )
REN
EMPTY FLAG / OUTPUT READY
( / )
QRDY
EMPTY
FULL FLAG / INPUT READY
( / )
FULL DRDY
PROGRAMMABLE
ALMOST-FULL ( )
PRAF
Figure 1. Single Device Configuration Signal Flow Diagram
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 4 of 42
Offset Register
Write Control
Logic
Write Pointer
SRAM
Input Register Output Register
Flag Logic
Output
Buffer Q35-0 x36, x18, x9
x36, x18, x9
D35-0
Read Pointer
Read Control
Logic Reset Bus
Configuration
FWFT/SDIIPAR LOAD SDEN
WCLK
FWFT/SDI
SFM
PFS1
PFS0
PRAF
/
FULL DRDY
PRAE
HALF
EMPTY QRDY
/
OE
MRST PRST BM1BM2 BM0ES
RCLK
RETZL RET REN
WEN
Figure 2. Device Architecture
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 5 of 42
WEN
SDEN
DNC1
Vcc
DNC1
D34
D32
Vcc
D31
D30
D29
D28
D27
D26
D25
D24
BM1
D35
D33
GND
D23
GND
D22
Vcc
D21
D18
D17
D16
D15
D14
Vcc
D12
GND
D11
D20
D19
GND
D13
Q35
Q34
GND
GND
Q31
Q30
Q29
Q27
Q26
Vcc
Q24
GND
GND
OE
Vcc
Vcc
Q33
Q32
Q28
Q25
Q20
Q19
Q17
Q16
Vcc
Vcc
Q15
Q13
Q12
GND
Q10
Q23
Q22
Q21
Q18
GND
Q14
Q11
D10
D9
D8
D7
D6
D4
Vcc
D2
D1
D0
Q0
Q2
Q3
Q4
Q5
GND
GND
D5
D3
GND
Q6
Vcc
Q7
Q8
Q9
Q1
FWFT/SDI
GND
BM0
PFS0
PFS1
Vcc
SFM
WCLK
Vcc
GND
BM2
RCLK
RETZL
GND
PRST
MRST
LOAD
FULL/DRDY
PRAF
HALF
ES
IPAR
PRAE
EMPTY/QRDY
RET
REN
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
TQFP - 128 (Drw No: PF-02A; Order code: PF)
Top View
NOTES:
1. DNC = Do Not Connect.
Figure 3. Device Pin Out
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 6 of 42
Pin # Pin Name Pin Symbol Input/Output Description
126 Master Reset
MRST Input
Master Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will
go high; EMPTY and PRAE will go low. In FWFT
mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard
mode. In both modes, all data outputs will go low.
Previous programmed configurations will not be
maintained.
127 Partial Reset
PRST Input
Partial Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will
go high; EMPTY and PRAE will go low. In FWFT
mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard
mode. In both modes, all data outputs will go low.
Previous programmed configurations will be maintained.
128 Write Clock WCLK Input
Writes data into queue during low to high transitions of
WCLK if WEN is set to low.
1 Write Enable WEN Input
Controls write operation into queue or offset registers
during low to high transition of WCLK.
125 Load Enable
LOAD Input
During Master Reset, set LOAD low to select parallel
programming or one of eight default offset values. Set
LOAD high to select serial programming or one of eight
default offset values. After Master Reset,
LOAD controls write/read, to/from offset registers during
low to high transition of WCLK/RCLK respectively. Use
in conjunction with WEN /REN .
115 Default
Programming 1 PFS1 Input
During Master Reset, select one of eight default offset
values. Use in conjunction with LOAD and PFS0.
118 Default
Programming 0 PFS0 Input
During Master Reset, select one of eight default offset
values. Use in conjunction with LOAD and PFS1.
07,08,09,
10,12,13,
15,16,17,
18,19,20,
21,23,25,
26,27,28,
30,31,32,
33,34,36,
38,39,40,
41,42,43,
45,46,47,
49,50,51.
Data Inputs D35-0 Input
36 - bit wide input data bus.
105 Read Clock RCLK Input
Reads data from queue during low to high transitions of
RCLK if REN is set to low.
104 Read Enable
REN Input Controls read operation from queue or offset registers
during low to high transition of RCLK.
Table 1. Pin Descriptions
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 7 of 42
Pin # Pin Name Pin Symbol Input/Output Description
102 Output Enable OE Input Setting OE low activates the data output drivers. Setting
OE high deactivates the data output drivers (High-Z).
99,98,97,
96,93,92,
91,90,89,
88,86,85,
82,81,80,
79,78,77,
75,74,71,
70,69,68,
66,65,64,
63,62,60,
58,57,56,
55,54,53
Data Outputs Q35-0 Output 36 - bit wide output data bus.
124
First Word Fall
Through/Serial
Data Input
FWFT/SDI Input
Selects FWFT timing or Standard timing mode during
Master Reset. After Master Reset, if serial programming
is selected ( LOAD = high), FWFT/SDI is used as the
serial data input for the offset registers. Serial data is
written during the low to high transition of WCLK. Use in
conjunction with SDEN .
2 Serial Data
Input Enable SDEN Input
If serial programming is selected, setting SDEN low and
LOAD low enables serial data input to be written into
offset registers during the low to high transition of WCLK.
112 Bus Matching 2 BM2 Input
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM1
and BM0.
6 Bus Matching 1 BM1 Input
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM2
and BM0.
119 Bus Matching 0 BM0 Input
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM2
and BM1.
114 Endian Select ES Input
During Master Reset, set ES high to select byte re-ordering
on data outputs or ES low to select no byte re-ordering on
data outputs.
103 Retransmit
RET Input
Data previously read from the queue can be retransmitted
by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes
the Read pointer to zero. Hence, all re-reads will always
start from the physical 0th (Read pointer = zero) location of
the queue.
107 Zero Latency
Retransmit RETZL Input
During Master Reset, set RETZL low to select zero
latency retransmit or RETZL high to select normal latency
retransmit.
123 Full/Data Input
Ready Flag FULL / DRDY Output
Queue is full when FULL goes low during the low to high
transition of WCLK. This prohibits further writes into the
queue. In FWFT mode, queue is full when DRDY goes
high during low to high transition of WCLK. This
prohibits further writes into the queue.
Table 1. Pin Descriptions (Continued)
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 8 of 42
Pin # Pin Name Pin Symbol Input/Output Description
108
Empty/Data
Output Ready
Flag
EMPTY / QRDY Output
Queue is empty when EMPTY goes low during the
low to high transition of RCLK. This prohibits further
reads from the queue. In FWFT mode, queue is empty
when QRDY goes high during the low to high
transition of RCLK. This prohibits further reads from
the queue.
113 Interspersed
Parity IPAR Input
During Master Reset, set IPAR low to select 9-bit
parallel programming mode or IPAR high to select 8-
bit parallel programming mode.
109
Synchronous
Partial Flag
Mode
SFM Input
During Master Reset, set SFM high to select
Synchronous Partial Flag mode or SFM low to select
Asynchronous Partial Flag mode.
121 Almost Full
PRAF Output
Queue is almost full when PRAF goes low during the
low to high transition of WCLK. Default (Full-offset)
or programmed offset values determine the status of
PRAF .
110 Almost Empty
PRAE Output
Queue is almost empty when PRAE goes low during
the low to high transition of RCLK. Default (Empty
+offset) or programmed offset values determine the
status of PRAE .
117 Half Full
HALF Output Queue is more than half full when HALF goes low.
Triggered by both WCLK and RCLK.
03, 05 Do Not
Connect DNC N/A
Do not connect.
04,11,24,
35,48,61,
72,73,87,
100,101,
111,122.
Power Vcc N/A
3.3V power supply.
14,22,29,
37,44,52,
59,67,76,
83,84,94,
95,106,
116,120
Ground GND N/A
0V Ground.
Table 1. Pin Descriptions (Continued)
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 9 of 42
Symbol Rating Com’l & Ind’l Unit
VTERM Terminal Voltage with
respect to GND -0.5 to + 4.5 V
TSTG Storage Temperature -55 to +125 °C
IOUT DC Output Current -50 to +50 mA
NOTES:
Absolute Max Ratings are for reference only. Permanent damage to the device may
occur if extended period of operation is outside this range. Standard operation should
fall within the Recommended Operating Conditions.
Table 2. Absolute Maximum Ratings
FQV36110, FQV36100, FQV3690, FQV3680, FQV3670,
FQV3660, FQV3650, FQV3640
Commercial
Clock = 6ns, 7.5ns, 10ns, 15ns
Industrial
Clock = 7.5ns, 10ns, 15ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
Recommended Operating Conditions
Vcc Supply Voltage Com’l / Ind’l 3.15 3.3 3.45 3.15 3.3 3.45 V
GND Supply Voltage 0 0 0 0 0 0 V
VIH Input High Voltage Com’l /
Ind’l 2.0 - 5.5 2.0 - 5.5 V
VIL Input Low Voltage Com’l /
Ind’l - - 0.8 - - 0.8 V
TA Operating Temperature
Commercial 0 - 70 0 - 70
°C
TA Operating Temperature
Industrial -40 - 85 -40 - 85
°C
DC Electrical Characteristics
ILI(1) Input Leakage Current (any
input) -10 - 10 -10 - 10
µA
ILO Output Leakage Current -10 - 10 -10 - 10 µA
VOH Output Logic “1” Voltage,
IOH=-2mA 2.4 - - 2.4 - - V
VOL Output Logic “0” Voltage, IOL
= 8mA - - 0.4 - - 0.4 V
Power Consumption
Icc1(2,3) Active Power Supply Current - - 40 - - 40 mA
Icc2(4) Standby Current - - 15 - - 15 mA
Capacitance at 100MHz Ambient Temperature (25°C)
Symbol Parameter Conditions Max. Unit
CIN(2) Input Capacitance VIN= 0V 10 pF
COUT(2,4) Output Capacitance VOUT= 0V 10 pF
NOTES:
1. Measurement with 0.4<=VIN<=Vcc
2. With output tri-stated ( OE = High)
3. Icc(1,2) is measured with WCLK and RCLK at 20 MHz
4. Design simulated, not tested.
Table 3. DC Specifications
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 10 of 42
Commercial Commercial & Industrial
FQV36100-6
FQV36100-6
FQV3690-6
FQV3680-6
FQV3670-6
FQV3660-6
FQV3650-6
FQV3640-6
FQV36100-7.5
FQV36100-7.5
FQV3690-7.5
FQV3680-7.5
FQV3670-7.5
FQV3660-7.5
FQV3650-7.5
FQV3640-7.5
FQV36100-10
FQV36100-10
FQV3690-10
FQV3680-10
FQV3670-10
FQV3660-10
FQV3650-10
FQV3640-10
FQV36100-15
FQV36100-15
FQV3690-15
FQV3680-15
FQV3670-15
FQV3660-15
FQV3650-15
FQV3640-15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Clock Cycle Frequency - 166 - 133 - 100 - 66 MHz
tA Data Access Time 1 4 2 5 2 6.5 2 10 ns
tWCLK Write Clock Cycle Time 6 - 7.5 - 10 - 15 - ns
tWCLKH Write Clock High Time 2.5 - 3.5 - 4.5 - 6 - ns
tWCLKL Write Clock Low Time 2.5 - 3.5 - 4.5 - 6 - ns
tRCLK Read Clock Cycle Time 6 - 7.5 - 10 - 15 - ns
tRCLKH Read Clock High Time 2.5 - 3.5 - 4.5 - 6 - ns
tRCLKL Read Clock Low Time 2.5 - 3.5 - 4.5 - 6 - ns
tDS Data Set-up Time 2.0 - 2.5 - 3.5 - 4 - ns
tDH Data Hold Time 0.5 - 0.5 - 0.5 - 1 - ns
tENS Enable Set-up Time 2.0 - 2.5 - 3.5 - 4 - ns
tENH Enable Hold Time 0.5 - 0.5 - 0.5 - 1 - ns
tRST Reset Pulse Width(1) 8 - 10 - 10 - 15 - ns
tRSTS Reset Set-up Time 10 - 15 15 - 15 - ns
tRSTR Reset Recovery Time 10 - 10 - 10 - 15 - ns
tRSTF Reset to Flag and Output Time - 10 - 15 - 15 - 15 ns
tOLZ Output Enable to Output in Low-Z(1) 0 - 0 - 0 - 0 - ns
tOE Output Enable to Output Valid 2 4 2 5 2 6 2 8 ns
tOHZ Output Enable to Output in High-Z(1) 2 4 2 6 2 6 2 8 ns
tFULL Write Clock to Full Flag - 4 - 5 - 6.5 - 10 ns
tEMPTY Read Clock to Empty Flag - 4 - 5 - 6.5 - 10 ns
tPRAFS Write Clock to Synchronous Almost-Full Flag - 4 - 5 - 6.5 - 10 ns
tPRAES Read Clock to Synchronous Almost-Empty Flag - 4 - 5 - 6.5 - 10 ns
tSKEW1 Skew time between Read Clock & Write Clock
for Full Flag / Empty Flag 4 - 5 - 7 - 9 - ns
tSKEW2 Skew time between Read Clock & Write Clock
for PRAE & PRAF 6 - 7 - 10 - 14 - ns
tLOADS Load Setup Time 2.0 - 2.5 - 3.5 - 4 - ns
tLOADH Load Hold Time 0.5 - 0.5 - 0.5 - 1 - ns
Table 4. AC Electrical Characteristics
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 11 of 42
Commercial Commercial & Industrial
FQV36100-6
FQV36100-6
FQV3690-6
FQV3680-6
FQV3670-6
FQV3660-6
FQV3650-6
FQV3640-6
FQV36100-7.5
FQV36100-7.5
FQV3690-7.5
FQV3680-7.5
FQV3670-7.5
FQV3660-7.5
FQV3650-7.5
FQV3640-7.5
FQV36100-10
FQV36100-10
FQV3690-10
FQV3680-10
FQV3670-10
FQV3660-10
FQV3650-10
FQV3640-10
FQV36100-15
FQV36100-15
FQV3690-15
FQV3680-15
FQV3670-15
FQV3660-15
FQV3650-15
FQV3640-15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRETS Retransmit Setup Time 2.5 - 3.5 - 3.5 - 4 - ns
tHALF Clock to HALF - 12 - 12.5 - 16 - 20 ns
tPRAFA Write Clock to Asynchronous
Programmable Almost-Full Flag - 12 - 12.5 - 16 - 20 ns
tPRAEA Read Clock to Asynchronous
Programmable Almost-Empty Flag - 12 - 12.5 - 16 - 20 ns
NOTES:
1. Design simulated, not tested.
Table 4. AC Electrical Characteristics (Continued)
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 12 of 42
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load, clock = 6ns, 7.5 ns Refer to Figure 4
Output Load*, clock = 10ns, 15ns Refer to Figure 5 & 6
* Include jig and scope capacitances
Table 5. AC Test Condition
20 30 50 80 100 200
1
2
3
4
Capacitance (pF)
t
CD (Typical, ns)
Figure 6. Lumped Capacitive Load
D.U.T.
510Ω
30pF*
330Ω
3.3V
Figure 5. Output Load
*Includes jig and scope capacitances.
for clock = 10ns, 15ns
Vcc/2
50 Ω
Z0 = 50 Ω
I/O
Figure 4. AC Test Load
for clock = 6ns, 7.5ns
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
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FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 13 of 42
Pin Functions
MRST Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as
Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will not
be maintained.
PRST Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRA
E
will go to the same state as
Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will be
maintained.
WCLK Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes
FULL / DRD
Y
and PRAF flags. WCLK and RCLK are independent of each other.
WEN Controls write operation into queue or offset registers during low to high transition of WCLK.
LOAD During Master Reset, set LOAD low to select parallel programming or one of eight default offset values.
Set LOAD high to select serial programming or one of eight default offset values. After Master Reset,
LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK
respectively for parallel programming. Use in conjunction with WEN /REN . During programming of
offset registers, PRAF and PRA
E
flag status is invalid. For Serial programming, LOAD is used to enable
serial loading of offset registers together with SDEN . Refer to Figure 7 & Table 13 for details.
PFS1 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD
and PFS1. Refer to Table 13 for details.
PFS0 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0.
Refer to Table 13 for details.
D35-0 36 - bit wide input data bus.
RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the
EMPT
Y
/QRDY and PRA
E
flags. RCLK and WCLK are independent of each other.
REN Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances
the Read pointer of the queue.
OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers
(High-Z). OE does not control advancement of Read pointer.
Q35-0 36 - bit wide output data bus.
FWFT/SDI Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial
programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers.
Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . In
FWFT mode, DRD
Y
and QRDY is used instead of FULL and EMPT
Y
. Refer to Table 11 for all flags
status. In Standard mode, FULL and EMPT
Y
are used instead of DRD
Y
and QRDY . Refer to Table 10
for all flags status.
SDEN If serial programming is selected, setting SDEN and LOAD low enables serial data to be written into offset
registers during the low to high transition of WCLK. During serial programming, PRAF and PRA
E
flags
status is invalid. Refer to Figure 7 for details.
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
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Page 14 of 42
Pin Functions (Continued)
BM2 During Master Reset, select one of five input and output bus width configurations. Use in conjunction
with BM1 and BM0. Refer to Table 12 for details.
BM1 During Master Reset, select one of five input and output bus width configurations. Use in conjunction
with BM2 and BM0. Refer to Table 12 for details.
BM0 During Master Reset, select one of five input and output bus width configurations. Use in conjunction
with BM2 and BM1. Refer to Table 12 for details.
ES During Master Reset, set ES high to select byte re-ordering on data outputs or set ES low to select no byte
re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 12 for details.
RET Data previously read from the queue can be retransmitted by asserting RE
T
pin at the low to high
transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all
re-reads will always start from the physical 0th (Read pointer = zero), location of the queue. Refer to
Diagram 7 & 8 for details.
RETZL During Master Reset, set RETZ
L
low to select zero latency retransmit or set RETZ
L
high to select
normal latency retransmit.
FULL / DRDY In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK. This
prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT mode,
queue is full when DRD
Y
goes high during the low to high transition of WCLK. This prohibits further
writes into the queue and prevents advancement of Write pointer. Refer to Table 10 & 11 for behavior of
FULL / DRD
Y
.
EMPTY / QRDY In Standard mode, queue is empty when EMPT
Y
goes low during the low to high transition of RCLK.
This prohibits further reads from the queue and prevents advancement of Read pointer. In FWFT mode,
queue is empty when QRDY goes low during the low to high transition of RCLK. This prohibits further
reads from the queue and prevents advancement of Read pointer. Refer to 10 & 11 for behavior of
EMPT
Y
/QRDY .
IPAR During Master Reset, set IPAR low to select 9-bit parallel programming mode or set IPAR high to select
8-bit parallel programming mode. In 9-bit mode, 9-bit wide data input/output bus width is used for
storing/fetching offset values. In 8-bit mode, 8-bit wide data input/output bus is used for
storing/fetching offset values.
SFM During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select
Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRA
E
are synchronous to WCLK
and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of PRAF and de-
assertion of PRA
E
. RCLK synchronizes the assertion of PRA
E
and de-assertion of PRA
E
.
PRAF In Synchronous mode, queue is almost full when PRAF goes low during the low to high transition of
WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . In
Asynchronous mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 10 & 11 for behavior
of PRAF .
PRAE In Synchronous mode, queue is almost empty when PRA
E
goes low during the low to high transition of
RCLK. Default (Empty+offset) or programmed offset values determine the status of PRA
E
. In
Asynchronous timing mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 10 & 11 for
behavior of PRA
E
.
HALF Queue is more than half full when HAL
F
goes low during the low to high transition of WCLK.
HAL
F
goes high during low to high transition of RCLK when queue is less than half full. Refer to
Table 10 & 11 for details.
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
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Page 15 of 42
LOAD WEN REN SDEN WCLK RCLK
FQV36110
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
FQV3650
FQV3640
Selection / Sequence
0 0 1 1
X
Parallel write to offset
registers:
Empty Offset
Full Offset
Parallel write
to registers:
1. PRAE
2. PRAF
0 1 0 1 X
Parallel read from offset
registers:
Empty Offset
Full Offset
Parallel read
from registers:
1. PRAE
2. PRAF
0 1 1 0
X
Serial shift into registers:
34 bits for the FQV36110
32 bits for the FQV36100
30 bits for the FQV3690
28 bits for the FQV3680
26 bits for the FQV3670
24 bits for the FQV3660
22 bits for the FQV3650
20 bits for the FQV3640
1 bit for each rising WCLK edge
Starting with Empty Offset (Low Byte)
Ending with Full Offset (High Byte)
X 1 1 1 X X
No Operation
1 0 X X
X Write Memory
1 X 0 X X
Read Memory
1 1 1 X X X No Operation
Figure 7. Programmable Flag Offset Programming Sequence
(FQV36110, FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650 and FQV3640)
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JULY 2002
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Device PRAF Programming (bits) PRAE Programming (bits)
D/Q16 - 0 Non-IPAR D/Q16 - 0 Non-IPAR
FQV36110 D/Q18 & D/Q16 – 9 & D/Q7 – 0 IPAR D/Q18 & D/Q17 – 9 & D/Q7 – 0 IPAR
D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR
FQV36100 D/Q16 – 9 & D/Q7 – 0 IPAR D/Q16 – 9 & D/Q7 – 0 IPAR
D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR
FQV3690 D/Q15 – 9 & D/Q7 – 0 IPAR D/Q15 – 9 & D/Q7 – 0 IPAR
D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR
FQV3680 D/Q14 – 9 & D/Q7 – 0 IPAR D/Q14 – 9 & D/Q7 – 0 IPAR
D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR
FQV3670 D/Q13 – 9 & D/Q7 – 0 IPAR D/Q13 – 9 & D/Q7 – 0 IPAR
D/Q11 - 0 Non-IPAR D/Q11 - 0 Non-IPAR
FQV3660 D/Q12 – 9 & D/Q7 – 0 IPAR D/Q12 – 9 & D/Q7 – 0 IPAR
D/Q10 - 0 Non-IPAR D/Q10 - 0 Non-IPAR
FQV3650 D/Q11 – 9 & D/Q7 – 0 IPAR D/Q11 – 9 & D/Q7 – 0 IPAR
D/Q9 - 0 Non-IPAR D/Q9 - 0 Non-IPAR
FQV3640 D/Q10 – 9 & D/Q7 – 0 IPAR D/Q10 – 9 & D/Q7 – 0 IPAR
Table 6. Parallel Offset Register Data Mapping Table for x36 Bus Width
Device PRAF Programming (bits) PRAE Programming (bits)
D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR
FQV36110 D/Q16 – 9 & D/Q7 – 0 IPAR D/Q16 – 9 & D/Q7 – 0 IPAR
D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR
FQV36100 D/Q16 – 9 & D/Q7 – 0 IPAR D/Q16 – 9 & D/Q7 – 0 IPAR
D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR
FQV3690 D/Q15 – 9 & D/Q7 – 0 IPAR D/Q15 – 9 & D/Q7 – 0 IPAR
D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR
FQV3680 D/Q14 – 9 & D/Q7 – 0 IPAR D/Q14 – 9 & D/Q7 – 0 IPAR
D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR
FQV3670 D/Q13 – 9 & D/Q7 – 0 IPAR D/Q13 – 9 & D/Q7 – 0 IPAR
D/Q11 - 0 Non-IPAR D/Q11 - 0 Non-IPAR
FQV3660 D/Q12 – 9 & D/Q7 – 0 IPAR D/Q12 – 9 & D/Q7 – 0 IPAR
D/Q10 - 0 Non-IPAR D/Q10 - 0 Non-IPAR
FQV3650 D/Q11 – 9 & D/Q7 – 0 IPAR D/Q11 – 9 & D/Q7 – 0 IPAR
D/Q9 - 0 Non-IPAR D/Q9 - 0 Non-IPAR
FQV3640 D/Q10 – 9 & D/Q7 – 0 IPAR D/Q10 – 9 & D/Q7 – 0 IPAR
Table 7. Parallel Offset Register Data Mapping Table for x18 Bus Width
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
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Page 17 of 42
Device PRAF Programming (bits) PRAE Programming (bits)
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
D/Q7 – 0 Mid Byte D/Q7 – 0 Mid Byte
FQV36110
D/Q0 High Byte D/Q0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV36100 D/Q7 – 0 High Byte D/Q7 – 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV3690 D/Q6– 0 High Byte D/Q6– 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV3680 D/Q5 – 0 High Byte D/Q5 – 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV3670 D/Q4 – 0 High Byte D/Q4 – 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV3660 D/Q3 – 0 High Byte D/Q3 – 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV3650 D/Q2 – 0 High Byte D/Q2 – 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV3640 D/Q1 – 0 High Byte D/Q1 – 0 High Byte
Table 8. Parallel Offset Register Data Mapping for Table x9 Bus Width
Device Standard Mode FWFT Mode
FQV36110 131,072 x 36 131,073 x 36
FQV36100 65,536 x 36 65,537 x 36
FQV3690 32,768 x 36 32,769 x 36
FQV3680 16,384 x 36 16,385 x 36
FQV3670 8,192 x 36 8,193 x 36
FQV3660 4,096 x 36 4,097 x 36
FQV3650 2,048 x 36 2,049 x 36
FQV3640 1,024 x 36 1,025 x 36
Table 9. Maximum Depth of Queue for Standard and FWFT Mode
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
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Page 18 of 42
FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640
Parallel Offset Write/Read Cycles for x9 Bus Width
Data Width
PRAF
PRAF
PRAE
PRAE
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q 3 D/Q1
75316420
75316420
15 13 11 914 12 10 8
15 13 11 914 12 10 8
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
FQV36110
Parallel Offset Write/Read Cycles for x9 Bus Width
Data Width
PRAF
PRAF
PRAE
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q 3 D/Q1
75316420
15 13 11 914 12 10 8
2nd Cycle
4th Cycle
5th Cycle
16
FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640
Parallel Offset Write/Read Cycles for x18 Bus Width
Data Width
Non-Interspersed Parity
Interspersed Parity
Data Width
Non-Interspersed Parity
Interspersed Parity
753164 2 0
7531
6420
8
13 11 9
14 12 10
8
13 11 9
14 12 10
PRAE
PRAF
1st Cycle
2nd Cycle
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1D/Q17 D/Q15 D/Q13 D/Q11 D/Q9D/Q16 D/Q14 D/Q12 D/Q10
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1D/Q17 D/Q15 D/Q13 D/Q11 D/Q9D/Q16 D/Q14 D/Q12 D/Q10
753164 2 0
75316 420813 11 9
14 12 10
8
13 11 9
14 12 10
15
15
15
15
75316420
15 13 11 914 12 10 8
16
3rd Cycle PRAE
1st Cycle PRAE
6th Cycle PRAF
Figure 8. Parallel Offset Write/Read Cycle Diagram
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
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Page 19 of 42
FQV36110, FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640
Parallel Offset Write/Read Cycles for x36 Bus Width
Data Width
Non-Interspersed Parity
Interspersed Parity
Data Width
Non-Interspersed Parity
Interspersed Parity
1314
PRAE
PRAF
D/Q17 D/Q15 D/Q13 D/Q11 D/Q9D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
D/Q18
D/Q19D/Q~ D/Q~D/Q~
D/Q35
1st Cycle
2nd Cycle
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1D/Q17 D/Q15 D/Q13 D/Q11 D/Q9D/Q16 D/Q14 D/Q12 D/Q10D/Q35 D/Q~ D/Q19D/Q~ D/Q~ D/Q18
753164 2 0
7531
6420
8
13 11 9
14 12 10
8
13 11 9
14 12 10
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1D/Q17 D/Q15 D/Q13 D/Q11 D/Q 9D/Q16 D/Q14 D/Q12 D/Q10D/Q35 D/Q~ D/Q19D/Q~ D/Q~ D/Q18
753164 2 0
7531
6420
8
13 11 9
14 12 10
8
13 11 9
14 12 10
FQV36110
Parallel Offset Write/Read Cycles for x18 Bus Width
Data Width
Non-Interspersed Parity
Interspersed Parity 753164 2 0
7531
6420
8
13 11 9
14 12 10
813 11 914 12 10
PRAE
1st Cycle
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1D/Q17 D/Q15 D/Q13 D/Q11 D/Q9D/Q16 D/Q14 D/Q12 D/Q10
15
15
Data Width
Non-Interspersed Parity
Interspersed Parity
PRAF3rd Cycle
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1D/Q17 D/Q15 D/Q13 D/Q11 D/Q9D/Q16 D/Q14 D/Q12 D/Q10
753164 2 0
75316 420813 11 9
14 12 10
8
13 11 9
14 12 10
15
15
Non-Interspersed Parity
Interspersed Parity
PRAE
2nd Cycle
16
16
Non-Interspersed Parity
Interspersed Parity
4th Cycle
16
16
PRAF
15
15
16
16
15
15
16
16
# of Bits for Offset Registers
17 bits for FQV36110
16 bits for FQV36100
15 bits for FQV3690
14 bits for FQV3680
13 bits for FQV3670
12 bits for FQV3660
11 bits for FQV3650
10 bits for FQV3640
Note: Don’t Care applies to all unused bits
Figure 8. Parallel Offset Write/Read Cycle Diagram (Continued)
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
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Page 20 of 42
FQV36110 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 65,536 H H H H H
65,537 to [131,072-(x+1)] H H L H H
(131,072-x) to 131,071 H L L H H
131,072 L L L H H
FQV36100 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 32,768 H H H H H
32,769 to [65,536-(x+1)] H H L H H
(65,536-x) to 65,535 H L L H H
65,536 L L L H H
FQV3690 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 16,384 H H H H H
16,385 to [32,768-(x+1)] H H L H H
(32,768-x) to 32,767 H L L H H
32,768 L L L H H
FQV3680 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 8,192 H H H H H
8,193 to [16,384-(x+1)] H H L H H
(16,384 -x) to 16,383 H L L H H
16,384 L L L H H
FQV3670 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 4,096 H H H H H
4,097 to [8,192-(x+1)] H H L H H
(8,192 -x) to 8,191 H L L H H
8,192 L L L H H
FQV3660 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 2,048 H H H H H
2,049 to [4,096-(x+1)] H H L H H
(4,096 –x) to 4,095 H L L H H
4,096 L L L H H
Table 10. Status Flags (Standard Mode)
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
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FQV3650 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 1,024 H H H H H
1,025 to [2,048-(x+1)] H H L H H
(2,048 -x) to 2,047 H L L H H
2,048 L L L H H
FQV3640 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 512 H H H H H
513 to [1,024-(x+1)] H H L H H
(1,024 –x) to 1,023 H L L H H
1,024 L L L H H
NOTES:
1. See Table 13 for values x, y.
Table 10. Status Flags (Standard Mode) (Continued)
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
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FQV36110 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1(1) L H H L L
(y+2) to 65,537 L H H H L
65,538 to [131,073-(x+1)] L H L H L
(131,073-x) to 131,072 L L L H L
131,073 H L L H L
FQV36100 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1(1) L H H L L
(y+2) to 32,769 L H H H L
32,770 to [65,537-(x+1)] L H L H L
(65,537-x) to 65,536 L L L H L
65,537 H L L H L
FQV3690 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1(1) L H H L L
(y+2) to 16,385 L H H H L
16,386 to [32,769-(x+1)] L H L H L
(32,769-x) to 32,768 L L L H L
32,769 H L L H L
FQV3680 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1(1) L H H L L
(y+2) to 8,193 L H H H L
8,194 to [16,385-(x+1)] L H L H L
(16,385 -x) to 16,384 L L L H L
16,385 H L L H L
FQV3670 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1(1) L H H L L
(y+2) to 4,097 L H H H L
4,098 to [8,193-(x+1)] L H L H L
(8,193-x) to 8,192 L L L H L
8,193 H L L H L
FQV3660 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1(1) L H H L L
(y+2) to 2,049 L H H H L
2,050 to [4,097-(x+1)] L H L H L
(4,097 -x) to 4,096 L L L H L
4,097 H L L H L
Table 11. Status Flags (FWFT Mode)
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FQV3650 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1(1) L H H L L
(y+2) to 1,025 L H H H L
1,026 to [2,049-(x+1)] L H L H L
(2,049 -x) to 2,048 L L L H L
2,049 H L L H L
FQV3640 DRDY PRAF HALF PRAE QRDY
0 L H H L H
1 to y+1(1) L H H L L
(y+2) to 513 L H H H L
514 to [1,025-(x+1)] L H L H L
(1,025 -x) to 1,024 L L L H L
1,025 H L L H L
NOTES:
1. See Table 13 for values x, y.
Table 11. Status Flags (FWFT Mode) (Continued)
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ES BM2 BM1 BM0 I/O Width D/Q35-27 D/Q26-18 D/Q17-9 D/Q8-0 Sequence
X 0 X X I 36 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 36 Byte 4 Byte 3 Byte 2 Byte 1 1st Read
0 1 0 0 I 36 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 18 X X Byte 4 Byte 3 1st Read
X X Byte 2 Byte 1 2
nd Read
0 1 0 1 I 36 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 9 X X X Byte 4 1st Read
X X X Byte 3 2nd Read
X X X Byte 2 3rd Read
X X X Byte1 4th Read
0 1 1 0 I 18 X X Byte 4 Byte 3 1st Write
X X Byte 2 Byte 1 2
nd Write
O 36 Byte 4 Byte 3 Byte 2 Byte 1 1st Read
0 1 1 1 I 9 X X X Byte 4 1st Write
X X X Byte 3 2nd Write
X X X Byte 2 3rd Write
X X X Byte1 4th Write
O 36 Byte 4 Byte 3 Byte 2 Byte 1 1st Read
1 1 0 0 I 36 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 18 X X Byte 2 Byte 1 1st Read
X X Byte 4 Byte 3 2
nd Read
1 1 0 1 I 36 Byte 4 Byte 3 Byte 2 Byte 1 1st Write
O 9 X X X Byte 1 1st Read
X X X Byte 2 2nd Read
X X X Byte 3 3rd Read
X X X Byte4 4th Read
1 1 1 0 I 18 X X Byte 4 Byte 3 1st Write
X X Byte 2 Byte 1 2
nd Write
O 36 Byte 2 Byte 1 Byte 4 Byte 3 1st Read
1 1 1 1 I 9 X X X Byte 4 1st Write
X X X Byte 3 2nd Write
X X X Byte 2 3rd Write
X X X Byte1 4th Write
O 36 Byte 1 Byte 2 Byte 3 Byte 4 1st Read
Table 12. Bus-Matching Table
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FQV3650
FQV3640
LOAD PFS1 PFS0
Default Offsets x, y(1)
0 0 0 127
0 0 1 255
0 1 0 511
0 1 1 63
1 0 0 31
1 0 1 7
1 1 0 15
1 1 1 3
FQV3650
FQV3640
LOAD PFS1 PFS0
Program Mode
1 X X Serial
0 X X Parallel
FQV3690
FQV3680
FQV3670
FQV3660
LOAD PFS1 PFS0
Default Offsets x, y(1)
0 0 0 127
0 0 1 255
0 1 0 511
0 1 1 63
1 0 0 1,023
1 0 1 15
1 1 0 31
1 1 1 7
FQV3690
FQV3680
FQV3670
FQV3660
LOAD PFS1 PFS0
Program Mode
1 X X Serial
0 X X Parallel
NOTES:
1. x = PRAF offset, y = PRAE offset.
Table 13. Default Programmable Flag Offsets
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FQV36110
FQV36100
LOAD PFS1 PFS0
Default Offsets x, y(1)
0 0 0 127
0 0 1 8,191
0 1 0 16,383
0 1 1 4,095
1 0 0 1,023
1 0 1 511
1 1 0 2,047
1 1 1 255
FQV36110
FQV36100
LOAD PFS1 PFS0
Program Mode
1 X X Serial
0 X X Parallel
NOTES:
1. x = PRAF offset, y = PRAE offset.
Table 13. Default Programmable Flag Offsets (Continued)
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Timing Diagrams
tRST
tRSTR
tRSTR
tRSTR
tRSTS
FWFT/SDI
tRSTR
tRSTS
tRSTS
PFS1/PFS0
tRSTS
ES
tRSTS
RETZL
tRSTS
SFM
tRSTS
IPAR
Q35- 0
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
tRSTS
tRSTS
tRSTS
tRSTS
MRST
REN
WEN
LOAD
RET
SDEN
/
EMPTY QRDY
PRAE
PRAF HALF/
/
FULL DRDY
If FWFT = 0, = 1
FULL
If FWFT = 1, = 0
DRDY
If FWFT = 1, = 1
QRDY
If FWFT = 0, = 0EMPTY
= 0OE
= 1
OE
tRSTS
BM2/BM1/BM0
Diagram 1. Master Reset Timing
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tRST
tRSTR
tRSTR
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
tRSTS
tRSTS
tRSTS
tRSTS
If FWFT = 0, = 1FULL
If FWFT = 1, = 0
DRDY
If FWFT = 1, = 1QRDY
If FWFT = 0, = 0
EMPTY
= 0
OE
= 1
OE
Q35- 0
RET
SDEN
/
EMPTY QRDY
PRAE
PRAF HALF/
/
FULL DRDY
WEN
REN
PRST
Diagram 2. Partial Reset Timing
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DW
i + 1
DW
i
No
Write
No
Write
No
Write
t
WCLK
t
WCLKH
t
WCLKL
t
FULL
t
FULL
t
FULL
t
FULL
t
DS
t
DH
t
DS
t
DH
t
SKEW1
t
ENS
t
ENH
t
ENS
t
ENH
t
A
t
A
Next Data ReadData ReadOutput Register Data
WCLK
D
35 - 0
RCLK
Q
35 - 0
FULL
REN
WEN
12 12
t
SKEW1
NOTES:
1. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, FULL
___________
will go high (after one WCLK cycle plus tFULL). If tSKEW1 is not met, then FULL
__________
will assert 1
or more WCLK cycles.
2. LOAD
___________
= High, OE
______
= Low.
Diagram 3. Write Cycle and Full Flag Timing (Standard Mode)
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DW
1
DW
2
DW
1
Last Word Last Word DW
2
t
RCLK
t
RCLKH
t
RCLKL
t
ENH
t
ENS
t
ENH
t
ENS
t
EMPTY
t
EMPTY
t
EMPTY
t
A
t
A
t
OEN
t
OHZ
t
OLZ
t
OLZ
t
SKEW1
t
ENS
t
ENH
t
ENS
t
ENH
t
ENH
t
ENS
t
DS
t
DH
t
DS
t
DH
t
A
RCLK
Q
35 - 0
WCLK
D
35 - 0
OE
WEN
EMPTY
REN
12
NOTES:
1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY
______________
will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY
______________
will assert 1 or
more RCLK cycles.
2. LOAD
___________
= High.
3. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK.
Diagram 4. Read Cycle, Empty Flag and First Data Word Latency Timing (Standard Mode)
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DW
[y+2]
DW
D
DW
[D-1]
DW
[D-x+3]
DW
[D-x+2]
DW
[D-x+1]
DW
[D-x]
DW
[D-x-1]
DW
[(D-1)/2+3]
DW
[(D-1)/2+2]
DW
[(D-1)/2+1]
DW
[y+4]
DW
[y+3]
DW
4
DW
3
DW
2
DW
1
312 12
WCLK
D
35 - 0
RCLK
Q
35 - 0
QRDY
PRAE
HALF
PRAF
DRDY
t
ENS
t
DH
t
DS
t
DS
t
DS
t
DS
t
ENH
t
SKEW1
t
SKEW2
t
FULL
t
HALF
t
A
t
EMPTY
1
Output Data Register DW
1
WEN
REN
2
t
PRAES
t
PRAFS
NOTES:
1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW1, QRDY
____________
will go low (after two RCLK cycle plus tEMPTY). If tSKEW1 is not met, then QRDY
____________
will assert 1 or more
RCLK cycles.
2. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE
___________
will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE
___________
will assert 1 or more
RCLK cycles.
3. LOAD
___________
= High, OE
______
= Low.
4. y = PRAE
___________
offset, x = PRAF
___________
offset.
5. D = maximum queue depth. Please refer to Table 9 for Depth.
6. First word latency: tSKEW1 + tEMPTY + 2 * tRCLK
Diagram 5. Write Timing (FWFT Mode)
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DW
1
DW
D
DW
[D-1]
DW
[D-y+2]
DW
[D-y+1]
DW
[D-y-1]
DW
[(D-1)/2+2]
DW
x+3
DW
x+2
DW
x+1
DW
3
DW
2
DW
1
DW
[D-y]
DW
[(D-1)/2+1]
DW
D
t
ENS
t
ENH
t
SKEW1
t
SKEW2
t
DS
t
DH
t
ENS
t
OHZ
t
OE
t
A
t
A
t
A
t
A
t
A
t
A
t
ENS
t
EMPTY
t
HALF
t
PRAFS
t
FULL
t
FULL
WCLK
WEN
D
35 - 0
RCLK
REN
OE
Q
35 - 0
QRDY
PRAE
HALF
PRAF
DRDY
12 12
12
t
PRAES
NOTES:
1. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY
____________
will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY
____________
will assert 1 or more
WCLK cycles.
2. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF
___________
will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF
___________
will assert 1 or more
WCLK cycles.
3. LOAD
____________
= High
4. y = PRAE
___________
Offset, x = PRAF
___________
offset.
5. D = maximum queue depth. Please refer to Table 9 for Depth.
Diagram 6. Read Timing (FWFT Mode)
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DWiDWi+1 DW1DW2
RCLK
Q 35 - 0
WCLK
tENS tENH tRETS
tAtA
tENS tENH
tA
tSKEW2
tRETS
tENS tENH
tEMPTY
tHALF
tEMPTY
tPRAES
tPRAFS
REN
WEN
RET
EMPTY
PRAE
HALF
PRAF
12
12
NOTES:
1. Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high.
2. OE = Low.
3. DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
4. Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.
Diagram 7. Retransmit Timing (Standard Mode)
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DW3
DW1
DWiDWi+1 DW2
RCLK
Q 35 - 0
WCLK
tENS tENH tRETS
tA
tSKEW2
tRETS
tENS tENH
tEMPTY
tHALF
tEMPTY
tPRAES
tPRAFS
1
tENH
tA
23
DW4
tAtA
tENS
PRAF
HALF
PRAE
QRDY
RET
WEN
REN
12
4
NOTES:
1. Upon completion of retransmit setup, a read operation can begin only after QRDY returns low.
2. OE = Low.
3. DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
4. Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.
5. Please refer to Table 9 for Depth.
Diagram 8. Retransmit Timing (FWFT Mode)
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RCLK
Q 35 - 0
WCLK
DWiDWi+1 DW1DW2DW3DW4
tRETS
tENS tENH
tSKEW2
tAtAtAtAtA
tENS tENH
tPRAES
tHALF
tPRAFS
WEN
REN
RET
EMPTY
PRAE
HALF
PRAF
123
12
NOTES:
1. If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
2. OE = Low; enables data to be read on outputs Q35 – 0.
3. DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset.
4. No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the
retransmit setup procedure. Please refer to Table 9 for Depth.
5. There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked.
6. RETZL is set Low during MRST .
Diagram 9. Zero Latency Retransmit Timing (Standard Mode)
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RCLK
Q 35 - 0
WCLK
DWiDW i+1 DW1DW2DW3DW4
tRETS
tENS tENH
tSKEW2
tAtAtAtAtA
tENS tENH
tPRAES
tHALF
tPRAFS
DW5
tA
PRAF
HALF
PRAE
QRDY
RET
WEN
REN
12345
12
NOTES:
1. If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
2. No more than D-2 words may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout
the retransmit setup procedure. Please refer to Table 9 for Depth.
3. OE = Low.
4. DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset.
5. There must be at least two words written to the queue before a retransmit operation can be invoked.
6. RETZL is set low during MRST .
Diagram 10. Zero Latency Retransmit Timing (FWFT Mode)
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WCLK
SDI
tENHtENS
tLOADHtLOADS
tDS
offset offset
tENH
tLOADH
tDH
BIT 0 BIT MSB BIT 0 BIT MSB
SDEN
LOAD
PRAE PRAF
*Refer to Table 14
Diagram 11. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode)
FQV36110 FQV36100 FQV3690 FQV3680 FQV3670 FQV3660 FQV3650 FQV3640
MSB 16 15 14 13 12 11 10 9
Table 14. Reference Table for Diagram 11
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tLOADS
tENS
tLOADH
tENH
tLOADH
tENH
tWCLKH tWCLKL
tWCLK
WCLK
D 35 - 0
offset
tDS tDH tDS tDH
WEN
LOAD
PRAE offset
PRAF
Diagram 12. Parallel Loading of Programmable Flag Registers (Standard and FWFT Mode)
tLOADS
tENS
tLOADH
tENH
tLOADH
tENH
tRCLKH tRCLKL
tRCLK
RCLK
Q 35 - 0 Output Register Data
tAtA
offset offset
LOAD
REN
PRAE PRAF
Diagram 13. Parallel Read of Programmable Flag Registers (Standard and FWFT Mode)
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tWCLKH tWCLKL
tENHtENS
tSKEW2
tENS tENH
12 1 2
WCLK
RCLK
REN
WEN
tPRAFS tPRAFS
D - ( x + 1 ) words in Queue D - x words in Queue D - ( x + 1 )
words in Queue
PRAF
NOTES:
1. x = PRAF
___________
offset.
2. D = maximum queue depth. Please refer to Table 9 for Depth.
3. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF
___________
will go high (after on WCLK cycle plus
tPRAFS). If tSKEW2 is not met, then PRAF
___________
will assert 1 or more WCLK cycles.
4. PRAF
___________
synchronizes to the rising edge of WCLK only.
Diagram 14. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
WCLK
RCLK
REN
WEN
PRAE
t
WCLKH t
WCLKL
t
WCLKL t
WCLKH
tENS tENH
y words in Queue
(2)
; y+1 words in Queue(3) y+1 words in Queue(2)
; y+2 words in Queue(3) y words in Queue(2)
;
y+1 words in Queue
(3)
t
PRAES t
PRAES
t
SKEW2
1 2 1 2
NOTES:
1. y = PRAE offset.
2. For Standard Mode.
3. For FWFT Mode.
4. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle plus
tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles.
5. PRAE synchronizes to the rising edge of RCLK only.
Diagram 15. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
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tWCLKH tWCLKL
tENS tENH
tPRAFA
tPRAFA
tENS
D - ( x + 1) words in Queue
D - x words in
Queue D - ( x + 1) words in Queue
WCLK
RCLK
WEN
PRAF
REN
NOTES:
1. x = PRAF offset.
2. D = maximum queue depth. Please refer to Table 9 for Depth.
3. PRAF is asserted to low on WCLK transition and reset to high on RCLK transition.
4. Select this mode by setting SFM low during Master Reset.
Diagram 16. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH tWCLKL
tENS tENH
tPRAEA
tPRAEA
tENS
y words in Queue(2); y+1 words in Queue(3) y+1 words in
Queue(2); y+2
words in Queue (3)
y words in Queue(2); y+1 words in Queue(3)
WCLK
RCLK
WEN
PRAE
REN
NOTES:
1. y = PRAE offset.
2. For Standard Mode.
3. For FWFT Mode.
4. PRAE is asserted to low on RCLK transition and reset to high on WCLK transition.
5. Select this mode by setting SFM low during Master Reset.
Diagram 17. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
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FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 41 of 42
D/2 words in Queue(1); [(D+1)/2] words in Queue(2)
D/2 + 1 words in
Queue(1);
[(D+1)/2 + 1] words
in Queue(2)
D/2 words in Queue(1);
[(D+1)/2] words in Queue(2)
tWCLKH tWCLKL
tENS tENH
tHALF
tHALF
tENS
WCLK
RCLK
WEN
HALF
REN
tENH
NOTES:
1. For Standard Mode.
2. For FWFT Mode.
3. Please refer to Table 9 for Depth.
Diagram 18. Half-Full Flag Timing (Standard and FWFT Mode)
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Flex
Q
TMIII
3F336B
FQV36110 · FQV36100 · FQV3690 · FQV3680 · FQV3670 · FQV3660 · FQV3650 · FQV3640
Page 42 of 42
Order Information:
HBA
Device Family
Device Type
Power
Speed (ns) *
Package**
Temperature Range
XX XXXXX X XX XX X
FQ V36110 (131,072 x 36) Low 6 – 166 MHz PF Blank – Commercial (0°C to 70°C)
V36100 (65,536 x 36) 7-5 – 133 MHz I – Industrial (-40° to 85°C)
V3690 (32,768 x 36) 10 – 100 MHz
V3680 (16,384 x 36) 15 – 66 MHz
V3670 (8,192 x 36)
V3660 (4,096 x 36)
V3650 (2,048 x 36)
V3640 (1,024 x 36)
*Speed – 6ns available only in Commercial temp (0°C to 70°C). Slower speeds available upon request.
**Package – 128 pin Plastic Thin Quad Flat Pack (TQFP)
Example:
FQV3680L6PF (16k x 36, 6ns, Commercial temp)
FQV3670L10PFI (8k x 36, 10ns, Industrial temp)
USA
Taiwan
2107 North First Street, Suite 415
San Jose, CA 95131, USA
www.hba.com
Tel: 408.453.8885
Fax: 408.453.8886
No. 81, Suite 8F-9, Shui-Lee Rd.
Hsinchu, Taiwan, R.O.C.
www.hba.com
Tel: 886.3.516.9118
Fax: 886.3.516.9181
