MSC8101VT1500F - Freescale Semiconductor

Freescale Semiconductor

Technical Data MSC8101

Rev. 19, 5/ 2008

MSC8101

Network Digital Signal Processor

The Freescale MSC8101 DSP is a very versatile device that integrates the high-performance SC140 four-ALU (arithmetic

logic unit) DSP core along with 512 KB of internal memory, a commu nications processor mod ule (CPM) , a 64 -bit b us, a ver y

flexible System Integration Unit (SIU), and a 16-chann el DMA engin e on a single device. With its f our-ALU core, the

MSC8101 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8101 CPM is a 32-

bit RISC-based commu nications protocol engine that can network to time-d ivision multiplexed (TDM) high ways , Ethernet ,

and asynchronous transfer mode (ATM) backbones. The MSC8101 60x-compatible bus interface facilitates its connection to

multi-master system architectures. The very large internal memory, 512 KB, reduces the need for external program and data

memories. The MSC8101 offers 1500 DSP MMACS (1200 core and 300 EFCOP) performance using an internal 300 MHz

clock with a 1.6 V core and independent 3.3 V input/output (I/O).

Figure 1. MSC8101 Block Diagram

UTOPIA

Other

Peripherals

MII

TDMs

CPM

MCC / UART / HDLC / Transparent /

Ethernet / Fast Ethernet / ATM / SCC

PIT

System Protection

Reset Control

Clock Control

SIU

8/16-bit

Host

SC140

Power

Management Clock/PLL 64-bit XA Data Bus

128-bit P-Bus

64-bit XB Data Bus

Extended Core

Interface

64-bit Local Bus

64- bit System Bus

Core

•

Serial Interface and TSA

3 × FCC

4 × SCC

SPI

I2C

2 × MCC

2 × SMC

Interrupt

Timers

Baud Rate

Parallel I/O

Generators

Controller

Dual Ported

RAM

Program

Sequencer Address

File

Data ALU

File

Address

ALU Data

ALU

64/32-bit

System

Bus

Interrupts

EOnCE™JTAG

2 × SDM A

RISC

Interface

DMA

Engine

Bridge

Q2PPC

Bridge

Boot

ROM

SRAM

512 KB

128-bit QBus

MEMC

L1 Interface

HDI16

MEMC

{

PIC

EFCOP

SIC_EXT

SIC Interrupts

The Freescale MSC8101

16-bit DSP is the first

member of the family of

DSPs based on the

StarCore SC140 DSP core.

The MSC8101 is available

in three core speed levels:

250, 275, and 300 MHz.

What’s Ne w?

Rev. 19 includes the following

changes:

•Table 2-4 changes VIL

reference for signal low

input current to 0.8 V..

MSC8101 Technical Data, Rev. 19

ii Freesca le Sem ico nd uctor

Table of Contents

MSC8101 Features .................................................................................................................................................................................... iii

Target Application s............................. ...................................... ...................................... ............................................................................iv

Product Documentation ..............................................................................................................................................................................iv

Chapter 1 Signals/Connections

1.1 Power Signals ........................................................................................................................................................................ 1-4

1.2 Clock Signals.........................................................................................................................................................................1-4

1.3 Reset, Conf ig uration, and EOnCE Even t Signals.................. ................................................................................................1-5

1.4 System Bus, HDI16, and Interrupt Signals............................................................................................................................ 1-6

1.5 Memory Controller Signals ................................................................................................................................................. 1-13

1.6 CPM Ports.......... ............... ................................ ................................ ................................................................................... 1-15

1.7 JTAG Test Access Port Signals............................................................................................................................................ 1-36

1.8 Reserve d Signals......... ...................................... ...................................... ............................................................................. 1-36

Chapter 2 Physical and Electrical Specifications

2.1 Absolute Maximum Ratings.................................................................................................................................................. 2-1

2.2 Recommende d Operating Conditi ons. ........ ............................................ ............................................................................... 2-2

2.3 Thermal Characterist ics............................ ...................................... ....................................................................................... 2-2

2.4 DC Electrical Characteristics................................................................................................................................................. 2-3

2.5 Clock Configuration .............................................................................................................................................................. 2-4

2.6 AC Timings............................................................................................................................................................................2-7

Chapter 3 Packaging

3.1 FC-PBGA Package Description.............................................................................................................................................3-1

3.2 Lidded FC-PBGA Package Mechanical Drawing............................... ................................. ............................................... 3-31

Chapter 4 Design Considerations

4.1 Thermal Desi gn Consi d er ations........................................................... .................................................................................. 4-1

4.2 Electrical Design Considerations........................................................................................................................................... 4-1

4.3 Power Considerations............................................................................................................................................................ 4-2

4.4 Layout Practices.......... ........................................................ ................................................................................................... 4-3

Ordering and Contact Information.................................................................................................... ..... ......................Back Cover

Data Sheet Conventions

pin and pin-

out Although the device package does not have pins, the term pins and pin-out are used for

convenience and indicate specific signal locations within the ball-grid array.

OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pi n is ac tive

when low.)

“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples: Signal/Symbol Logic State Signal State Voltage

PIN True Asserted VIL/VOL

PIN False Deasserted VIH/VOH

PIN True Asserted VIH/VOH

PIN False Deasserted VIL/VOL

Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor iii

MSC8101 Features

• SC140 core

— Architecture optimized for efficient C/C++ code compilation

— Four 16-bit ALUs and two 32-bit AGUs

— 1200 DSP MMACS running at 300 MHz

— Very low power dissi pation

— Variable-length execution set (VLES) ex ecution model

— JTAG/Enhanced OnCE debug port

• Communications processor module (CPM)

— Programma ble protocol machine using a 32-bit RISC engine

— 155 Mbps ATM interface (including AAL 0/1/2/5)

— 10/100 Mbit Ethernet interface

— Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface

— HDLC support up to T3 rates, or 256 channels

• 64- or 32-bit wide bus interface

— Support for bursts for high efficiency

— Glueless interface to 60x-compatible bus systems

— Multi-master support

• Enhanced filter coprocessor (EFCOP)

— Independently and concurrently executes long filters (such as echo cancellation)

— Runs at 250/275/300 MHz and provides 250/275/300 MMACS performance

• Programmable memory controller

— Control for up to eight banks of external memory

— User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM,

EPROM, and Flash memory) and other user-definable peripherals

— Dedicated pipelined SDRAM memory interface

• Large internal SRAM

— 256K 16-bit words (512 KB)

— Unified program and data space configurable by the application

— Word and byte addressable

• DMA controller

— 16 DMA channels, FIFO based, with burst capabilities

— Sophisticated addressing capabilities

• Small foot print package

—17 mm × 17 mm lidded FC-PBGA lead-bearing or lead-free package

• Very low power consumption

— Separate power supply for internal logic (1.6 V) and for I/O (3.3 V)

• Enhanced 16-bit parallel host in terface (HDI16)

— Supports a variety of microcontroller, microprocessor, and DSP bus interfaces

• Phase-lock loops (PLLs)

—System PLL

— CPM DPLLs (SCC and SCM)

• Process technology

— 0.13 micron copper interconnect process technology

MSC8101 Technical Data, Rev. 19

iv Freesca le Sem ico nd uctor

Target Applications

The MSC8101 targets applications requiring very high performance, very large amounts of internal memory, and

such netw orki ng cap abi li ti es as:

• Third-generation wideband wireless infrastructure systems

• Packet Telephony systems

• Multi-channel mod e m banks

• Multi-channel xDS L

Product Documentation

The documents listed in Table 1 are required for a complete description of the MSC8101 and are necessary to

design properly with the part. Documentation is available from the following sources (see back cover for details):

• A local Freescale distributor

• A Freescale Semiconductor sales office

• A Freescale Semiconductor Literature Distribution Center

• The wor ld wide web (WWW)

Table 1. MSC8101 Documentation

Name Description Order Number

MSC8101

Technical Data MSC8101 features list and physical, electrical, timing, and package

specifications MSC8101/D

MSC8101 User’s Guide Detailed functional description of the MSC8101 memory

configuration, operation, and register programming MSC8101UG/D

MSC8101 Pocket Guide Quick reference information for application development. MSC8101PG/D

MSC8101 Reference Manual Detailed description of the MSC8101 processor core and instruction

set MSC8101RM/D

SC140 DSP Core Reference Manual Detailed description of the SC140 family processor core and

instruction set MNSC140CORE/D

Application Notes Documents describing specific applications or optimized device

operation including code examples See the MSC8101 product

website

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-1

Signals/Connections 1

The MSC8101 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and

Figure 1-2. Table 1-1 lists the functional groups, states the number of signal connections in each group, and

references the table that gives details on multiplexed signals within each group. Figure 1-1 shows MSC8101

external signals organized by function. Figure 1-2 indicates how the parallel input/output (I/O) ports signals are

multiplexed. Because the parallel I/O design supported by the MSC8101 communications processor module

(CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins are not numbered

sequentially.

Table 1-1. MSC8101 Functional Signal Groupings

Functional Group Number of Signal

Connections Detailed Description

Power (VCC, VDD, and GND) 80 Table 1-2 on page 1-4

Clock 6Table 1-3 on page 1-4

Reset, configuration, and EOnCE 11 Table 1-4 on page 1-5

System bus, HDI16, and interrupts 133 Table 1-5 on page 1-7

Memory Controller 27 Table 1-6 on page 1-13

CPM Input/Output Parallel Ports Port A 26 Table 1-7 on page 1-16

Port B 14 Table 1-8 on page 1-21

Port C 18 Table 1-9 on page 1-24

Port D 8 Table 1-10 on page 1-33

JTAG Tes t Acc ess Port 5 Table 1-11 on page 1-36

Reserved (denotes connections that are always reserved) 5 Table 1-12 on page 1-36

MSC8101 Technical Data, Rev. 19

1-2 Freescale Sem ico nd uctor

Signals/Connections

32 ↔A[0–31]

VDD →14 5↔TT[0–4]

VDDH →25 4↔TSIZ[0–3]

VCCSYN →1 1 ↔TBST

VCCSYN1 →1 1 ↔IRQ1 GBL

3→Reserved BADDR[29–31] IRQ[2–3, 5]

GND →37 1↔BR

GNDSYN →1 1 ↔BG

GNDSYN1 →1 1 ↔ABB IRQ2

1↔TS

1↔AACK

1←ARTRY

For the signals

multiplexed on

Ports A–D,

see Figure 1-2

Port A 1↔DBG

PA[31–6] ↔26 1↔DBB IRQ3

32 ↔D[0–31]

Port B HDI16 Signals

PB[31–18] ↔14 16 ↔D[32–47] HD[0–15]

4↔D[48–51] HA[0–3]

Port C 1↔D52 HCS1

PC[31–2 2, 15–12, 7–4] ↔18 Single DS Double DS

1↔D53 HRW HRD/HRD

Port D 1↔D54 HDS/HDS HWR/HWR

PD[31–29, 19–16, 7] ↔8Single HR Double HR

1↔D55 HREQ/HREQ HTRQ/HTRQ

1↔D56 HACK/HACK HRRQ/HRRQ

TMS →1 1 ↔D57 HDSP

TDI →1 1 ↔D58 HDDS

TCK →1 1 ↔D59 H8BIT

TRST →1 1 ↔D60 HCS2

TDO ←1 4 ↔D[61–63] Reserved

1←Reserved DP0 Reserved EXT_Br2

EOnCE Event RESET

Configuration 1↔IRQ1 DP1 IRQ1 EXT_BG2

EED ↔1 1 ↔IRQ2 DP2 Reserved EXT_DBG2

EE0 DBREQ ↔1 1 ↔IRQ3 DP3 Reserved EXT_BR3

EE1 HPE ↔1 1 ↔IRQ4 DP4 DREQ3 EXT_BG3

EE[2–3] ↔2 1 ↔IRQ5 DP5 DREQ4 EXT_DBG3

EE[4–5] BTM[0–1] ↔2 1 ↔IRQ6 DP6 DACK3 IRQ6

PORESET →1 1 ↔IRQ7 DP7 DACK4 IRQ7

RSTCONF →1 1 ↔TA

HRESET ↔1 1 ↔TEA

SRESET ↔1 1 ←NMI

1→NMI_OUT

1↔PSDVAL

1↔IRQ7 INT_OUT

8→CS[0–7]

CLKIN →1 1 →BCTL1

BNK-

SEL[0–2] TC[0–2] MODCK[1–3] →3 2 →BADDR[27–28]

CLKOUT ←1 1 →ALE

DLLIN →1 1 →BCTL0

8→PWE[0–7] PSDDQM[0–7] PBS[0–7]

1→PSDA10 PGPL0

1→PSDWE PGPL1

1→POE PSDRAS PGPL2

TEST →1 1 →PSDCAS PGPL3

THERM[1–2] ↔2 1 ↔PGTA PUPMWAIT PPBS PGPL4

SPARE1, SPARE5 ↔2 1 →PSDAMUX PGPL5

Note: Refer to the System Interface Unit (SIU ) chapter in the MSC8101 Reference Manual for details on how to configure these pins.

Figure 1-1. MSC8 101 Ex terna l Sig nals

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-3

FCC1

ATM/UTOPIA

MPHY

Master

mux poll

or Slave

MPHY

Master

dir. poll

FCC1

Ethernet

MII

HDLC/

transp. HDLC

Serial Nibble GPIO

TXENB COL PA31

TXCLAV TXCLAV0 CRS RTS PA30

TXSOC (master) TX_ER PA29

RXENB TX_EN PA28

RXSOC

(slave) RX_DV PA27

RXCLAV RXCLAV0 RX_ER SDMA PA26

TXD0 MSNUM0 PA25

TXD1 MSNUM1 PA24

TXD2 PA23

TXD3 PA22

TXD4 TXD3 TXD3 PA21

TXD5 TXD2 TXD2 PA20

TXD6 TXD1 TXD1 PA19

TXD7 TXD0 TXD TXD0 PA18

RXD7 RXD0 RXD RXD0 PA17

RXD6 RXD1 RXD1 PA16

RXD5 RXD2 RXD2 PA15

RXD4 RXD3 RXD3 PA14

RXD3 MSNUM2 PA13

RXD2 SI1 MSNUM3 PA12

RXD1 TDMA1 MSNUM4 PA11

RXD0 SMC2 Serial Nibble MSNUM5 PA10

SMTXD L1TXD L1TXD0 PA9

FCC2 SMRXD L1RXD L1RXD0 PA8

Ethernet

MII

HDLC/

transp. HDLC SMSYN L1TSYNC SI2 PA7

Serial Nibble SCC2 L1RSYNC TDMB2 PA6

TX_ER RXD L1TXD PB31

RX_DV TXD L1RXD PB30

TX_EN L1RSYNC PB29

RX_ER RTS RTS/TENA L1TSYNC PB28

COL TDMC2

L1TXD PB27

CRS L1RXD PB26

TXD3 TXD3 L1TXD3 L1TSYNC PB25

TXD2 TXD2 L1RXD3 L1RSYNC PB24

TXD1 TXD1 L1RXD2 TDMD2

L1TXD PB23

TXD0 TXD TXD0 L1RXD1 L1RXD PB22

RXD0 RXD RXD0 L1TXD2 L1TSYNC PB21

RXD1 RXD1 L1TXD1 L1RSYNC I2CPB20

RXD2 RXD2 SDA PB19

RXD3 RXD3 SCL BRGs Clocks Timers PB18

Ext. Req. BRG1O CLK1 TGATE1 PC31

EXT1 BRG2O CLK2 TOUT1 PC30

SCC1

CTS/CLSN BRG3O CLK3 TIN2 PC29

CTS/CLSN SIU Ti m er I np u t BRG4O CLK4 TIN1/

TOUT2 PC28

CLK5 BRG5O CLK5 TGATE2 PC27

TMCLK BRG6O CLK6 TOUT3 PC26

DMA

DACK2 BRG7O CLK7 TIN4 PC25

Ext. Req. DREQ2 BRG8O CLK8 TIN3/

TOUT4 PC24

EXT2 DACK1 CLK9 PC23

SCC1 LIST1 DREQ1 CLK10 PC22

TXADDR0 CTS/CLSN SMTXD PC15

RXADDR0 CD/RENA LIST2 PC14

TXADDR1 CTS/CLSN LIST4 PC13

RXADDR1 FCC1 CD/RENA LIST3 PC12

TXADDR2 TXADDR2/

TXCLAV1 CTS LIST1 PC7

RXADDR2 RXADDR2/

RXCLAV1 CD LIST2 PC6

FCC2 SMC1

CTS SMTXD LIST3 PC5

CD SMRXD LIST4 PC4

RXD DRACK1/DONE1 PD31

TXD DRACK2/DONE2 PD30

RXADDR3 RXCLAV2 RTS/TENA SPI PD29

TXADDR4 TXCLAV3 SPISEL BRG1O PD19

RXADDR4 RXCLAV3 SPICLK PD18

RXPRTY SPIMOSI BRG2O PD17

TXPRTY SPIMISO PD16

TXADDR3 TXCLAV2 SMSYN PD7

Figure 1-2. CPM Port A–D Pin Multiplexed Functionality

MSC8101 Technical Data, Rev. 19

1-4 Freescale Sem ico nd uctor

Signals/Connections

1.1 Power Signals

1.2 Clock Signals

Table 1-2. Power and Ground Signal Inputs

Power Name Description

VDD Internal Logic Power

VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with

an extremely low impedance path to the VDD power rail.

VDDH Input/Out put Power

This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.

VCCSYN System PLL Power

VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input

should be provided with an extremely low impedance path to the VCC powe r rail.

VCCSYN1 SC140 PLL Power

VCC dedicated for use with the SC140 core PLL. The voltage should be well-regulated and the input should be provided

with an extremely low impedance path to the VCC power rail.

GND System Ground

An isolated ground for the internal processing logic. This connection must be tied externally to all chip ground

connections, except GNDSYN and GNDSYN1. The user must provide adequate external decoupling capacitors.

GNDSYN System PLL Ground

Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to

ground.

GNDSYN1 SC140 PL L Ground 1

Ground dedicated for SC140 core PLL use. The connection should be provided with an extremely low-impedance path

to ground.

Table 1-3. Clock Signals

Signal Name Type Signal Description

CLKIN Input Clock In

Primary clock input to the MSC8101 PLL.

MODCK1

TC0

BNKSEL0

Input

Output

Clock Mode Input 1

Defines the operating mode of internal clock circuits.

Transfer Code 0

Supplies information that can be useful for debugging bus transactions initiated by the MSC8101.

Bank Select 0

Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.

MODCK2

TC1

BNKSEL1

Input

Output

Clock Mode Input 2

Defines the operating mode of internal clock circuits.

Transfer Code 1

Supplies information that can be useful for debugging bus transactions initiated by the MSC8101.

Bank Select 1

Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.

MODCK3

TC2

BNKSEL2

Input

Output

Clock Mode Input 3

Defines the operating mode of internal clock circuits.

Transfer Code 2

Supplies information that can be useful for debugging bus transactions initiated by the MSC8101.

Bank Select 2

Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.

Reset, Configuration, and EOnCE Event Signals

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-5

1.3 Reset, Configuration, and EOnCE Event Signals

CLKOUT Output Clock Out

The system bus clock.

DLLIN Input DLLIN

Synchronizes with an external device.

Note: When the DLL is disabled, connect this signal to GND.

Table 1-4. Reset, Configuration, and EOnCE Event Signals

Signal Name Type Signal Description

DBREQ

EE01

Input

Output

Debug Request

Determines whether to go into SC140 Debug mode when PORESET is deasserted.

Enhanced OnCE (EOnCE) Event 0

After PORESET is deasserted, you can configure EE0 as an input (default) or an output.

Debug request, enable Address Event Detection Channel 0, or generate an EOnCE event.

Detection by Address Event Detection Channel 0. Used to trigger external debugging equipment.

HPE

EE11

Input

Output

Host Port Enab le

When this pin is asserted during PORESET, the Host port is enabled, the system data bus is 32 bits

wide, and the Host must program the reset configuration word.

EOnCE Event 1

After PORESET is deasserted, you can configure EE1 as an input (default) or an output.

Enable Address Eve nt Detection Channel 1 or generate an EOnCE event.

Debug Acknowledge or detection by Address Event Detection Channel 1. Used to trigger external

debugging equipment.

EE21

Input

Output

EOnCE Event 2

After PORESET is deasserted, you can configure EE2 as an input (default) or an output.

Enable Address Eve nt Detection Channel 2 or generate an EOnCE event or enable the Event

Counter.

Detection by Address Event Detection Channel 2. Used to trigger external debugging equipment.

EE31

Input

Output

EOnCE Event 3

After PORESET is deasserted, you can configure EE3 as an input (default) or an output. See the

emulation and debug chapter in the SC140 DSP Core Reference Manual for details on the ERCV

Enable Address Eve nt Detection Channel 3 or generate one of the EOnCE events.

The DSP has read the EOnCE Receive Register (ERCV). Triggers external debugging equipment.

Table 1-3. Clock Signals (Continued)

Signal Name Type Signal Description

MSC8101 Technical Data, Rev. 19

1-6 Freescale Sem ico nd uctor

Signals/Connections

1.4 Syste m Bus, HD I16, and Interrupt Signa ls

The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines.

Individual assignment of a signal to a specific signal line is configured through registers in the System Interface

Unit (SIU) and the Host Interface (HDI16). 1-5 describes the signals in this group.

Note: To boot from the host interface, the HDI16 must be enabled by pulling up the HPE signal line during

PORESET. The configur ation word must then be loaded fro m the host. The confi guration word must set the

Intern al Spa ce Port Size bit in the Bus Cont ro l Re gi st er (BCR[ ISPS] ) to change the syste m data bus width

from 64 bits to 32 bits and reassign the upper 32 bits to their HDI16 functions. Never set the Host Port

Enable (HEN) bit in the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is

first changed from 64 bits to 32 bits. Otherwise, unpredictable operation may occur.

BTM[0–1]

EE41

EE51

Input

Output

Input

Output

Boot Mode 0–1

Determines the MSC8101 boot mode when PORESET is deasserted. See the emulation and debug

chapter in the SC140 DSP Core Reference Manual for details on how to set these pins.

EOnCE Event 4

After PORESET is deasserted, you can configure EE4 as an input (default) or an output. See the

emulation and debug chapter in the SC140 DSP Core Reference Manual for details on the ETRSMT

Enable Address Eve nt Detection Channel 4 or generate an EOnCE event.

The DSP wrote the EOnCE Transmit Register (ETRSMT). Triggers external debugging equipment.

EOnCE Event 5

After PORESET is deasserted, you can configure EE5 as an input (default) or an output.

Enable Address Eve nt Detection Channel 5.

Detection by Address Event Detection Channel 5. Triggers external debugging equipment.

EED1

Input

Output

Enhanced OnCE (EOnCE) Event Detection

After PORESET is deasserted, you can configure EED as an input (default) or output:

Enable the Data Event Detection Channel.

Detection by the Data Event Detection Channel. Triggers external debugging equipment.

PORESET Input Power-On Reset

When asserted, this line causes the MSC8101 to enter power-on reset state.

RSTCONF Input Reset Configuration

Used during reset configuration sequence of the chip. A detailed explanation of its function is

provided in the “Power-On Reset Flow” and “Hardware Reset Configuration” sections of the

MSC8101 Reference Manual.

HRESET Input Hard Reset

When asserted, this open-drain line causes the MSC8101 to enter the hard reset state.

SRESET Input Soft Reset

When asserted, this open-drain line causes the MSC8101 to enter the soft reset state.

Note: See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on how to configure these pins.

Table 1-4. Reset, Configuration, and EOnCE Event Signals (Continued)

Signal Name Type Signal Description

System Bus, HDI16, and Interrupt Signals

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-7

Although there are eight interrupt request (IRQ) connections to the core processor, there are multiple external lines

that can co nnect to these inter nal signal lines. Afte r reset, the default con figurati on includes two IRQ1 and two IRQ7

input lines. The designer must select one line for each required interrupt and reconfigure the other external signal

line or lines for alternate functions.

Table 1-5. System Bus, HDI16, and Interrupt Signals

Signal Data Flow Description

A[0–31] Input/Output Address Bus

When the MSC8101 is in external master bus mode, these pins function as the address bus. The

MSC8101 drives the address of its internal bus masters and responds to addresses generated by

external bus masters. When the MSC8101 is in Internal Master Bus mode, these pins are used as

address lines connected to memory devices and are controlled by the MSC8101 memory controller.

TT[0–4] Input/Output Bus Transfer Type

The bus master drives these pins during the address tenure to specify the type of transaction.

TSIZ[0–3] Input/Output Transfer Size

The bus master drives these pins with a value indicating the number of bytes transferred in the

current transaction.

TBST Input/Output Bus T ransfer Burst

The bus master asserts this pin to indicate that the current transaction is a burst transaction

(transfers four quad words).

IRQ1

GBL

Input

Input/Output

Interr upt Re que st 11

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Global1

When a master within the chip initiates a bus transaction, it drives this pin. When an external master

initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is

global and it should be snooped by caches in the system.

Reserved

BADDR29

IRQ2

Output

Input

The primary configuration is reserved.

Burst Address 291

One of five outputs of the memory controller. These pins connect directly to memory devices

controlled by the MSC8101 memory controller.

Interr upt Re que st 21

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Reserved

BADDR30

IRQ3

Output

Input

The primary configuration is reserved.

Burst Address 301

One of five outputs of the memory controller. These pins connect directly to memory devices

controlled by the MSC8101 memory controller.

Interr upt Re que st 31

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Reserved

BADDR31

IRQ5

Output

Input

The primary configuration is reserved.

Burst Address 311

One of five outputs of the memory controller. These pins connect directly to memory devices

controlled by the MSC8101 memory controller.

Interr upt Re que st 51

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

MSC8101 Technical Data, Rev. 19

1-8 Freescale Sem ico nd uctor

Signals/Connections

BR Input/Output

Output

Input

Bus Request2

An output when an external arbiter is used. The MSC8101 asserts this pin to request ownership of

the bus.

An input when an internal arbiter is used. An external master should assert this pin to request bus

ownership from the internal arbiter.

BG Input/Output

Output

Input

Bus Grant2

An output when an internal arbiter is used. The MSC8101 asserts this pin to grant bus ownership to

an external bus master.

An input when an external arbiter is used. The external arbiter should assert this pin to grant bus

ownership to the MSC8101.

ABB

IRQ2

Input/Output

Output

Input

Address Bus Busy1

The MSC8101 asserts this pin for the duration of the address bus tenure. Following an address

acknowledge (AACK) signal, which terminates the address bus tenure, the MSC8101 deasserts

ABB for a fraction of a bus cycle and then stops driving this pin.

The MSC8101 does not assume bus ownership while it this pin is asserted by an external bus

master.

Interr upt Re que st 21

One of the eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

TS Input/Output Bus Transfer Start

Signals the beginning of a new address bus tenure. The MSC8101 asserts this signal when one of

its internal bus masters (SC140 core or DMA controller) begins an address tenure. When the

MSC8101 senses this pin being asserted by an external bus master, it responds to the address bus

tenure as required (snoop if enabled, access internal MSC8101 resources, memory controller

support).

AACK Input/Output Address Acknowledge

A bus slave asserts this signal to indicate that it identified the address tenure. Assertion of this signal

terminates the address tenure.

ARTRY Input Address Retry

Assertion of this signal indicates that the bus transaction should be retried by the bus master. The

MSC8101 asserts this signal to enforce data coherency with its internal cache and to prevent

deadlock situations.

DBG Input/Output

Output

Input

Data Bus Grant2

An output when an internal arbiter is used. The MSC8101 asserts this pin as an output to grant data

bus ownership to an external bus master.

An input when an external arbiter is used. The external arbiter should assert this pin as an input to

grant data bus ownership to the MSC8101.

DBB

IRQ3

Input/Output

Output

Input

Data Bus Busy1

The MSC8101 asserts this pin as an output for the duration of the data bus tenure. Following a TA,

which terminates the data bus tenure, the MSC8101 deasserts DBB for a fraction of a bus cycle and

then stops driving this pin.

The MSC8101 does not assume data bus ownership while DBB is asserted by an external bus

master.

Interr upt Re que st 31

One of the eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

D[0–31] Input/Output Data Bus Most Significant Word

In write transactions the bus master drives the valid data on this bus. In read transactions the slave

drives the valid data on this bus. In Host Port Disabled mode, these 32 bits are part of the 64-bit data

bus. In Host Port Enabled mode, these bits are used as the bus in 32-bit mode.

Table 1-5. System Bus, HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

System Bus, HDI16, and Interrupt Signals

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-9

D[32–47]

HD[0–15]

Input/Output

Data Bus Bits 32–47

In write transactions the bus master drives the valid data on this bus. In read transactions the slave

drives the valid data on this bus.

Host Data2

When the HDI16 interface is enabled, these signals are lines 0-15 of the bidirectional tri-state data

bus.

D[48–51]

HA[0–3]

Input/Output

Input

Data Bus Bits 48–51

In write transactions the bus master drives the valid data on these pins. In read transactions the

slave drives the valid data on these pins.

Host Address Line 0–33

When the HDI16 interface bus is enabled, these lines address internal host registers.

D52

HCS1

Input/Output

Input

Data Bus Bit 52

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Chip Select3

When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select

is a logical OR of HCS1 and HCS2.

D53

HRW

HRD/HRD

Input/Output

Input

Data Bus Bit 53

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Read Write Select3

When the HDI16 interface is enabled in Single Strobe mode, this is the read/write input (HRW).

Host Read Strobe3

When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the read

data strobe Schmitt trigger input (HRD/HRD). The polarity of the data strobe is programmable.

D54

HDS/HDS

HWR/HWR

Input/Output

Input

Data Bus Bit 54

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Data Strobe3

When the HDI16 is programmed to interface with a single data strobe host bus, this pin is the data

strobe Schmitt trigger input (HDS/HDS). The polarity of the data strobe is programmable.

Host Write Data Strobe3

When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the write

data strobe Schmitt trigger input (HWR/HWR). The polarity of the data strobe is programmable.

D55

HREQ/HREQ

HTRQ/HTRQ

Input/Output

Output

Data Bus Bit 55

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Request3

When the HDI16 is programmed to interface with a single host request host bus, this pin is the host

request output (HREQ/HREQ). The polarity of the host request is programmable. The host request

may be programmed as a driven or open-drain output.

Transmit Host Request3

When the HDI16 is programmed to interface with a double host request host bus, this pin is the

transmit host request output (HTRQ/HTRQ). The signal can be programmed as driven or open

drain. The polarity of the host request is programmable.

Table 1-5. System Bus, HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

MSC8101 Technical Data, Rev. 19

1-10 Freescale Semico nd uct or

Signals/Connections

D56

HACK/HACK

HRRQ/HRRQ

Input/Output

Output

Data Bus Bit 56

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Acknowledge3

When the HDI16 is programmed to interface with a single host request host bus, this pin is the host

acknowledge Schmitt trigger input (HACK). The polarity of the host acknowledge is programmable.

Receive Host Request3

When the HDI16 is programmed to interface with a double host request host bus, this pin is the

receive host request output (HRRQ/HRRQ). The signal can be programmed as driven or open drain.

The polarity of the host request is programmable.

D57

HDSP

Input/Output

Input

Data Bus Bit 57

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Data Strobe Polarity3

When the HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP).

D58

HDDS

Input/Output

Input

Data Bus Bit 58

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Dual Data Strobe3

When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS).

D59

H8BIT

Input/Output

Input

Data Bus Bit 59

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

H8BIT3

When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit or 16-bit mode.

D60

HCS2

Input/Output

Input

Data Bus Bit 60

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Chip Select 3

When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select

is a logical OR of HCS1 and HCS2.

D[61–63]

Reserved

Input/Output Data Bus Bits 61–63

Used only in 60x-mode-only mode. In write transactions the bus master drives the valid data on this

bus. In read transactions the slave drives the valid data on this bus.

These dedicated signals are reserved when the HDI16 is enabled.3

Reserved

DP0

EXT_BR2

Input

Input/Output

Input

The primary configuration is reserved.

Data Parity 01

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity zero pin should give odd parity (odd number of ones) on the group of signals that includes

data parity 0 and D[0–7].

External Bus Request 21,2

An external master asserts this pin to request bus ownership from the internal arbiter.

Table 1-5. System Bus, HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

System Bus, HDI16, and Interrupt Signals

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-11

IRQ1

DP1

EXT_BG2

Input

Input/Output

Output

Interr upt Re que st 11

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 11

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity one pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 1 and D[8–15].

External Bus Grant 21,2

The MSC8101 asserts this pin to grant bus ownership to an external bus master.

IRQ2

DP2

EXT_DBG2

Input

Input/Output

Output

Interr upt Re que st 21

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 21

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity two pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 2 and D[16–23].

External Data Bus Grant 21,2

The MSC8101 asserts this pin to grant data bus ownership to an external bus master.

IRQ3

DP3

EXT_BR3

Input

Input/Output

Input

Interr upt Re que st 31

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 31

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity three pin should give odd parity (odd number of ones) on the group of signals that includes

data parity 3 and D[24–31].

External Bus Request 31,2

An external master asserts this pin to request bus ownership from the internal arbiter.

IRQ4

DP4

DREQ3

EXT_BG3

Input

Input/Output

Input

Output

Interr upt Re que st 41

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 41

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity four pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 4 and D[32–39].

DMA Request 31

An external peripheral uses this pin to request DMA service.

External Bus Grant 31,2

The MSC8101 asserts this pin to grant bus ownership to an external bus master.

Table 1-5. System Bus, HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

MSC8101 Technical Data, Rev. 19

1-12 Freescale Semico nd uct or

Signals/Connections

IRQ5

DP5

DREQ4

EXT_DBG3

Input

Input/Output

Input

Output

Interr upt Re que st 51

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 51

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity five pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 5 and D[40–47].

DMA Request 41

An external peripheral uses this pin to request DMA service.

External Data Bus Grant 31,2

The MSC8101 asserts this pin to grant data bus ownership to an external bus master.

IRQ6

DP6

DACK3

Input

Input/Output

Output

Interr upt Re que st 61

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 61

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity six pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 6 and D[48–55].

DMA Acknowledge 31

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

IRQ7

DP7

DACK4

Input

Input/Output

Output

Interr upt Re que st 71

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 71

The master or slave that drives the data bus also drives the data parity signals. The value driven on

the data parity seven pin should give odd parity (odd number of ones) on the group of signals that

includes data parity 7 and D[56–63].

DMA Acknowledge1

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

TA Input/Output Transfer Acknowledge

Indicates that a data beat is valid on the data bus. For single beat transfers, assertion of TA

indicates the termination of the transfer. For burst transfers, TA is asserted four times to indicate the

transfer of four data beats with the last assertion indicating the termination of the burst transfer.

TEA Input/Output Transfer Error Acknowledge

Indicates a bus error. masters within the MSC8101 monitor the state of this pin. The MSC8101

internal bus monitor can assert this pin if it identifies a bus transfer that is hung.

NMI Input Non-Maskable Interrupt

When an external device asserts this line, the MSC8101 NMI input is asserted.

NMI_OUT Output Non-Maskable Interrupt

Driven from the MSC8101 internal interrupt controller. Assertion of this output indicates that a

non-maskable interrupt, pending in the MSC8101 internal interrupt controller, is waiting to be

handled by an external host.

PSDVAL Input/Output Data Valid

Indicates that a data beat is valid on the data bus. The difference between the TA pin and PSDVAL

is that the TA pin is asserted to indicate data transfer terminations while the PSDVAL signal is

asserted with each data beat movement. Thus, when TA is asserted, PSDVAL is asserted, but when

PSDVAL is asserted, TA is not necessarily asserted. For example when the SDMA initiates a double

word (2x64 bits) transfer to a memory device that has a 32-bit port size, PSDVAL is asserted three

times without TA, and finally both pins are asserted to terminate the transfer.

Table 1-5. System Bus, HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

Memory Controller Signals

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-13

1.5 Memory Contr oller Signals

Refer to the memory controller chapter in the MSC8101 Reference Manual (MSC8101RM/D) for detailed

information about configuring these signals.

IRQ7

INT_OUT

Input

Output

Interr upt Re que st 71

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Interrupt Output1

Driven from the MSC8101 internal interrupt controller. Assertion of this output indicates that an

unmasked interrupt is pending in the MSC8101 internal interrupt controller.

Notes: 1. See the SIU chapter in the MSC8101 Reference Manual for details on how to configure these pins.

2. When used as the bus control arbiter for the system bus, the MSC8101 can support up to three external bus masters. Each

master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG,

EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to

indicate whether the external master is or is not a MSC8101 master device. See the Bus Configuration Register (BCR)

description in the SIU chapter in the MSC8101 Reference Manual for details on how to configure these pins. The second and

third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins

(BR/BG/DBG) have a dual function. When the MSC8101 is not the bus arbiter, these signals (BR/BG/DBG) are used by the

MSC8101 to obtain master control of the bus.

3. See the host interface (HDI16) chapter in the MSC8101 Reference Manual for details on how to configure these pins.

Table 1-6. Memory Controller Signals

Signal Data Flow Description

CS[0–7] Output Chip Select

Enable specific memory devices or peripherals connected to MSC8101 buses.

BCTL1 Output Buffer Control 1

Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined

by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8101

Reference Manual for details.

BADDR[27–28] Output Burst Address 27–28

Two of five outputs of the memory controller. These pins connect directly to memory devices

controlled by the MSC8101 memory controller.

ALE Output Address Latch Enable

Controls the external address latch used in external master bus configuration.

BCTL0 Output Buffer Control 0

Controls buffers on the data bus. The exact function of this pin is defined by the value of

SIUMCR[BCTLC]. See the System I nterface Unit (SIU ) chapter in the MSC8101 Reference Manual

for details.

PWE[0–7]

PSDDQM[0–7]

PBS[0–7]

Output

Bus Write Enable

Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins select byte lanes for

write operations.

Bus SDRAM DQM

Outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

Bus UPM Byte Select

Outputs of the User-Programmable Machine (UPM ) in the memory controller. These pins select

specific byte lanes during memory operations. The timing of these pins is programmed in the UPM.

The actual driven value depends on the address and size of the transaction and the port size of the

accessed device.

Table 1-5. System Bus, HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

MSC8101 Technical Data, Rev. 19

1-14 Freescale Semico nd uct or

Signals/Connections

PSDA10

PGPL0

Output

Bus SDRAM A10

Output from the bus SDRAM controller. This pin is part of the address when a row address is driven.

It is part of the command when a column address is driven.

Bus UPM General-Purpose Line 0

One of six general-purpose output lines of the UPM. The values and timing of this pin are

programmed in the UPM.

PSDWE

PGPL1

Output

Bus SDRAM Write Enable

Output from the bus SDRAM controller. This pin should connect to the SDRAM WE input signal.

Bus UPM General-Purpose Line 1

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

POE

PSDRAS

PGPL2

Output

Bus Output Enable

Output of the bus GPCM. Controls the output buffer of memory devices during read operations.

Bus SDRAM RAS

Output from the bus SDRAM controller. This pin should connect to the SDRAM Row Address Strobe

(RAS) input signal.

Bus UPM General-Purpose Line 2

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

PSDCAS

PGPL3

Output

Bus SDRAM CAS

Output from the bus SDRAM controller. This pin should connect to the SDRAM Column Address

Strobe (CAS) input signal.

Bus UPM General-Purpose Line 3

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

PGTA

PUPMWAIT

PPBS

PGPL4

Input

Output

GPCM TA

Terminates transactions during GPCM operation. Requ ires an external pull up resistor for proper

operation.

Bus UPM Wait

Input to the UPM. An external device can hold this pin high to force the UPM to wait until the device

is ready for the operation to continue.

Bus Parity Byte Select

In systems that store data parity in a separate chip, this output is the byte-select for that chip.

Bus UPM General-Purpose Line 4

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

PSDAMUX

PGPL5

Output

Bus SDRAM Address Multiplexer

Controls the SDRAM address multiplexer when the MSC8101 is in External Master mode.

Bus UPM General-Purpose Line 5

One of six general-purpose output lines from the UPM. The values and timing of this pin are

programmed in the UPM.

Table 1-6. Memory Controller Signals (Continued)

Signal Data Flow Description

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-15

1.6 CPM Ports

The MSC8101 CPM supports the subset of MPC8260 signals as described below.

• The MSC8101 CPM includes the following set of communication controllers:

• Two full-duplex fast serial communications controllers (FCCs) that support:

— Asynchronous transfer mode (ATM) through a UTOPIA 8 interface (FCC1 only)—The MSC8101 can

operate as one of the following:

°UTOPIA slave device

°UTOPIA multi-PHY master device using direct polling for up to 4 PHY devices

°UTOPIA multi-PHY master device using multiplex polling that can address up to 31 PHY devices at addresses 0–30

(address 31 is reserved as a null port).

— IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII)

— High-level data link control (HDLC) Protocol:

°Serial mode—Transfers data one bit at a time

°Nibble mode—Transfers data four bits at a time

— Transparent mode serial operation

• One FCC that opera tes with the TSA only

• Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64

Kbps each, mult iple xed on up to four TDM in terfa ces

• Two full-duplex serial communications controllers (SCCs) that support the following protocols:

— IEEE 802.3/fast Ethernet through a media-independent interface (MII)

— HDLC Protocol:

°Serial mode—Transfers data one bit at a time

°Nibble mode—Transfers data four bits at a time

— Synchronous data link control (SDLC)

— LocalTalk (HDLC-based local area network protocol)

— Universal asynchronous receiver/transmitter (UART)

— Synchronous UART (1x clock mode)

— Binary synchronous (BISYNC) communication

— Transparent mode serial operation

• Two additional SCCs that operate with the TSA only

• Two full-duplex serial management controllers (SMCs) that support the following protocols:

— General circ uit int erface (GC I)/in tegra ted se rvice s digi tal ne twork (ISDN ) monitor and C/I channels (TSA

only)

— UART

— Transparent mode serial operation

• Serial peripheral interface (SPI) support for master or slave operation

• Inter-integrated circuit (I2C) bus controller

• Time-slot assigner (TSA) that supports multiplexing from any of the SCCs, FCCs, SMCs, and two MCCs onto

four time-division multiplexed (TDM) interfaces. The TSA uses two serial interfaces (SI1 and SI2). SI1 uses

TDMA1 which supports both serial and nibble mode. SI2 does not support nibble mode and includes TDMB2,

TDMC2, and TDMD2, which operate only in serial mode.

The individual sets of externals signals associated with a specific protocol and data transfer mode are multiplexed

across any or all of the ports, as shown in Figure 1-2. The following sections describe the signals supported by

Ports A–D.

MSC8101 Technical Data, Rev. 19

1-16 Freescale Semico nd uct or

Signals/Connections

1.6.1 Port A Signals

Table 1-7. Port A Signals

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated Signal

Protocol

PA31 FCC1: TXENB

UTOPIA master

FCC1: TXENB

UTOPIA slave

FCC1: COL

MII

Output

Input

FCC1: UTOPIA Master Transmit Enable

Asserted by the MSC8101 (UTOPIA master PHY) when there is valid

transmit cell data (TXD[0–7]).

FCC1: UTOPIA Slave Transmit Enable

Asserted by an external UTOPIA master PHY when there is valid

transmit cell data (TXD[0–7]).

FCC1: Media Independent Interface Collision Detect

Asserted by an external fast Ethernet PHY when collision is detected.

PA30 FCC1: TXCLAV

UTOPIA slave

FCC1: TXCLAV

UTOPIA master, or

FCC1: TXCLAV0

UTOPIA master, Multi-PHY, direct

polling

FCC1: RTS

HDLC, Serial and Nibble

FCC1: CRS

MII

Output

Input

Output

Input

FCC1: UTOPIA Slave Transmit Cell Available

Asserted by the MSC8101 (UTOPIA slave PHY) when the MSC8101

can accept one complete ATM cell.

FCC1: UTOPIA Master Transmit Cell Available

Asserted by an external UTOPIA slave PHY to indicate that it can accept

one complete ATM cell.

FCC1: UTOPIA Master Transmit Cell Available Multi-PHY Direct

Polling

Asserted by an external UTOPIA slave PHY using direct polling to

indicate that it can accept one complete ATM cell.

FCC1: Request To Send

In the standard modem interface signals supported by FCC1 (RTS,

CTS, and CD). RTS is asynchronous with the data. RTS is typically used

in conjunction with CD. The MSC8101 FCC1 transmitter requests the

receiver to send data by asserting RTS low. The request is accepted

when CTS is returned low.

FCC1: Media Independent Interface Carrier Sense

Asserted by an external fast Ethernet PHY to indicate activity on the

cable.

PA29 FCC1: TXSOC

UTOPIA master

FCC1: TX_ER

MII

Output

FCC1: UTOPIA Transmit Start of Cell

Asserted by the MSC8101 (UTOPIA master PHY) when TXD[0–7]

contains the first valid byte of the cell.

FCC1: Media Independent Interface Transmit Error

Asserted by the MSC8101 to force propagation of transmit errors.

PA28 FCC1: RXENB

UTOPIA master

FCC1: RXENB

UTOPIA slave

FCC1: TX_EN

MII

Output

Input

Output

FCC1: UTOPIA Master Receive Enable

Asserted by the MSC8101 (UTOPIA master PHY) to indicate that

RXD[0–7] and RXSOC are to be sampled at the end of the next cycle.

RXD[0–7] and RXSOC are enabled only in cycles following those with

RXENB asserted.

FCC1: UTOPIA Master Receive Enable

Asserted by an external PHY to indicate that RXD[0–7] and RXSOC is to

be sampled at the end of the next cycle. RXD[0–7] and RXSOC are

enabled only in cycles following those with RXENB asserted.

FCC1: Media Independent Interface Transmit Enable

Asserted by the MSC8101 when transmitting data.

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-17

PA27 FCC1: RXSOC

UTOPIA slave

FCC1: RX_DV

MII

Output

Input

FCC1: UTOPIA Receive Start of Cell

Asserted by the MSC8101 (UTOPIA slave) for an external PHY when

RXD[0–7] contains the first valid byte of the cell.

FCC1: Media Independent Interface Receive Data Valid

Asserted by an external fast Ethernet PHY to indicate that valid data is

being sent. The presence of carrier sense but not RX_DV indicates

reception of broken packet headers, probably due to bad wiring or a bad

circuit.

PA26 FCC1: RXCLAV

UTOPIA slave

FCC1: RXCLAV

UTOPIA master, or

RXCLAV0

UTOPIA m a ster, Multi-PH Y , direct

polling

FCC1: RX_ER

MII

Output

Input

FCC1: UTOPIA Slave Receive Cell Available

Asserted by the MSC8101 (UTOPIA slave PHY) when one complete

ATM cell is available for transfer.

FCC1: UTOPIA Master Receive Cell Availab le

Asserted by an external PHY when one complete ATM cell is available

for tran sfer.

FCC1: UTOPIA Master Receive Cell Available 0 Direct Polling

Asserted by an external PHY when one complete ATM cell is available

for tran sfer.

FCC1: Media Independent Interface Receive Error

Asserted by an external fast Ethernet PHY to indicate a receive error,

which often indicates bad wiring.

PA25 FCC1: TXD0

UTOPIA

SDMA: MSNUM0

Output

FCC1: UTOPIA Transmit Data Bit 0

The MSC8101 outputs ATM cell octets (UTOPIA interface data) on

TXD[0–7]. TXD0 is the least significant bit. When no ATM data is

available, idle cells are inserted. A cell is 53 bytes.

Module Serial Number Bit 0

The MSNUM has 6 bits that identify devices using the serial DMA

(SDMA) modules. MSNUM[0–4] is the sub-block code of the current

peripheral controller using SDMA. MSNUM5 indicates the section,

transmit (0) or receive (1), that is active during the transfer. The

information is recorded in the SDMA transfer error registers.

PA24 FCC1: TXD1

UTOPIA

SDMA: MSNUM1

Output

FCC1: UTOPIA Transmit Data Bit 1

The MSC8101 outputs ATM cell octets (UTOPIA interface data) on

TXD[0–7]. This is bit 1 of the transmit data. TXD7 is the most significant

bit. When no ATM data is available, idle cells are inserted. A cell is 53

bytes.

Module Serial Number Bit 1

The MSNUM has 6 bits that identify devices using the serial DMA

(SDMA) modules. MSNUM[0–4] is the sub-block code of the current

peripheral controller using SDMA. MSNUM5 indicates the section,

transmit (0) or receive (1), that is active during the transfer. The

information is recorded in the SDMA transfer error registers.

PA23 FCC1: TXD2

UTOPIA Output FCC1: UTOPIA Transmit Data Bit 2

The MSC8101 outputs ATM cell octets (UTOPIA interface data) on

TXD[0–7]. This is bit 2 of the transmit data. TXD7 is the most significant

bit. When no ATM data is available, idle cells are inserted. A cell is 53

bytes.

Table 1-7. Port A Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated Signal

Protocol

MSC8101 Technical Data, Rev. 19

1-18 Freescale Semico nd uct or

Signals/Connections

PA22 FCC1: TXD3

UTOPIA Output FCC1: UTOPIA Transmit Data Bit 3

The MSC8101 outputs ATM cell octets (UTOPIA interface data) on

TXD[0–7]. This is bit 3 of the transmit data. TXD7 is the most significant

bit. When no ATM data is available, idle cells are inserted. A cell is 53

bytes.

PA21 FCC1: TXD4

UTOPIA

FCC1: TXD3

MII and HDLC nibble

Output

FCC1: UTOPIA Transmit Data Bit 4

The MSC8101 outputs ATM cell octets (UTOPIA interface data) on

TXD[0–7]. This is bit 4 of the transmit data. TXD7 is the most significant

bit. When no ATM data is available, idle cells are inserted. A cell is 53

bytes.

FCC1: MII and HDLC Nibble Transmi t Data Bit 3

TXD[3–0] supports MII and HDLC nibble modes in FCC1. TXD3 is the

most significant bit.

PA20 FCC1: TXD5

UTOPIA

FCC1: TXD2

MII and HDLC nibble

Output

FCC1: UTOPIA Transmit Data Bit 5

The MSC8101 outputs ATM cell octets (UTOPIA interface data) on

TXD[0–7]. This is bit 5 of the transmit data. TXD7 is the most significant

bit. When no ATM data is available, idle cells are inserted. A cell is 53

bytes.

FCC1: MII and HDLC Nibble Transmi t Data Bit 2

TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. This is

bit 2 of the transmit data. TXD3 is the most significant bit.

PA19 FCC1: TXD6

UTOPIA

FCC1: TXD1

MII and HDLC nibble

Output

FCC1: UTOPIA Transmit Data Bit 6

The MSC8101MSC8101 outputs ATM cell octets (UTOPIA interface

data) on TXD[0–7]. This is bit 6 of the transmit data. TXD7 is the most

significant bit. When no ATM data is available, idle cells are inserted. A

cell is 53 bytes.

FCC1: MII and HDLC Nibble Transmi t Data Bit 1

TXD[3–0] is supported by MII and HDLC transparent nibble modes in

FCC1. This is bit 1 of the transmit data. TXD3 is the most significant bit.

PA18 FCC1: TXD7

UTOPIA

FCC1: TXD0

MII and HDLC nibble

FCC1: TXD

HDLC serial and transpare nt

Output

FCC1: UTOPIA Transmit Data Bit 7.

The MSC8101 outputs ATM cell octets (UTOPIA interface data) on

TXD[0–7]. TXD7 is the most significant bit. When no ATM data is

available, idle cells are inserted. A cell is 53 bytes.

FCC1: MII and HDLC Nibble Transmi t Data Bit 0

TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. TXD0

is the least significant bit.

FCC1: HDLC Serial and Transparent Transmit Data Bit

This is the single transmit data bit in supported by HDLC serial and

transparent modes.

Table 1-7. Port A Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated Signal

Protocol

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-19

PA17 FCC1: RXD7

UTOPIA

FCC1: RXD0

MII and HDLC nibble

FCC1: RXD

HDLC serial and transpare nt

Input

FCC1: UTOPIA Receive Data Bit 7.

The MSC8101 inputs ATM cell octets (UTOPIA interface data) on

RXD[0–7]. RXD7 is the most significant bit. When no ATM data is

available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY

configurations, RXD[0–7] is tri-stated, enabled only when RXENB is

asserted.

FCC1: MII and HDLC Nibble Receive Data Bit 0

RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD0 is

the least significant bit.

FCC1: HDLC Serial and Transparent Receive Data Bit

This is the single receive data bit supported by HDLC and transparent

modes.

PA16 FCC1: RXD6

UTOPIA

FCC1: RXD1

MII and HDLC nibble

Input

FCC1: UTOPIA Receive Data Bit 6.

The MSC8101 inputs ATM cell octets (UTOPIA interface data) on

RXD[0–7]. This is bit 6 of the receive data. RXD7 is the most significant

bit. When no ATM data is available, idle cells are inserted. A cell is 53

bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,

enabled only when RXENB is asserted.

FCC1: MII and HDLC Nibble Receive Data Bit 1

This is bit 1 of the receive nibble data. RXD3 is the most significant bit.

PA15 FCC1: RXD5

UTOPIA

RXD2

MII and HDLC nibble

Input

FCC1: UTOPIA Receive Data Bit 5

The MSC8101 inputs ATM cell octets (UTOPIA interface data) on

RXD[0–7]. This is bit 5 of the receive data. RXD7 is the most significant

bit. When no ATM data is available, idle cells are inserted. A cell is 53

bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,

enabled only when RXENB is asserted.

FCC1: MII and HDLC Nibble Receive Data Bit 2

This is bit 2 of the receive nibble data. RXD3 is the most significant bit.

PA14 FCC1: RXD4

UTOPIA

FCC1: RXD3

MII and HDLC nibble

Input

FCC1: UTOPIA Receive Data Bit 4.

The MSC8101 inputs ATM cell octets (UTOPIA interface data) on

RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant

bit. When no ATM data is available, idle cells are inserted. A cell is 53

bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,

enabled only when RXENB is asserted.

FCC1: MII and HDLC Nibble Receive Data Bit 3

RXD3 is the most significant bit of the receive nibble bit.

PA13 FCC1: RXD3

UTOPIA

SDMA: MSNUM2

Input

Output

FCC1: UTOPIA Receive Data Bit 3

The MSC8101 inputs ATM cell octets (UTOPIA interface data) on

RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant

bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is

tri-stated, enabled only when RXENB is asserted.

Module Serial Number Bit 2

The MSNUM has 6 bits that identify devices using the serial DMA

(SDMA) modules. MSNUM[0–4] is the sub-block code of the current

peripheral controller using SDMA. MSNUM5 indicates the section,

transmit (0) or receive (1), that is active during the transfer. The

information is recorded in the SDMA transfer error registers.

Table 1-7. Port A Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated Signal

Protocol

MSC8101 Technical Data, Rev. 19

1-20 Freescale Semico nd uct or

Signals/Connections

PA12 FCC1: RXD2

UTOPIA

SDMA: MSNUM3

Input

Output

FCC1: UTOPIA Receive Data Bit 2

The MSC8101 inputs ATM cell octets (UTOPIA interface data) on

RXD[0–7]. This is bit 2 of the receive data. RXD7 is the most significant

bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is

tri-stated, enabled only when RXENB is asserted.

Module Serial Number Bit 3

The MSNUM has 6 bits that identify devices using the serial DMA

(SDMA) modules. MSNUM[0–4] is the sub-block code of the current

peripheral controller using SDMA. MSNUM5 indicates the section,

transmit (0) or receive (1), that is active during the transfer. The

information is recorded in the SDMA transfer error registers.

PA11 FCC1: RXD1

UTOPIA

SDMA: MSNUM4

Input

Output

FCC1: UTOPIA RX Receive Data Bit 1

The MSC8101 inputs ATM cell octets (UTOPIA interface data) on

RXD[0–7]. This is bit 1 of the receive data. RXD7 is the most significant

bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is

tri-stated, enabled only when RXENB is asserted.

Module Serial Number Bit 4

The MSNUM has 6 bits that identify devices using the serial DMA

(SDMA) modules. MSNUM[0–4] is the sub-block code of the current

peripheral controller using SDMA. MSNUM5 indicates the section,

transmit (0) or receive (1), that is active during the transfer. The

information is recorded in the SDMA transfer error registers.

PA10 FCC1: RXD0

UTOPIA

SDMA: MSNUM5

Input

Output

FCC1: UTOPIA RX Receive Data Bit 0

The MSC8101 inputs ATM cell octets (UTOPIA interface data) on

RXD[0–7]. RXD0 is the least significant bit of the receive data. A cell is

53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,

enabled only when RXENB is asserted.

Module Serial Number Bit 5

The MSNUM has 6 bits that identify devices using the serial DMA

(SDMA) modules. MSNUM[0–4] is the sub-block code of the current

peripheral controller using SDMA. MSNUM5 indicates the section,

transmit (0) or receive (1), that is active during the transfer. The

information is recorded in the SDMA transfer error registers.

PA9 SMC2: SM T XD

SI1 TDMA1: L1TXD0

TDM nibble

Output

SMC2: Serial Managemen t Transmit Data

The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.

Not all signals are used for all applications. SMCs are full-duplex ports

that supports three protocols or modes: UART, transparent, or general-

circuit interface (GCI). See also PC15.

Time-Division Multiplexing A1: Layer 1 Transmit Data Bit 0

L1TXD0 is the least significant bit of the TDM nibble data.

PA8 SMC2: SM R XD

SI1 TDMA1: L1RXD0

TDM nibble

SI1 TDMA1: L1RXD

TDM serial

Input

SMC2: Serial Managemen t Receive Data

The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.

Not all signals are used for all applications. SMCs are full-duplex ports

that supports three protocols or modes: UART, transparent, or general-

circuit interface (GCI).

Time-Division Multiplexing A1: Layer 1 Nibble Receive Data Bit 0

L1RXD0 is the least significant bit received in nibble mode.

Time-Division Multiplexing A1: Layer 1 Serial Receive Data

TDMA1 receives serial data from L1RXD.

Table 1-7. Port A Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated Signal

Protocol

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-21

1.6.2 Port B Signals

PA7 SMC2: SM SYN

SI1 TDMA1: L1TSYNC

TDM nibble and TDM serial

Input

SMC2: Serial Management Synchronization

The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.

Not all signals are used for all applications. SMCs are full-duplex ports

that supports three protocols or modes: UART, transparent, or general-

circuit interface (GCI).

Time-Division Multiplexing A1: Layer 1 Transmit Synchronization

The synchronizing signal for the transmit channel. See the Serial

Interface with time-slot assigner chapter in the MSC8101 Reference

Manual.

PA6 SI1 TDMA1: L1RSYNC

TDM nibble and TDM serial Input Time-Division Multiplexing A1: Layer 1 Receive Synchronization.

The synchronizing signal for the receive channel.

Table 1-8. Port B Signals

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

PB31 FCC2: TX_ER

MII

SCC2: RXD

SI2 TDMB2: L1TXD

TDM serial

Output

Input

Output

FCC2: Media Independent Interface Transmit Error

Asserted by the MSC8101 to force propagation of transmit errors.

SCC2: Receive Data

SCC2 receives serial data from RXD.

Time-Division Multiplexing B2: Layer 1 Transmit Data

TDMB2 transmits serial data out of L1TXD.

PB30 SCC2: TX D

FCC2: RX_DV

MII

SI2 TDMB2: L1RXD

TDM serial

Output

Input

SCC2: T ransmit Data.

SCC2 transmits serial data out of TXD.

FCC2: Media Independent Interface Receive Data Valid

Asserted by an external fast Ethernet PHY to indicate that valid data is

being sent. The presence of carrier sense, but not RX_DV, indicates

reception of broken packet headers, probably due to bad wiring or a bad

circuit.

Time-Division Multiplexing B2: Layer 1 Receive Data

TDMB2 receives serial data from L1RXD.

PB29 FCC2: TX_EN

MII

SI2 TDMB2: L1RSYNC

TDM serial

Output

Input

FCC2: Media Independent Interface Transmit Enable

Asserted by the MSC8101 when transmitting data.

Time-Division Multiplexing B2: Layer 1 Receive Synchronization

The synchronizing signal for the receive channel.

Table 1-7. Port A Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated Signal

Protocol

MSC8101 Technical Data, Rev. 19

1-22 Freescale Semico nd uct or

Signals/Connections

PB28 FCC2: RTS

HDLC serial, HDLC nibble, and

transparent

FCC2: RX_ER

MII

SCC2: RTS, TENA

SI2 TDMB2: L1TSYNC

TDM serial

Output

Input

Output

Input

FCC2: Request to Send

One of the standard modem interface signals supported by FCC2 (RTS,

CTS, and CD). RTS is asynchronous with the data. RTS is typically us ed

in conjunction with CD. The MSC8101 FCC2 transmitter requests the

receiver to send data by asserting RTS low. The request is accepted

when CTS is returned low.

FCC2: Media Independent Interface Receive Error

Asserted by an external fast Ethernet PHY to indicate a receive error,

which often indicates bad wiring.

SCC2: Request to Send, Transmit Enable

Typically used in conjunction with CD supported by SCC2. The

MSC8101 SCC2 transmitter requests the receiver to send data by

asserting RTS low. The request is accepted when CTS is returned low.

TENA is the signal used in Ethernet mode.

Time-Division Multiplexing B2: Layer 1 Transmit Synchronization

The synchronizing signal for the transmit channel. See the serial

interface with time-slot assigner chapter in the MSC8101 Reference

Manual.

PB27 FCC2: COL

MII

SI2 TDMC2: L1TXD

TDM serial

Input

Output

FCC2: Media Independent Interface Collision Detect

Asserted by an external fast Ethernet PHY when a collision is detected.

Time-Division Multiplexing C2: Layer 1 Transmit Data

TDMC2 transmits serial data out of L1TXD.

PB26 FCC2: CRS

MII

SI2 TDMC2: L1RXD

TDM serial

Input

FCC2: Media Independent Interface Carrier Sense Input

Asserted by an external fast Ethernet PHY to indicate activity on the

cable.

Time-Division Multiplexing C2: Layer 1 Receive Data

TDMC2 receives serial data from L1RXD.

PB25 FCC2: TXD3

MII and HDLC nibble

SI1 TDMA1: L1TXD3

TDM nibble

SI2 TDMC2: L1TSYNC

TDM serial

Output

Input

FCC2: MII and HDLC Nibble Transmi t Data Bit 3

TXD3 is bit 3 and the most significant bit of the transmit data nibble.

Time-Division Multiplexing A1: Nibble Layer 1 T ransmit Data Bit 3

L1TXD3 is bit 3 and the most significant bit of the transmit data nibble.

Time-Division Multiplexing C2: Layer 1 Transmit Synchronization

The synchronizing signal for the transmit channel. See the Serial

Interface with Time-Slot Assigner chapter in the MSC8101 Reference

Manual.

PB24 FCC2: TXD2

MII and HDLC nibble

SI1 TDMA1: L1RXD3

nibble

SI2 TDMC2: L1RSYNC

serial

Output

Input

FCC2: MII and HDLC Nibble: Transmit Data Bit 2

TXD2 is bit 2 of the transmit data nibble.

Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 3

L1RXD3 is bit 3 and the most significant bit of the receive data nibble.

Time-Division Multiplexing C2: Layer 1 Receive Synchronization

The synchronizing signal for the receive channel.

Table 1-8. Port B Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-23

PB23 FCC2: TXD1

MII and HDLC nibble

SI1 TDMA1: L1RXD2

TDM nibble

SI2 TDMD2: L1TXD

TDM serial

Output

Input

Output

FCC2: MII and HDLC Nibble: Transmit Data Bit 1

TXD1 is bit 1 of the transmit data nibble.

Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 2

L1RXD2 is bit 2 of the receive data nibble.

Time-Division Multiplexing D2: Layer 1 Transmit Data

TDMA1 transmits serial data out of L1TXD.

PB22 FCC2: TXD0

MII and HDLC nibble

FCC2: TXD

HDLC serial and transparent

SI1 TDMA1: L1RXD1

TDM nibble

SI2 TDMD2: L1RXD

TDM serial

Output

Input

FCC2: MII and HDLC Nibble Transmi t Data Bit 0

TXD0 is bit 0 and the least significant bit of the transmit data nibble.

FCC2: HDLC Serial and Transparent Transmit Data

Serial data is transmitted via TXD.

Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 1

L1RXD1 is bit 1 of the receive data nibble.

Time-Division Multiplexing D2: Layer 1 Receive Data

Serial data is received via L1RXD.

PB21 FCC2: RXD0

MII and HDLC nibble

FCC2: RXD

HDLC serial and transparent

SI1 TDMA1: L1TXD2

TDM nibble

SI2 TDMD2: L1TSYNC

TDM serial

Input

Output

Input

FCC2: MII and HDLC Nibble Receive Data Bit 0

RXD0 is bit 0 and the least significant bit of the receive data nibble.

FCC2: HDLC Serial and Transparent Receive Data

Serial data is received via RXD.

Time-Division Multiplexing A1: Nibble Layer 1 T ransmit Data Bit 2

L1TXD2 is bit 2 of the transmit data nibble.

Time-Division Multiplexing D2: Layer 1 Transmit Synchronize Data

The synchronizing signal for the transmit channel. See the Serial

Interface with Time-Slot Assigner chapter in the MSC8101 Reference

Manual.

PB20 FCC2: RXD1

MII and HDLC nibble

SI1 TDMA1: L1TXD1

TDM nibble

SI2 TDMD2: L1RSYNC

TDM serial

Input

Output

Input

FCC2: MII and HDLC Nibble: Receive Data Bit 1

RXD1 is bit 1 of the receive data nibble.

Time-Division Multiplexing A1: Nibble Layer 1 T ransmit Data Bit 1

L1TXD1 is bit 1 of the transmit data nibble.

Time-Division Multiplexing D2: Layer 1 Receive Synchronize Data

The synchronizing signal for the receive channel.

PB19 FCC2: RXD2

MII and HDLC nibble

I2C: SDA

Input

Input/ Output

FCC2: MII and HDLC Nibble Receive Data Bit 2

RXD2 is bit 2 of the receive data nibble.

I2C: Inter-Integrated Circuit Serial Data

The I2C interface comprises two signals: serial data (SDA) and serial

clock (SDA). The I2C controller uses a synchronous, multimaster bus

that can connect several integrated circuits on a board. Clock rates run

up to 520 kHz@25 MHz system clock.

Table 1-8. Port B Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

MSC8101 Technical Data, Rev. 19

1-24 Freescale Semico nd uct or

Signals/Connections

1.6.3 Port C Signals

PB18 FCC2: RXD3

MII and HDLC nibble

I2C: SCL

Input

Input/Output

FCC2: MII and HDLC Nibble Receive Data Bit 3

RXD3 is bit 3 and the most significant bit of the receive data nibble.

I2C: Inter-Integrated Circuit Serial Clock

The I2C interface comprises two signals: serial data (SDA) and serial

clock (SDA). The I2C controller uses a synchronous, multimaster bus

that can connect several integrated circuits on a board. Clock rates run

up to 520 kHz@25 MHz system clock.

Table 1-9. Port C Signa ls

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

PC31 BRG1O

CLK1

TIMER1/2: TGATE1

Output

Input

Baud-Rate Generator 1 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

BRG1O can be the internal input to the SIU timers. When CLK5 is selected

(see PC27 below), it is the source for BRG1O which is the default input for

the SIU timers. See the system interface unit (SIU) chapter in the

MSC8101 Reference Manual for additional information. If CLK5 is not

enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26

below), the BRG1O input to the SIU timers is disabled.

Clock 1

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

Timer 1/2: Ti mer Gate 1

The timers can be gated/restarted by an external gate signal. There are

two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls

timer 3 and/or 4.

Table 1-8. Port B Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-25

PC30 BRG2O

CLK2

Timer1 : TOUT1

EXT1

Output

Input

Output

Input

Baud-Rate Generator 2 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

Clock 2

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

Timer 1: Timer Out 1

The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4])

when the reference value is reached. This signal can be an active-low

pulse or a toggle of the current output. The output can also connect

internally to the input of another timer, resulting in a 32-bit timer.

External Request 1

Asserts an internal request to the CPM processor. The signal can be

programmed as level- or edge-sensitive, and also has programmable

priority. Refer to the RISC Controller Configuration Register (RCCR)

description in the Chapter 17 of the MSC8101 Reference Manual for

programming information. There are no current microcode applications for

this request line. It is reserved for future development.

PC29 BRG3O

CLK3

TIN2

SCC1: CTS, CLSN

Output

Input

Baud-Rate Generator 3 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

Clock 3

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

Timer Input 2

A timer can have one of the following sources: another timer, system

clock, system clock divided by 16 or a timer input. The CPM supports up to

4 timer inputs. The timer inputs can be captured on the rising, falling or

both edges.

SCC1: Clear to Send, Collision

Typically used in conjunction with RTS. The MSC8101 SCC1 transmitter

sends out a request to send data signal (RTS). The request is accepted

when CTS is returned low. CLSN is the signal used in Ethernet mode. See

also PC15.

Table 1-9. Port C Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

MSC8101 Technical Data, Rev. 19

1-26 Freescale Semico nd uct or

Signals/Connections

PC28 BRG4O

CLK4

TIN1

Timer2 : TOUT2

SCC2: CTS, CLSN

Output

Input

Output

Input

Baud-Rate Generator 4 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

Clock 4

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

Timer Input 1

A timer can have one of the following sources: another timer, system

clock, system clock divided by 16 or a timer input. The CPM supports up to

4 timer inputs. The timer inputs can be captured on the rising, falling or

both edges.

Timer 2: Timer Output 2

The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4])

when the reference value is reached. This signal can be an active-low

pulse or a toggle of the current output. The output can also be connected

internally to the input of another timer, resulting in a 32-bit timer.

SCC2: Clear to Send, Collision

Typically used in conjunction with RTS. The MSC8101 SCC2 transmitter

sends out a request to send data signal (RTS). The request is accepted

when CTS is returned low. CLSN is the signal used in Ethernet mode. See

also PC13.

PC27 BRG5O

CLK5

TIMER3/4: TGATE2

Output

Input

Baud-Rate Generator 5 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

Clock 5

When selected, CLK5 is a source for the SIU timers via BRG1O. See the

System Interface Unit (SIU) chapter in the MSC8101 Reference Manual

for additional information. If CLK5 is not enabled, BRG1O uses an internal

input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU

timers is disabled.

Timer 3/4: Ti mer Gate 2

The timers can be gated/restarted by an external gate signal. There are

two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls

timer 3 and/or 4.

Table 1-9. Port C Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-27

PC26 BRG6O

CLK6

Timer3 : TOUT3

TMCLK

Output

Input

Output

Input

Baud-Rate Generator 6 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or provide an output to one of the 8 BRG pins.

Clock 6

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

Timer 3: Timer Out 3

The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4])

when the reference value is reached. This signal can be an active-low

pulse or a toggle of the current output. The output can also connect

internally to the input of another timer, resulting in a 32-bit timer.

Timer Clock

When selected, TMCLK is the designated input to the SIU timers. When

TMCLK is configured as the input to the SIU timers, the BRG1O input is

disabled. See the System Interface Unit (SIU) chapter in the MSC8101

Reference Manual for additional information.

PC25 BRG7O

CLK7

TIN4

DMA: DACK2

Output

Input

Output

Baud-Rate Generator 7 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or provide an output to one of the 8 BRG pins.

Clock 7

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

Timer Input 4

A timer can have one of the following sources: another timer, system

clock, system clock divided by 16 or a timer input. The CPM supports up to

4 timer inputs. The timer inputs can be captured on the rising, falling or

both edges.

DMA: Data Acknowledge 2

DACK2, DREQ2, DRACK2 and DONE2 belong to the SIU DMA controller.

DONE2 and DRACK2 are signals on the same pin and therefore cannot be

used simultaneously. There are two sets of DMA pins associated with the

PIO ports.

Table 1-9. Port C Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

MSC8101 Technical Data, Rev. 19

1-28 Freescale Semico nd uct or

Signals/Connections

PC24 BRG8O

CLK8

TIN3

Timer4 : TOUT4

DMA: DREQ2

Output

Input

Output

Input

Baud-Rate Generator 8 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

Clock 8

The CPM supports up to 10 clock input pins. The clocks are sent to the

bank-of-clocks selection logic, where they can be routed to the controllers.

Timer Input 3

A timer can have one of the following sources: another timer, system

clock, system clock divided by 16, or a timer input. The CPM supports up

to four timer inputs. The timer inputs can be captured on the rising, falling,

or both edges.

Timer 4: Timer Out 4

The timers (Timer1–4]) can output a signal on a timer output (TOUT[1–4 ])

when the reference value is reached. This signal can be an active-low

pulse or a toggle of the current output. The output can also be connected

internally to the input of another timer, resulting in a 32-bit timer.

DMA: Data Request 2

DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller.

DONE2 and DRACK2 are signals on the same pin and therefore cannot be

used simultaneously. There are two sets of DMA pins associated with the

PIO ports.

PC23 CLK9

DMA: DACK1

EXT2

Input

Output

Input

Clock 9

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

DMA: Data Acknowledge 1

DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller.

DONE1 and DRACK1 are signals on the same pin and therefore cannot be

used simultaneously. There are two sets of DMA pins associated with the

PIO ports.

External Request 2

External request input line 2 asserts an internal request to the CPM

processor. The signal can be programmed as level- or edge-sensitive, and

also has programmable priority. Refer to the risc controller configuration

Manual for programming information. There are no current microcode

applications for this request line. It is reserved for future development.

Table 1-9. Port C Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-29

PC22 SI1: L1ST1

CLK10

DMA: DREQ1

Output

Input

Input/ Output

Serial Interface 1: Layer 1 Strobe 1

The MSC8101 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also generate output wave forms for such

applications as stepper-motor control.

Clock 10

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

DMA: Request 1

DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller.

DONE1 and DRACK1 are signals on the same pin and therefore cannot be

used simultaneously. There are two sets of DMA pins associated with the

PIO ports.

PC15 SMC2: SMT XD

SCC1: CTS/CLSN

FCC1: TXADDR0

UTOPIA master

FCC1: TXADDR0

UTOPIA slave

Output

Input

Output

Input

SMC2: Serial Managemen t Transmit Data

The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not

all signals are used for all applications. SMCs are full-duplex ports that

support three protocols or modes: UART, transparent, or general-circuit

interface (GCI). See also PA9.

SCC1: Clea r To Send, Collision

Typically used in conjunction with RTS. The MSC8101 SCC1 transmitter

sends out a request to send data signal (RTS). The request is accepted

when CTS is returned low. CLSN is the signal used in Ethernet mode. See

also PC29.

FCC1: UTOPIA Master Transmit Address Bit 0

This is master transmit address bit 0.

FCC1: UTOPIA Slave Transmit Address Bit 0

This is slave transmit address bit 0.

PC14 SI1: L1ST2

SCC1: CD, RENA

FCC1: RXADDR0

UTOPIA master

FCC1: RXADDR0

UTOPIA slave

Output

Input

Output

Input

Serial Interface 1: Layer 1 Strobe 2

The MSC8101 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also be generate output wave forms for

such applications as stepper-motor control.

SCC1: Carrier Detect, Receive Enable

Typically used in conjunction with RTS supported by SCC1. The

MSC8101MSC8101 SCC1 transmitter requests the receiver to send data

by asserting RTS low. The request is accepted when CTS is returned low.

FCC1: UTOPIA Multi-PHY Master Receive Address Bit 0

This is master receive address bit 0.

FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 0

This is slave receive address bit 0.

Table 1-9. Port C Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

MSC8101 Technical Data, Rev. 19

1-30 Freescale Semico nd uct or

Signals/Connections

PC13 SI1: L1ST4

SCC2: CTS,CLSN

FCC1:TXADDR1

UTOPIA master

FCC1: TXADDR1

UTOPIA slave

Output

Input

Output

Input

Serial Interface 1: Layer 1 Strobe 4

The MSC8101 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also generate output wave forms for such

applications as stepper-motor control.

SCC2: Clear to Send, Collision

Typically used in conjunction with RTS. The MSC8101 SCC2 transmitter

sends out a request to send data signal (RTS). The request is accepted

when CTS is returned low. CLSN is the signal used in Ethernet mode. See

also PC28.

FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 1

This is master transmit address bit 1.

FCC1: UTOPIA Multi-PHY Slave Tran smit Address Bit 1

This is slave transmit address bit 1.

PC12 SI1: L1ST3

SCC2: CD, RENA

FCC1: RXADDR1

UTOPIA master

FCC1: RXADDR1

UTOPIA slave

Output

Input

Output

Input

Serial Interface 1: Layer 1 Strobe 3

The MSC8101 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also generate output wave forms for such

applications as stepper-motor control.

SCC2: Carrier Detect, Request Enable

Typically used in conjunction with RTS supported by SCC2. The MSC8101

SCC2 transmitter requests to the receiver that it sends data by asserting

RTS low. The request is accepted when CTS is returned low.

FCC1: UTOPIA Multi-PHY Master Receive Address Bit 1

This is master receive address bit 1.

FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 1

This is slave receive address bit 1.

Table 1-9. Port C Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-31

PC7 SI2: L1ST1

FCC1: CTS

HDLC serial, HDLC nibble,

and transparent

FCC1: TXADDR2

UTOPIA master

FCC1: TXADDR2

UTOPIA slave

FCC1: TXCLAV1

UTOPIA multi-PHY master, direct

polling

Output

Input

Output

Input

Serial Interface 2: Strobe 1

The MSC8101 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also generate output wave forms for such

applications as stepper-motor control.

FCC1: Clear To Send

In the standard modem interface signals supported by FCC1 (RTS, CTS,

and CD). CTS is asynchronous with the data.

FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2

This is master transmit address bit 2.

FCC1: UTOPIA Multi-PHY Slave Tran smit Address Bit 2

This is slave transmit address bit 2.

FCC1: UTOPIA Multi-PHY Master Tran smit Cell Available 1 Direct

Polling

Asserted by an external UTOPIA slave PHY to indicate that it can accept

one complete ATM cell.

PC6 SI2: L1ST2

FCC1: CD

HDLC serial, HDLC nibble,

and transparent

FCC1: RXADDR2

UTOPIA master

FCC1: RXADDR2

UTOPIA slave

FCC1: RXCLAV1

UTOPIA multi-PHY master, direct

polling

Output

Input

Output

Input

Serial Interface 2: Layer 1 Strobe 2

The MSC8101 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also generate output wave forms for such

applications as stepper-motor control.

FCC1: Carrier Detect

In the standard modem interface signals supported by FCC1 (RTS, CTS,

and CD). CD is an input asynchronous with the data.

FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2

This is master receive address bit 2.

FCC1: UTOPIA Slave Receive Address Bit 2

This is slave receive address bit 2.

FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1 Direct

Polling

Asserted by an external PHY when one complete ATM cell is available for

transfer.

Table 1-9. Port C Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

MSC8101 Technical Data, Rev. 19

1-32 Freescale Semico nd uct or

Signals/Connections

PC5 SMC1: SMTXD

SI2: L1ST3

FCC2: CTS

HDLC serial, HDLC nibble,

and transparent

Output

Input

SMC1: Transmit Data

The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not

all signals are used for all applications. SMCs are full-duplex ports that

supports three protocols or modes: UART, transparent, or general-circuit

interface (GCI).

Serial Interface 2: Layer 1 Strobe 3

The MSC8101 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also generate output wave forms for such

applications as stepper-motor control.

FCC2: Clear To Send

In the standard modem interface signals supported by FCC2 (RTS, CTS,

and CD). CTS is asynchronous with the data.

PC4 SMC1: SMRXD

SI2: L1ST4

FCC2: CD

HDLC serial, HDLC nibble,

and transparent

Input

Output

Input

SMC1: Receive Data

The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not

all signals are used for all applications. SMCs are full-duplex ports that

supports three protocols or modes: UART, transparent, or general-circuit

interface (GCI).

Serial Interface 2: Layer 1 Strobe 4

The MSC8101 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also generate output wave forms for such

applications as stepper-motor control.

FCC2: Carrier Detect

In the standard modem interface signals supported by FCC2 (RTS, CTS

and CD). CD is asynchronous with the data.

Table 1-9. Port C Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-33

1.6.4 Port D Signals

Table 1-10. Port D Signals

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

PD31 SCC1: RXD

DMA: DRACK1

DMA: DONE1

Input

Output

Input/ Output

SCC1: Receive Data

SCC1 receives serial data from RXD.

DMA: Data Request Acknowledge 1

DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA

controller. DONE1 and DRACK1 are signals on the same pin and

therefore cannot be used simultaneously. There are two sets of DMA

pins associated with the PIO ports.

DMA: Done 1

DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA

controller. DONE1 and DRACK1 are signals on the same pin and

therefore cannot be used simultaneously. There are two sets of DMA

pins associated with the PIO ports.

PD30 SCC1: TX D

DMA: DRACK2

DMA: DONE2

Output

Input/ Output

SCC1: T ransmit Data

SCC1 transmits serial data out of TXD.

DMA: Data Request Acknowledge 2

DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA

controller. DONE2 and DRACK2 are signals on the same pin and

therefore cannot be used simultaneously. There are two sets of DMA

pins associated with the PIO ports.

DMA: Done 2

DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA

controller. DONE2 and DRACK2 are signals on the same pin and

therefore cannot be used simultaneously. There are two sets of DMA

pins associated with the PIO ports.

PD29 SCC1: RTS, TE N A

FCC1: RXADDR3

UTOPIA master

FCC1: RXADDR3

UTOPIA slave

FCC1: RXCLAV2

UTOPIA multi-PHY master, direct

polling

Output

Input

SCC1: Request to Send, Transmit Enable

Typically used in conjunction with CD supported by SCC2. The

MSC8101 SCC1 transmitter requests the receiver to send data by

asserting RTS low. The request is accepted when CTS is returned low.

TENA is the signal used in Ethernet mode.

FCC1: UTOPIA Multi-PHY Master Receive Address Bit 3

This is master receive address bit 3.

FCC1: UTOPIA Slave Receive Address Bit 3

This is slave receive address bit 3.

FCC1: UTOPIA Multi-PHY Master Receive Cell Available 2 Direct

Polling

Asserted by an external PHY when one complete ATM cell is available

for tran sfer.

MSC8101 Technical Data, Rev. 19

1-34 Freescale Semico nd uct or

Signals/Connections

PD19 FCC1: TXADDR4

UTOPIA master

FCC1: TXADDR4

UTOPIA slave

FCC1: TXCLAV3

UTOPIA multi-PHY master, direct

polling

BRG1O

SPI: SPISEL

Output

Input

Output

Input

FCC1: Multi-PHY Master Transmit Address Bit 4 Multiplexed Polling

This is master transmit address bit 4.

FCC1: UTOPIA Slave Transmit Address Bit 4

This is slave transmit address bit 4.

FCC1: UTOPIA Multi-PHY master Tr ansmit Cell Available 3 Direct

Polling

Asserted by an external UTOPIA slave PHY to indicate that it can accept

one complete ATM cell.

Baud Rate Generator 1 Output

The CPM supports up to 8 BRGs for use internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

BRG1O can be the internal input to the SIU timers. When CLK5 is

selected (see PC27 above), it is the source for BRG1O which is the

default input for the SIU timers. See the system interface unit (SIU)

chapter in the MSC8101 Reference Manual for additional information. If

CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is

enabled (see PC26 above), the BRG1O input to the SIU timers is

disabled.

SPI: Select

The SPI interface comprises four signals: master out slave in

(SPIMOSI ), ma ster in slave out (SPIMISO ), clock (SPICLK) and select

(SPISEL). The SPI can be configured as a slave or master in single- or

multiple-master environments. SP ISEL is the enable input to the SPI

slave. In a multimaster environment, SPISEL (always an input) detects

an error when more than one master is operating. SPI masters must

output a slave select signal to enable SPI slave devices by using a

separate general-purpose I/O signal. Assertion of an SPI SPISEL while

it is master causes an error.

PD18 FCC1: RXADDR4

UTOPIA master

FCC1: RXADDR4

UTOPIA slave

FCC1: RXCLAV3

UTOPIA multi-PHY master, direct

polling

SPI: SPICLK

Output

Input

Input/ Output

FCC1: UTOPIA Master Receive Address Bit 4

This is master receive address bit 4.

FCC1: UTOPIA Slave Receive Address Bit 4

This is slave receive address bit 4.

FCC1: UTOPIA Multi-PHY Master Receive Cell Available 3 Direct

Polling

Asserted by an external PHY when one complete ATM cell is available

for tran sfer.

SPI: Cl ock

The SPI interface comprises four signals: master out slave in

(SPIMOSI ), ma ster in slave out (SPIMISO ), clock (SPICLK) and select

(SPISEL). The SPI can be configured as a slave or master in single- or

multiple-master environments. SP ICLK is a gated clock, active only

during data transfers. Four combinations of SPICLK phase and polarity

can be configured. When the SPI is a master, SPICLK is the clock

output signal that shifts received data in from SPIMISO and transmitted

data ou t to SPIMOSI.

Table 1-10. Port D Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

CPM Ports

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 1-35

PD17 BRG2O

FCC1: RXPRTY

UTOPIA

SPI: SPIMOSI

Output

Input

Input/ Output

Baud Rate Generator 2 Output

The CPM supports up to 8 BRGs for use internally to the MSC8101

and/or to provide an output to one of the 8 BRG pins.

FCC1: UTOPIA Receive Parity

This is the odd parity bit for RXD[0–7].

SPI: Master Output Slave Input

The SPI interface comprises our signals: master out slave in (SPIMOSI),

master in slave out (SPIMISO), clock (SPICLK) and select (S PI SE L).

The SPI can be configured as a slave or master in single- or multiple-

master environments. When the SPI is a slave, SPICLK is the clock

input that shifts received data in from SPIMOSI and transmitted data out

through SPIMISO.

PD16 FCC1: T XPRTY

UTOPIA

SPI: SPIMISO

Output

Input/ Output

FCC1: UTOPIA Transmit Parity

This is the odd parity bit for TXD[0–7].

SPI: Master Input Sl ave Outp ut

The SPI interface comprises four signals: master out slave in

(SPIMOSI ), ma ster in slave out (SPIMISO ), clock (SPICLK) , and select

(SPISEL). The SPI can be configured as a slave or master in single- or

multiple-master environments. When the SPI is a slave, SPICLK is the

clock input that shifts received data in from SPIMOSI and transmitted

data out through SPIMISO.

PD7 SMC1: SMSYN

FCC1: TXADDR3

UTOPIA master

FCC1: TXADDR3

UTOPIA slave

FCC1: TXCLAV2

UTOPIA multi-PHY master, direct

polling

Input

Output

Input

SMC1: Serial Management Synchronization

The SMC interface consists of SMTXD, SMRXD, SMSYN and a clock.

Not all signals are used for all applications. SMCs are full-duplex ports

that support three protocols or modes: UART, transparent or general-

circuit interface (GCI).

FCC1: UTOPIA Master Transmit Address Bit 3

This is master transmit address bit 3.

FCC1: UTOPIA Slave Transmit Address Bit 3

This is slave transmit address bit 3.

FCC1: UTOPIA Multi-PHY Master Tran smit Cell Available 2 Direct

Polling

Asserted by an external UTOPIA slave PHY to indicate that it can accept

one complete ATM cell.

Table 1-10. Port D Signals (Continued)

Name Dedicated

I/O Data

Direction Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

MSC8101 Technical Data, Rev. 19

1-36 Freescale Semico nd uct or

Signals/Connections

1.7 JTAG Test Access Por t Signals

The MSC8101 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test

Access Port and Boundary-Scan Architecture specification and described in Table 1-11.

1.8 Reserved Signals

Table 1-11. JTAG Test Access Port Signals

Signal Name Type Signal Description

TCK Input Test Clock

A test clock signal for synchronizing JTAG test logic.

TDI Input Test Data Input

A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and

has an internal pull-up resistor.

TDO Output Test Data Output

A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively

driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK.

TMS Input Test Mode Select

Sequences the test controller’s state machine, is sampled on the rising edge of TCK, and has an

internal pull-up resistor.

TRST Input Test Reset

Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted

after power up.

Table 1-12. Reserved Signals

Signal Name Type Signal Description

TEST Input Test

Used for manufacturing testing. You must connect this input to GND.

THERM[1–2] — Leave disconnected.

SPARE 1 , 5 — Spare Pins

Leave disconnected for backward compatibility with future revisions of this device.

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-1

Physical and Electrical Specifications 2

This document contains detailed information on environmental limits, power considerations, DC/AC electrical

characteristics, and AC timing specifications for the MSC8101 communications processor, mask set 2K87M. For

additional information, see the MSC8101 Reference Manual.

2.1 Absolute Maximum Ratings

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another

specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation

of process parameter values in one direction. The minimum specification is calculated using the worst case for the

same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the

same device with a “minimum” value for another specification; adding a maximum to a minimum represents a

condition that can never exist. Table 2-1 describes the maximum electrical ratings for the MSC8101.

CAUTION

This device contains circuitry protecting against damage due to

high stat ic voltage or electr ical fields; howev er, normal precau tions

should be taken to avoid exceeding maximum voltage ratings.

Reliability is enhanced if unused inputs are tied to an appropriate

logic voltage level (for example, either GND or VCC).

Table 2-1. Absolute Maximum Ratings2

Rating Symbol Value Unit

Core supply voltage3VDD –0.2 to 1.7 V

PLL supply voltage3VCCSYN –0.2 to 1.7 V

I/O supply voltage3VDDH –0.2 to 3.6 V

Input voltage3VIN (GND – 0.2) to 3.6 V

Maximum operating temperature range4TJ–40 to 120 °C

Storage temperature range TSTG –55 to +150 °C

Notes: 1. F unctional operating conditions are given in Table 2-2.

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

3. The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In

turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not

exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at

any time, including during power-on reset. See Section 4.2, Electrical Design Considerations, on page 4-1 for more

information.

4. Section 4.1, Thermal Design Considerations, on page 4-1 includes a formula for computing the chip junction temperature

(TJ).

MSC8101 Technical Data, Rev. 19

2-2 Freescale Sem ico nd uctor

Physical and Electrical Specifications

2.2 Recommended Oper ating Conditions

Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2.3 Thermal Characteristics

Table 2-3 describes thermal characteristics of the MSC8101.

See Section 4.1, Thermal Design Considerations, on page 4-1 for details on these characteristics.

Table 2-2. Rec omm end ed Op erati ng Condi ti ons

Rating Symbol Value Unit

SC140 core supply voltage VDD 250/275 MHz: 1.5 to 1.7

300 MHz: 1.55 to 1.7 V

PLL supply voltage VCCSYN 250/275 MHz: 1.5 to 1.7

300 MHz: 1.55 to 1.7 V

I/O supply voltage VDDH 3.135 to 3.465 V

Input voltage VIN –0.2 to VDDH + 0.2 V

Operating temperature range TJ250/275 MHz: –40 to 105

300 MHz: –40 to 75 °C

°C

Table 2-3. Thermal Characteri stics

Characteristic Symbol

Lidded FC-PBGA

17 × 17 mm Unit

Natural Convectio n 200 ft/min

(1 m/s) airflow

Junction-to-ambient , single-layer board1, 2 RθJA or θJA 50 37 °C/W

Junction-to-ambient , four-layer board1, 3 RθJA or θJA 22 18 °C/W

Junction-to-board3RθJB or θJB 15 °C/W

Junction-to-case4RθJC or θJC 0.8 °C/W

Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and EIA/JES D51-2 with the single layer board horizontal.

3. Per JEDEC JES D51-6 with the board (JESD51-9) horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface without thermal grease. TBD = to be determined. If a thin (less

than 50 micron) thermal grease interface is established to a heat sink from the lid, the junction to sink thermal resistance is

about 0.7 °C/W.

DC Electrical Characteristics

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-3

2.4 DC Electrical Characte ristics

This section describes the DC electrical characteristics for the MSC8101. The measurements in Table 2-4 assume

the following system conditions:

•T

J = 0 – 100 °C

•VDD = 1.6 V ± 5% VDC

•VDDH = 3.3 V ± 5% VDC

•GND = 0 VDC

Note: The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same

direction (for example, both VDDH and VDD vary by ± 5 percent).

Table 2-4. DC Electrical Char ac te ristics

Characteristic Symbol Min Max Unit

Input high voltage1, all inputs except CLKIN VIH 2.0 3.465 V

Input low voltage1VIL GND 0.8 V

CLKIN input high voltage VIHC 2.5 3.465 V

CLKIN input low voltage2VILC GND 0.8 V

Input leakage current, VIN = VDDH IIN —10µA

Tri-state (high impedance off state) leakage current,

VIN = VDDH

IOZ —10µA

Signal low input current3, VIL = 0.8 V IL— –4.0 mA

Signal high input current3, VIH = 2.0 V IH—4.0mA

Output high voltage, IOH = –2 mA, except open drain pins VOH 2.4 — V

Output low voltage, IOL= 3.2 mA VOL —0.4V

Notes: 1. See F igu re 2-1 for undershoot and overshoot voltages.

2. The optimum CLKIN duty cycle is obtained when: VILC = VDDH – VIHC.

3. Not tested. Guaranteed by design.

Figure 2-1. Overshoot/Undershoot Voltage for VIH and VIL

Table 2-5. Typical Power Dissipation

Characteristic Symbol Typical Unit

Core power dissipation at 300 MHz PCORE 450 mW

CPM power dissipation at 200 MHz PCPM 320 mW

SIU power dissipation at 100 MHz PSIU 80 mW

Core leakage power PLCO 3mW

CPM leakage power PLCP 6mW

SIU leakage power PLSI 2mW

GND

GND – 0.3 V

GND – 0.7 V

VIL

VIH

Must not exceed 10% of clock period

VDDH + 20%

VDDH + 10%

VDDH

MSC8101 Technical Data, Rev. 19

2-4 Freescale Sem ico nd uctor

Physical and Electrical Specifications

2.5 Clock Configuration

The following sections provide a general description of clock configuration.

2.5.1 Valid Clock Modes

Table 2-6 shows the maximum frequency values for each rated core frequency (250, 275, or 300 MHz). The user

must ensure that ma ximum frequen cy val ues ar e not e xcee ded.

Six bit values map the MSC8101 cl ocks to o ne of the valid c onfigura tion mode o ptions. Ea ch option determine s the

CLKIN, SC140, system bus, SCC clock, CPM, and CLKOUT frequencies. The six bit values are derived from three

dedicated input pins (MODCK[1–3]) and three b its from th e hard reset confi gurat ion word (MODCK_H). To

configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for the SC140, SCC

clocks, CPM parallel I/O ports, and system buses, the MODCK[1–3] pins are sampled and combined with the

MODCK_H values when the internal power-on reset (internal PORESET) is deasserted. Clock configuration

changes only when the internal PORESET signal is deasserted. The following factors are configured:

• SPLL pre-division factor (SPLL PDF)

• SPLL multiplication factor (SPLL MF)

• Bus post-division factor (Bus DF)

• CPM division factor (CPM DF)

• Core division factor (Core DF)

• CPLL pre-division factor (CPLL PDF)

• CPLL multiplication factor (CPLL MF)

The SCC division factor (SCC DF) is fixed at 4. The BRG division factor (BRG DF) is configured through the

System Clock Control Register (SCCR) and can be 4, 16 (default after reset), 64, or 256.

Note: Refer to Clock Mode Selection for MSC8101 and MSC8103 Mask Set 2K87M (AN2306) for details on

clock configuration.

2.5.2 Clocks Programming Model

This section describes the clock registers in detail. The registers discussed are as follows:

• System Clock Control Register (SCCR)

• System Clock Mode Register (SCMR)

Table 2-6. Maximum Frequencies

Characteristic Maximum Frequency in MHz

Core Frequency 250 275 300

CPM Frequency (CPMCLK) 166.67 183.33 200

Bus Frequency (BCLK) 83.33 91.67 100

Serial Communication Controller Clock Frequency (SCLK) 83.33 91.67 100

Baud Rate Generator Clock Frequency (BRGCLK) 83.33 91.67 100

External Clock Output Frequency (CLKOUT) 83.33 91.67 100

Clock Configuration

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-5

2.5.2.1 System Clock Control Register

SCCR is memory-mapped into the SIU register map of the MSC8101.

2.5.2.2 System Clock Mode Register

SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control

signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For

details of the available setting options, see AN2306/D.

Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

—

Type Reserved

Reset —

Bit16171819202122232425262728293031

—

CLKODIS

—DFBRG

Type Reserved R/W Reserved R/W

Reset — 0 — 0 1

Figure 2-2. System Clock Control Register (SCCR)—0x10C80

Table 2-7. SCCR Bit Descriptions

Name

Bit No. Defaults Description Settings

PORESET Hard Reset

—

0–26 — — Reserve d. Write to 0 fro future compatibility.

CLKODIS

27 0 Unaffected CLKOUT Disable

Disables the CLKOUT signal. The value of

CLKOUT when disabled is indeterminate (can be 1

or 0).

0 CLKOUT enabled (default)

1 CLKOUT disabled

—

28–29 — — Reserve d. Write to 0 fro future compatibility.

DFBRG

30–31 01 Unaffected Division Factor for the BRG Clock Defines the

BRGCLK frequency . Changing this value does not

result in a loss of lock condition.

00 Divide by 4

01 Divide by 16 (default value)

10 Divide by 64

11 Divide by 256

Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

COREPDF COREMF BUSDF CPMDF

Type R

Reset —

Bit16171819202122232425262728293031

SPLLPDF SPLLMF —DLLDIS —COREDF

Type R

Reset —

Figure 2-3. System Clock Mode Register (SCMR)—0x10C88

MSC8101 Technical Data, Rev. 19

2-6 Freescale Sem ico nd uctor

Physical and Electrical Specifications

Table 2-8. SCMR Field Descriptions

Name

Bit No.

Defaults Description Settings

PORESET Hard Reset

COREPDF

0–3 Configuration

Pins Unaffected Core PLL Pre-Division Factor 0000 CPLL PDF = 1

0001 CPLL PDF = 2

0010 CPLL PDF = 3

0011 CPLL PDF = 4

All other combinations not used.

COREMF

4–7 Configuration

Pins Unaffected Core Multiplication Fa ctor 0101 CPLL MF = 10

0110 CPLL MF = 12

0111 CPLL MF = 14

All other combinations not used.

BUSDF

8–11 Configuration

Pins Unaffected 60x-compatible Bus Division Factor 0001 Bus DF = 2

0010 Bus DF = 3

0011 Bus DF = 4

0100 Bus DF = 5

0101 Bus DF = 6

All other combinations not used.

CPMDF

12–15 Configuration

Pins Unaffected CPM Division Factor 0000 CPM DF = 1

0001 CPM DF = 2

0010 CPM DF = 3

All other combinations not used.

SPLLPDF

16–19 Configuration

Pins Unaffected SPLL Pre-Divis ion Factor 0000 SPLL PDF = 1

0001 SPLL PDF = 2

0010 SPLL PDF = 3

0011 SPLL PDF = 4

0100 SPLL PDF = 5

0101 SPLL PDF = 6

All other combinations not used

SPLLMF

20–23 Configuration

Pins Unaffected SPLL Multipli ca t i on Factor 0101 SPLL MF = 10

0110 SPLL MF = 12

0111 SPLL MF = 14

1000 SPLL MF = 16

1001 SPLL MF = 18

1010 SPLL MF = 20

1011 SPLL MF = 22

1100 SPLL MF = 24

1101 SPLL MF = 26

1110 SPLL MF = 28

1111 SPLL MF = 30

All other combinations not used

—

24 ——Reserved

DLLDIS

25 Configuration

Pins Unaffected DLL Disable 0 DLL operation is enabled

1 DLL is disabled

—

26–27 ——Reserved

COREDF

28–31 Configuration

Pins Unaffected Core Division Factor 0000 CORE DF = 1

0001 CORE DF = 2

0010 CORE DF = 3

0011 CORE DF = 4

0100 CORE DF = 5

0101 CORE DF = 6

All other combinations not used.

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-7

2.6 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and

inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50 Ω transmission line.

2.6.1 Ou tput Buffer Impedan ces

2.6.2 Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power.

Section 2. 6.3 des crib es the cl ocking charac te rist ics. Sec tion 2.6.4 describes the reset and power-up characteristics.

You must use the following guidelines when starting up an MSC8101 device:

•PORESET and TRST must be a ssert ed ext ernal ly fo r th e dur ation of t he power -up se quen ce. See Table 2-14

for timi ng.

• If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up

the VDDH levels and then the VDD leve ls (see Figure 2-5 and Figure 2-6).

•CLKIN can start togg ling afte r VDDH reaches it s nominal leve l, but it must toggle befo re VDD reaches 0.5 V to

guarantee correct device operation (see Figure 2-4 and Figure 2-6).

The foll owing fig ures show a cceptabl e start-up sequence examples. Figur e 2-4 shows a sequen ce in whic h VDD and

VDDH are raised together. Figure 2-5 shows a sequence in which CLKIN starts toggling after VDDH reaches its

nomina l le vel and bef ore VDD is appl ied. Figure 2-6 shows a sequence in which VDD is rais ed af ter VDDH and CLKIN

begins to toggle shortly before VDD reaches the 0.5 V level.

Table 2-9. Output Buffer Impedances

Output Buffers Typical Impedance (Ω)

System Bus 35

Memory Controller 35

Parallel I/O 55

Note: These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.

Figure 2-4. Start-Up Sequence with VDD and VDDH Raised Together

Voltage

Time

o.5 V

3.3 V

1.6 V

VDDH Nominal Level

PORESET/TRST Asserted

VDD Nominal Level

CLKIN Starts Toggling

VDD/VDDH Applied

PORESET/TRST Deasserted

2.2 V

VDDH = Nominal Value

VDD = Nominal V alue

MSC8101 Technical Data, Rev. 19

2-8 Freescale Sem ico nd uctor

Physical and Electrical Specifications

2.6.3 Clocking and Timing Characteristics

Figure 2-5. Start-Up Sequence with CLKIN Started After VDDH and Before VDD

Figure 2-6. Start-Up Sequence with VDDH Raised Before VDD with CLKIN Started Before VDD = 0.5 V

Table 2-10. System Clock Parameters

Characteristic Minimum Maximum Unit

Phase Jitter between BCLK and DLLIN — 0.5 ns

CLKIN frequency1,2 18 100 MHz

CLKIN slope — 5 ns

DLLIN slope — 2 ns

CLKOUT frequency jitter — (0.01/CLKOUT) + CLKIN jitter ns

Delay between CLKOUT and DLLIN — 5 ns

Notes: 1. Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after the

predivider (SPLLMFCLK) higher than 18 MHz.

2. CLKIN should have a 50% ± 5% duty cycle.

Voltage

Time

3.3 V

1.6 V

VDDH Nominal

PORESET/TRST asser ted

VDD Nominal

CLKIN starts toggling

VDDH applied

PORESET/TRST Deasserted

VDD applied

1.06 V

DDH

= Nominal

VDD = Nominal

Voltage

Time

o.5 V

3.3 V

1.6 V

VDDH Nominal

PORESET/TRST asserted

VDD Nominal

CLKIN starts toggling

VDDH applied PORESET/TRST deasser ted

VDD applied

1.06 V

DDH

= Nominal

VDD = Nominal

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-9

2.6.4 Reset Timing

The MSC8101 has several inputs to the reset logic:

• Power-on reset (PORESET)

• External hard reset (HRESET)

• External soft reset (SRESET)

Asserting an external PORESET causes concurrent assertion of an internal PORESET signal, HRESET, and SRESET.

When the external PORESET signal is deasserted, the MSC8101 samples several configuration pins:

•RSTCONF—determines whether the MSC8101 is a master (0) or slave (1) device

•DBREQ—determines whether to operate in normal mode (0) or invoke the SC140 debug mode (1)

•HPE—disable (0) or enable (1) the hos t port (HDI16)

•BTM[0–1]—boot from external memory (00) or the HDI16 (01)

All thes e rese t s ources are fe d into the re set con trol ler, which t akes di f feren t act ions dep end ing on t he sourc e of th e

reset. The reset status register indicates the last sources to cause a reset. Table 2-12 describes reset causes.

2.6.4.1 Reset Operation

The reset contro l logi c deter mines th e cau se of a re set, sy nchroni zes it if nec ess ary, and resets the appr opria te logi c

modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized

only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. The

MSC8101 has three mechanisms for reset configuration: host reset configuration, hardware reset configuration,

and reduced reset configuration.

Table 2-11. Clock Ranges

Clock Symbol

Maximum Rated Core Frequen cy

All Max. Values for SC140 Clock Rating of:

Min 250 MHz 275 MHz 3 00 MHz

Input Clock CLKIN 18 MHz 83.3 91.67 MHz 100 MHz

SPLL MF Clock SPLLMFCLK 18 MHz 31.25 34.38 MHz 37.5 MHz

Bus/Output BCLK

CLKOUT 18 MHz 83.3 MHz 91.67 MHz 100 MHz

Serial Communications Controller SCLK 35 MHz 83.3 MHz 91.67 MHz 100 MHz

Communications Processor Module CPMCLK 70 MHz 166.7 MHz 183.3 MHz 200 MHz

SC140 Core DSPCLK 72 MHz 250 MHz 275 MHz 300 MHz

Baud Rate Generator

• For BRG DF = 4

• For BRG DF = 16 (default)

• For BRG DF = 64

• For BRG DF = 256

BRGCLK 36 MHz

9 MHz

2.25 MHz

562.5 KHz

83.3 MHz

20.83 MHz

5.21 MHz

1.3 MHz

91.67 MHz

22.91 MHz

5.73 MHz

1.43 MHz

100 MHz

25 MHz

6.25 MHz

1.56 MHz

Table 2-12. Reset Causes

Name Direction Description

Power-on reset

(PORESET)Input PORESET initiates the power-on reset flow that resets all the MSC8101s and configures

various attributes of the MSC8101, including its clock mode.

Hard reset

(HRESET)Input/Output The MSC8101 can detect an external assertion of HRESET only if it occurs while the

MSC8101 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-

drain pin.

Soft reset

(SRESET)Input/Output The MSC8101 can detect an external assertion of SRESET only if it occurs while the

MSC8101 is not asserting reset. SRESET is an open-drain pin.

MSC8101 Technical Data, Rev. 19

2-10 Freescale Semico nd uct or

Physical and Electrical Specifications

2.6.4.2 Power-On Reset Flow

Asserting the PORESET external pin initiates the power-on reset flow.

Note: PORESET and TRST must be asserted externally for the duration of the power-up sequence.

As Table 2-13 shows, the MSC8101 has five configuration pins, four of which are multiplexed with the SC140

EONCE Event (EE[0–1], EE[4–5]) pins and the fifth of which is the RSTCONF pin. These pins are sampled at the

rising edge of PORESET. In addition to these configuration pins, three (MODCK[1–3]) pins are sampled by the

MSC8101. The signals on these pins and the MODCK_H valu e in the Hard Reset Configuration Word determin e

the PLL locking mode, by defining the ratio between the DSP clock, the bus clocks, and the CPM clock

frequencies.

Table 2-13. External Configuration Signals

Pin Description Settings

RSTCONF Reset Config ur a t ion

Input line sampled by the MSC8101 at the rising edge of

PORESET.

0 Reset Configuration Master.

1 Reset Configuration Slave.

DBREQ/ EE0 E O NCE Event Bit 0

Input line sampled after SC140 core PLL locks. Holding EE0

high when PORESET is deasserted puts the SC140 into

Debug mode.

0 SC140 starts the normal processing

mode after reset.

1 SC140 enters Debug mode immediately

after reset.

HPE/EE1 Host Port Enable

Input line sampled at the rising edge of PORESET. If

asserted, the Host port is enabled, the system data bus is

32-bit wide, and the Host must program the reset

configuration word.

0 Host port disabled (hardware reset

configuration enabled).

1 Host port enabled.

BTM[0–1]/

EE[4–5] Boot Mode

Input lines sampled at the rising edge of PORESET, which

determine the MSC8101 Boot mode.

00 MSC8101 boots from external memory.

01 MSC8101 boots from HDI16.

10 Reserved.

11 Reserved.

Table 2-14. Reset Timing

No. Characteristics Expression Min Max Unit

1 Required external PORESET duration minimum

• CLKIN = 18 MHz

• CLKIN = 75 MHz

16 / CLKIN 888.8

213.3 —

—ns

2 Delay from deassertion of external PORESET to deassertion of

internal PORESET

• CLKIN = 18 MHz

• CLKIN = 75 MHz

1024 / CLKIN

56.89

13.65 μs

μs

3 Delay from deassertion of internal PORESET to SPLL lock

• SPLLM FCLK = 18 MHz

• SPLLM FCLK = 25 MHz

800 / SPLLMFCLK 44.4

32.0 μs

μs

4 Delay from SPLL lock to DLL lock

• DLL enabled

— BCLK = 18 MHz

— BCLK = 75 MHz

• DLL disabled

3073 / BLCK

—

170.72

40.97

0.0

μs

5 Delay from SPLL lock to HRESET deassertion

• DLL enabled

— BCLK = 18 MHz

— BCLK = 75 MHz

• DLL disabled

— BCLK = 18 MHz

— BCLK = 75 MHz

3585 / BLCK

512 / BLCK

199.17

47.5

28.4

6.83

μs

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-11

2.6.4.3 Host Reset Configuration

Host res et config uration a llows the h ost to program the reset configur ation word via the Host port aft er PORESET is

deasser te d, as d escri bed in th e MSC8101 Re ference Manual. Th e MSC8101 s amples t he si gnals descr ibed i n Table

2-13 one the rising edge of PORESET when the signal is deasserted.

If HPE is sampled high, the host port is enabled. In this mode the RSTCONF pin must be pulled up. The device

extends the internal PORESET until the host programs the reset configuration word register. The host must write

four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration word,

which is 32 bits wide. For more information, see the MSC8101 Reference Manual . The re set con fi gur ati on word is

programmed before the internal PLL and DLL in the MSC8101 are locked. The host must program it after the

rising edge of the PORESET input. In this mode, the host must have its own clock that does not depend on the

MSC8101 clock. After the PLL and DLL are locked, HRESET remains asserted for another 512 bus clocks and is

then rele ased. The SRESET is released three bus cl ocks later (s ee Figure 2-7).

2.6.4.4 Hardware Reset Configuration

Hardware reset configuration is enabled if HPE is sample d l ow at the ris ing edge of PORESET. The val ue d ri ven on

RSTCONF while PORESET changes from assertion to deassertion determines the MSC8101 configuration. If

RSTCONF is deasserted (driven high) while PORESET changes, the MSC8101 acts as a configuration slave. If

6 Delay from SPLL lock to SRESET deassertion

• DLL enabled

— BCLK = 18 MHz

— BCLK = 75 MHz

• DLL disabled

— BCLK = 18 MHz

— BCLK = 75 MHz

3588 / BLCK

515 / BLCK

199.33

47.84

28.61

6.87

μs

Note: Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence.

Figure 2-7. Host Reset Configuration Timing

Table 2-14. Reset Timing (Continued)

No. Characteristics Expression Min Max Unit

PORESET

Internal

HRESET

Input

Output (I/O)

SRESET

Output (I/O)

HRESET/SRESET are

extended for 512/515 BUS

clocks, respectively , from PLL

and DLL lock

PLL locks after

800 SPLLMFCLKs and

DLL locks 3073 BUS clocks

after PLL is locked.

When DLL is disabled,

reset period is shortened by

DLL lock time.

RSTCONF, HPE

pins are sampled

HRM, BTM

Any time Host programs

Word MODCK_H bits

are ready for PLL.

MODCK[1–3] pins

are sampled.

PORESET

Reset Conf igur ati on

235

assert ed for

min 16

CLKIN.

PLL locked DLL locked

MSC8101 Technical Data, Rev. 19

2-12 Freescale Semico nd uct or

Physical and Electrical Specifications

RSTCONF is asserted (driven low) whi le PORESET changes, the MSC8101 acts as a configuration master. Section

2.6.4.4, Hardware Reset Configuration, explains the configuration sequence and the terms “configuration master”

and “configuration slave.”

Directly after the deassertion of PORESET and choice of the reset operation mode as configuration master or

configuration slave, the MSC8101 starts the configuration process. The MSC8101 asserts HRESET and SRESET

throughout the power-on reset process, including configuration. Configuration takes 1024 CLOCKIN cycles, after

which MODCK[1–3] are sampled to determine the MSC8101’s working mode.

Next, the MSC8101 ha lts unt il th e SPLL locks. The SPLL locks a ccordi ng to MODCK[1–3], which ar e samp led, and

to MODCK_H taken from the Reset Configur ation Word. SPLL locki ng ti me is 800 refe re nce cloc ks, whi ch is the

clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8101 are enabled.

If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is

locked. Duri ng PLL and DLL locking, HRESET and SRESET are assert ed. HRESET remains ass erted for anothe r 512

BUS clocks and is then released. The SRESET is released three bus clocks later. If the DLLDIS bit in the reset

configuration word is set, the DLL is bypassed and there is no locking process, thus saving the DLL locking time.

Figure 2-8 shows the power-on reset flow.

Figure 2-8. Hardware Reset Configuration Timing

PORESET

Internal

HRESET

Input

SRESET

RSTCONF is sampled for

master/slave determination

MODCK[1–3] are sampled.

MODCK_H bits are ready

for PLL.

HRESET/SRESET are

extended for 512/515 bus

clocks, respectively, from PLL

and DLL Lock time.

In reset configuration mode:

reset configuration sequence

occurs in this period. PLL locks after

800 SPLLMF CLK s. DLL

locks 3073 bus clocks after

PLL is locked.

When DLL is disabled , reset

period is shortened by 3073

bus clocks.

Output (I/O)

asserted for

min 16

CLKIN.

23 4

PLL locked DLL locked

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-13

2.6.5 System Bus Access Timing

2.6.5.1 Core Data Transfers

Generally, all MSC8101 bus and system output signals are driven from the rising edge of the reference clock

(REFCLK), which is DLLIN. Memory controller signals, however, trigger on four points within a DLLIN cycle.

Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at th e rising edg e of DLLIN (and

T3 at t he fa ll ing e dge), b ut the s pacing of T2 and T4 dep ends on the PLL c lock rat io se le cted, as Table 2-15 shows.

Figure 2-9 is a graphical representation of Table 2-15.

Note: The UPM machine and GPCM machine outputs change on the internal tick determined by the memory

controller programming; the AC specifications are relative to the internal tick. SDRAM machine outputs

change only on the DLLIN rising edge.

Table 2-15. Tick Spacing for Memory Controller Signals

PLL Clock Ratio Tick Spacing (T1 Occurs at the Rising Edge of DLLIN)

T2 T3 T4

1:2, 1:3, 1:4, 1:5, 1:6 1/4 DLLIN 1/2 DLLIN 3/4 DLLIN

1:2.5 3/10 DLLIN 1/2 DLLIN 8/10 DLLIN

1:3.5 4/14 DLLIN 1/2 DLLIN 11/14 DLLIN

Figure 2-9. Internal Tick Spacing for Memory Controller Signals

Table 2-16. AC Timing for SIU Inputs

No. Characteristic Value2Units

10 Hold time for all signals after the 50% level of the DLLIN rising edge 0.5 ns

11a ABB/AACK set-up time before the 50% level of the DLLIN rising edge 3.5 ns

11b DBG/DBB/BR/TC set-up time before the 50% level of the DLLIN rising edge 5.0 ns

11c ARTRY set-up time before the 50% level of the DLLIN rising edge 4.0 ns

11d TA set-up time before the 50% level of the DLLIN rising edge

• Pipeline mode

• Non-pipeline mode 3.5

4.0 ns

11e TEA set-up time before the 50% level of the DLLIN rising edge

• Pipeline mode

• Non-pipeline mode 4.0

3.0 ns

11f PSDVAL set-up time before the 50% level of the DLLIN rising edge

• Pipeline mode

• Non-pipeline mode 3.5

3.5 ns

DLLIN

T1 T2 T3 T4

DLLIN

T1 T2 T3 T4

for 1:2.5

for 1:3.5

DLLIN

T1 T2 T3 T4

for 1:2, 1:3, 1:4, 1:5, 1:6

MSC8101 Technical Data, Rev. 19

2-14 Freescale Semico nd uct or

Physical and Electrical Specifications

11g TS set-up time before the 50% level of the DLLIN rising edge 5.0 ns

11h BG set-up time before the 50% level of the DLLIN rising edge 4.5 ns

12 Data bus set-up time before the 50% level of the DLLIN rising edge in Normal

• Pipeline mode

• Non-pipeline mode 2.5

5.0 ns

13 Data bus set-up time before the 50% level of the DLLIN rising edge in ECC and PARITY modes

• Pipeline mode

• Non-pipeline mode 2.5

8.0 ns

14 DP set-up time before the 50% level of the DLLIN rising edge

• Pipeline mode

• Non-pipeline mode 4.0

9.0 ns

15a Address bus set-up time before the 50% level of the DLLIN rising edge

• Extra cycle mode (SIUBCR[EXDD] = 0)

• Non-extra cycle mode (SIUBCR[EXDD] = 1) 5.0

8.0 ns

15b Address attributes: TT/TBST/TSIZ/GBL set-up time before the 50% level of the DLLIN rising edge

• Extra cycle mode (SIUBCR[EXDD] = 0)

• Non-extra cycle mode (SIUBCR[EXDD] = 1) 5.0

5.5 ns

161PUPMWAIT/IRQ signals set-up time before the 50% level of the DLLIN rising edge 3.0 ns

Notes: 1. T he set-up time for these signals is for synchronous operation. Any set-up time can be used for asynchronous operation.

2. Input specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are

measured at the pin.

Table 2-17. AC Timing for SIU Outputs

No. Characteristic Min. Maximum2

Units

30 pF 50 pF

31a TA delay from the 50% level of the DLLIN rising edge

• Pipeline mode

• Non-pipeline mode 1.0

1.0 5.0

4.0 6.5

5.5 ns

31b TEA delay from the 50% level of the DLLIN rising edge

• Pipeline mode

• Non-pipeline mode 1.0

1.0 3.0

3.5 4.5

5.0 ns

31c PSDVAL delay from the 50% level of the DLLIN rising edge

• Pipeline mode

• Non-pipeline mode 1.0

1.0 4.0

3.5 5.5

5.0 ns

32a Address bus delay from the 50% level of the DLLIN rising edge

• Multi master mode (SI UBCR[EBM] = 1)

• Single master mode (SIUBCR[EBM] = 0) 1.0

1.0 6.3

5.5 7.8

7.0 ns

32b Address attributes: TT/TBST/TSIZ/GBL delay from the 50% level of the DLLIN rising edge 1.0 5.5 7.0 ns

32c B ADDR delay from the 50% level of the DLLIN rising edge 1.0 3.5 5.0 ns

33a Data bus delay from the 50% level of the DLLIN rising edge

• Pipeline mode

• Non-pipeline mode 1.0

1.0 5.0

6.0 6.5

7.5 ns

33b DP delay from the 50% level of the DLLIN rising edge

• Pipeline mode

• Non-pipeline mode 1.0

1.0 4.0

6.5 5.5

8.0 ns

34 Memory controller signals/ALE delay from the 50% level of the DLLIN rising edge 1.0 5.5 7.0 ns

35a DBG/BR/DBB delay from the 50% level of the DLLIN rising edge 1.0 4.0 5.5 ns

35b AACK/ABB/CS delay from the 50% level of the DLLIN rising edge 1.0 4.5 6.0 ns

Table 2-16. AC Timing for SIU Inputs

No. Characteristic Value2Units

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-15

35c BG delay from the 50% level of the DLLIN rising edge 1.0 4.0 5.5 ns

35d TS delay from the 50% level of the DLLIN rising edge 1.0 3.5 5.0 ns

36 Delay from the 50% level of the DLLIN rising edge for all other signals 1.0 4.5 6.0 ns

Notes: 1. The maximum bus frequency depends on the mode:

• I n 60x-compatible mode connected to another MSC8101 device, the frequency is determined by adding the input and output

longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when

connected to another MSC8101 device, the frequency is determined by adding the input and output longest timing values,

which results in a frequency of 75 MHz for 30 pF output capacitance.

• Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in slower bus

frequencies.

• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8101.

2. Output specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are

measured at the pin.

Table 2-17. AC Timing for SIU Outputs

No. Characteristic Min. Maximum2

Units

30 pF 50 pF

MSC8101 Technical Data, Rev. 19

2-16 Freescale Semico nd uct or

Physical and Electrical Specifications

Figure 2-10. Bus Signal Timing

DLLIN

AACK/ARTRY/TA/TEA/DBG/BG/BR

Data bus inputs—normal mode

PUPMWAIT/IRQn input

PSDVAL/TEA/TA outputs

Address bus/TT[0–4]/TC[0–2]/ TBST/TSIZ[0–3]/GBL/BADDR[27–31] outputs

Data bus outputs

All other normal mode outputs

11 10

33a

DP outputs 33b

Memory controller/ALE signals 34

Data bus inputs—ECC and parity modes 10

AACK/ARTRY/ABB/TS/DBG/BG/BR/DBB/CS signa ls 35

DP inputs 14

Address bus/TT[0–4]/TC[0–2]/TB ST/TSIZ[0–3]/GBL inputs

PSDVAL/ABB/DBB/TS inputs

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-17

2.6.5.2 DMA Data Transfers

Table 2-18 describes the D MA signa l timing.

The DREQ signal is synchron ized wit h the fall ing edge of DLLIN. DONE timing i s relati ve to the ri sing edg e of DLLIN.

To achieve fast response, a synchronized peripheral should assert DREQ according to the timin gs in Table 2-18.

Figure 2-11 shows synchronous peripheral interaction.

Table 2-18. DMA Signals

Number Characteristic Minimum Maximum Units

72 DREQ set-up time before DLLIN falling edge 6 — ns

73 DREQ hold time after DLLIN falling edge 0.5 — ns

74 DONE set-up time before DLLIN rising edge 9 — ns

75 DONE hold time after DLLIN rising edge 0.5 — ns

76 DACK/DRACK/DONE delay after DLLIN rising edge 0.5 9 ns

Figure 2-11. DMA Signals

DLLIN

DREQ

DONE Input

DACK/DONE/DRACK Outputs

74 75

MSC8101 Technical Data, Rev. 19

2-18 Freescale Semico nd uct or

Physical and Electrical Specifications

2.6.6 HDI16 Signals

Table 2-19. Host Interface (HDI16) Timing1, 2

Number Characteristics3Expression Value Unit

44a Read data strobe minimum assertion width4

HACK read minimum assertion width (1.5 × TC) + 5.0 Note 11 ns

44b Read data strobe minimum deassertion width4

HACK read minimum deassertion width TC + 5.0 Note 11 ns

44c Read data strobe minimum deassertion width4 after “Last Data Register”

reads5,6, or between two consecutive CVR, ICR, or ISR reads7

HACK minimum deassertion width after “Last Data Register” reads5,6

(2.5 × TC) + 5.0 Note 11 ns

45 Write data strobe minimum assertion width8

HACK write minimum assertion width (1.5 × TC) + 5.0 Note 11 ns

46 Write data strobe minimum deassertion width8

HACK write minimum deassertion width after ICR, CVR and Data Register

writes5(2.5 × TC) + 5.0 Note 11 ns

47 Host data input minimum set-up time before write data strobe deassertion8

Host data input minimum set-up time before HACK write deassertion — 5.0 ns

48 Host data input minimum hold time after write data strobe deassertion8

Host data input minimum hold time after HACK write deassertion — 5.0 ns

49 Read data strobe minimum assertion to output data active from high

impedance4

HACK read minimum assertion to output data active from high impedance — 5.0 ns

50 Read data strobe maximum assertion to output data valid4

HACK read maximum assertion to output data valid (2.0 × TC) + 5.0 Note 11 ns

51 Read data strobe maximum deasse rtion to output data high impedance4

HACK read maximum deassertion to output data high impedance — 5.0 ns

52 Output data minimum hold time after read data strobe deassertion4

Output data minimum hold time after HACK read deassertion — 5.0 ns

53 HCS[1–2] minimum assertion to read data strobe assertion4—5.0ns

54 HCS[1–2] minimum assertion to write data strobe assertion8—5.0ns

55 HCS[1–2] maximum assertion to output data valid TC + 5.0 Note 11 ns

56 HCS[1–2] minimum hold time after data strobe deassertion9—0.0ns

57 HA[0–3], HRW minimum set-up time before data strobe assertion9

• Read

•Write

—0

5.0 ns

58 HA[0–3], HRW minimum hold time after data strobe deassertion9—5.0ns

61 Maximum delay from read data strobe deassertion to host request deassertion

for “Last Data Register” read4, 5, 10 (3.5 × TC) + 5.0 Note 11 ns

62 Maximum delay from write data strobe deassertion to host request deassertion

for “Last Data Register” write5,8,10 (3.0 × TC) + 5 Note 11 ns

63 Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1)

deassertion to HREQ assertion. (5.0 × TC) + 5.0 Note 11 ns

64 Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD =1)

assertion to HREQ deassertion (3.5 × TC) + 5.0 Note 11 ns

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-19

Figure 2-12 and Figure 2-13 show HDI16 read signal timing. Figur e 2-14 and Figure 2-15 show HDI16 write

signal timing.

Notes: 1. TC = 1/ DSPCLK. At 300 MHz, TC = 3.3 ns

2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

3. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF

4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.

5. In 64-bit mode, The “last data register” is the register at address $7, which is the last location to be read or written in data

transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).

6. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers

without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.

7. This timing is applicable only if two consecutive reads from one of these registers are executed.

8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.

9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe

(HDS/HDS) in the single data strobe mode.

10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host

request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full

(treat as level Host Request).

11. Comp ute the value using the expression.

Figure 2-12. Read Timing Diagram, Single Data Strobe

Table 2-19. Host Interface (HDI16) Timing1, 2 (Continue d)

Number Characteristics3Expression Value Unit

HDS

HA[0–3]

HCS[1–2]

HD[0–15]

55 44c

44b

44a

5857

HREQ (single host request)

HRW

57 58

HRRQ (double host request)

MSC8101 Technical Data, Rev. 19

2-20 Freescale Semico nd uct or

Physical and Electrical Specifications

Figure 2-13. Read Timing Diagram, Double Data Strobe

Figure 2-14. Write Timing Diagram, Single Data Strobe

HRD

HA[0–3]

HCS[1–2]

HD[0–15]

55 44a

44b

44a

5857

HREQ (single host request)

HRRQ (double host request)

HDS

HA[0–3]

HCS[1–2]

HD[0–15]

5857

HRW

57 58

HREQ (single host request)

HTRQ (double host request)

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-21

Figure 2-16 shows Host DMA read timing.

Figure 2-15. Write Timing Diagram, Double Data Strobe

Figure 2-16. Host DMA Read Timing Diagram, HPCR[OAD] = 0

HWR

HA[0–3]

HCS[1–2]

HD[0–15]

5857 56

HREQ (single host request)

HTRQ (double host request)

RX[0–3]

Read

Data

Valid

44a

44b

49 52

(Output)

HREQ

HACK

HD[0–15]

(Output)

MSC8101 Technical Data, Rev. 19

2-22 Freescale Semico nd uct or

Physical and Electrical Specifications

Figure 2-17 shows Host DMA write timing.

2.6.7 CPM Timings

Figure 2-17. Host DMA Write Timing Diagram, HPCR[OAD] = 0

Table 2-20. CPM Input Characteristics

No. Characteristic Typical Unit

39 FCC input set-up time before low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial clock input) 10

5ns

17 FCC input hold time after low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial clock input) 0

3ns

18 SCC/SMC/SPI/I2C input set-up time before low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial clock input) 20

5ns

19 SCC/SMC/SPI/I2C input hold time after low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial clock input) 0

5ns

20 TDM input set-up time before low-to-high serial clock transition 5 ns

21 TDM input hold time after low-to-high serial transition 5 ns

22 PIO/TIMER/DMA input set-up time before low-to-high serial clock transition 10 ns

23 PIO/TIMER/DMA input hold time after low-to-high serial clock transition 3 ns

Note: FCC, SCC, SMC, SPI, I2C are Non-Multiplexed Serial Interface signals.

Table 2-21. CPM Output Characteristics

No. Characteristic Min Max Unit

41 FCC output delay after low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial input clock) 0

18 ns

TX[0–3]

Write

Data

Valid

47 48

(Output)

HREQ

HACK

HD[0–15]

(Output)

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-23

38 SCC/SMC/SPI/I2C output delay after low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial input clock) 0

020

30 ns

40 TDM output delay after low-to-high serial clock transition 5 15 ns

42 PIO/TIMER/DMA output delay after low-to-high serial clock transition 1 14 ns

Note: FCC, SCC, SMC, SPI, I2C are non-multiplexed serial interface signals.

Figure 2-18. FCC Inte rnal Cloc k Diagram

Figure 2-19. FCC External Clock Diagram

Figure 2-20. SCC/SMC/SPI/I2C Internal Clock Diagram

Figure 2-21. SCC/SMC/SPI/I2C External Clock Diagram

Table 2-21. CPM Output Characteristics

No. Characteristic Min Max Unit

BRGxO

FCC inputs

FCC outputs

29a 17a

41a

Serial input clock

FCC inputs

FCC outputs

39b 17b

41b

BRGxO

SCC/SMC/SPI/I2C inputs

SCC/SMC/SPI/I2C outputs

18a

19a

38a

Serial input clock

SCC/SMC/SPI/I2C inputs

SCC/SMCSPI/I2C outputs

18b 19b

38b

MSC8101 Technical Data, Rev. 19

2-24 Freescale Semico nd uct or

Physical and Electrical Specifications

Note: The ti ming values ref er to minimum system timing requirements. Actual implementation requi r es

conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and

output signals associated with the referenced internal controllers and supported communication protocols.

For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling

mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of

signals; the direction (input or output) of some of the shared signal names depends on the selected mode.

2.6.8 JTAG Signals

Figure 2-22. TDM Signal Diagram

Figure 2-23. PIO, Timer, and DMA Signal Diagram

Table 2-22. JTAG Timi ng

No. Characteristics All frequencies Unit

Min Max

500 TCK frequency of operation 0.0 40.0 MHz

501 TCK cyc le time 25.0 — ns

502 TCK clock pulse width measured at 1.6 V 12.5 — ns

503 TCK rise and fall times 0.0 3.0 ns

508 TMS, TDI data set-up time 6.0 — ns

509 TMS, TDI data hold time 3.0 — ns

510 TCK low to TDO data valid 0.0 15.0 ns

511 TCK low to TDO high impedance 0.0 20.0 ns

512 TRST assert time 100.0 — ns

513 TRST set-up time to TCK low 40.0 — ns

Serial input clock

TDM inputs

TDM outputs

20 21

DLLIN

PIO/TIMER/DMA inputs

PIO/TIM E R/D M A output s

AC Timings

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 2-25

Figure 2-24. Test Clock Input Timing Diagram

Figure 2-25. Test Access Port Timing Diagram

Figure 2-26. TRST Timing Diagram

TCK

(Input)

VMVM

VIH VIL

501

502 502

503503

TCK

(Input)

TDI

(Input)

TDO

(Output)

TDO

(Output)

TDO

(Output)

VIH

VIL

Input Data Valid

Output Data Valid

TMS

508 509

510

511

510

TCK

(Input)

TRST

(Input)

513

512

MSC8101 Technical Data, Rev. 19

2-26 Freescale Semico nd uct or

Physical and Electrical Specifications

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-1

Packaging 3

This chapter provides information about the MSC8101 package, including diagrams of the package pinouts and

tables showing how the signals discussed in Chapter 1 are allocated. The MSC8101 is available in a 332-pin

lidded fli p chip-plastic ball g rid array (FC-PBGA) .

3.1 FC-PBGA Package De scription

Figur e 3-1 a nd Figure 3-2 show top a nd bottom v iews of t he FC-PBGA pac kage, incl uding pi nouts. Table 3-1 lists

the MSC8101 signals alphabetically by signal name. Connections with multiple names are listed individually by

each name. Signals with programmable polarity are shown both as signals which are asserted low (default) and

high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is listed once

with the va rious signa ls that ar e mu lt ip lexed to it. For simp li ci ty, signal s wi t h prog rammable pola rity are sh own in

this table only with their default name (asserted low).

Note: The package description in this chapter applies to packages with lead-bearing and lead-free spheres.

MSC8101 Technical Data, Rev. 19

3-2 Freescale Sem ico nd uctor

Packaging

Figure 3-1. MSC8101 Flip Chip Plastic Ball Grid Array (FC-PBGA), Top View

1342567810 141312119

Top View

15 16

EE1

PA29

PA28

18 19

THERM

IRQ1

PA31

PB30

TDO

EE4

PA27

PB27

PC25

PC24

PC22

PB21

PB23

PA21

IRQ5

EE0

PD30

PD29

DP0

IRQ3

TMS

PD31

EED

EE3

PB28

PC26

PA25

PA24

SPARE

PB22

PD19

PA18

PB19

THERM

PC30

PC29

IRQ4

TRST

PC31

EE5

EE2

PC28

PB26

PB25

PB24

PA22

PA20

PC15

PA15

PD18

IRQ2

VDD

PB29

TCK

PB31

VDD

VDDH

VDD

VDDH

VDD

PA23

PB18

PA17

PC12

SRESET

PD16

IRQ6

GND

VDDH

GND

VDD

GND

PC23

PB20

PA19

PC13

NMI_

NMI

D17

D14

PA30

GND

D15

D16

D12

GND

D13

PC27

PA16

PD17

GND

VDDH

VCC

GND

VCC

GND

D11

GND

D10

GND

TDI

IRQ7

VDDH

GND

PA26

GND

VDDH

PC14

HRESET

TEST

RST

D22

D19

D20

D21

GND

D18

VDDH

CLKIN

DLL_IN

VDD

CLK

PA11

PA14

PA13

D62

PWE5

PSDA

PWE1

D61

PWE6

TEA

PWE7

PSDA

CS1

CS5

A28

A23

A19

A16

A11

D27

D24

D25

D26

D23

GND

VDD

GND

VDDH

PA12

PD7

PA9

PA10

D32

D29

D30

D31

GND

D28

VDDH

PC6

PC4

VDDH

PC7

PA7

PC5

PA8

D37

D34

D35

D36

D33

GND

VDDH

TSIZ3

GND

VDD

PA6

ABB

INT

SPARE

D42

D39

D40

D41

GND

D38

VDD

TT1

GND

VDDH

AACK

ARTRY

D46

D43

GND

D44

D45

PSD

BADDR

GND

VDDH

CS6

A21

TT0

GND

VDD

TBST

D51

D48

GND

PWE2

D49

D50

GND

BADDR

PSD

D47

GND

A26

GND

VDDH

TT3

TT4

TT2

D55

D52

VDDH

GND

D53

D54

VDDH

GND

VDDH

GND

VDDH

GND

VDDH

D60

D57

VDDH

D58

D59

VDDH

VDD

D56

VDD

CS0

VDDH

VDD

A15

A12

D63

GBL

PGTA

PWE0

DBB

DBG

MOD

ALE

MOD

CS3

CS7

A30

A27

A24

A20

A13

A10

A17

10 MOD

CK1

CK2

CK3

31 30

MUX

CS2

SYN1 OUT

CONF SYN1

OUT SYN

RESET

SYN

VAL

BADDR

POE

PWE4

BCTL0

PSD

CAS

PWE3

BCTL1

CS4

A31

A29

A25

A22

A14

A18

1342567810 1413121191516

18 19

_OUT

MSC8101

TSIZ1

TSIZ2

TSIZ0

Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name.

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-3

Figure 3-2. MSC8101 Flip Chip Plastic Ball Grid Array (FC-PBGA), Bottom Vie

134256781014 13 12 11 9

Bottom View

1516

EE1

PA29

PA28

1819 17

THERM

IRQ1

PA31

PB30

TDO

EE4

PA27

PB27

PC25

PC24

PC22

PB21

PB23

PA21

IRQ5

EE0

PD30

PD29

DP0

IRQ3

TMS

PD31

EED

EE3

PB28

PC26

PA25

PA24

SPARE

PB22

PD19

PA18

PB19

THERM

PC30

PC29

IRQ4

TRST

PC31

EE5

EE2

PC28

PB26

PB25

PB24

PA22

PA20

PC15

PA15

PD18

IRQ2

VDD

PB29

TCK

PB31

VDD

VDDH

VDD

VDDH

VDD

PA23

PB18

PA17

PC12

SRESET

PD16

IRQ6

GND

VDDH

GND

VDD

GND

PC23

PB20

PA19

PC13

NMI_

NMI

D17

D14

PA30

GND

D15

D16

D12

GND

D13

PC27

PA16

PD17

GND

VDDH

VCC

GND

VCC

GND

D11

GND

D10

GND

TDI

IRQ7

VDDH

GND

PA26

GND

VDDH

PC14

HRESET

TEST

RST

D22

D19

D20

D21

GND

D18

VDDH

CLKIN

DLL_IN

VDD

CLK

PA11

PA14

PA13

D62

PWE5

PSDA

PWE1

D61

PWE6

TEA

PWE7

PSDA

CS1

CS5

A28

A23

A19

A16

A11

D27

D24

D25

D26

D23

GND

VDD

GND

VDDH

PA12

PD7

PA9

PA10

D32

D29

D30

D31

GND

D28

VDDH

PC6

PC4

VDDH

PC7

PA7

PC5

PA8

D37

D34

D35

D36

D33

GND

VDDH

GND

VDD

PA6

ABB

INT

SPARE

D42

D39

D40

D41

GND

D38

VDD

TT1

GND

VDDH

AACK

ARTRY

D46

D43

GND

D44

D45

PSD

BADDR

GND

VDDH

CS6

A21

TT0

GND

VDD

TBST

D51

D48

GND

PWE2

D49

D50

GND

BADDR

PSD

D47

GND

A26

GND

VDDH

TT3

TT4

TT2

D55

D52

VDDH

GND

D53

D54

VDDH

GND

VDDH

GND

VDDH

GND

VDDH

D60

D57

VDDH

D58

D59

VDDH

VDD

D56

VDD

CS0

VDDH

VDD

A15

A12

D63

GBL

PGTA

PWE0

DBB

DBG

MOD

ALE

MOD

CS3

CS7

A30

A27

A24

A20

A13

A10

A17

MOD

CK1

CK2

CK3

3130

MUX

CS2

SYN1

OUT

5CONF

SYN1

OUT

SYN

RESET

SYN

VAL

BADDR

POE

PWE4

BCTL0

PSD

CAS

PWE3

BCTL1

CS4

A31

A29

A25

A22

A14

A18

134256781014 13 12 11 91516

1819 17

_OUT

MSC8101

TSIZ1

TSIZ3

TSIZ0

TSIZ2

Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name.

MSC8101 Technical Data, Rev. 19

3-4 Freescale Sem ico nd uctor

Packaging

Table 3-1. MSC8101 Signal Listing By Name

Signal Name Number

A0 W15

A1 N14

A2 V15

A3 T14

A4 U15

A5 W16

A6 V16

A7 W17

A8 U16

A9 V17

A10 W18

A11 U17

A12 T16

A13 V18

A14 V19

A15 R16

A16 T17

A17 U18

A18 U19

A19 R17

A20 T18

A21 M13

A22 T19

A23 P17

A24 R18

A25 R19

A26 M14

A27 P18

A28 N17

A29 P19

A30 N18

A31 N19

AACK T12

ABB V11

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-5

ALE H18

ARTRY U12

BADDR27 D19

BADDR28 B19

BADDR29 C19

BADDR30 H14

BADDR31 H13

BCTL0 F19

BCTL1 L19

BG V12

BNKSEL0 E18

BNKSEL1 F18

BNKSEL2 G18

BR H17

BRG1O H3

BRG1O V2

BRG2O J3

BRG2O N7

BRG3O K3

BRG4O L3

BRG5O L7

BRG6O M2

BRG7O N1

BRG8O P1

BTM0 E1

BTM1 F3

CD for FCC1 N10

CD for FCC2 P10

CD/RENA fo r SCC1 T6

CD/REN A for SCC 2 V4

CLK1 H3

CLK2 J3

CLK3 K3

CLK4 L3

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

MSC8101 Technical Data, Rev. 19

3-6 Freescale Sem ico nd uctor

Packaging

CLK5 L7

CLK6 M2

CLK7 N1

CLK8 P1

CLK9 N5

CLK10 R1

CLKIN N8

CLKOUT T8

COL for FCC1 G1

COL for FCC2 M1

CRS for FCC1 J7

CRS for FCC2 M3

CS0 M16

CS1 L17

CS2 K19

CS3 L18

CS4 M19

CS5 M17

CS6 L13

CS7 M18

CTS for FCC1 T10

CTS for FCC2 W10

CTS/CLSN for SCC1 K3

CTS/CLSN for SCC1 V3

CTS/CLSN for SCC2 L3

CTS/CLSN for SCC2 T5

D0 B3

D1 A3

D2 C4

D3 B4

D4 A4

D5 C5

D6 B5

D7 A5

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-7

D8 D6

D9 C6

D10 B6

D11 A6

D12 G7

D13 E7

D14 D7

D15 C7

D16 B7

D17 A7

D18 F8

D19 D8

D20 C8

D21 B8

D22 A8

D23 G9

D24 D9

D25 C9

D26 B9

D27 A9

D28 F10

D29 D10

D30 C10

D31 B10

D32 A10

D33 G11

D34 D11

D35 C11

D36 B11

D37 A11

D38 F12

D39 D12

D40 C12

D41 B12

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

MSC8101 Technical Data, Rev. 19

3-8 Freescale Sem ico nd uctor

Packaging

D42 A12

D43 D13

D44 C13

D45 B13

D46 A13

D47 E14

D48 D14

D49 C14

D50 B14

D51 A14

D52 D15

D53 C15

D54 B15

D55 A15

D56 E16

D57 D16

D58 C16

D59 B16

D60 A16

D61 C17

D62 A17

D63 A18

DACK1 N5

DACK2 N1

DACK3 D5

DACK4 F6

DBB C18

DBG B18

DBREQ D2

DLLIN P8

DP0 C2

DP1 B1

DP2 D4

DP3 B2

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-9

DP4 C3

DP5 A2

DP6 D5

DP7 F6

DRACK1/DONE1 H2

DRACK2/DONE2 J2

DREQ1 R1

DREQ2 P1

DREQ3 C3

DREQ4 A2

EE0 D2

EE1 D1

EE2 E3

EE3 E2

EE4 E1

EE5 F3

EED F2

EXT_BG2 B1

EXT_BG3 C3

EXT_BR2 C2

EXT_BR3 B2

EXT_DBG2 D4

EXT_DBG3 A2

EXT1 H3

EXT2 N5

GBL D18

GND F11

GND F13

GND F15

GND F5

GND F7

GND F9

GND G10

GND G12

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

MSC8101 Technical Data, Rev. 19

3-10 Freescale Semico nd uct or

Packaging

GND G14

GND G6

GND G8

GND H15

GND H5

GND H7

GND J14

GND J5

GND J6

GND K13

GND K15

GND K6

GND K7

GND L14

GND L15

GND L5

GND L6

GND M15

GND M5

GND N6

GND N9

GND P11

GND P12

GND P13

GND P14

GND P15

GND P6

GND P7

GND P9

GNDSYN V7

GNDSYN1 U7

H8BIT B16

HA0 D14

HA1 C14

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-11

HA2 B14

HA3 A14

HACK/HACK E16

HCS1/HCS1 D15

HCS2/HCS2 A16

HD0 A10

HD1 G11

HD2 D11

HD3 C11

HD4 B11

HD5 A11

HD6 F12

HD7 D12

HD8 C12

HD9 B12

HD10 A12

HD11 D13

HD12 C13

HD13 B13

HD14 A13

HD15 E14

HDDS C16

HDS/HDS B15

HDSP D16

HPE D1

HRD/HRD C15

HREQ/HREQ A15

HRESET V6

HRRQ/HRRQ E16

HRW C15

HTRQ/HTRQ A15

HWR/HWR B15

INT_OUT W11

IRQ1 B1

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

MSC8101 Technical Data, Rev. 19

3-12 Freescale Semico nd uct or

Packaging

IRQ1 D18

IRQ2 C19

IRQ2 D4

IRQ2 V11

IRQ3 B2

IRQ3 C18

IRQ3 H14

IRQ4 C3

IRQ5 A2

IRQ5 H13

IRQ6 D5

IRQ7 F6

IRQ7 W11

L1RSYNC for SI1 TDMA1 T11

L1RSYNC for SI2 TDMB2 K4

L1RSYNC for SI2 TDMC2 P3

L1RSYNC for SI2 TDMD2 P5

L1RXD for SI1 TDMA1 Serial U10

L1RXD for SI2 TDMB2 H1

L1RXD for SI2 TDMC2 M3

L1RXD for SI2 TDMD2 T2

L1RXD0 for SI1 TDMA1 Nibble U10

L1RXD1 for SI1 TDMA1 Nibble T2

L1RXD2 for SI1 TDMA1 Nibble V1

L1RXD3 for SI1 TDMA1 Nibble P3

L1TSYNC for SI1 TDMA1 V10

L1TSYNC for SI2 TDMB2 L2

L1 TSYNC fo r SI2 TD M C 2 N 3

L1 TSYNC fo r SI2 TD M D 2 T1

L1TXD for SI1 TDMA1 Serial W9

L1TXD for SI2 TDMB2 H4

L1TXD for SI2 TDMC2 M1

L1TXD for SI2 TDMD2 V1

L1TXD0 for SI1 TDMA1 Nibble W9

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-13

L1TXD1 for SI1 TDMA1 Nibble P5

L1TXD2 for SI1 TDMA1 Nibble T1

L1TXD3 for SI1 TDMA1 Nibble N3

LIST1 for SI1 R1

LIST1 for SI2 T10

LIST2 for SI1 T6

LIST2 for SI2 N10

LIST3 for SI1 V 4

LIST3 for SI2 W10

LIST4 for SI1 T5

LIST4 for SI2 P10

MODCK1 E18

MODCK2 F18

MODCK3 G18

MSNUM0 N2

MSNUM1 P2

MSNUM2 U8

MSNUM3 T9

MSNUM4 V8

MSNUM5 U9

NMI U5

NMI_OUT V5

PA6 T11

PA7 V10

PA8 U10

PA9 W9

PA10 U9

PA11 V8

PA12 T9

PA13 U8

PA14 W8

PA15 W3

PA16 M7

PA17 T4

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

MSC8101 Technical Data, Rev. 19

3-14 Freescale Semico nd uct or

Packaging

PA18 W2

PA19 R5

PA20 T3

PA21 U1

PA22 R3

PA23 P4

PA24 P2

PA25 N2

PA26 M6

PA27 L1

PA28 K1

PA29 J1

PA30 J7

PA31 G1

PB18 R4

PB19 U2

PB20 P5

PB21 T1

PB22 T2

PB23 V1

PB24 P3

PB25 N3

PB26 M3

PB27 M1

PB28 L2

PB29 K4

PB30 H1

PB31 H4

PBS0 K18

PBS1 K17

PBS2 K14

PBS3 J19

PBS4 H19

PBS5 D17

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-15

PBS6 B17

PBS7 F17

PC4 P10

PC5 W10

PC6 N10

PC7 T10

PC12 V4

PC13 T5

PC14 T6

PC15 V3

PC22 R1

PC23 N5

PC24 P1

PC25 N1

PC26 M2

PC27 L7

PC28 L3

PC29 K3

PC30 J3

PC31 H3

PD7 V9

PD16 U4

PD17 N7

PD18 U3

PD19 V2

PD29 K2

PD30 J2

PD31 H2

PGPL0 E17

PGPL1 F14

PGPL2 G19

PGPL3 E19

PGPL4 J18

PGPL5 J17

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

MSC8101 Technical Data, Rev. 19

3-16 Freescale Semico nd uct or

Packaging

PGTA J18

POE G19

PORESET W5

PPBS J18

PSDA10 E17

PSDAMUX J17

PSDCAS E19

PSDDQM0 K18

PSDDQM1 K17

PSDDQM2 K14

PSDDQM3 J19

PSDDQM4 H19

PSDDQM5 D17

PSDDQM6 B17

PSDDQM7 F17

PSDRAS G19

PSDVAL G13

PSDWE F14

PUPMWAIT J18

PWE0 K18

PWE1 K17

PWE2 K14

PWE3 J19

PWE4 H19

PWE5 D17

PWE6 B17

PWE7 F17

Reserved A17

Reserved A18

Reserved C2

Reserved C17

Reserved C19

Reserved H14

Reserved H13

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-17

RSTCONF U6

RTS for FCC1 J7

RTS for FCC2 L2

RTS/TENA for SC C1 K2

RTS/TENA for SCC2 L2

RX_DV for FCC1 L1

RX_DV for FCC2 H1

RX_ER for FCC1 M6

RX_ER for FCC2 L2

RXADDR0 for FCC1 UTOPIA 8 T6

RXADDR1 for FCC1 UTOPIA 8 V4

RXADDR2 for FCC1 UTOPIA 8 N10

RXADDR2/RXCLAV1 for FCC1 UTOPIA 8 N10

RXADDR3 for FCC1 UTOPIA 8 K2

RXADDR4 for FCC1 UTOPIA 8 U 3

RXCLAV for FCC1 UTOPIA 8 M6

RXCLAV0 for FCC1 UTOPIA 8 M6

RXCLAV2 for FCC1 UTOPIA 8 K2

RXCLAV3 for FCC1 UTOPIA 8 V4

RXD for FCC1 transparent/HDLC serial T4

RXD for FCC2 transparent/HDLC serial T1

RXD for SCC1 H2

RXD for SCC2 H4

RXD0 for FCC1 MII/HDLC nibble T4

RXD0 for FCC1 UTOPIA 8 U9

RXD0 for FCC2 MII/HDLC nibble T1

RXD1 for FCC1 MII/HDLC nibble M7

RXD1 for FCC1 UTOPIA 8 V 8

RXD1 for FCC2 MII/HDLC nibble P5

RXD2 for FCC1 MII/HDLC nibble W3

RXD2 for FCC1 UTOPIA 8 T9

RXD2 for FCC2 MII/HDLC nibble U2

RXD3 for FCC1 MII/HDLC nibble W8

RXD3 for FCC1 UTOPIA 8 U8

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

MSC8101 Technical Data, Rev. 19

3-18 Freescale Semico nd uct or

Packaging

RXD3 for FCC2 MII/HDLC nibble R4

RXD4 for FCC1 UTOPIA 8 W8

RXD5 for FCC1 UTOPIA 8 W3

RXD6 for FCC1 UTOPIA 8 M7

RXD7 for FCC1 UTOPIA 8 T4

RXENB for FCC1 K1

RXPRTY for FCC1 UTOPIA 8 N7

RXSOC for FCC1 L1

SCL R4

SDA U2

SMRXD for SMC1 P10

SMRXD for SMC2 U10

SMSYN for SMC1 V9

SMSYN for SMC 2 V10

SMTXD for SMC1 W10

SMTXD for SMC2 W9

SMTXD for SMC2 V3

SPARE1 R2

SPARE5 U11

SPICLK U3

SPIMISO U4

SPIMOSI N7

SPISEL V2

SRESET W4

TA J13

TBST U13

TC0 E18

TC1 F18

TC2 G18

TCK G4

TDI H6

TDO F1

TEA G17

TEST W6

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-19

TGATE1 H3

TGATE2 L7

THERM1 C1

THERM2 D3

TIN1/TOUT2 L3

TIN2 K3

TIN3/TOUT4 P1

TIN4 N1

TMCLK M2

TMS G2

TOUT1 J3

TOUT3 M2

TRST G3

TS T13

TSIZ0 V13

TSIZ1 W13

TSIZ2 W12

TSIZ3 N11

TT0 N13

TT1 N12

TT2 U14

TT3 V14

TT4 W14

TX_EN for FCC1 MII K1

TX_EN for FCC2 MII K4

TX_ER for FCC1 MII J1

TX_ER for FCC2 MII H4

TXADDR0 for FCC1 UTOPIA 8 V3

TXADDR1 for FCC1 UTOPIA 8 T5

TXADDR2 for FCC1 UTOPIA 8 T10

TXADDR3 for FCC1 UTOPIA 8 V9

TXADDR4 for FCC1 UTOPIA 8 V2

TXCLAV for FCC1 UTOPIA 8 J7

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

MSC8101 Technical Data, Rev. 19

3-20 Freescale Semico nd uct or

Packaging

TXCLAV0 for FCC1 UTOPIA 8 J7

TXCLAV1 for FCC1 UTOPIA 8 T10

TXCLAV2 for FCC1 UTOPIA 8 V9

TXCLAV3 for FCC1 UTOPIA 8 V2

TXD for FCC1 transparent/HDLC serial W2

TXD for FCC2 transparent/HDLC serial T2

TXD for SCC1 J2

TXD for SCC2 H1

TXD0 for FCC1 MII/HDLC nibble W2

TXD0 for FCC1 UTOPIA 8 N2

TXD0 for FCC2 MII/HDLC nibble T2

TXD1 for FCC1 MII/HDLC nibble R5

TXD1 for FCC1 UTOPIA 8 P2

TXD1 for FCC2 MII/HDLC nibble V1

TXD2 for FCC1 MII/HDLC nibble T3

TXD2 for FCC1 UTOPIA 8 P4

TXD2 for FCC2 MII/HDLC nibble P3

TXD3 for FCC1 MII/HDLC nibble U1

TXD3 for FCC1 UTOPIA 8 R3

TXD3 for FCC2 MII/HDLC nibble N3

TXD4 for FCC1 UTOPIA 8 U1

TXD5 for FCC1 UTOPIA 8 T3

TXD6 for FCC1 UTOPIA 8 R5

TXD7 for FCC1 UTOPIA 8 W2

TXENB for FCC1 G1

TXPRTY for FC C1 UTOPIA 8 U4

TXSOC for FCC1 J1

VCCSYN W7

VCCSYN1 T7

VDD E12

VDD E5

VDD E9

VDD F16

VDD F4

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-21

VDD H16

VDD J4

VDD L16

VDD L4

VDD N4

VDD P16

VDD R11

VDD R13

VDD R8

VDDH E10

VDDH E11

VDDH E13

VDDH E15

VDDH E4

VDDH E6

VDDH E8

VDDH G15

VDDH G16

VDDH G5

VDDH J15

VDDH J16

VDDH K16

VDDH K5

VDDH M4

VDDH N15

VDDH N16

VDDH R10

VDDH R12

VDDH R14

VDDH R15

VDDH R6

VDDH R7

VDDH R9

VDDH T15

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

MSC8101 Technical Data, Rev. 19

3-22 Freescale Semico nd uct or

Packaging

Table 3-2. MSC8101 Signal Listing by Pin Designator

Number Signal Name

A2 IRQ5 / DP5 / DREQ4 / EXT_DBG3

A3 D1

A4 D4

A5 D7

A6 D11

A7 D17

A8 D22

A9 D27

A10 D32 / HD0

A11 D37 / HD5

A12 D42 / HD10

A13 D46 / HD14

A14 D51 / HA3

A15 D55 / HREQ / HTRQ

A16 D60 / HCS2

A17 D62 / Reserved

A18 D63 / Reserved

IRQ1

/ DP1 /

EXT_BG2

B2 IRQ3 / DP3 /

EXT_BR3

B3 D0

B4 D3

B5 D6

B6 D10

B7 D16

B8 D21

B9 D26

B10 D31

B11 D36 / HD4

B12 D41 / HD9

B13 D45 / HD13

B14 D50 / HA2

B15 D54 / HDS / HWR

B16 D59 / H8BIT

B17 PWE6 / PSDDQM6 / PBS6

B18 DBG

B19 BADDR28

C1 THERM1

C2 Reserved / DP0 / EXT_BR2

C3 IRQ4 / DP4 / DREQ3 / EXT_BG3

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-23

C4 D2

C5 D5

C6 D9

C7 D15

C8 D20

C9 D25

C10 D30

C11 D35 / HD3

C12 D40 / HD8

C13 D44 / HD12

C14 D49 / HA1

C15 D53 / HRW / HRD

C16 D58 / HDDS

C17 D61

C18

DBB

/ IRQ3

C19 BADDR29 / IRQ2

D1 HPE / EE1

D2 DBREQ / EE0

D3 THERM2

D4 IRQ2 / DP2 /

EXT_DBG2

IRQ6

/ DP6 / DACK3

D6 D8

D7 D14

D8 D19

D9 D24

D10 D29

D11 D34 / HD2

D12 D39 / HD7

D13 D43 / HD11

D14 D48 / HA0

D15 D52 / HCS1

D16 D57 / HDSP

D17

PWE5

PSDDQM5

/ PBS5

D18

IRQ1

GBL

D19 BADDR27

E1 BTM0 / EE4

E2 EE3

E3 EE2

E4 VDDH

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

MSC8101 Technical Data, Rev. 19

3-24 Freescale Semico nd uct or

Packaging

E5 VDD

E6 VDDH

E7 D13

E8 VDDH

E9 VDD

E10 VDDH

E11 VDDH

E12 VDD

E13 VDDH

E14 D47 / HD15

E15 VDDH

E16 D56 / HACK / HRRQ

E17 PSDA10 / PGPL0

E18 MODCK1 / TC0 / BNKSEL0

E19

PSDCAS

/ PGPL3

F1 TDO

F2 EED

F3 BTM1 / EE5

F4 VDD

F5 GND

IRQ7

/ DP7 / DACK4

F7 GND

F8 D18

F9 GND

F10 D28

F11 GND

F12 D38 / HD6

F13 GND

F14

PSDWE

/ PGPL1

F15 GND

F16 VDD

F17

PWE7

PSDDQM7

/ PBS7

F18 MODCK2 / TC1 / BNKSEL1

F19 BCTL0

G1 PA31 / FCC1:UTOPIA8:TXENB / FCC1 :MII:C O L

G2 TMS

G3 TRST

G4 TCK

G5 VDDH

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-25

G6 GND

G7 D12

G8 GND

G9 D23

G10 GND

G11 D33 / HD1

G12 GND

G13 PSDVAL

G14 GND

G15 VDDH

G16 VDDH

G17 TEA

G18 MODCK3 / TC2 / BNKSEL2

G19

POE

PSDRAS

/ PGPL2

H1 PB30 / FCC2:MII:RX_DV / SCC2:TXD / TDBM2:L1RXD

H2 PD31 / SCC1:RXD / DRACK1 / DONE1

H3 PC31 / BRG1O / CLK1 / TGATE1

H4 PB31 / FCC2:MII:TX_E R / SCC2:RXD / TDMB 2 :L1 TXD

H5 GND

H6 TDI

H7 GND

H13 Reserved / BADDR31 / IRQ5

H14 Reserved / BADDR30 / IRQ3

H15 GND

H16 VDD

H17 BR

H18 ALE

H19 PWE4 / PSDDQM4 / PBS4

J1 PA29 / FCC1:UTOPIA8:TXSOC / FCC1:MII:TX_ER

J2 PD30 / SCC1:TXD / DMA:DRACK2/DONE2

J3 PC30 / EXT1 / BRG 2 O / C L K2 / TOUT1

J4 VDD

J5 GND

J6 GND

J7 PA3 0 / FC C 1 : U TO PIA8 :T XC LAV / FC C 1:UTOPIA8 :T XC L AV0 / FC C 1 :M II:CR S /

FCC1:HDLC and transparent:RTS

J13 TA

J14 GND

J15 VDDH

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

MSC8101 Technical Data, Rev. 19

3-26 Freescale Semico nd uct or

Packaging

J16 VDDH

J17 PSDAM U X / PG PL5

J18 PGTA

/ PUPM WAIT / PPBS / PGPL4

J19 PWE3 /

PSDDQM3

/ PBS3

K1 PA28 / FCC1:UTOPIA8:RXENB / FCC 1 :MII:T X_ EN

K2 PD29 / FCC1:UTOPIA8:RXADDR3 / FCC1:UTOPIA8:RXCLAV2 /

SCC1:RTS/TENA

K3 PC29 / SCC1:C T S / SCC1:CLSN / BRG3O / CLK3 / TIN2

K4 PB29 / FCC2:MII:TX_EN / TDMB2:L 1 R SYNC

K5 VDDH

K6 GND

K7 GND

K13 GND

K14 PWE2 /

PSDDQM2

/ PBS2

K15 GND

K16 VDDH

K17 PWE1 /

PSDDQM1

/ PBS1

K18 PWE0 /

PSDDQM0

/ PBS0

K19 CS2

L1 PA27 / FCC1 :UTOPIA8 :R XSOC / FCC 1 :MII:R X_DV

L2 PB28 / FCC2:RX_ER / FCC2:HDLC:RTS / SCC2:RTS/TENA / TDMB2:L1TSYNC

L3 PC28 / SCC2:CTS/CLSN / BRG4O / CLK4 / TIN1/TOUT2

L4 VDD

L5 GND

L6 GND

L7 PC27 / CLK5 / BRG5O / TGATE2

L13 CS6

L14 GND

L15 GND

L16 VDD

L17 CS1

L18 CS3

L19 BCTL1

M1 PB27 / FCC2:MII:COL / TDMC2:L1TXD

M2 PC26 / TMCLK / BRG6O / CLK6 / TOUT3

M3 PB2 6 / F C C 2 :MII:CRS / TDMC2:L1R XD

M4 VDDH

M5 GND

M6 PA26 / FC C1:UTO PIA8:RXCLAV / FCC1 :UT O PIA8:RXCLAV0 /

FCC1:MII:RX_ER

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-27

M7 PA16 / FCC1:UTOPIA8:RXD6 / FCC1:MII and HDLC nibble:RXD1

M13 A21

M14 A26

M15 GND

M16 CS0

M17 CS5

M18 CS7

M19 CS4

N1 PC25 / DMA:DACK2 / BRG7O / CLK7 / TIN4

N2 PA25 / FCC1:UTOPIA8 :TXD0 / SD MA:MS NUM0

N3 PB 25 / FCC2:MII and HDLC nibble:TXD3 / TDMA1:nibble:L1TXD3 /

TDMC2:L1TSYNC

N4 VDD

N5 PC23 / EXT2 / DMA:DACK1 / CLK9

N6 GND

N7 PD17 / FCC 1:U T O PI A8: R XPRTY / SPI:SP IMOSI / BR G 2 O

N8 CLKIN

N9 GND

N10 PC6 / FCC1:UTOPIA8:RXADDR2 / FCC1:UTOPIA8:RXADDR2/RXCLAV1 /

FCC1:CD / SI2:LIST2

N11 TSIZ3

N12 TT1

N13 TT0

N14 A1

N15 VDDH

N16 VDDH

N17 A28

N18 A30

N19 A31

P1 PC24 / DMA:DREQ2 / BRG8O / CLK8 / TIN3/ TOUT4

P2 PA24 / FCC1:UTOPI A8 :TXD1 / SD MA:MS NUM1

P3 PB24 / FCC2:MII and HDLC nibble:TXD2 / TDMA1:nibble:L1RXD3 /

TDMC2:L1RSYNC

P4 PA23 / FCC1:UTOPIA8:TXD2

P5 PB20 / FCC2:MII and HDLC nibble:RXD1 / TDMA1:nibble:L1TXD1 /

TDMD2:L1RSYNC

P6 GND

P7 GND

P8 DLLIN

P9 GND

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

MSC8101 Technical Data, Rev. 19

3-28 Freescale Semico nd uct or

Packaging

P10 PC4 / FCC2:CD / SMC1:SM R XD / SI2:L IST4

P11 GND

P12 GND

P13 GND

P14 GND

P15 GND

P16 VDD

P17 A23

P18 A27

P19 A29

R1 PC22 / SI1:LIST1 / DREQ1 / CLK10

R2 SPARE1

R3 PA22 / FCC 1 :UTOPIA8:T XD 3

R4 PB18 / FCC2:MII and HDLC nibble:RXD3 / I2C:SCL

R5 PA19 / FCC1:UTOPIA8:TXD6 / FCC1:MII and HDLC nibble:TXD1

R6 VDDH

R7 VDDH

R8 VDD

R9 VDDH

R10 VDDH

R11 VDD

R12 VDDH

R13 VDD

R14 VDDH

R15 VDDH

R16 A15

R17 A19

R18 A24

R19 A25

T1 PB21 / FCC2:MII and HDLC nibble:RXD0 /

FCC2:transparent and HDLC serial:RXD /TDMA1:nibble:L1TXD2 /

TDMD2:L1TSYNC

T2 PB22 / FCC2:MII and HDLC nibble TXD0 /

FCC2:transparent and HDLC serial TXD /TDMA1:nibble L1RXD1 /

TDMD2:L1RXD

T3 PA20 / FCC1:UTOPIA8 TXD5 / FCC1:MII and HDLC nibble TXD2

T4 PA17 / FCC1:UTOPIA8 RXD7 / FCC1:MII and HDLC nibble RXD0 /

FCC1:transparent and HDLC serial RXD

T5 PC13 / FCC1:UTOPIA8:TXADDR1 / SCC2:CTS/CLSN / SI1:LIST4

T6 PC14 / FCC1:UTOPIA8:RXADDR0 / SCC1:CD/RE NA / SI 1:LI ST 2

T7 VCCSYN1

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

FC-PBGA Package Description

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-29

T8 CLKOUT

T9 PA12 / FCC1 :UT O PI A8: R XD 2 / SDMA:MSN U M 3

T10 PC7 / FCC1:UTOPIA8:TXADDR2 /

FCC1:UTOPIA8:TXADDR2/TXCLAV1 / FCC1:CTS / SI1:LIST1

T11 PA6 / TDMA1:L1RSYNC

T12 AACK

T13 TS

T14 A3

T15 VDDH

T16 A12

T17 A16

T18 A20

T19 A22

U1 PA21 / FCC1:TXD4 / FCC1:MII and HDLC nibble TXD3

U2 PB19 / FCC2:MII and HDLC nibble RXD2 / I2C:SDA

U3 PD18 / FCC1:UTOPIA8:RXADDR4 / FCC1:UTOPIA8:RXCLAV3 / SPI:SPICLK

U4 PD16 / FCC1:UTOPIA8:TXPRTY / SPI:SPIMISO

U5 NMI

U6 RSTCONF

U7 GNDSYN1

U8 PA13 / FCC1:UTO PI A8: R XD3 / SDMA:M SN UM2

U9 PA10 / FCC1:UTO PI A8: R XD0 / SDMA:M SN UM5

U10 PA8 / SMC2:SMRXD / TDMA1:serial L1RXD / TDMA1:nibble L1RXD0

U11 SPARE5

U12 ARTRY

U13 TBST

U14 TT2

U15 A4

U16 A8

U17 A11

U18 A17

U19 A18

V1 PB23 / FCC2:MII and HDLC nibble:TXD1 / TDMA1:nibble:L1RXD2 /

TDMD2:L1TXD

V2 PD19 / FCC1:UTOPIA8:TXADDR4 / FCC1:UTOPIA:TXCLAV3 / SPI:SPISEL /

BRG1O

V3 P C15 / FCC1:UTOPIA8:TXADDR0 / SCC1:CTS/CLSN / SM C2:S MTXD

V4 PC12 / FCC1:UTOPIA8:RXADDR1 / SCC2:CD/RE NA / SI 1:LI ST 3

V5 NMI_OUT

V6 HRESET

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

MSC8101 Technical Data, Rev. 19

3-30 Freescale Semico nd uct or

Packaging

V7 GNDSYN

V8 PA11 / FCC1 :U T O PI A8: RXD 1 / SDMA:M SNU M4

V9 PD7 / FCC1:UTOPIA8:TXADDR3 / FCC1:UTOPIA8:TXCLAV2 / SMC1:SMSYN

V10 PA7 / SMC2:SMSYN / TDMA1:L1TSYNC

V11 ABB / IRQ 2

V12 BG

V13 TSIZ0

V14 TT3

V15 A2

V16 A6

V17 A9

V18 A13

V19 A14

W2 PA18 / FCC1:UTOPIA8:TXD7 / FCC1:MII and HDLC nibble:TXD0 /

FCC1:transparent and HDLC serial:TXD

W3 PA15 / FCC1:UTOPIA8: RX D5 / FCC1:MII and HDLC nibble:RXD2

W4 SRESET

W5 PORESET

W6 TEST

W7 VCCSYN

W8 PA14 / FCC1:UTOPIA8 RX D4 / FCC1:MII and HDLC nibble:RXD3

W9 PA9 / SMC2:SMT XD / TDMA 1:serial:L1TXD / TDMA1: nibble:L1TXD0

W10 PC5 / FCC2:CTS / SMC1:SMTXD / SI2:L IS T3

W11

IRQ7 / INT_OUT

W12 TSIZ2

W13 TSIZ1

W14 TT4

W15 A0

W16 A5

W17 A7

W18 A10

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

Lidded FC-PBGA Package Mechanical Drawing

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 3-31

3.2 Lidded FC-PBGA Package Mechanical Drawing

Figure 3-3. Case 1473-01 Mechanical Information, 332-pin Lidded FC-PBGA Package

Notes:

1. Dimensioning and to lerancing

per ASME Y14.5M–1994.

2. Dimensions in millimeters.

3. Maximum sold er ball diameter

measured pa rallel to Datum A

4. Primary Datum A and the

seating plane are defined by

the spherical crowns of the

solder balls.

CASE 1473-01

MSC8101 Technical Data, Rev. 19

3-32 Freescale Semico nd uct or

Packaging

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 4-1

Design Considerations 4

This chapter includes design and layout guidelines for manufacturing boards using the MSC8102.

4.1 Thermal Design Considerations

The average chip-junction temperature, TJ, in °C can be obtained from the following:

TJ = TA + (P D • θJA) Equation 1

where

TA = ambient temperature °C

θJA = package thermal resistance, junction to ambient, °C/W

PD = PINT + PI/O in W

PINT = IDD × VDD in W—chip internal power

PI/O = power dissipation on output pins in W—user determined

The user should set TA and PD such that TJ does not exceed the maximum operating conditions. In case TJ is too

high, the user should either lower the ambient temperature or the power dissipation of the chip.

4.2 Electrical Design Considerations

The input voltage must not excee d t he I/O supply VDDH by mor e t han 2.5 V at any time, i ncl udi ng dur ing power-on

reset. In turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V dur ing power -on reset, but for no more tha n 100 ms.

VDDH should not exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed

VDDH by more than 0.4 V at any time, including during power-on reset. Therefore the recommendation is to use

“bootstrap” diodes between the power rails, as shown in Figure 4-1.

Figure 4-1. Bootstrap Diodes for Power-Up Sequencing

I/O Power

Core/PLL

Supply

MUR420

3.3 V (VDDH)

1.6 V (VDD/VCCSYN)

MSC8101 Technical Data, Rev. 19

4-2 Freescale Sem ico nd uctor

Design Considerations

Select the bootstrap diodes such that a nominal VDD/VCCSYN is sourced from the VDDH power supply until the

VDD/VCCSYN power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected in

series ; ea ch has a fo rward vol tage ( VF) of 0. 6 V at high curr ents, so these di odes pro vid e a 2.4 V drop, main taini ng

0.9 V on the 1.6 V power line. Once the core/PLL power supply stabilizes at 1.6 V, the bootstrap diodes will be

reverse biased with negligible leakage current. The VF should be effective at the current levels required by the

processor. Do not use diodes with a nominal VF that drops too low at high current.

4.3 Power Considerations

The internal po wer dissip ation cons ists of three components:

PINT = PCORE + PSIU + PCPM

Power dissipation depends on the operating frequency of the different portions of the chip. Table 2-5 provides

typical power values at the specified operating frequencies. To determine the typical power dissipation for a given

set of frequencies, use the following equations:

PCORE (f) = ((PCORE – PLCO)/fCORE) × fCOREA + PLCO

PCPM (f) = ((PCPM – PLCP)/fCPM) × fCPMA + PLCP

PSIU (f) = ((P SIU – PLSI)/fSIU) × fSIUA + PLSI

Where:

fCORE is the core frequency, fSIU is the SIU frequency, and fCPM is the CPM frequency specified in Table 2-5

in MHz

fCOREA is the actual core frequency, FSIUA is the actual SIU frequency, and FCPMA is the ac tual CP M fre-

quency in MHz

PLCO, PLSI, and PLCP are the leakage power values specified in Table 2-5

All power numbers are in mW

Power consumption is assumed to be linear with frequency. The first part of each equation computes a

mw/MHz value that is then scaled based on the actual frequency used.

To det ermine a total power dissip ation in a sp ecific appl icatio n, you must add th e power va lues derived from the

above se t of equat ions to the value derived f or I/O po wer cons umption usi ng the fo llowing eq uation fo r each out put

pin:

P = C × VDDH2 × f × 10–3 Equation 2

Where: P = power in mW, C = load capacitance in pF, f = output switching frequency in MHz.

For an application in which external data memory is used in a 32-bit single bus mode and no other outputs are

active, the core runs at 200 MHz, the CPM runs at 100 MHz and the SIU runs at 50 MHz, power dissipation is

calculated as follows:

Assumptions:

• External data memory is accessed every second cycle with 10% of address pins switching.

• External data memory writes occurs once every eight cycles with 50% of data pins switching.

• Each address and data pin has a 30 pF total load at the pin.

• The application operates at VDDH = 3.3 V.

Layout Practices

MSC8101 Technical Data, Rev. 19

Freescale Semic ond uc tor 4-3

Since the address pins switch once at every second cycle, the address pins frequency is a quarter of the bus

frequency (that is, 25 MHz).

For the same reason the data pins frequency is 3.125 MHz.

Calculating internal power (from Table 2-5 values):

PCORE (200) = ((PCORE – PLCO)/300) × 200 + PLCO =((450 – 3) / 300 × 200 + 3 = 301

PCPM (100) = ((PCPM – PLCP) / 200) × 100 + PLCP = ((320 – 6) / 200) × 100 + 6 = 163

PSIU (50) = ((PSIU – PLSI) / 100) × 50 + PLSI = ((80 – 2) / 100) × 50 + 2 = 41

PINT = PCORE(200) + PCPM(100) + PSIU(50) = 301 + 163 + 41 = 505

PD = PINT + PI/O = 505 + 67 = 572

Maximum allowed ambient temperature is:

TA = TJ – (PD × θJA)

4.4 Layout Practices

Each VCC and VDD pin on the MSC8101 should be provided with a low-impedance path to the board’s power

supply. Similarly, each GND pin should be provided with a low-impedance path to ground. The power supply pins

drive distinct groups of logic on the chip. The VCC power supply should be bypassed to ground using at least four

0.1 µF by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and

associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per

capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes.

All output pins on the MSC8101 have fast rise and fall times. Printed circuit board (PCB) trace interconnection

length should be minimized in order to minimize undershoot and reflections caused by these fast output switching

times. Th is recommend ation particular ly appli es to th e address and data busses. Maxi mum PCB trace lengths of six

inches are recommended. Capacitance calculations should consider all device loads as well as parasitic

capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in

systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND

circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to

minimize the noise levels on the PLL supply pins.

There are 2 pairs of PLL supply pins: VCCSYN-GNDSYN and VCCSYN1-GNDSYN1. Each pair supplies one PLL. To

ensure internal clock stability, fi lter t he power to the VCCSYN and VCCSYN1 inputs with a circuit similar to the one in

Figure 0-1.. To filter as much noise as possible, place the circuit as close as possible to VCCSYN and VCCSYN1. The

0.01-µF capacitor should be closest to VCCSYN and VCCSYN1, followed by the 10-µF capacitor, the 10-nH inductor,

and finally the 10-Ω resistor to VDD. These traces should be kept short and direct.

Table 4-1. Power Dissipation

Pins Number of Pins

Switching × C × VDDH2× f × 10–3 Power in mW

Address

Data, HRD, HRW

CLKOUT

× 30

× 3.32

× 12.5 × 10–3

× 3. 125 × 10–3

× 50 × 10–3

16.25

34.75

Total PI/O 67

MSC8101 Technical Data, Rev. 19

4-4 Freescale Sem ico nd uctor

Design Considerations

GNDSYN and GNDSYN1 should be pr ovided with an extremely low impedance pa th to ground a nd should be byp assed

to VCCSYN and VCCSYN1, respectively, by a 0.01-µF capacitor located as close as possible to the chip package. The

user should also bypass GNDSYN and GNDSYN1 to VCCSYN and VCCSYN1 with a 0.01-µF capacitor as closely as

possible to the chip package

Figure 0-1. VCCSYN and VCCSYN1 Bypass

VDD

0.01 µF

10 µF

VCCSYN

10Ω10nH

MSC8101

Rev. 19

5/2008

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Orderi ng Info r ma tion

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and

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Part Supply

Voltage Package Type Pin

Count Mask

Set

Core

Frequency

(MHz)

Order Number

Pb-free spheres Pb-bearing spheres‘

MSC8101 1.6 V core

3.3 V I/O Lidded Flip Chip Plastic Ball

Grid Array (FC-PBGA) 332 2K87M 250 MSC8101VT1250F MSC8101M1250F

275 MSC8101VT1375F MSC8101M1375F

300 MSC8101VT1500F MSC8101M1500F