© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 3 1Publication Order Number:
NCP4687/D
NCP4687
500 mA, High PSRR, LDO
Linear Voltage Regulator
The NCP4687 is a CMOS 500 mA LDO linear voltage regulator
with high output voltage accuracy which features a high ripple
rejection, low supply current with low dropout and chip enable with
built−in low RDS(on) NMOS transistor for fast output capacitor
discharging a s option. The device is composed of the voltage reference
unit, error amplifier, resistor divider for output voltage sensing or
precise output voltage setting. The current limit and thermal shutdown
makes the device very suitable for industrial applications and portable
communication equipments.
Features
•Operating Input Voltage Range: 2.5 V to 5.25 V
•Output Voltage Range: 0.7 to 3.6 V (available in 0.1 V steps)
•±0.8% Output Voltage Accuracy @ Vout > 1.8 V
•Output noise : 40 mVrms
•Line Regulation: 0.02%/V
•Current Limit Circuit
•High PSRR: 75 dB at 1 kHz, 70 dB at 10 kHz
•Thermal Shutdown
•Available in SOT−23−5, SOT−89−5 and uDFN 1.2 x 1.2 mm
Packages
•These Devices are Pb−Free and are RoHS Compliant
Typical Applications
•Home Appliances, Industrial Equipment
•DVB−T and DVB−S Receivers
•Car Audio Equipment, Navigation Systems
•Notebook Adaptors, LCD TVs, Cordless Phones and Private LAN
Systems
VIN VOUT
CE
GND
VIN VOUT
NCP4687x
SENSE
Figure 1. Typical Application Schematic
C1
1.0 mF
C2
1.0 mF
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See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
ORDERING INFORMATION
SOT89−5
CASE 528AB
XX, XXX= Specific Device Code
ZZ = Lot Code
MM = Date Code
MARKING
DIAGRAMS
XDFN6
CASE 711AH
SOT−23−5
CASE 1212
XX
MM
XXX
XZZ
1
1
XXXMM
1
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2
Current Limit &
Thermal Protection
V
in
GND
Vref
C
E
Vout
SENSE
Current Limit &
Thermal Protection
Vin
GND
Vref
CE
Vout
SENS
E
Figure 2. Simplified Schematic Block Diagram
NCP4687xxx
NCP4687Dxx
PIN FUNCTION DESCRIPTION
Pin No.
SOT−23−5 Pin No.
SOT−89−5 Pin No.
DFN1212 Pin Name Description
1 4 6 VIN Input pin
2 2 3 GND Ground pin
3 3 4 CE Chip enable pin (“H” active)
4 1 2 SENSE Output Voltage Sensing
5 5 1 VOUT Output pin
5 NC Non Connected
*EP EP Exposed Pad (leave floating or connect to GND)
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ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage VIN 0 − 6 V
Output Voltage VOUT −0.3 to VIN − 0.3 V
Chip Enable Input VCE −0.3 − 6 V
Power Dissipation SOT−23−5 PD420 mW
Power Dissipation uDFN 1.2 x 1.2 mm 600
Power Dissipation SOT−89−5 900
Junction Temperature TJ−40 to 150 °C
Storage Temperature TSTG −55 to 125 °C
ESD Capability, Human Body Model (Note 1) ESDHBM 2000 V
ESD Capability, Machine Model (Note 1) ESDMM 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78
THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Characteristics, SOT−23−5
Thermal Resistance, Junction−to−Air RqJA 238 °C/W
Thermal Characteristics, uDFN 1.2x1.2
Thermal Resistance, Junction−to−Air RqJA 167 °C/W
Thermal Characteristics, SOT−89−5
Thermal Resistance, Junction−to−Air RqJA 111 °C/W
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ELECTRICAL CHARACTERISTICS −40°C ≤ TA ≤ 85°C; CIN = COUT = 1.0 mF, unless otherwise noted. Typical values are at
TA = +25°C.
Parameter Test Conditions Symbol Min Typ Max Unit
Operating Input Voltage VOUT ≤ 1.5 V VIN 2.5 5.25 V
VOUT > 1.5 V VOUT + 1 5.25
Output Voltage Ta = 25°C, VOUT > 1.8 V VOUT x0.992 x1.008 V
−40°C < Ta < 85°C, VOUT > 1.8 V x0.985 x1.015 V
Ta = 25°C, VOUT ≤ 1.8 V −18 +18 mV
−40°C < Ta < 85°C, VOUT ≤ 1.8 V −55 +55 mV
Output Voltage Temp.
Coefficient −40°C < Ta < 85°C, VOUT > 1.8 V ±30 ppm/°C
−40°C < Ta < 85°C, VOUT ≤ 1.8 V ±100
Load Regulation 1 mA < IOUT ≤ 500 mA LoadReg 1 20 mV
Line Regulation Set VOUT + 0.5 V < VIN < 5.25 V LineReg 0.02 0.1 %/V
Dropout Voltage IOUT = 500 mA 0.7 V ≤ VOUT < 0.8 V VDO 0.58 0.88 V
0.8 V ≤ VOUT < 0.9 V 0.52 0.80
0.9 V ≤ VOUT < 1.0 V 0.45 0.70
1.0 V ≤ VOUT < 1.2 V 0.42 0.64
1.2 V ≤ VOUT < 1.4 V 0.35 0.53
1.4 V ≤ VOUT < 1.8 V 0.31 0.48
1.8 V ≤ VOUT < 2.1 V 0.27 0.41
2.1 V ≤ VOUT < 2.5 V 0.25 0.38
2.5 V ≤ VOUT < 3.0 V 0.23 0.34
3.0 V ≤ VOUT < 3.6 V 0.22 0.32
Output Current IOUT 500 mA
Short Current Limit VOUT = 0 V ISC 50 mA
Quiescent Current IOUT = 0 mA VOUT > 1.5 V IQ80 115 mA
VOUT ≤ 1.5 V 75
Standby Current VIN = VIN max, VCE = 0 V ISTB 0.1 1.0 mA
CE Pin Pull−Down Current IPD 0.3 0.6 mA
CE Pin Threshold Voltage CE Input Voltage “H” VCEH 1.0 VIN V
CE Input Voltage “L” VCEL 0.4
Power Supply Rejection
Ratio VOUT ≤ 2.0 V @ VIN = 3.0 V
,
VOUT > 2.0 V @ VIN =
= Set VOUT + 1.0 V,
DVIN_PK−PK = 0.2 V,
IOUT = 30 mA
f = 1 kHz PSRR 75 dB
f = 10 kHz 70
Output Noise Voltage IOUT = 30 mA , f = 10 Hz to 100 kHz, VOUT > 1.8 V VNOISE 20 x
VOUT mVrms
IOUT = 30 mA, f = 10 Hz to 100 kHz, VOUT ≤ 1.8 V 40 x
VOUT
Thermal Shutdown /
Hysteresis 165/65 °C
Auto−discharge N−MOS
Resistance VIN = 4.0 V, VCE = 0.0 V (Note 2) RDS(on) 60 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2.
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TYPICAL CHARACTERISTICS
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 100 200 300 400 500 600 700 800
Figure 3. Output Voltage vs. Output Current
0.7 V Version
IOUT, OUTPUT CURRENT (mA)
VOUT, OUTPUT VOLTAGE (V)
VIN = 1.4 V
1.7 V
2.7 V
3.5 V
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400 500 600 700 800 900
VIN = 4.0 V
3.5 V
3.0 V
Figure 4. Output Voltage vs. Output Current
2.5 V Version
IOUT, OUTPUT CURRENT (mA)
VOUT, OUTPUT VOLTAGE (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
0 100 200 300 400 500 600 700 800
Figure 5. Output Voltage vs. Output Current
3.6 V Version
IOUT, OUTPUT CURRENT (mA)
VOUT, OUTPUT VOLTAGE (V)
VIN = 4.1 V
4.6 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0123456
VOUT, OUTPUT VOLTAGE (V)
Figure 6. Output Voltage vs. Input Voltage 0.7 V
Version
VIN, INPUT VOLTAGE (V)
IOUT = 50 mA
30 mA
1 mA
0
0.5
1
1.5
2
2.5
3
0123456
VOUT, OUTPUT VOLTAGE (V)
Figure 7. Output Voltage vs. Input Voltage 2.5 V
Version
VIN, INPUT VOLTAGE (V)
1 mA
30 mA
IOUT = 50 mA 0
0.5
1
1.5
2
2.5
3
3.5
4
0123456
VOUT, OUTPUT VOLTAGE (V)
Figure 8. Output Voltage vs. Input Voltage 3.6 V
Version
VIN, INPUT VOLTAGE (V)
1 mA
30 mA
IOUT = 50 mA
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TYPICAL CHARACTERISTICS
0.67
0.68
0.69
0.7
0.71
0.72
−50 −25 0 25 50 75 100
TJ, JUNCTION TEMPERATURE (°C)
VOUT, OUTPUT VOLTAGE (V)
Figure 9. Output Voltage vs. Temperature,
0.7 V Version
2.45
2.47
2.49
2.51
2.53
2.55
−50 −25 0 25 50 75 100
TJ, JUNCTION TEMPERATURE (°C)
VOUT, OUTPUT VOLTAGE (V)
Figure 10. Output Voltage vs. Temperature,
2.5 V Version
3.57
3.58
3.59
3.6
3.61
3.62
TJ, JUNCTION TEMPERATURE (°C)
VOUT, OUTPUT VOLTAGE (V)
Figure 11. Output Voltage vs. Temperature,
3.6 V Version
−50 −25 0 25 50 75 100 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 100 200 300 400 500
IOUT, OUTPUT CURRENT (mA)
VDO, DROPOUT VOLTAGE (V)
Figure 12. Dropout Voltage vs. Output Current,
0.7 V Version
25°C
85°C
−40°C
0
0.05
0.1
0.15
0.2
0.25
0.3
0 100 200 300 400 500
IOUT, OUTPUT CURRENT (mA)
VDO, DROPOUT VOLTAGE (V)
Figure 13. Dropout Voltage vs. Output Current,
2.5 V Version
25°C
85°C
−40°C
0
0.05
0.1
0.15
0.2
0.25
0 100 200 300 400 500
IOUT, OUTPUT CURRENT (mA)
VDO, DROPOUT VOLTAGE (V)
Figure 14. Dropout Voltage vs. Output Current,
3.6 V Version
25°C
85°C
−40°C
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TYPICAL CHARACTERISTICS
0
20
40
60
80
100
0123456
VIN, INTPUT VOLTAGE (V)
Iq, QUIESCENT CURRENT (mA)
Figure 15. Quiescent Current vs. Input
Voltage, 0.7 V Version
0
20
40
60
80
100
120
0123456
VIN, INTPUT VOLTAGE (V)
Figure 16. Quiescent Current vs. Input
Voltage, 2.5 V Version
Iq, QUIESCENT CURRENT (mA)
0
20
40
60
80
100
120
140
0123456
VIN, INTPUT VOLTAGE (V)
Iq, QUIESCENT CURRENT (mA)
Figure 17. Quiescent Current vs. Input
Voltage, 3.6 V Version
10
20
30
40
50
60
70
80
90
100
100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 18. PSRR vs. Frequency, 0.7 V Version
PSRR (dB)
IOUT = 1 mA
150 mA 50 mA
300 mA
10
20
30
40
50
60
70
80
90
100
100 1k 10k 100k 1M
FREQUENCY (Hz)
PSRR (dB)
Figure 19. PSRR vs. Frequency, 2.5 V Version
150 mA
300 mA IOUT = 1 mA
50 mA
10
20
30
40
50
60
70
80
90
100
100 1k 10k 100k 1M
50 mA
IOUT = 1 mA
300 mA
150 mA
FREQUENCY (Hz)
Figure 20. PSRR vs. Frequency, 3.6 V Version
PSRR (dB)
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TYPICAL CHARACTERISTICS
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Figure 21. Output Noise vs. Frequency, 0.7 V
Version
VN (mVrms/√Hz)
FREQUENCY (Hz)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Figure 22. Output Noise vs. Frequency, 2.5 V
Version
FREQUENCY (Hz)
VN (mVrms/√Hz)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Figure 23. Output Noise vs. Frequency, 3.6 V
Version
VN (mVrms/√Hz)
FREQUENCY (Hz)
1.7
2.2
2.7
3.2
0.680
0.685
0.690
0.695
0.700
0.705
0.710
0 4 8 12 16 20 24 28 32 36 40
Figure 24. Line Transients, 0.7 V Version
VOUT (V)
t (ms)
VIN (V)
100 1k 10k 100k 1M10 100 1k 10k 100k 1M10
100 1k 10k 100k 1M10
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TYPICAL CHARACTERISTICS
3.5
4.0
4.5
5.0
2.480
2.485
2.490
2.495
2.500
2.505
2.510
0 4 8 12 16 20 24 28 32 36 40
Figure 25. Line Transients, 2.5 V Version
VOUT (V)
t (ms)
VIN (V)
4.6
5.1
5.6
6.1
3.580
3.585
3.590
3.595
3.600
3.605
3.610
0 4 8 12 16 20 24 28 32 36 40
Figure 26. Line Transients, 3.6 V Version
VOUT (V)
t (ms)
VIN (V)
0
200
400
600
0.62
0.64
0.66
0.68
0.70
0.72
0.74
0 102030405060708090100
Figure 27. Load Transients, 0.7 V Version, Load
Step 1 mA to 400 mA
VOUT (V)
t (ms)
IOUT (mA)
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TYPICAL CHARACTERISTICS
2.42
2.44
2.46
2.48
2.50
2.52
2.54
0 102030405060708090100
600
400
200
0
Figure 28. Load Transients, 2.5 V Version, Load
Step 1 mA to 400 mA
VOUT (V)
t (ms)
IOUT (mA)
0
200
400
600
3.52
3.54
3.56
3.58
3.60
3.62
3.64
0 102030405060708090100
Figure 29. Load Transients, 3.6 V Version, Load
Step 1 mA to 400 mA
VOUT (V)
t (ms)
IOUT (mA)
0
50
100
150
0.680
0.685
0.690
0.695
0.700
0.705
0.710
0.715
0 102030405060708090100
VOUT (V)
t (ms)
IOUT (mA)
Figure 30. Load Transients, 0.7 V Version, Load
Step 50 mA to 100 mA
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TYPICAL CHARACTERISTICS
0
50
100
150
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
0 102030405060708090100
VOUT (V)
t (ms)
IOUT (mA)
Figure 31. Load Transients, 2.5 V Version, Load
Step 50 mA to 100 mA
0
50
100
150
3.580
3.585
3.590
3.595
3.600
3.605
3.610
3.615
0 102030405060708090100
VOUT (V)
t (ms)
IOUT (mA)
Figure 32. Load Transients, 3.6 V Version, Load
Step 50 mA to 100 mA
0
1.25
2.5
3.75
−0.2
0.0
0.2
0.4
0.6
0.8
0 50 100 150 200 250 300
VOUT (V)
t (ms)
VCE (V)
Figure 33. Turn On with CE Behavior, 0.7 V
Version
Chip Enable
IOUT = 1 mA
IOUT = 100 mA
IOUT = 400 mA
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TYPICAL CHARACTERISTICS
0
1.75
3.5
5.25
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
0 50 100 150 200 250 300
VOUT (V)
t (ms)
VCE (V)
Figure 34. Turn On with CE Behavior, 2.5 V
Version
Chip Enable
IOUT = 1 mA
IOUT = 100 mA
IOUT = 400 mA
−1.0
0.0
1.0
2.0
3.0
4.0
0 50 100 150 200 250 300
6
4
2
0
VOUT (V)
t (ms)
VCE (V)
Figure 35. Turn On with CE Behavior, 3.6 V
Version
Chip Enable
IOUT = 1 mA
IOUT = 100 mA
IOUT = 400 mA
0
1.25
2.5
3.75
−0.2
0.0
0.2
0.4
0.6
0.8
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VOUT (V)
t (ms)
VCE (V)
Figure 36. Turn Off with CE Behavior, 0.7 V
Version
IOUT = 1 mA
IOUT = 100 mA
IOUT = 500 mA
Chip Enable
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TYPICAL CHARACTERISTICS
0
1.75
3.5
5.25
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VOUT (V)
t (ms)
Figure 37. Turn Off with CE Behavior, 2.5 V
Version
IOUT = 1 mA
IOUT = 100 mA
IOUT = 500 mA
Chip Enable
0.0
2.3
4.6
6.9
−1
0
1
2
3
4
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VCE (V)
VOUT (V)
t (ms)
Figure 38. Turn Off with CE Behavior, 3.6 V
Version
VCE (V)
IOUT = 1 mA
IOUT = 100 mA
IOUT = 500 mA
Chip Enable
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APPLICATION INFORMATION
A typical application circuit for NCP4687 series is shown
in the Figure 39.
VIN VOUT
CE
GND
VIN VOUT
NCP4687x
SENSE
Figure 39. Typical Application Schematic
C1
1.0 mF
C2
1.0 mF
Input Decoupling Capacitor (C1)
A 1.0 mF ceramic input decoupling capacitor should be
connected a s close as possible to the input and ground pin o f
the NCP4687 device. Higher values and lower ESR
improves line transient response.
Output Decoupling Capacitor (C2)
A 1.0 mF ceramic output decoupling capacitor is sufficient
to achieve stable operation of the device. If tantalum
capacitor is used, and its ESR is high, the loop oscillation
may result. The capacitor should be connected as close as
possible to the output and ground pin. Larger values and
lower ESR improves dynamic parameters.
Enable Operation
The enable pin CE may be used for turning the regulator
on and off. The IC is switched on when a high level voltage
is applied to the CE pin. The enable pin has an internal pull
down current source which assure off state of LDO in case
the CE pin will stay floating. If the enable function is not
needed connect CE pin to VIN.
The D version of the NCP4687 device includes a
transistor between VOUT and GND that is used for faster
discharging of the output capacitor. This function is
activated when the IC goes into disable mode.
Thermal Consideration
As a power across the IC increase, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and also the ambient
temperature affect the rate of temperature increase for the
part. When the device has good thermal conductivity
through the PCB the junction temperature will be relatively
low in high power dissipation applications.
The IC includes internal thermal shutdown circuit that
stops operation of regulator, if junction temperature is
higher than 165°C. After that, when junction temperature
decreases below 100°C, the operation of voltage regulator
would restart. While high power dissipation condition is, the
regulator starts and stops repeatedly and protects itself
against overheating.
Sense Pin
The SENSE pin improves significantly the load
regulation. The connection resistance between the LDO and
the load given by PCB parameters has reduced impact to
load regulation. If possible, use wide PCB traces as short as
possible.
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ORDERING INFORMATION
Device Marking Nominal Output
Voltage Feature Package Shipping†
NCP4687DH12T1G A12D 1.2 V Auto discharge SOT−89
(Pb−Free) 1000 / Tape & Reel
NCP4687DH15T1G A15D 1.5 V Auto discharge SOT−89
(Pb−Free) 1000 / Tape & Reel
NCP4687DH18T1G A18D 1.8 V Auto discharge SOT−89
(Pb−Free) 1000 / Tape & Reel
NCP4687DH25T1G A25D 2.5 V Auto discharge SOT−89
(Pb−Free) 1000 / Tape & Reel
NCP4687DH33T1G A33D 3.3 V Auto discharge SOT−89
(Pb−Free) 1000 / Tape & Reel
NCP4687DMX18TCG 9P 1.8 V Auto discharge XDFN6
(Pb−Free) 5000 / Tape & Reel
NCP4687DMX25TCG 9X 2.5 V Auto discharge XDFN6
(Pb−Free) 5000 / Tape & Reel
NCP4687DMX33TCG 0G 3.3 V Auto discharge XDFN6
(Pb−Free) 5000 / Tape & Reel
NCP4687DSN18T1G J18 1.8 V Auto discharge SOT−23
(Pb−Free) 3000 / Tape & Reel
NCP4687DSN25T1G J25 2.5 V Auto discharge SOT−23
(Pb−Free) 3000 / Tape & Reel
NCP4687DSN28T1G J28 2.8 V Auto discharge SOT−23
(Pb−Free) 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-
cifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
SOT−23 5−LEAD
CASE 1212
ISSUE A
DIM MIN MAX
MILLIMETERS
A1 0.00 0.10
A2 1.00 1.30
b0.30 0.50
c0.10 0.25
D2.70 3.10
E2.50 3.10
E1 1.50 1.80
e0.95 BSC
L
L1 0.45 0.75
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DATUM C IS THE SEATING PLANE.
A
1
5
23
4
D
E1
B
L1
E
eC
M
0.10 C S
BS
A
b
5X
A2 A1
S
0.05
C
L
0.20 ---
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.95
DIMENSIONS: MILLIMETERS
PITCH
5X
3.30
0.56
5X
0.85
A--- 1.45
RECOMMENDED
A
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PACKAGE DIMENSIONS
ÍÍÍ
ÍÍÍ
ÍÍÍ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25mm FROM TERMINAL TIPS.
4. COPLANARITY APPLIES TO ALL OF THE
TERMINALS.
A
SEATING
PLANE
D
E
0.05 C
A
A1
2X
2X 0.05 C
XDFN6 1.20x1.20, 0.40P
CASE 711AH
ISSUE O
DIM
A
MIN MAX
MILLIMETERS
--- 0.40
A1 0.00 0.05
b0.13 0.23
D
E
e
L
PIN ONE
REFERENCE
0.05 C
0.05 C
NOTE 3
L
eb
3
66X
1
4
MOUNTING FOOTPRINT*
0.15 0.25
BOTTOM VIEW
E2
DIMENSIONS: MILLIMETERS
0.40
6X
0.24
6X
1.40
0.40
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
E2 0.25 0.35
TOP VIEW
B
SIDE VIEW
NOTE 4
RECOMMENDED
C
6X
A
M
0.05 BC
PACKAGE
OUTLINE
D2 0.89 0.99
L1
1.20 BSC
1.20 BSC
0.40 BSC
0.05 BSC
D2
1.00
0.36
NCP4687
http://onsemi.com
18
PACKAGE DIMENSIONS
SOT−89, 5 LEAD
CASE 528AB
ISSUE O
MOUNTING FOOTPRINT*
RECOMMENDED
C0.10
TOP VIEW
SIDE VIEW
BOTTOM VIEW
C
H
1
DIM MIN MAX
MILLIMETERS
A1.40 1.60
b1 0.37 0.57
b0.32 0.52
c0.30 0.50
D4.40 4.60
D2 1.40 1.80
E2.40 2.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. LEAD THICKNESS INCLUDES LEAD FINISH.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
5. DIMENSIONS L, L2, L3, L4, L5, AND H ARE MEAS-
URED AT DATUM PLANE C.
e1.40 1.60
L1.10 1.50
H4.25 4.45
L2 0.80 1.20
L3 0.95 1.35
L4 0.65 1.05
L5 0.20 0.60
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
D
E
Ac
23
54
L
L5
eebb1 L2
D2
L4
L3
2X
0.62
DIMENSIONS: MILLIMETERS
1
2X 1.50
1.30
2.79 0.45 1.50
1.65
4.65
4X 0.57 1.75
1
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