CY7C09569V-133BAC - Cypress Semiconductor Corp.

PRELIMINARY

3.3V 16K/32K x 36

FLEx36™ Synchronous Dual-Port Static RAM

7C09579V: 10/97

Revision: May 1, 2000

CY7C09569V

CY7C09579V

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Ma y 1, 2 000

Features

• True dual-ported memory cells which allow simulta-

neous access of the sam e me mory location

• Two Flow-Thr ough/Pipeline d devices

—16K x 36 organi zation (CY7C09569V)

—32K x 36 organi zation (CY7C09579V)

• 0.25-micron CMOS f or optimum speed/power

• Three modes

—Flow-Through

—Pipelined

—Burst

• Bus- Mat ching Capa bili ties on Right Port (x36 t o x18 or

x9)

• Byte-Select Capabili ties on Left Port

• 133-MHz Pipelined Operation

• High-speed clock to data access 4.1/5/ 6/8 ns

• 3.3V Low operating power

—Active = 260 mA (typi cal)

— St a ndby = 10 µA (typical)

• Fully synchronous interface for ease of use

• Bur st counters incremen t addresses internally

—Shorten cycle times

—Minimize bus noise

—Supported in Flow -Through and Pipelined m odes

• Counter Address Read Back via I/O lines

• Single Chip Enable

• Automatic power-down

• Commercial and Ind ustr ial Temperature Ranges

• Compact pac kage

—144-Pin TQFP (20 x 20 x 1.4 mm)

—172-Ball BG A (1.0 mm pitch) (15 x 15 x .51 mm)

Note:

1. A0–A13 for 16K; A0–A14 for 32K devices.

Logic Block Diagram

R/WL

B0–B3

OEL

FT/PipeL

I/O18L–I/O26L

A0–A13/14L

CLKL

ADSL

CNTENL

CNTRSTL

A0–A13/14R

CLKR

ADSR

CNTENR

CNTRSTR

Counter/

Address

Decode

True Dual-Port e d

RAM Array

Counter/

Address

Decode

[1] [1]

14/15 14/15

I/O27L–I/O35L 9

I/O0L–I/O8L 9

I/O9L–I/O17L 9

CEL

I/O

Control

Left

Port

Control

Logic

R/WR

OER

FT/PipeR

I/OR

CER

I/O

Control

Right

Port

Control

Logic

Bus

Match 9/18/36

SIZE

Fo r the most recent information, visit the Cypress web site at www .cypress.com

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Functional Description

The CY7C09569V and CY7C09579V are high-speed 3.3V

synchr onou s CMOS 16K and 32K x 36 dual -port static RAMs .

Two port s are p ro vided, permitti ng indep endent , si mul taneous

access f or reads and writes to any location in memory. Regis-

ters on control, address, and data lines allow for minimal set-

up and hol d times. In pipelined out put mode, data is regi stered

for decreased cycle time. Clock to data valid tCD2 = 4.1 ns

(pipelined). Flow-through mode can also be used to bypass

the pipelined output register to eliminate access latency. In

flow-thr ough m ode data will be available tCD1 = 10. 5 ns after

the address is c locke d into t he de vice. Pipelined output or f lo w-

through mode is selected vi a the FT/Pipe pin.

Each port cont ains a b urst co unt er on the input addr ess regi s-

ter. The internal writ e puls e width is independent of the exter-

nal R/W LOW duration. The internal write pulse is self-timed

to allow t he shortest possible cycle times.

A HIGH on CE for one cl ock cy cl e will po wer do wn the i nternal

circuitry to reduce the static power consumption. In the pipe-

lined mode, one cycle is required w ith CE LOW to re acti vate

the outputs.

Counter Enable Inputs ar e provided to stal l the oper ation of the

address i nput and utilize the internal address generat ed by the

internal counter for fast interleaved memory applications. A

port’s burst counter is loaded with the port’s Address Strobe

(ADS). When the por t’s Count Enable (CNTEN) is asserted,

the address counter will increment on each LOW-to-HIGH

transition of that port’s clock signal. This will read/write one

word f rom/in to each su cces siv e add ress lo catio n until CNTEN

is deasserted. The counter can address the entire memory

array and wil l lo op back to the sta rt. Count er Reset (CNT RST)

is used to re set the burst counter.

All parts are available in 144-Pin Thin Quad Plastic Flatpack

(TQFP) and 172-Ball Ball Grid Array (BG A) p ackages.

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Pin Configurations

Notes:

2. This pin is A14L for CY7C09579V.

3. This pin is A14R for CY7C09579V.

144-PinThin Quad Flatpack (TQFP)

Top View

I/O32L

I/O33R

I/O23L

I/O33L 2

I/O34L I/O34R

I/O35L I/O35R

A0L A0R

A1L A1R

A2L A2R

A3L A3R

A4L A4R

A5L A5R

A6L A6R

A7L

108

A7R

107

106

SIZE

105

104

vss

OEL

103

OER

R/WL

102

R/WR

VDD

101

VDD

VSS

100

VSS

CEL

CER

CLKL

CLKR

ADSL

ADSR

CNTRSTL

CNTRSTR

CNTENL

CNTENR

FT/PIPEL

FT/PIPER

A8L

A8R

A9L

A9R

A10L

A10R

A11L

A11R

A12L

A12R

A13L

A13R

I/O26L

I/O26R

I/O25L

I/O25R

I/O24L

I/O24R

I/O22L I/O31L

VSS VSS

I/O21L I/O30L

I/O20L I/O29L

I/O19L I/O28L

I/O18L I/O27L

VDD VDD

I/O8L I/O17L

I/O7L I/O16L

I/O6L I/O15L

I/O5L I/O14L

VSS VSS

I/O4L I/O13L

I/O3L I/O12L

I/O2L

143

I/O11L

I/O1L

142

I/O10L

I/O0L

141

I/O9L

I/O0R

140

I/O9R

I/O1R

139

I/O10R

I/O2R

138

I/O11R

I/O3R

137

I/O12R

I/O4R

136

I/O13R

VSS

135

VSS

I/O5R

134

I/O14R

I/O6R

133

I/O15R

I/O7R

132

I/O16R

I/O8R

131

I/O17R

VDD

130

VDD

I/O18R

129

I/O27R

123

I/O19R

128

I/O28R

122

I/O20R

127

I/O29R

121

I/O21R

126

I/O30R

120

VSS

125

VSS

119

I/O22R

124

I/O31R

118

I/O23R I/O32R

117

116

115

114

113

112

111

110

109

144

CY 7C09569 V ( 16K x 36)

CY 7C09579 V ( 32K x 36)

[2] [3]

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Pin Configurations (continued)

172 - B a ll B a ll G r id Ar ray (B G A )

Top View

1234567891011121314

AI/O32L I/O30L NC VSS I/O13L VDD I/O11L I/O11R VDD I/O13R VSS NC I/O30R I/O32R

BA0L I/O33L I/O29 I/O17L I/O14L I/O12L I/O9L I/O9R I/O12R I/O14R I/O17R I/O29R I/O33R A0R

CNC A1L I/O31L I/O27L NC I/O15L I/O10L I/O10R I/O15R NC I/O27R I/O31R A1R NC

DA2L A3L I/O35L I/O34L I/O28L I/O16L VSS VSS I/O16R I/O28R I/O34R I/O35R A3R A2R

EA4L A5L NC B0L NC NC NC NC BM NC A5R A4R

FVDD A6L A7L B1L NC NC SIZE A7R A6R VDD

GOEL B2L B3L CEL CER VSS BE OER

HVSS R/WLA8LCLKL CLKR A8R R/WR VSS

JA9L A10L VSS ADSL NC NC ADSR VSS A10R A9R

KA11L A12L NC CNTRSTL NC NC NC NC CNTRSTR NC A12R A11R

LFT/PIPELA13L CNTENL I/O26L I/O25L I/O19L VSS VSS I/O19R I/O25R I/O26R CNTENR A13R FT/PIPER

MNC NC[2] I/O22L I/O18L NC I/O7L I/O2L I/O2R I/O7R NC I/O18R I/O22R NC[3] NC

NI/O24L I/O20L I/O8L I/O6L I/O5L I/O3L I/O0L I/O0R I/3R I/O5R I/O6R I/O8R I/O20R I/O24R

PI/O23L I/O21L NC VSS I/O4L VDD I/O1L I/O1R VDD I/O4R VSS NC I/O21R I/O23R

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Selection G uide

CY7C09569V

CY7C09579V

-133

CY7C09569V

CY7C09579V

-100

CY7C09569V

CY7C09579V

-83

CY7C09569V

CY7C09579V

-67

fMAX2 (MHz) (Pipelined) 133 100 83 67

Max. Access Time (ns) (C lock to Data, Pipelined) 4.1 5 6 8

Typical Operat ing Current ICC (mA) 260 250 240 230

Typical Standb y Current for I SB1 ( m A) (Both Ports TTL Level ) 35 30 25 25

Typ ical Standby Current f or ISB3 (µA) ( Both Ports CMOS Le vel) 10 µA 10 µA10 µA 10 µA

Pin Definitions

Left Port Right Port Description

A0L–A13/14L A0R–A13/14R Address Inputs (A0–A13 f or 16K, A0–A14 for 32K devices).

ADSLADSRAddress Strobe Input. Used as an address qualifier. Thi s si gnal should be asser ted LOW to

assert the part us ing the e xternally s upplied a ddre ss on Add res s Pins. To load this addr ess into

the Burs t Ad dress Counte r both ADS and CNTEN ha ve to be LOW. ADS i s disab led if CNTRST

is asserted LOW

CELCERChip Enable Input.

CLKLCLKRClock Signal. This input can be free-running or strobed. Maxim um clock input rate is fMAX.

CNTENLCNTENRCounter Enable Input. Assert ing this signal LOW increments the b urst address counter of it s

respect ive port on eac h rising edge of CLK. CNTEN is disab led if CNTRST is asserted LOW.

CNTRSTLCNTRSTRCount er Reset In put. Asse rti ng this signal LO W rese ts the b urs t address counter of i ts res pec-

tiv e port to zero. CNTRST is not disabled by asserting ADS or CNTEN.

I/O0L–I/O35L I/O0R–I/O35R Data Bus Input/Output.

OELOEROu tpu t Enab le Input. This sig nal must be asserted LO W to enable t he I/O data pin s during read

operations.

R/WLR/WRRead/ Write Enable Inp ut. This signal is ass erted LOW to write t o the dual port m em ory array.

For read operations, asser t this pin HIGH.

FT/PIPELFT/PIPERFlow-Through/Pipelined Select Input. For flow-t hrough mode operation, assert thi s pin LOW.

For pipelined mode operation, assert this pi n HIGH.

B0L–B3L Byte Select I nputs. Asserting these s ignals en able read a nd write op erations to the correspond-

ing bytes of the memory array.

BM, SIZE Select Pins for Bus Matching. See Bus Matching for detai ls.

BE Big Endian Pin. See Bus Matching for details .

VSS Ground Input.

VDD P ower Input.

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Maximum Ratings

(Above which the us eful life may be impaired. For user guide-

li nes, not tested .)

Storage Temperature... ........ .... ........ .. ........ –65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +4.6V

DC Voltage Applied to

Outputs in High Z State ...........................–0.5V to VDD+0.5V

DC Input Voltage...................................–0 . 5V to VDD+0.5V[4]

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage ... .. ..... ....... ........ .. ..... ........ .. .>2001V

Latch-Up Current....... ............................. ..... ....... ..... >200 mA

Note:

4. Pulse width < 20 ns.

Operating Range

Range Ambient

Temperature VDD

Commercial 0°C to +7 0 °C 3.3V ± 165 mV

Industrial –40°C to +85°C 3.3V ± 165 mV

Shaded areas contain advance information.

Electrical Characteristics Ov er th e Ope rating Range

Parameter Description

CY7C09569V

CY7C09579V

Unit

-133 -100 -83 -67

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

VOH Output HIGH Voltage

(VDD = Mi n ., IOH = –4.0 mA) 2.4 2.4 2.4 2.4 V

VOL Output LO W Voltage

(VDD = Mi n ., IOL= +4. 0 mA) 0.4 0.4 0.4 0.4 V

VIH Input HIGH Voltage 2.0 2.0 2.0 2.0 V

VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V

IOZ Ou tput Leaka ge Current –10 10 –10 10 –10 10 –10 10 µA

ICC Operating Current (VDD

= Max ., IOUT = 0 mA)

Ou tputs Disabled

Com’l. 260 410 250 385 240 360 230 340 mA

Ind. 270 385 mA

ISB1 Standby Current (Both

P orts TTL Lev el) CEL &

CER ≥ VIH, f = fMAX

Com’l. 35 80 30 75 25 70 25 65 mA

Ind. 35 85 mA

ISB2 Standby Current (One

Port TTL Level) CEL |

CER ≥ VIH, f = fMAX

Com’l. 180 230 170 220 160 210 150 200 mA

Ind. 170 235 mA

ISB3 Standby Current (Both

Ports CMOS Level) CEL

& CER ≥ VDD – 0.2V,

f = 0

Com’l. 0.01 1 0.01 1 0.01 1 0.01 1 mA

Ind. 0.01 1mA

ISB4 Standby Current (One

Port CMOS Level) CEL

| CER ≥ VIH, f = fMAX

Com’l. 160 210 150 200 140 190 130 180 mA

Ind. 150 200 mA

Shaded areas contain adv ance information.

Capacitance

Parameter Description Test Conditions Max. Unit

CIN Input Capac it ance TA = 25 °C, f = 1 MHz,

VDD = 3.3V 10 pF

COUT Output Capacitance 10 pF

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Notes:

5. External AC Test Load Capacitance = 10 pF.

6. (Internal I/O pad Capacitance = 10 pF) + AC Test Load.

AC Test Load and Waveforms

=1.5V

OUTPUT

(a) Normal Load (Load 1)

R = 50

Ω

= 50

Ω

[5]

3.0V

VSS 90% 90%

10%

3ns 3ns

10%

≤≤

ALL INPUT PULSES

3.3V

OUTPUT

C = 5 p F

(b) Three-State Del ay (Load 2)

R2 = 4 35

Ω

R1 = 5 90

Ω

(b) Load Derati ng Curve

30 60 80 100 200

∆

tcd2 for 133 MHz (ns)

Capacitance (pF)

20[6]

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Switching Characteristics O ver the Operat ing Range

Parameter Description

CY7C09569V

CY7C09579V

Unit

-133 -100 -83 -67

Min. Max. Min. Max. Min. Max. Min. Max.

fMAX1 fMax Flow-Through 83 67 45 40 MHz

fMAX2 fMax Pipelined 133 100 83 67 M Hz

tCYC1 Cl ock Cycle Time - Flow-T hrough 12 15 22 25 ns

tCYC2 Cl ock Cycle Time - Pipelined 7.5 10 12 15 ns

tCH1 Clock HIGH Time - Flow-Through 4.8 6.5 7.5 8.5 ns

tCL1 Clock LOW Time - Flow-Thr ough 4.8 6.5 7.5 8.5 ns

tCH2 Clock HIGH Time - Pipelined 3 4 5 6.5 ns

tCL2 Clock LOW Time - Pipelined 3 4 5 6.5 ns

tRClock Rise Time 2333ns

tFClock Fall Time 2333ns

tSA Address Set-Up Time 3.0 3.5 4 4 ns

tHA Address Hold Time 0.5 0.5 0.5 0.5 ns

tSB Byte Select Set -Up Time 3.0 3.5 4 4 ns

tHB Byte Select Hold Time 0.5 0.5 0.5 0.5 ns

tSC Chip Enable Set-Up Time 3.0 3. 5 4 4 ns

tHC Chip Enable Hold Time 0.5 0. 5 0.5 0.5 ns

tSW R/W Set-Up Time 3.0 3.5 4 4 ns

tHW R/W Hold Time 0.5 0.5 0.5 0.5 ns

tSD Input Da ta Set-Up Time 3.0 3.5 4 4 ns

tHD Input Da ta Hol d Time 0.5 0.5 0.5 0.5 ns

tSAD ADS Set-Up Time 3.0 3.5 4 4 ns

tHAD ADS Hold Time 0.5 0.5 0.5 0.5 ns

tSCN CNTEN Set-Up Time 3.0 3.5 4 4 ns

tHCN CNTEN Hold Time 0.5 0.5 0.5 0.5 ns

tSRST CNTRST Set-Up Time 3.0 3.5 4 4 ns

tHRST CNTRST Hold Time 0.5 0.5 0.5 0.5 ns

tOE Output Enable to Data Valid 6.5 8 9 10 ns

tOLZ[7, 8] OE to Low Z 1222ns

tOHZ[7 , 8] OE to High Z 6171717ns

tCD1 Clock to Data Valid - Flow-Through 10.5 12.5 18 20 ns

tCD2 Clock to Data Valid - Pipel ined 4.1 5 6 8 ns

tCA1 Cloc k to Cou nter Address Valid - Flo w-

Through 10.5 12.5 18 20 ns

tCA2 Clock to Co unter Addr ess V al id - Pipel ined 8 9 10 11 ns

tDC Data Output Hold After Clock HIGH1222ns

tCKHZ[7, 8] Clock HIGH to Output High Z 14.5262728ns

tCKLZ[7, 8] Clock HIGH to Output Low Z 1222ns

Notes:

7. This parameter is guaranteed by design, but it is not production tested.

8. Test conditions used are Load 2.

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Port to Port De lays

tCWDD Write Port Clock HIGH to Read Data Delay 24 30 35 35 ns

tCCS Clock to Clock Set-Up Time 6.5 9 10 12 ns

Switching Characteristics O ver the Operating Range (continued)

Parameter Description

CY7C09569V

CY7C09579V

Unit

-133 -100 -83 -67

Min. Max. Min. Max. Min. Max. Min. Max.

Switching Wa vef orms

Read Cycle for Flow-Through Output (FT/PIPE = VIL)[ 9, 10 , 1 1, 12]

Notes:

9. OE is asy nchronously controlled; all other inputs are synchronous to the rising clock edge.

10. ADS = VIL, CNTEN = VIL and CNTRS T = VIH.

11. The output is disabled (high-impedance state) by CE=VIH following the next rising edge of the clock.

12. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.

tCH1 tCL1

tCYC1

tSC tHC

tDC

tOHZ

tOE

tSC tHC

tSW tHW

tSA tHA

tCD1 tCKHZ

tDC

tOLZ

tCKLZ

AnAn+1 An+2 An+3

QnQn+1 Qn+2

CLK

R/W

ADDRESS

DATAOUT

tSB tHB

B0-3

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Read Cycle for Pipelined Operati on (FT/PIPE = VIH)[9, 10, 11, 12]

Bus Match Read Cycle for Flo w -Through Output (FT/PIPE = VIL)[9, 11, 13, 14, 15]

Notes:

13. Timing shown is for x18 bus matching; x9 bus matching is simi lar with 4 cycles between address inputs.

14. See table “Right Port Operation “for data output on first and subsequent cycles.

15. CNTEN = VIL. In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at VIH

level all the time e xcept when loading the initial external address (i.e. ADS = VIL only required when reading or writing the first Byte or Word).

Swi tchi n g Wavef o rms (continued)

tCH2 tCL2

tCYC2

tSC tHC

tSW tHW

tSA tHA

AnAn+1

CLK

R/W

ADDRESS

DATAOUT

An+2 An+3

tSC tHC

tOHZ

tOE

tOLZ

tDC

tCD2

tCKLZ

QnQn+1 Qn+2

1 Latency

tSB tHB

B0-3

tCH1 tCL1

tCYC1

tDC

tSC tHC

tSW tHW

tSA tHA

tDC

tCKLZ

AnAnAn+1 An+1

QnQnQn+1

CLK

R/W

ADDRESS

DATAOUT

OE LOW

Qn+1

1st

Cycle 1st

Cycle

2nd

Cycle 2nd

Cycle

tCD1

ADS

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Bus Match Read Cycle for Pipe li ned Operation (FT/PIPE = VIH)[9, 11, 13, 14, 15]

Bank Select Pipeli ned Read[16, 17]

Notes:

16. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet.

ADDRESS(B1) = ADDRESS(B2).

17. B0 = B1 = B2 = B3 = BM = SIZE = A DS = CNTEN = VIL, CNTRST = VIH.

Swi tchi n g Wavef o rms (continued)

tCH2

CLK

R/W

ADDRESS

DATAOUT

AnAnAn+1 An+1

QnQn+1

tCYC2 tCL2

tSC tHC

tSW tHW

tSA tHA

1 Latency

tCD2

tCLKZ

LOW 1st Cycle 2nd Cycle 1st Cycle

CD2 tCD2

tDC tDC tDC

ADS

A0A1A2A3A4A5

tSA tHA

tSC tHC

tSA tHA

tSC tHC

tSC tHC tCKHZ

tDC

tCD2

tCKLZ

tCD2 tCD2 tCKHZ

tCKLZ

tCD2 tCKHZ

tCKLZ

tCD2

tCH2 tCL2

tCYC2

CLKL

ADDRESS(B1)

CE(B1)

DATAOUT(B2)

DATAOUT(B1)

ADDRESS(B2)

CE(B2)

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Left P ort Write to Fl ow-Through Right Port Read[17, 18, 19, 20, 21]

Pipelined Read-to-Write-to-Read (OE = VIL)[12, 22, 23, 24]

Notes:

18. The same waveforms apply for a right port write to flow-through left port read.

19. CE = B0 = B1 = B2 = B3 = ADS = CNTEN=VIL; CNTRST= VIH.

20. OE = VIL for the right port, which i s being read from. OE = VIH for the left port, which is being written to.

21. It tCCS ≤ maximum specified, then data from right port READ is not v alid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid

until tCCS + tCD1 (tCWDD does not appl y in this case).

22. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.

23. CE = ADS = CNTEN = VIL; CNTRST = VIH.

24. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.

Swi tchi n g Wavef o rms (continued)

tSA tHA

tSW tHW

tSD tHD

MATCH

VALID

tCCS

tSW tHW

tDC

tCWDD

tCD1

MATCH

tSA tHA

MATCH

VALID VALID

tDC

tCD1

CLKL

R/WL

ADDRESSL

DATAINL

ADDRESSR

DATAOUTR

CLKR

R/WR

tCYC2tCL2

tCH2

tHC

tSC

tHW

tSW

tHA

tSA

tHW

tSW

tCD2 tCKHZ

tSD tHD

tCKLZ tCD2

NO OPERATION WRITEREAD READ

CLK

R/W

ADDRESS

DATAIN

DATAOUT

AnAn+1 An+2 An+2

Dn+2

An+3 An+4

QnQn+3

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Pipelined Read-to-Write-to-Read (OE Controlled)[ 11 , 22 , 23 , 24]

Swi tchi n g Wavef o rms (continued)

tCYC2tCL2

tCH2

tHC

tSC

tHW

tSW

tHA

tSA

AnAn+1 An+2 An+3 An+4 An+5

tHW

tSW

tSD tHD

Dn+2

tCD2

tOHZ

READ READWRITE

Dn+3 tCKLZ tCD2

QnQn+4

CLK

R/W

ADDRESS

DATAIN

DATAOUT

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Bus Match Pipelined Read-to-Write-to-Read (O E = VIL)[11, 13, 14, 15, 23, 24, 25]

Note:

25. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain s tatic for any particular port configuration.

Swi tchi n g Wavef o rms (continued)

CLK

R/W

ADDRESS

DATAIN

DATAOUT

AnAnAn+1 An+1 An+2 An+2 An+3 An+3 An+4 An+4

QnQnQn+3 Qn+3

Dn+2 Dn+2

1s t Word 2nd Word

1st Word 2nd Word 1st W o rd 2nd Word

tCH2

tCYC2

tCL2

tSC tHC

tSW tHW

tSA tHA

READ READ READ READ READ READ

Operation1st C ycle 2n d Cyc le 1st C y cle 2nd Cycle

WRITE WRITE

1st C ycle 2n d Cyc le

tCD2 tCD2

tCKHZ

tCKLZ

tCD2 tDC

tSD tHD

ADS

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Flow- Through Read-to-Wr it e-to-Read (OE = VIL)[10, 12, 13, 14, 23 , 24]

Flow- Through Read-to-Wr it e-to-Read (OE Controll ed)[10 , 12, 22, 23, 24]

Swi tchi n g Wavef o rms (continued)

tCH1 tCL1

tCYC1

tSW tHW

tSA tHA

tSW tHW

tSD tHD

AnAn+1 An+2 An+2 An+3 An+4

Dn+2

QnQn+1 Qn+3

tCD1 tCD1

tDC tCKHZ

tCD1 tCD1

tCKLZ tDC

READ NO

OPERATION WRITE READ

CLK

ADDRESS

R/W

DATAIN

DATAOUT

tCH1 tCL1

tCYC1

tSW tHW

tSA tHA

tCD1 tDC

tOHZ

READ

AnAn+1 An+2 An+3 An+4 An+5

Dn+2 Dn+3

tSW tHW

tSD tHD

tCD1 tCD1

tCKLZ tDC

Qn+4

tOE

WRITE READ

CLK

ADDRESS

R/W

DATAIN

DATAOUT

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Bus Match Flow-Through Read -t o-Write-to-Read (OE = VIL)[11, 13, 14, 15, 23, 24, 25]

Swi tchi n g Wavef o rms (continued)

CLK

R/W

ADDRESS AnAnAn+1 An+1 An+1 An+1 An+1 An+2

DATAOUT

DATAIN

QnQnQn+1 Qn+1

Dn+1 Dn+1

tCH1 tCL1

tCYC1

tHC

tSC

tHW

tSW

tHA

tSA

tHW

tSW

1st W o rd 2nd Word

tHD

tSD

1s t Word 2nd Word

1st Cycle 2nd Cycle 1st Cycle 2nd Cycle 1st Cycle 2nd Cycle

READ READ WRITE WRITE READ READNo

Operation

tCD1

tCD1 tDC tCKHZ tCD1 tCD1

tCKLZ tDC

ADS

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Pipelined Read with Addr ess Counter Advance[26]

Flow -Through Read with Address Counter Advance[26]

Note:

26. CE = OE = VIL; R/W = CNTRST = VIH.

Swi tchi n g Wavef o rms (continued)

COUNTER HOLD

READ WITH COUNTER

tSA tHA

tSAD tHAD

tSCN tHCN

tCH2 tCL2

tCYC2

tSAD tHAD

tSCN tHCN

Qx–1QxQnQn+1 Qn+1 Qn+2

tDC

tCD2

READ WITH COUNTER

READ

EXTERNAL

ADDRESS

CLK

ADDRESS

ADS

DATAOUT

CNTEN

tCH1 tCL1

tCYC1

tSA tHA

tSAD tHAD

tSCN tHCN

QxQnQn+1 Qn+2 Qn+2

tSAD tHAD

tSCN tHCN

tDC

tCD1

COUNTER HOLD

READ WITH COUNTER

READ

EXTERNAL

ADDRESS

READ

WITH

COUNTER

CLK

ADDRESS

ADS

DATAOUT

CNTEN

Qn+3

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Write with Addr ess Counter Advance (Flow-Thr ough or Pip eli ned O utputs)[27, 28]

Notes:

27. CE= B0 = B1 = B2 = B3 = R/W = VIL; CNTRST = VIH.

28. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = VILand CNTRST=VIH.

Swi tchi n g Wavef o rms (continued)

tCH2 tCL2

tCYC2

AnAn+1 An+2 An+3 An+4

Dn+1 Dn+1 Dn+2 Dn+3 Dn+4

tSAD tHAD

tSCN tHCN

tSD tHD

WRITE EXTERNAL WRITE WITH COUNTER

ADDRESS WRITE W ITH

COUNTER WRITE COUNTER

HOLD

CLK

ADDRESS

INTERNAL

CNTEN

ADS

DATAIN

ADDRESS

tSA tHA

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Counter Reset (Pip e lined Outputs )[11 , 22 , 29 , 30 , 31 ]

Notes:

29. CE = B0 = B1 = B2 = B3 = VIL.

30. No dead cycle exists during counter reset. A READ or W RITE cycle may be coincidental with the counter reset.

31. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATAOUT should be in the High-Impedance state

during a valid WRITE cycle.

Swi tchi n g Wavef o rms (continued)

CLK

ADDRESS

INTERNAL

CNTEN

ADS

DATAIN

ADDRESS

CNTRST

R/W

DATAOUT

AnAmAp

Ax01AnAmAp

Q1Qn

tCH2 tCL2

tCYC2

tSA tHA

tSW tHW

tSRST tHRST

tSD tHD

tCD2 tCD2

tCKLZ

[31]

RESET ADDRESS 0

COUNTER WRITE READ

ADDRESS 0 ADDRESS 1

READ READ

ADDRESS AnADDRESS Am

READ

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Counter Reset (Flo w-Through Outputs)[22, 24, 29, 30, 31]

Swi tchi n g Wavef o rms (continued)

tCH2 tCL2

tCYC2

CLK

ADDRESS

INTERNAL

CNTEN

ADS

DATAIN

ADDRESS

CNTRST

R/W

DATAOUT Q0Q1

AX01AnAn+1

tSRST tHRST

tSD tHD

tSW tHW

AnAn+1

tSA tHA

COUNTER

RESET WRITE

ADDRESS 0 READ

ADDRESS 1 READ

ADDRESS n

tCD1

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Pipelined Read of State of Address Counter [32, 33, 34]

Flow- Through Read of State of Add ress Counter [32, 33, 35]

Notes:

32. CE = OE = VIL; R/W = CNTRST = VIH.

33. When reading ADDRESSOUT in x9 Bus Match mode, readout of AN is extended by 1 cy cle.

34. For Pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycl es for x36 and x18 mode and for 3

consecutive cycles for x9 mode.

35. For flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x36.

Swi tchi n g Wavef o rms (continued)

CNTEN

CLK

tCH2 tCL2

tCYC2

ADDRESS

ADS

Qx-2 Qx-1 Qn

n+1

n+2

tSA tHA

tSAD tHAD

tSCN tHCN

tSCN tHCN tSCN tHCN

tSAD tHAD

LOAD

ADDRESS

EXTERNAL COUNTER

HOLD

READ WITH COUNTER

tCA2

INTERNAL

ADDRESS An+1 An+2

READ WITH

COUNTER

tDC

READ COUNTER A DDRESS

DATAOUT

CNTEN

CLK

tCH1 tCL1

ADDRESS

ADS

QxQnAn

n+1

n+2

tSA tHA

tSAD tHAD

tSCN tHCN tSCN tHCN

tSCN tHCN

tSAD tHAD

LOAD

EXTERNAL

tCYC1

ADDRESS COUNTER

HOLD

READ WITH COUNTER

n+3

tDC

tCA1

INTERNAL

ADDRESS AnAn+1 An+2 An+3

DATAOUT

READ COUNTER ADDRESS

READ WITH

COUNTER

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Rea d /Write an d En able Op er ation[36, 37 , 38 ]

Inputs Outputs

OE CLK CE R/W I/O0–I/O35 Operation

X H X High-Z Deselected[39]

X L L DIN Write

L L H DOUT Read[39]

H X L X High-Z Outputs Disabled

Address Counter Cont rol Operation[36, 40]

Address Previous

Address CLK OE R/W ADS CNTEN CNTRST Mode Operation

X X X X X X L Reset Counter Rese t

AnX X X L L H Load Address Load into Cou nter

AnAnL H L H H Hold +

Read External Addr ess Blocked -

Counter Addr ess Read out

X AnX X H H H Hold External Address Blocked -

Counter Disabled

X AnX X H L H Incre-

ment Counter Increment

Notes:

36. “X” = “Don’t Care,” “H” = VIH, “L” = VIL.

37. ADS, CNTEN, CNTRST = “Don’t Care.”

38. OE is an asynchronous input signal.

39. W hen CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.

40. Counter operation is independent of CE.

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Right Port Configurat ion[25, 41]

Right Port Operation[42]

Readout of Internal Address Counter[43]

BM SIZE Confi guration I/O Pins used

00 x36 I/O

0R–35R

10 x18 I/O

0R–17R

11 x9 I/O

0R–8R

Configuration BE Data on 1st Cycle Data on 2nd Cycle Data on 3rd Cyc le Data on 4th Cycle

x18 0 DQ0R–17R DQ18R–35R --

x18 1 DQ18R–35R DQ0R–17R --

x9 0 DQ0R–8R DQ9R–17R DQ18R–26R DQ27R–35R

x9 1 DQ27R–35R DQ18R–26R DQ9R–17R DQ0R–8R

Configur ation Address on 1st Cycle I /O Pins used on 1st Cycle Address on 2nd

Cycle I/O Pins used on 2nd

Cycle

Left Port x36 A0L–14L I/O3L–17L --

Right Port x36 A0R–14R I/O3R–17R --

Right Port x18 W A, A0R–14R I/O2R–17R --

Right Por t x9 A6R–14R I/O0R–8R BA, WA, A0R–5R I/O1R–8R

Left Port Operation

Control Pin Effe ct

B0 I/O0–8 Byte Control

B1 I/O9–17 Byte Control

B2 I/O18–26 Byte Control

B3 I/O27–35 Byte Control

Notes:

41. In x36 mode, BE input is a “Don’t Care”.

42. DQ represents data output of the chip.

43. x18 and x9 configuration apply to right port only.

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Counter Operation

The CY7C09569V/09579V Dual-Port RAM (DPRAM) con-

tai ns on-chi p add ress coun ters ( one f or ea ch port) f or the syn-

chronous members of the product family. Besides the main

x36 f ormat, the right port al lows b us matching ( x18 or x9, use r-

selectable). An internal sub-counter provides the extra ad-

dresses required to sequence out the 36-bit word in 18-bit or

9-bit increments. The sub-counter counts up in the “Lit tle E n -

dian” mode, and counts down if the user has chosen the “Big

Endian” mode. The address counter is required to be in incr e-

ment mode in order for the sub-counter to sequence out the

second wor d (in x 18 mode) or t he remain ing thr ee b ytes (in x 9

mode).

For a x36 format (the only act ive format on the left port), each

addres s count er in the CY 7C09579V uses addr ess es (A0–14).

For the right port (allowing for the bus-matching feature), a

maximum of t wo address bits (out of a 2-bit sub-counter) are

added.

1. ADSL/R (pin #23/86 ) is a p ort's address strobe , allowi ng the

loading of that port's burst counters if the corresponding

CNTENL/R pin is active as well.

2. CNTENL/R (pin #25/84) is a port's count enable, pr ovided

to stall the ope ration of the address input and utilize t he

internal add ress generated by the internal counter for f ast

interleaved memory applications; wh en asserted, the ad-

dress c ounter will increment on each positi ve transit ion of

that port's clock signal.

3. CNTRSTL/R (pin #24/85) i s a port's burst counter reset .

A new r ead- back ( Hold +Read Mode) feature ha s been ad ded,

which is di ff er ent bet ween t he lef t and right po rt due to t he b us

matching feature p rovided only for the right port. In read-back

mode the internal address of the counter wil l be read from the

data I/Os as shown in Figure 1.

Bus Match Operation

The rig ht port of the CY7C09569V/0957 9V 16K/32Kx36 dual-

port SRAM can be configured in a 36-bit long-word, 18-bit

word, or 9-bi t b yte f o rmat f or d ata I/ O . The d ata lines are divid -

ed into four lanes, each consisting of 9 bits (byte-size data

lines).

The Bus Match Select (BM) pin works with Bus Size Select

(SIZE) and Big Endian Select (BE) to select the bus width

(long-word, word, or byte) and data sequencing arrangement

for the righ t port of the dual -port devi ce. A logic “0” applied to

both the Bus Match Sel ect (BM) pin an d to t he Bus Siz e Select

(S IZE ) pin w ill s elec t l ong- word ( 36- bit) opera tio n. A lo gic “1”

level applied to the Bus Match Select (BM) pin will enable

whether b yte or word bu s width opera tion on the right port I/Os

depending on the logic l evel applied to the SIZE pi n. The level

of Bus Match Select (BM) must be static throughout normal

device operation.

The Bus Size Select (SIZE) pin selects either a byte or word

data arrangement on the right port when the Bus Match Sel ect

(BM) pin is HI GH. A logi c “1” on t he SIZE pin whe n the BM pin

is HIGH selects a byte bus (9-bit ) data arrangement). A logic

“0” on the SIZE pin when the BM pin is HIGH selects a word

bus (18-bit) data ar rangement. The le vel of the Bus Siz e Select

(SIZE) must also be static throughout normal device operation.

The Big Endian Select (BE) pin is a multiple-function pin during

word or byte bus selection (BM = 1). BE is used in Big Endian

Select mode to determine t he order b y which bytes (or words)

of data are transferred through the r ight data port. A logic “0”

on the BE pin will select Little Endian data sequencing ar-

rangement and a log ic “1” on the BE pin will sel ect a Big Endi-

an data sequencing arrangement. Under these circumstanc-

es, the level on the BE pin should be static throughout dual-

por t operation.

Long-Word (36-bi t) Operation

Bus Match Select (BM) and Bus Size Select (SIZE) set to a

logic “0” will enable standard cycle long-word (36-bit) opera-

tion. In this mode, th e right port’s I/O oper a tes e ssenti ally in an

identical fashion to the left port of the dual-port SRAM. How-

ever no Byte Select cont rol is availab le. All 36 bits of t he long-

word are shift ed into and out of the right port’s I/O buffer stag-

es. Al l read and write timing parameters may be ident ical wit h

respect to t he two data ports. When the ri ght p ort is con fi gured

fo r a long-w ord siz e , Big- Endian Sel ect (BE) pin has no appl i-

catio n and their inputs are “don’t care”[44] f or th e ex ternal user .

CY7C09569V

CY7C09579V

RAM

ARRAY

____________

______________

_______

Address Read-Back

Figur e 1 . Count er Opera tion Dia gram

CY7C09569V

CY7C09579V

16K/32Kx36

Dual Port

BM SIZE

/x9, x18, x36

US MODE

Figure 2. Bus Mat ch Operati on Diagram

Note:

44. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are tempor arily a “Don’t Care” (along

with unused inputs) mus t not be allowed to float. They must be forced either HIGH or LOW.

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Word (18-bit) Operation

W ord ( 18-bit ) b us s izing operat ion i s enabl ed whe n Bus Ma tch

Select (BM) is set to a logic “1” a nd the Bus Si ze Select (SIZE)

pin i s set to a logic “0”. I n this mode , 18 bits of da ta are ported

through I/O0R–17R. The level applied to the Big Endian (BE) pin

determin es the ri ght po rt d ata I/O seq uencing ord er (Bi g Endi-

an or Little Endian).

During wor d ( 18- bit) bus size operation, a l ogic LOW applied

to the BE pin will select Little Endian operation. In this case,

the least significant data word is read from the r ight por t first

or writt en to the right port f irst. A l ogic “1” on t he BE pin durin g

word (18-bit) bus size operation will select Big Endian opera-

tion resulting in the most significant data word being trans-

ferred through the right port first. Internally, the data will be

stor ed in th e appropri ate 36- bit LSB or MSB I/ O memory loca-

ti on. Devi ce operat i on r equir es a minimum of tw o cl ock cyc les

to read or write during word (18-bit) bus size operation. An

internal sub-counter automatically increments the right port

multiplexer control when Little or Big Endian operation is in

effect.

Byte (9-bit) Operation

Byte (9-bit) bus sizing operation is enabled when Bus Match

Select (BM) is set to a logic “1” a nd the Bus Si ze Select (SIZE)

pin is set to a l ogic “1”. In this mode, 9 bits of dat a are ported

through I/O0R–8R.

Big Endian and Little Endian data sequencing is available for

dual-port operation. The level applied to the Big Endian pin

(BE) under these circumstances will deter mine the r ight port

data I/ O sequencing order (Big or Little Endian). A logic LOW

appli ed to the BE pin during b yte (9- bit) bus si ze op er ation will

select Little Endi an operati on. I n thi s case , the least significant

data byte is read from the r ight port first or written to the right

po rt first. A lo gi c “1” on the BE pin during by te (9-bit) bus size

operat ion wi ll select Big Endian oper ation res ulting in the most

significant data word to be transferred through the right port

fir st. Internally, the data will be stored in the appropriate 36-bit

LSB or MSB I/O memory location. Device operati on requires

a minimum of f our clock cycles to read or write du ring byte (9-

bit) bus size operati on. An internal sub-counter automatically

increments the right port multiplexer control when Little or Bi g

Endian op eration is in eff ect. When t ransf erring dat a in byt e (9 -

bit) bus match format, the unused I/O pins (I/O9RQ–35R) are

three-stated.

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Orde ring Information

Shaded areas contain adv ance information.

Document #: 38-00743-B

16K x36 3.3V Synchronous Dual-Port SRAM

Speed

(MHz) Orderi ng Code Package

Name Package Type Operating

Range

133 CY7C09569V-133AC A144 144-Pin Thin Quad Flat Pack Commercial

CY7C09569V-133BAC BB172 17 2-B a ll B a ll G r id Ar ray (BGA ) Com me rcia l

100 CY7C09569V-100AC A144 144-Pin Thin Quad Flat Pack Commercial

CY7C09569V-100BAC BB172 17 2-B a ll B a ll G r id Ar ray (BGA ) Com me rcia l

83 CY7C09569V-83AC A144 144-Pin Thin Quad Flat Pack Commercial

CY7C09569V-83AI A144 144-Pin Thin Quad Flat Pack Industrial

CY7C09569V-83BAC BB172 17 2-B a ll B a ll G r id Ar ray (BGA ) Commercial

CY7C09569V-83BAI BB172 1 7 2- B a ll B a ll Gr id Ar ray (BG A ) Industrial

67 CY7C09569V-67AC A144 144-Pin Thin Quad Flat Pack Commercial

CY7C09569V-67BAC BB172 17 2-B a ll B a ll G r id Ar ray (BGA ) Commercial

32K x36 3.3V Synchronous Dual-Port SRAM

Speed

(MHz) Orderi ng Code Package

Name Package Type Operating

Range

133 CY7C09569V-133AC A144 144-Pin Thin Quad Flat Pack Commercial

CY7C09569V-133BAC BB172 17 2-B a ll B a ll G r id Ar ray (BGA ) Com me rcia l

100 CY7C09579V-100AC A144 144-Pin Thin Quad Flat Pack Commercial

CY7C09579V-100BAC BB172 17 2-B a ll B a ll G r id Ar ray (BGA ) Com me rcia l

83 CY7C09579V-83AC A144 144-Pin Thin Quad Flat Pack Commercial

CY7C09579V-83AI A144 144-Pin Thin Quad Flat Pack Industrial

CY7C09579V-83BAC BB172 17 2-B a ll B a ll G r id Ar ray (BGA ) Commercial

CY7C09579V-83BAI BB172 1 7 2- B a ll B a ll Gr id Ar ray (BG A ) Industrial

67 CY7C09579V-67AC A144 144-Pin Thin Quad Flat Pack Commercial

CY7C09579V-67BAC BB172 17 2-B a ll B a ll G r id Ar ray (BGA ) Commercial

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V: 10/97

Revision: May 1, 2000

Package D i ag r ams

144-Pin Plastic Thin Quad Flat Pack (TQFP) A144

51-85047-A

CY7C09569V

CY7C09579V

PRELIMINARY

7C09579V:

Revision: May 1, 2000

of any circuit ry other than circu itry embodied i n a Cypress Sem ic onductor product. Nor does it conv ey or imply any license under patent or oth er rights . Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package D i ag r ams (continued)

172-Bal l BGA BB172

51-85114