1White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
*ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
8Mx64 Flash 3.3V Page Mode Multi-Chip Package
Access Times of 110, 120ns
Packaging
• 159 PBGA, 13x22mm – 1.27mm pitch
Page Mode
• Page size is 8 words: Fast page read access from
random locations within the page.
Uniform Sector Architecture
• One hundred twenty-eight 64 kword / 128KB
Sectors
Single power supply operation
• 3 volt read, erase, and program operations
I/O Control
• All input levels (address, control, and DQ input
levels) and outputs are determined by voltage on
VIO input. VIO range is 1.65 to VCC
Write operation status bits indicate program and
erase operation completion
Suspend and Resume commands for program and
erase operations
Hardware Reset# input resets device
WP#/ACC Input
• Accelerates programming time for greater
throughput.
• Protects fi rst and last sector regardless of sector
protection settings
Secured Silicon Sector region
• 128-word/256-byte sector for permanent, secure
identifi cation through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
• May be programmed and locked at the factory or
by the customer
100,000 erase cycles per sector typical
20-year data retention typical
* This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
FEATURES
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White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
TBD
WE1# WE2#
CS2#
WE3#
CS3#
WE4#
CS4#CS1#
R Y/BY#
RESET#
OE #
A-1, A0-22
WP#/ACC
DQ16-31 DQ32-47 DQ48-63
DQ0-15
8M X 16 8M X 16 8M X 16 8M X 16
V
IO
V
IO
V
CC
GND
GND
GND
GND
GND
GND
V
IO
V
CC
V
IO
V
CC
V
IO
GND
GND
DQ33
OE#
A2
A3
A4
DQ
17
DQ24
DQ16
CS2#
V
CC
GND
GND
DQ41
DQ43
A0
WP#/ACC
A6
A17
WE
2
#
DQ19
DQ26
DQ18
DQ25
GND
GND
WE
3
#
DQ45
A22
A11
A9
RY/BY#
DQ29
DQ21
DQ28
DQ20
DQ27
GND
V
CC
V
CC
V
CC
V
IO
V
IO
DQ47
V
CC
GND
V
CC
GND
DNU*
DQ31
DQ23
DQ30
DQ22
V
IO
NC
DQ49
A12
V
IO
GND
A14
DQ9
DQ1
DQ8
DQ0
CS
1
#
V
CC
GND
DNU
DQ59
A16
A7
A1
A5
DQ4
DQ11
DQ3
DQ10
DQ2
GND
GND
WE
4
#
DQ61
A21
A10
RESET#
A18
WE
1
#
DQ6
DQ13
DQ5
DQ12
GND
GND
V
CC
DQ63
DQ40 DQ35 DQ37 DQ39 DQ56 DQ51 DQ53 DQ55
DQ32 DQ42 DQ44 DQ46 DQ48 DQ58 DQ60 DQ62
CS
3
# DQ34 DQ36 DQ38 CS
4
# DQ50 DQ52 DQ54
A20
A15
A13
A8
A19
DQ15
DQ7
DQ14
GND
GND
V
IO
V
CC
V
IO
V
CC
GND
GND
GND*
GND
GND
GND
V
IO
V
CC
V
IO
V
CC
V
IO
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
123456789 10
FIG 3: BLOCK DIAGRAM
FIG 2: PIN DESCRIPTION
DQ0-63 Data Inputs/Outputs
A0-22 Address Inputs
WE#1-4 Write Enables
CS#1-4 Chip Selects
OE# Output Enable
RESET# Hardware Reset
WP#/ACC Hardware Write
Protection/Acceleration
RY/BY# Ready/Busy Output
VCC Power Supply
VIO Versitile I/O Input
GND Ground
DNU Do Not Use
FIG 1: PIN CONFIGURATION
FOR W78M64VP-XSBX (TOP VIEW)
* Ball L5 is reserved for A23 for future upgrades.
TBD
TB
TB
2#2#
BD
D
BD
BD
BD
WE3#WE3#
CS3#CS3#
DQ
1
T
T
TBD
TBD
BD
BD
8M X 16
M X 1
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White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
GENERAL DESCRIPTION
The W78M64VP-XSBX is a 512Mb, 3.3 volt-only Page
Mode memory device.
The device offers fast page access times allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has separate chip
enable (CS#), write enable (WE#) and output enable (OE#)
controls.
The device offers uniform 64 Kword (128Kb) Sectors:
Page Mode Features
The page size is 8 words. After initial page access is
accomplished, the page mode operation provides fast read
access speed of random locations within that page.
Standard Flash Memory
Features
The device requires a 3.3 volt power supply for both read
and write functions. Internally generated and regulated
voltages are provided for the program and erase operations
Page Mode Features
The page size is 8 words. After initial page access is
accomplished, the page mode operation provides fast read
access speed of random locations within that page.
Device Operations
This section describes the read, program, erase,
handshaking, and reset features of the Flash devices.
Operations are initiated by writing specifi c commands or
a sequence with specifi c address and data patterns into
the command registers ( see Table 38 and table 39). The
command register itself does not occupy andy addressable
memory location; rather, it is composed of latches that store
the commands, along with the address and data information
needed to execute the command. The contents of the
register serves as input to the internal state machine and
the state machine outputs dictate the function of the device.
Writing incorrect address and data values or writing them in
an improper sequence may place the device in an unknown
state, in which case the system must pull the RESET# pin
low or power cycle the device to return the device to the
reading array data mode.
Device Operation Table
The device must be setup appropriately for each operation.
Table 2 describes the required state of each control pin for
any particular operation.
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to
set the voltage levels that the device generates and tolerates
on all inputs and outputs (address, control, and DQ signals).
VIO range is 1.65 to VCC.
For example, a VIO of 1.65-3.6 volts allows for I/O at the
1.8 or 3 volt levels, driving and receiving signals to and from
other 1.8 or 3 V devices on the same data bus.
Read
All memories require access time to output array data. In a
read operation, data is read from one memory location at
a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes
the data on its outputs to arrive with the address on its
inputs.
The device defaults to reading array data after device power-
up or hardware reset. To read data from the memory array,
the system must fi rst assert a valid address on Amax-A0,
while driving OE# and CE# to VIL. WE# must remain at
VIH. All addresses are latched on the falling edge of CE#.
Data will appear on DQ15-DQ0 after address access time
(tACC), which is equal to the delay from stable addresses
to valid output data.
The OE# signal must be driven to VIL. Data is output on
DQ15-DQ0 pins after the access time (tOE) has
elapsed from the falling edge of OE#, assuming the tACC
access time has been meet.
Page Read Mode
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random
locations within a page. The page size of the device is 8
words/16 bytes. The appropriate page is selected by the
higher address bits A(max)-A3.
Address bits A2-A0 in word mode (A2 to A-1 in byte
mode) determine the specifi c word within a page. The
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W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
microprocessor supplies the specifi c word location. The
random or initial page access is equal to tACC or tCE and
subsequent page read accesses (as long as the locations
specifi ed by the microprocessor falls within that page)
is equivalent to tPACC. When CE# is deasserted and
reasserted for a subsequent access, the access time is
tACC or tCE. Fast page mode accesses are obtained by
keeping the “read-page addresses” constant and changing
the “intra-read page” addresses.
Autoselect
The Autoselect mode provides manufacturer ID, Device
identifi cation, and sector protection information, through
identifi er codes output from the internal register (separate
from the memory array) on DQ7-DQ0. This mode is primarily
intended for programming equipment to automatically
match a device to be programmed with its corresponding
programming algorithm (see Table 4). The Autoselect codes
can also be accessed in-system.
There are two methods to access autoselect codes. One
uses the autoselect command, the other applies VID on
address pin A9.
When using programming equipment, the autoselect mode
requires VID (11.5 V to 12.5 V) on address pin A9. Address
pins must be as shown in Table 3.
To access Autoselect mode without using high
voltage on A9, the host system must issue the
Autoselect command.
The Autoselect command sequence may be written
to an address within a sector that is either in the read
or erase-suspend-read mode.
The Autoselect command may not be written while
the device is actively programming or erasing.
The system must write the reset command to return
to the read mode (or erase-suspend-read mode if the
sector was previously in Erase Suspend).
It is recommended that A9 apply VID after power-
up sequence is completed. In addition, it is
recommended that A9 apply from VID to VIH/VIL
before power-down the VCC/VIO.
See Table 38 for command sequence details.
When verifying sector protection, the sector address
must appear on the appropriate highest order
address bits (see Table 5 to Table 6). The remaining
address bits are don't care. When all necessary
bits have been set as required, the programming
equipment may then read the corresponding
identifi er code on DQ15-DQ0. The Autoselect
codes can also be accessed in-system through the
command register.
Program/Erase Operations
These devices are capable of several modes of programming
and or erase operations which are described in detail in the
following sections.
During a write operation, the system must drive CE# and
WE# to VIL and OE# to VIH when providing address,
command, and data. Addresses are latched on the last
falling edge of WE# or CE#, while data is latched on the
1st rising edge of WE# or CE#.
The Unlock Bypass feature allows the host system to send
program commands to the Flash device without fi rst writing
unlock cycles within the command sequence. See Unlock
Bypass section for details on the Unlock Bypass function.
Note the following:
When the Embedded Program algorithm is complete,
the device returns to the read mode.
The system can determine the status of the program
operation by reading the DQ status bits. Refer to
the Write Operation Status for information on these
status bits.
An “0” cannot be programmed back to a “1.” A
succeeding read shows that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Any commands written to the device during the
Embedded Program/Erase are ignored except the
Suspend commands.
Secured Silicon Sector, Autoselect, and CFI
functions are unavailable when a program operation
is in progress.
A hardware reset and/or power removal immediately
terminates the Program/Erase operation and the
Program/Erase command sequence should be
reinitiated once the device has returned to the read
mode to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries for single word programming
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October 2008
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ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
operation. See Write Buffer Programming when
using the write buffer.
Programming to the same word address multiple
times without intervening erases is permitted.
Single Word Programming
Single word programming mode is one method of
programming the Flash. In this mode, four Flash command
write cycles are used to program an individual Flash
address. The data for this programming operation could
be 8 or 16-bits wide.
While the single word programming method is supported
by most Spansion devices, in general Single Word
Programming is not recommended for devices that support
Write Buffer Programming. See Table 38 for the required bus
cycles and FIG: 4 for the fl owchart. When the Embedded
Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The
system can determine the status of the program operation
by reading the DQ status bits. Refer to Write Operation
Status for information on these status bits.
During programming, any command (except the
Suspend Program command) is ignored.
The Secured Silicon Sector, Autoselect, and CFI
functions are unavailable when a program operation
is inprogress.
A hardware reset immediately terminates the
program operation. The program command
sequence should
be reinitiated once the device has returned to the
read mode, to ensure data integrity.
Programming to the same address multiple times
continuously (for example, “walking” a bit within a
word) is permitted.
Write Buffer Programming
Write Buffer Programming allows the system to write a
maximum of 32 words in one programming operation. This
results in a faster effective word programming time than the
standard “word” programming algorithms.
The Write Buffer Programming command sequence is
initiated by fi rst writing two unlock cycles. This is followed by
a third write cycle containing the Write Buffer Load command
written at the Sector Address in which programming occurs.
At this point, the system writes the number of “word locations
minus 1” that are loaded into the page buffer at the Sector
Address in which programming occurs. This tells the
device how many write buffer addresses are loaded with
data and therefore when to expect the “Program Buffer
to Flash” confirm command. The number of locations
to program cannot exceed the size of the write buffer or
the operation aborts. (Number loaded = the number of
locations to program minus 1. For example, if the system
programs 6 address locations, then 05h should be written
to the device.)
The system then writes the starting address/data
combination. This starting address is the fi rst address/data
pair to be programmed, and selects the “write-buffer-page”
address. All subsequent address/data pairs must fall within
the elected-write-buffer-page.
The “write-buffer-page” is selected by using the addresses
AMAX–A5.
The “write-buffer-page” addresses must be the same for all
address/data pairs loaded into the write buffer. (This means
Write Buffer Programming cannot be performed across
multiple “write-buffer-pages.” This also means that Write
Buffer Programming cannot be performed across multiple
sectors. If the system attempts to load programming data
outside of the selected “write-buffer-page”, the operation
ABORTs.)
After writing the Starting Address/Data pair, the system
then writes the remaining address/data pairs into the write
buffer.
Note that if a Write Buffer address location is loaded multiple
times, the “address/data pair” counter is decremented for
every data load operation. Also, the last data loaded at
a location before the “Program Buffer to Flash” confi rm
command is the data programmed into the device. It is
the software's responsibility to comprehend ramifi cations
of loading a write-buffer location more than once. The
counter decrements for each data load operation, NOT
for each unique write-buffer-address location. Once the
specifi ed number of write buffer locations have been loaded,
the system must then write the “Program Buffer to Flash”
command at the Sector Address. Any other address/data
write combinations abort the Write Buffer Programming
operation. The Write Operation Status bits should be used
while monitoring the last address location loaded into the
write buffer. This eliminates the need to store an address
in memory because the system can load the last address
location, issue the program confi rm command at the last
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October 2008
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loaded address location, and then check the write operation
status at that same address. DQ7, DQ6, DQ5, DQ2, and
DQ1 should be monitored to determine the device status
during Write Buffer Programming.
The write-buffer “embedded” programming operation
can be suspended using the standard suspend/resume
commands. Upon successful completion of the Write Buffer
Programming operation, the device returns to READ mode.
The Write Buffer Programming Sequence is ABORTED
under any of the following conditions:
Load a value that is greater than the page buffer size
during the “Number of Locations to Program” step.
Write to an address in a sector different than the one
specifi ed during the Write-Buffer-Load command.
Write an Address/Data pair to a different write-
buffer-page than the one selected by the “Starting
Address” during the “write buffer data loading” stage
of the operation.
Writing anything other than the Program to Buffer
Flash Command after the specifi ed number of “data
load” cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7
= DATA# (for the “last address location loaded”),
DQ6 = TOGGLE, DQ5 = 0. This indicates that
the Write Buffer Programming Operation was
ABORTED. A “Write-to- Buffer-Abort reset” command
sequence is required when using the write buffer
Programming features in Unlock Bypass mode. Note
that the Secured Silicon sector, autoselect, and CFI
functions are unavailable when a program operation
is in progress.
Write buffer programming is allowed in any sequence of
memory (or address) locations. These fl ash devices are
capable of handling multiple write buffer programming
operations on the same write buffer address range without
intervening erases.
Use of the write buffer is strongly recommended
for programming when multiple words are to be
programmed.
Sector Erase
The sector erase function erases one or more sectors in the
memory array. (See Table 38 and FIG: 6.) The device does
not require the system to preprogram a sector prior to erase.
The Embedded Erase algorithm automatically programs
and verifi es the entire memory to an all zero data pattern
prior to electrical erase. After a successful sector erase,
all locations within the erased sector contain FFFFh. The
system is not required to provide any controls or timings
during these operations.
After the command sequence is written, a sector erase time-
out of no less than tSEA occurs. During the timeout period,
additional sector addresses may be written. Loading the
sector erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50
μs. Any sector erase address and command following the
exceeded time-out (50μs) may or may not be accepted. Any
command other than Sector Erase or Erase Suspend during
the time-out period resets that sector to the read mode. The
system can monitor DQ3 to determine if the sector erase
timer has timed out. The time-out begins from the rising edge
of the fi nal WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the
sector returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing
sector. Refer to Section write operation status section for
information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the sector
erase command sequence should be reinitiated once that
sector has returned to reading array data, to ensure the
sector is properly erased.
The Unlock Bypass feature allows the host system to send
program commands to the Flash device without fi rst writing
unlock cycles within the command sequence. See Unlock
Bypass Section for details on the Unlock Bypass function.
FIG: 6 illustrates the algorithm for the erase operation.
Refer to Erase and Programming Performance Section for
parameters and timing diagrams.
Chip Erase Command
Sequence
Chip erase is a six-bus cycle operation as indicated by
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White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
Table 38. These commands invoke the Embedded Erase
algorithm, which does not require the system to preprogram
prior to erase. The Embedded Erase algorithm automatically
preprograms and verifi es the entire memory to an all zero
data pattern prior to electrical erase. After a successful chip
erase, all locations of the chip contain FFFFh. The system
is not required to provide any controls or timings during
these operations. The Command Defi nitions shows the
address and data requirements for the chip erase command
sequence.
When the Embedded Erase algorithm is complete, that
sector returns to the read mode and addresses are no
longer latched. The system can determine the status of the
erase operation by using DQ7 or DQ6/DQ2. Refer to “Write
Operation Status” for information on these status bits.
The Unlock Bypass feature allows the host system to send
program commands to the Flash device without fi rst writing
unlock cycles within the command sequence. See Unlock
Bypass Section for details on the Unlock Bypass function.
Any commands written during the chip erase operation are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that sector
has returned to reading array data, to ensure the entire
array is properly erased.
Erase Suspend/Erase
Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. The sector address is required when writing this
command. This command is valid only during the sector
erase operation, including the minimum tSEA time-out
period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the
chip erase operation.
When the Erase Suspend command is written during the
sector erase operation, the device requires a maximum of 20
μs (5 μs typical) to suspend the erase operation. However,
when the Erase Suspend command is written during the
sector erase time-out, the device immediately terminates
the time-out period and suspends the erase operation.
After the erase operation has been suspended, the device
enters the erase-suspend-read mode. The system can
read data from or program data to any sector not selected
for erasure. (The device “erase suspends” all sectors
selected for erasure.) Reading at any address within
erase-suspended sectors produces status information on
DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2
together, to determine if a sector is actively erasing or is
erase-suspended.
After an erase-suspended program operation is complete,
the device returns to the erase-suspend-read mode. The
system can determine the status of the program operation
using write operation status bits, just as in the standard
program operation.
In the erase-suspend-read mode, the system can also issue
the Autoselect command sequence. Refer to Write Buffer
Programming Section and the Autoselect Section.
To resume the sector erase operation, the system must write
the Erase Resume command. The address of the erase-
suspended sector is required when writing this command.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after the
chip has resumed erasing.
Program Suspend/Program
Resume Commands
The Program Suspend command allows the system
to interrupt an embedded programming operation or a
“Write to Buffer” programming operation so that data can
read from any non-suspended sector. When the Program
Suspend command is written during a programming
process, the device halts the programming operation within
15 μs maximum (5 μs typical) and updates the status bits.
Addresses are “don't-cares” when writing the Program
Suspend command.
After the programming operation has been suspended, the
system can read array data from any nonsuspended sector.
The Program Suspend command may also be issued during
a programming operation while an erase is suspended. In
this case, data may be read from any addresses not within
a sector in Erase Suspend or Program Suspend. If a read
is needed from the Secured Silicon Sector area, then user
must use the proper command sequences to enter and
exit this region.
The system may also write the Autoselect Command
Sequence when the device is in Program Suspend
mode. The device allows reading Autoselect codes in the
suspended sectors, since the codes are not stored in the
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W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
memory array. When the device exits the Autoselect mode,
the device reverts to Program Suspend mode, and is ready
for another valid operation. See Autoselect Section.
After the Program Resume command is written, the device
reverts to programming. The system can determine the
status of the program operation using the write operation
status bits, just as in the standard program operation. See
Write Operation Status Section for more information.
The system must write the Program Resume command
(address bits are “don't care”) to exit the Program Suspend
mode and continue the programming operation. Further
writes of the Program Resume command are ignored.
Another Program Suspend command can be written after
the device has resumed programming.
Accelerated Program
Accelerated single word programming and write buffer
programming operations are enabled through the WP#/
ACC pin. This method is faster than the standard program
command sequences.
NOTE
The accelerated program functions must not be used more
than 10 times per sector. If the system asserts VHH on this
input, the device automatically enters the aforementioned
Unlock Bypass mode and uses the higher voltage on the
input to reduce the time required for program operations.
The system can then use the Write Buffer Load command
sequence provided by the Unlock Bypass mode. Note that
if a “Write-to-Buffer-Abort Reset” is required while in Unlock
Bypass mode, the full 3-cycle RESET command sequence
must be used to reset the device. Removing VHH from the
ACC input, upon completion of the embedded program
operation, returns the device to normal operation.
Sectors must be unlocked prior to raising WP#/ACC
to VHH.
The WP#/ACC pin must not be at VHH for
operations other than accelerated programming, or
device damage may result.
It is recommended that WP#/ACC apply VHH after
power-up sequence is completed. In addition, it is
recommended that WP#/ACC apply from VHH to
VIH/VIL before powering down VCC/VIO.
Unlock Bypass
This device features an Unlock Bypass mode to facilitate
shorter programming commands. Once the device enters
the Unlock Bypass mode, only two write cycles are required
to program data, instead of the normal four cycles.
This mode dispenses with the initial two unlock cycles
required in the standard program command sequence,
resulting in faster total programming time. The Command
Defi nitions shows the requirements for the unlock bypass
command sequences.
During the unlock bypass mode, only the Read, Program,
Write Buffer Programming, Write-to-Buffer-Abort Reset,
and Unlock Bypass Reset commands are valid. To exit the
unlock bypass mode, the system must issue the two-cycle
unlock bypass reset command sequence. The fi rst cycle
must contain the sector address and the data 90h. The
second cycle need only contain the data 00h. The sector
then returns to the read mode.
Write Operation Status
The device provides several bits to determine the status of
a program or erase operation. The following subsections
describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and
DQ7.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of
the final WE# pulse in the command sequence. Note
that the Data# Polling is valid only for the last word being
programmed in the write-buffer-page during Write Buffer
Programming. Reading Data# Polling status on any word
other than the last word to be programmed in the write-
buffer-page returns false status information.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed
to DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to read
valid status information on DQ7. If a program address falls
within a protected sector, Data# polling on DQ7 is active,
then that sector returns to the read mode.
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During the Embedded Erase Algorithm, Data# polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The
system must provide an address within any of the sectors
selected for erasure to read valid status information on
DQ7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data# Polling on DQ7
is active for approximately 100 μs, then the device returns
to the read mode. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads DQ7 at an address within a
protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or
Erase operation, DQ7 may change asynchronously with
DQ6-DQ0 while Output Enable (OE#) is asserted low.
That is, the device may change from providing status
information to valid data on DQ7. Depending on when the
system samples the DQ7 output, it may read the status or
valid data. Even if the device has completed the program or
erase operation and DQ7 has valid data, the data outputs
on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00
appears on successive read cycles.
See the following for more information: Table 18, shows the
outputs for Data# Polling on DQ7. FIG: 7, shows the Data#
Polling algorithm; and FIG: 22, shows the Data# Polling
timing diagram.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the fi nal WE# pulse in the command
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address that is being
programmed or erased causes DQ6 to toggle. When the
operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for
approximately 100μs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erasesuspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the
device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6
toggles for approximately 1μs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program Algorithm
is complete.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-
asserted and reasserted to show the change in state.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the fi nal WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. But DQ2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and mode
information. Refer to Table 18 to compare outputs for DQ2
and DQ6.
Reading Toggle Bits DQ6/
DQ2
Whenever the system initially begins reading toggle bit status,
it must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the fi rst read.
After the second read, the system would compare the new
value of the toggle bit with the fi rst. If the toggle bit is not
toggling, the device has completed the program or erases
operation. The system can read array data on DQ7–DQ0
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on the following read cycle. However, if after the initial two
read cycles, the system determines that the toggle bit is still
toggling, the system also should note whether the value of
DQ5 is high (see DQ5: Exceeded Timing Limits). If it is, the
system should then determine again whether the toggle bit
is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erases operation. If it is still toggling, the device did not
complete the operation successfully, and the system must
write the reset command to return to reading array data. The
remaining scenario is that the system initially determines
that the toggle bit is toggling and DQ5 has not gone high.
The system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when
it returns to determine the status of the operation. Refer to
FIG: 7 for more details.
NOTE
When verifying the status of a write operation (embedded
program/erase) of a memory sector, DQ6 and DQ2 toggle
between high and low states in a series of consecutive and
contiguous status read cycles. In order for this toggling
behavior to be properly observed, the consecutive status bit
reads must not be interleaved with read accesses to other
memory sectors. If it is not possible to temporarily prevent
reads to other memory sectors, then it is recommended
to use the DQ7 status bit as the alternative method of
determining the active or inactive status of the write
operation.
DQ5: Exceeded Timing
Limits
DQ5 indicates whether the program or erase time has
exceeded a specifi ed internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed. The device
does not output a 1 on DQ5 if the system tries to program a
1 to a location that was previously programmed to 0. Only
an erase operation can change a 0 back to a 1. Under this
condition, the device ignores the bit that was incorrectly
instructed to be programmed from a 0 to a 1, while any
other bits that were correctly requested to be changed from
1 to 0 are programmed. Attempting to program a 0 to a 1
is masked during the programming operation. Under valid
DQ5 conditions, the system must write the reset command
to return to the read mode (or to the erase-suspend-read
mode if a sector was previously in the erase-suspend-
program mode).
DQ3: Sector Erase Timeout
State Indicator
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not erasure
has begun. (The sector erase timer does not apply to the
chip erase command.) If additional sectors are selected
for erasure, the entire time-out also applies after each
additional sector erase command. When the time-out period
is complete, DQ3 switches from a “0” to a “1.” If the time
between additional sector erase commands from the system
can be assumed to be less than tSEA, then the system need
not monitor DQ3. See Sector Erase for more details.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the
command sequence, and then read DQ3. If DQ3 is “1,”
the Embedded Erase algorithm has begun; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is “0,” the device
accepts additional sector erase commands. To ensure
the command has been accepted, the system software
should check the status of DQ3 prior to and following each
sub-sequent sector erase command. If DQ3 is high on the
second status check, the last command might not have
been accepted. Table 18 shows the status of DQ3 relative
to the other status bits.
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was
aborted. Under these conditions DQ1 produces a “1”.
The system must issue the “Write to Buffer Abort Reset”
command sequence to return the device to reading array
data. See Write Buffer Programming for more details.
Writing Commands/
Command Sequences
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During a write operation, the system must drive CE# and
WE# to VIL and OE# to VIH when providing an address,
command, and data. Addresses are latched on the last
falling edge of WE# or CE#, while data is latched on the 1st
rising edge of WE# or CE#. An erase operation can erase
one sector, multiple sectors, or the entire device. Table 1
indicate the address space that each sector occupies. The
device address space is divided into uniform 64KW/128KB
sectors. A sector address is the set of address bits required
to uniquely select a sector. ICC2 in “DC Characteristics”
represents the active current specifi cation for the write
mode. “AC Characteristics” contains timing specifi cation
tables and timing diagrams for write operations.
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress or
complete. The RY/BY# status is valid after the rising edge of
the fi nal WE# pulse in the command sequence. Since RY/
BY# is an open-drain output, several RY/BY# pins can be
tied together in parallel with a pull-up resistor to VCC. This
feature allows the host system to detect when data is ready
to be read by simply monitoring the RY/BY# pin, which is a
dedicated output and controlled by CE# (not OE#).
Hardware Reset
The RESET# input provides a hardware method of resetting
the device to reading array data. When RESET# is driven
low for at least a period of tRP (RESET# Pulse Width), the
device immediately terminates any operation in progress,
tristates all outputs, resets the confi guration register, and
ignores all read/write commands for the duration of the
RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity Program/Erase operations that were
interrupted should be reinitiated once the device is ready to
accept another command sequence.
When RESET# is held at VSS, the device draws VCC reset
current (ICC5). If RESET# is held at VIL, but not at VSS, the
standby current is greater. RESET# may be tied to the
system reset circuitry which enables the system to read the
boot-up fi rmware from the Flash memory upon a system
reset.
Software Reset
Software reset is part of the command set (see Table 12.1
on page 69) that also returns the device to arrayread mode
and must be used for the following conditions:
1. to exit Autoselect mode
2. when DQ5 goes high during write status operation that
indicates program or erase cycle was not successfully
completed
3. exit sector lock/unlock operation.
4. to return to erase-suspend-read mode if the device was
previously in Erase Suspend mode.
5. after any aborted operations
The following are additional points to consider when using
the reset command:
This command resets the sectors to the read and
address bits are ignored.
Reset commands are ignored during program and
erase operations.
The reset command may be written between the
cycles in a program command sequence before
programming begins (prior to the third cycle). This
resets the sector to which the system was writing to
the read mode.
If the program command sequence is written to a
sector that is in the Erase Suspend mode, writing
the reset command returns that sector to the erase-
suspend-read mode.
The reset command may be written during an
Autoselect command sequence.
If a sector has entered the Autoselect mode while
in the Erase Suspend mode, writing the reset
command returns that sector to the erase-suspend-
read mode.
If DQ1 goes high during a Write Buffer Programming
operation, the system must write the “Write to Buffer
abort Reset” command sequence to RESET the
device to reading array data. The standard RESET
command does not work during this condition.
To exit the unlock bypass mode, the system must
issue a two-cycle unlock bypass reset command
sequence [see Command Defi nitions for details].
Advanced Sector Protection/
Unprotection
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The Advanced Sector Protection/Unprotection feature
disables or enables programming or erase operations in any
or all sectors and can be implemented through software and/
or hardware methods, which are independent of each other.
This section describes the various methods of protecting
data stored in the memory array. An overview of these
methods in shown in FIG: 8.
Lock Register
As shipped from the factory, all devices default to the
persistent mode when power is applied, and all sectors
are unprotected. The device programmer or host system
must then choose which sector protection method to use.
Programming (setting to “0”) any one of the following two
one-time programmable, non-volatile bits locks the part
permanently in that mode:
Lock Register Persistent Protection Mode Lock Bit
(DQ1)
Lock Register Password Protection Mode Lock Bit
(DQ2)
NOTES
Notes
1. If the password mode is chosen, the password must
be programmed before setting the corresponding lock
register bit.
2. After the Lock Register Bits Command Set Entry
command sequence is written, reads and writes for Sector
0 are disabled, while reads from other sectors are allowed
until exiting this mode.
3. If both lock bits are selected to be programmed (to zeros)
at the same time, the operation aborts.
4. Once the Password Mode Lock Bit is programmed,
the Persistent Mode Lock Bit is permanently disabled,
and no changes to the protection scheme are allowed.
Similarly, if the Persistent Mode Lock Bit is programmed,
the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can
operate in any of the following three states:
1. Constantly locked. The selected sectors are protected and
can not be reprogrammed unless PPB lock bit is cleared
via a password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected
and can be altered via software commands.
3. Unlocked. The sectors are unprotected and can be erased
and/or programmed.
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for
each sector and have the same endurances as the Flash
memory. Preprogramming and verifi cation prior to erasure
are handled by the device, and therefore do not require
system monitoring.
NOTES
1. Each PPB is individually programmed and all are erased
in parallel.
2. While programming PPB for a sector, array data can
be read from any other sector, except Sector 0 (used
for Data# Polling) and the sector in which sector PPB is
being programmed.
3. Entry command disables reads and writes for the sector
selected.
4. Reads within that sector return the PPB status for that
sector.
5. All Reads must be performed using the read mode.
6. The specifi c sector address (A22-A16) are written at the
same time as the program command.
7. If the PPB Lock Bit is set, the PPB Program or erase
command does not execute and times-out without
programming or erasing the PPB.
8. There are no means for individually erasing a specifi c
PPB and no specifi c sector address is required for this
operation.
9. Exit command must be issued after the execution which
resets the device to read mode and reenables reads and
writes for Sector 0.
10. The programming state of the PPB for a given sector
can be verifi ed by writing a PPB Status Read Command
to the device as described by the fl ow chart shown in
FIG: 9.
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Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each
sector and can be individually modifi ed. DYBs only control
the protection scheme for unprotected sectors that have
their PPBs cleared (erased to “1”). By issuing the DYB Set or
Clear command sequences, the DYBs are set (programmed
to “0”) or cleared (erased to “1”), thus placing each sector in
the protected or unprotected state respectively. This feature
allows software to easily protect sectors against inadvertent
changes yet does not prevent the easy removal of protection
when changes are needed.
NOTE
1. The DYBs can be set (programmed to “0”) or cleared
(erased to “1”) as often as needed. When the parts are
fi rst shipped, the PPBs are cleared (erased to “1”) and
upon power up or reset, the DYBs can be set or cleared
depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen,
(erased to “1”), then the sectors may be modified
depending upon the PPB state of that sector (see Table
20).
3. The sectors would be in the protected state If the option
to set the DYBs after power up is chosen (programmed
to “0”).
4. It is possible to have sectors that are persistently locked
with sectors that are left in the dynamic state.
5. The DYB Set or Clear commands for the dynamic sectors
signify protected or unprotectedstate of the sectors
respectively. However, if there is a need to change the
status of the persistently locked sectors, a few more steps
are required. First, the PPB Lock Bit must be cleared
by either putting the device through a power-cycle, or
hardware reset. The PPBs can then be changed to
refl ect the desired settings. Setting the PPB Lock Bit
once again locks the PPBs, and the device operates
normally again.
6. To achieve the best protection, it is recommended to
execute the PPB Lock Bit Set command early in the
boot code and protect the boot code by holding WP#/
ACC = VIL. Note that the PPB and DYB bits have the
same function when WP#/ACC = VHH as they do when
ACC =VIH.
Persistent Protection Bit
Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile
bit for all sectors. When set (programmed to “0”), it locks
all PPBs and when cleared (programmed to “1”), allows
the PPBs to be changed. There is only one PPB Lock Bit
per device.
NOTE
1. No software command sequence unlocks this bit unless
the device is in the password protection mode; only a
hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to “0”) only
after all PPBs are conFIG:d to the desired settings.
Password Protection Method
The Password Protection Method allows an even higher
level of security than the Persistent Sector Protection Mode
by requiring a 64-bit password for unlocking the device PPB
Lock Bit. In addition to this password requirement, after
power up and reset, the PPB Lock Bit is set “0” to maintain
the password mode of operation. Successful execution
of the Password Unlock command by entering the entire
password clears the PPB Lock Bit, allowing for sector PPBs
modifi cations.
NOTES
1. There is no special addressing order required for
programming the password. Once the Password is written
and verifi ed, the Password Mode Locking Bit must be set
in order to prevent access.
2. The Password Program Command is only capable of
programming “0”s. Programming a “1” after a cell is
programmed as a “0” results in a time-out with the cell
as a “0”.
3. The password is all “1”s when shipped from the factory.
4. All 64-bit password combinations are valid as a
password.
5. There is no means to verify what the password is after
it is set.
6. The Password Mode Lock Bit, once set, prevents reading
the 64-bit password on the data bus and further password
programming.
7. The Password Mode Lock Bit is not erasable.
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8. The lower two address bits (A1–A0) are valid during the
Password Read, Password Program, and Password
Unlock.
9. The exact password must be entered in order for the
unlocking function to occur.
10. The Password Unlock command cannot be issued
any faster than 1 μs at a time to prevent a hacker from
running through all the 64-bit combinations in an attempt
to correctly match a password.
11. Approximately 1 μs is required for unlocking the device
after the valid 64-bit password is given to the device.
12. Password verifi cation is only allowed during the password
programming operation.
13. All further commands to the password region are
disabled and all operations are ignored.
14. If the password is lost after setting the Password Mode
Lock Bit, there is no way to clear the PPB Lock Bit.
15. Entry command sequence must be issued prior to any
of any operation and it disables reads and writes for
Sector 0. Reads and writes for other sectors excluding
Sector 0 are allowed.
16. If the user attempts to program or erase a protected
sector, the device ignores the command and returns
to read mode.
17. A program or erase command to a protected sector
enables status polling and returns to read mode without
having modifi ed the contents of the protected sector.
18. The programming of the DYB, PPB, and PPB Lock for a
given sector can be verifi ed by writing individual status
read commands DYB Status, PPB Status, and PPB
Lock Status to the device.
Hardware Data Protection
Methods
The device offers two main types of data protection at the
sector level via hardware control:
When WP#/ACC is at VIL, the either the highest or
lowest sector is locked (device specifi c).
There are additional methods by which intended or
accidental erasure of any sectors can be prevented via
hardware means. The following subsections describes
these methods:
WP#/ACC METHOD
The Write Protect feature provides a hardware method of
protecting one outermost sector. This function is provided
by the WP#/ACC pin and overrides the previously discussed
Sector Protection/Unprotection method.
If the system asserts VIL on the WP#/ACC pin, the device
disables program and erase functions in the highest or
lowest sector independently of whether the sector was
protected or unprotected using the method described in
Advanced Sector Protection/Unprotection.
If the system asserts VIH on the WP#/ACC pin, the device
reverts to whether the boot sectors were last set to be
protected or unprotected. That is, sector protection or
unprotection for these sectors depends on whether they
were last protected or unprotected.
The WP#/ACC pin must be held stable during a command
sequence execution. WP# has an internal pull-up; when
unconnected, WP# is set at VIH.
NOTE
If WP#/ACC is at VIL when the device is in the standby
mode, the maximum input load current is increased.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets to
reading array data. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control inputs to prevent unintentional writes
when VCC is greater than VLKO.
WRITE PULSE “GLITCH PROTECTION”
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
POWER-UP WRITE INHIBIT
If WE# = CE# = RESET# = VIL and OE# = VIH during power
up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
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Power Conservation Modes
STANDBY MODE
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of
the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at VCC ±
0.3 V. The device requires standard access time (tCE) for
read access, before it is ready to read data. If the device
is deselected during erasure or programming, the device
draws active current until the operation is completed. ICC4
in “DC Characteristics” represents the standby current
specifi cation
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC + 30 ns. The
automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available
to the system. ICC6 represents the automatic sleep mode
current specifi cation.
HARDWARE RESET# INPUT
OPERATION
The RESET# input provides a hardware method of resetting
the device to reading array data. When RESET# is driven
low for at least a period of tRP
, the device immediately
terminates any operation in progress, tristates all outputs,
and ignores all read/write commands for the duration of
the RESET# pulse. The device also resets the internal
state machine to reading array data. The operation that
was interrupted should be reinitiated once the device is
ready to accept another command sequence to ensure
data integrity.
When RESET# is held at VSS ± 0.3 V, the device draws ICC
reset current (ICC5). If RESET# is held at VIL but not within
VSS ± 0.3 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and thus,
a system reset would also reset the Flash
memory, enabling the system to read the boot-up fi rmware
from the Flash memory.
OUTPUT DISABLE (OE#)
When the OE# input is at VIH, output from the device is
disabled. The outputs are placed in the high impedance
state. (With the exception of RY/BY#.)
SECURED SILICON SECTOR FLASH
MEMORY REGION
Secured Silicon Sector Flash Memory Region The Secured
Silicon Sector provides an extra Flash memory region that
enables permanent part identifi cation through an Electronic
Serial Number (ESN). The Secured Silicon Sector is 128
words in length and all Secured Silicon reads outside of the
128-word address range returns invalid data. The Secured
Silicon Sector Indicator Bit, DQ7, (at Autoselect address
03h) is used to indicate whether or not the Secured Silicon
Sector is locked when shipped from the factory.
Please note the following general conditions:
On power-up, or following a hardware reset, the
device reverts to sending commands to the normal
address space.
Reads outside of sector SA0 return memory array
data.
Sector SA0 is remapped from memory array to
Secured Silicon Sector array.
Once the Secured Silicon Sector Entry Command
is issued, the Secured Silicon Sector Exit command
must be issued to exit Secured Silicon Sector Mode.
The Secured Silicon Sector is not accessible when
the device is executing an Embedded Program or
Embedded Erase algorithm.
The ACC function and unlock bypass modes are
not available when the Secured Silicon Sector is
enabled.
FACTORY LOCKED SECURED SILICON
SECTOR
The Factory Locked Secured Silicon Sector is always
protected when shipped from the factory and has the
Secured Silicon Sector Indicator Bit (DQ7) permanently set
to a “1”. This prevents cloning of a factory locked part and
ensures the security of the ESN and customer code once
the product is shipped to the fi eld.
These devices are available pre-programmed with one of
the following:
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A random, 8 Word secure ESN only within the
Secured Silicon Sector (at addresses 000000H -
000007H)
Both a random, secure ESN and customer code
through the Spansion programming service.
Customers may opt to have their code programmed through
the Spansion programming services. Spansion programs
the customer's code, with or without the random ESN. The
devices are then shipped from the Spansion factory with
the Secured Silicon Sector permanently locked. Contact
your local representative for details on using Spansion
programming services.
CUSTOMER LOCKABLE SECURED
SILICON SECTOR
The Customer Lockable Secured Silicon Sector is always
shipped unprotected (DQ7 set to “0”), allowing customers to
utilize that sector in any manner they choose. If the security
feature is not required, the Secured Silicon Sector can be
treated as an additional Flash memory space.
Please note the following:
Once the Secured Silicon Sector area is protected,
the Secured Silicon Sector Indicator Bit is
permanently set to “0.”
The Secured Silicon Sector can be read any number
of times, but can be programmed and locked only
once. The Secured Silicon Sector lock must be used
with caution as once locked, there is no procedure
available for unlocking the Secured Silicon Sector
area and none of the bits in the Secured Silicon
Sector memory space can be modifi ed in any way.
The accelerated programming (ACC) and unlock
bypass functions are not available when the Secured
Silicon Sector is enabled.
Once the Secured Silicon Sector is locked and
verifi ed, the system must write the Exit Secured
Silicon Sector Region command sequence which
return the device to the memory array at sector 0.
SECURED SILICON SECTOR ENTRY/
EXIT COMMAND SEQUENCES
The system can access the Secured Silicon Sector region
by issuing the three-cycle Enter Secured Silicon Sector
command sequence. The device continues to access
the Secured Silicon Sector region until the system issues
the four-cycle Exit Secured Silicon Sector command
sequence.
See Command Definitions [Secured Silicon Sector
Command Table, Appendix
Table 38 for address and data requirements for both
command sequences.
The Secured Silicon Sector Entry Command allows the
following commands to be executed
Read customer and factory Secured Silicon areas
Program the customer Secured Silicon Sector
After the system has written the Enter Secured Silicon
Sector command sequence, it may read the Secured Silicon
Sector by using the addresses normally occupied by sector
SA0 within the memory array. This mode of operation
continues until the system issues the Exit Secured Silicon
Sector command sequence, or until power is removed from
the device.
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TABLE 1 SECTOR & MEMORY ADDRESS MAP
Uniform Sector Size Sector Count Sector Range Address Range (16-bit) Notes
Sector Count 128
SA00 0000000h - 000FFFFh Sector Starting Address
:
SA127 07F0000 - 7FFFFF Sector Ending Address
TABLE 2 DEVICE OPERATIONS
Operation CE# OE# WE# RESET# WP3/
ACC Addresses
(Note 1) DQ0 - DQ7 DQ8 - DQ15
BYTE# = VIH BYTE# = VIL
Read L L H H X AIN DOUT DOUT
DQ8-DQ14 = High-Z,
DQ15 = A-1
Write (Program/
Erase) L H L H (Note 2) AIN (Note 3) (Note 3)
Accelerated Program L H L H VHH AIN (Note 3) (Note 3)
Standby VCC ±
0.3V XX
VCC ±
0.3V H X High-Z High-Z High-Z
Output Disable L H H H X X High-Z High-Z High-Z
Reset X X X L X X High-Z High-Z High-Z
Legend
L = Logic Low = VIL, H = Logic High = VIH, VHH = 11.5–12.5V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes
1. Addresses are AMax:A0 in word mode; AMax:A-1 in byte mode.
2. If WP# = VIL, on the outermost sector remians protected. If WP# = VIH, the outermost secotr is unprotected. WP# has an internal pull-up; when uconnected, WP# is a VIH. All sectors
are unprotected wen shipped from the factory ( The Secured Silicon Sector can be factory protected depending on version ordered.)
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm.
TABLE 3 AUTOSELECT CODES, (HIGH VOLTAGE METHOD)
Description CE# OE# WE# Amax
to
A16
A14
to
A10 A9 A8
to
A7
A5
to
A4
A3
to
A2 A1 A0
DQ8 to DQ15
DQ7 to DQ0
BYTE#
=VIH BYTE#
=VIL
Device
ID
Cycle 1
LL H X XV
ID XL
L L H 22 X 7Eh
Cycle 2 H H L 22 X 21h
Cycle 3 H H H 22 X 01h
Sector Group Protection
Verifi cation LL H SAXV
ID XLLHL X X
01h
(unprotected),
00h
(unprotected)
Secured Silicon Sector
Indicator Bit (DQ7), WP#
protects highest address
sector
LL H X XV
ID XLLHH X X
99h (factory
locked), 19h (not
factory locked)
Secured Silicon Sector
Indicator Bit (DQ7), WP#
protects lowest address
sector
LL H X XV
ID XLLHH X X
89h (factory
locked), 09h (not
facotry locked)
Legend
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. VID = 11.5V to 12.5V
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TABLE 4 AUTOSELECT ADDRESSES IN SYSTEM
Uniform Sector Size Sector Count Read Data (word/byte mode)
Manufacturer ID (Base) + 00h xx02h/h1
Device ID, Word 1 (Base) + 01h 227Eh/7Eh
Device ID, Word 2 (Base) + 0Eh 2221h/01h
Device ID, Word 3 (Base) + 0Fh 2201h/01h
Secure Device Verify (Base) + 03h XX19h/19h = Note Factory Locked. XX99h/99h = Factory locked
XX09h/09h = Note Factory Locked. XX89h/89h = Factory locked
Sector Protect Verify (SA) + 02h xx01h/01h = Locked. XX00h/00h = Unlocked
TABLE 5 AUTOSELECT ENTRY IN SYSTEM
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1
Write
Base + AAAh Base + 555h 0x00AAh
Unlock Cycle 2 Base + 555h Base + 2AAh 0x0055h
Autoselect Command Base + AAAh Base + 555h 0x0090h
TABLE 6 AUTOSELECT EXIT
Cycle Operation Byte address Word Address Data
Unlock Cycle 1 Write Base + XXXh Base + XXXh 0x00F0h
Note
1. Any offset within the device works.
2. base = base address.
TABLE 7 SINGLE WORD/BYTE PROGRAM
(LLD Function = lld_ProgramCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1
Write
Base + AAAh Base + 555h 00AAh
Unlock Cycle 2 Base + 555h Base + 2AAh 0055h
Program Setup Base + AAAh Base + 555h 00A0h
Program Byte Address Word Adress Data
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TABLE 8 WRITE BUFFER PROGRAM
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle Description Operation Byte Address Word Address Data
1 Unlock
Write
Base + AAAh Base + 555h 00AAh
2 Unlock Base + 555h Base + 2AAh 0055h
3 Write Buffer Load Command Sector Address 0025h
4 Write Word Count Sector Address Word Count (N-1)h
Number of words (N) loaded into the wrtie buffer can be from 1 to 32 words (1 to 64 bytes).
5 to 36 Load Buffer Word N Write Program Address, Word N Word N
Last Write Buffer to Flash Sector Address 0029h
Notes
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37.
3. For maximum effi ciency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
TABLE 9 SECTOR ERASE
(LLD Function = lld_SectorEraseCmd)
Cycle Description Operation Byte Address Word Address Data
1 Unlock
Write
Base + AAAh Base + 555h 00AAh
2 Unlock Base + 555h Base + 2AAh 0055h
3 Setup Command Base + AAAh Base + 555h 0080h
4 Unlock Base + AAAh Base + 555h 00AAh
5 Unlock Base + 555h Base + 2AAh 0055h
6 Sector Erase Command Sector Address 0030h
Unlimited additional sectors may be selected for erase; command(s) must be written within 50μs
Notes
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37.
3. For maximum effi ciency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
TABLE 10 SECTOR ERASE
(LLD Function = lld_SectorEraseCmd)
Cycle Description Operation Byte Address Word Address Data
1 Unlock
Write
Base + AAAh Base + 555h 00AAh
2 Unlock Base + 555h Base + 2AAh 0055h
3 Setup Command Base + AAAh Base + 555h 0080h
4 Unlock Base + AAAh Base + 555h 00AAh
5 Unlock Base + 555h Base + 2AAh 0055h
6 Chip Erase Command Base + AAAh Base + 555h 0010h
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TABLE 11 ERASE SUSPEND
(LLD Function = lld_EraseSuspendCmd)
Cycle Operation Byte address Word Address Data
1 Write Base + XXXh Base + XXXh 00B0h
TABLE 13 PROGRAM SUSPEND
(LLD Function = lld_ProgramSuspendCmd)
Cycle Operation Word Address Data
1 Write Base + XXXh 00B0h
TABLE 12 ERASE RESUME
(LLD Function = lld_EraseSuspendCmd)
Cycle Operation Byte address Word Address Data
1 Write Sector Address Sector Address 0030h
TABLE 15 UNLOCK BYPASS ENTRY
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle Description Byte address Word Address Data
1 Unlock
Write
Base + 555h 00AAh
2 Unlock Base + 2AAh 0055h
3 Entry Command Base + 555h 0020h
TABLE 14 PROGRAM RESUME
(LLD Function = lld_ProgramSuspendCmd)
Cycle Operation Word Address Data
1 Write Base + XXXh 0030h
TABLE 16 UNLOCK BYPASS PROGRAM
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle Description Byte address Word Address Data
1 Program Setup Command Write Base + xxxh 00AAh
2 Program Command Program Address 0055h
TABLE 17 UNLOCK BYPASS PROGRAM
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle Description Byte address Word Address Data
1 Reset Cycle 1 Write Base + xxxh 0090h
2 Reset Cycle 2 Base + xxxh 0000h
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TABLE 18 WRITE OPERATION STATUS
Status DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) DQ1 RY/BY#
Standard Mode
Embedded Program
Algorithm DQ7# Toggle 0 N/A No toggle 0 0
Embedded Erase
Algorithm 0 Toggle 0 1 Toggle N/A 0
Program
Suspend Mode Program Suspend Read
Program-Suspended
Sector Invalid (not allowed) 1
Non-Suspend Sector Data 1
Erase Suspend
Mode
Erase-Suspend Read
Erase-Suspended
Sector 1 No toggle 0 N/A Toggle N/A 1
Non-Erase Suspended
Sector Data 1
Erase-Suspend-Program (Embedded Program) DQ7# Toggle 0 N/A N/A N/A 0
Write-to-Buffer Busy (Note 3) DQ7# Toggle 0 N/A N/A 0 0
Abort (Note 4) DQ7# Toggle 0 N/A N/A 1 0
Notes
1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer toDQ5: Exceeded Timing Limits on page
39 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation
TABLE 19 SOFTWARE FUNCTIONS RESET
(LLD Function = lld_ResetCmd)
Cycle Operation Byte Address Word Address Data
Reset Command Write Base + xxxh Base + xxxh 00F0h
TABLE 20 LOCK REGISTER
DQ15-3 DQ2 DQ1 DQ0
Don't Care Password Protection Mode
Lock Bit
Persistent Protection Mode
Lock Bit
Secured Silicon Sector
Protection Bit
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TABLE 22 LOCK REGISTER
Secured Silicon Sector Address
Range Customer Lockable ESN Factory Locked ExpressFlash Factory Locked
000000h-000007h Determined by customer ESN ESN or determinded by customer
000008h-000007Fh Unavailable Determinined by customer
TABLE 23 SECURED SILICON SECTOR ENTRY
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1
Write
Base + AAAh Base + 555h 00AAh
Unlock Cycle 2 Base + 555h Base + 2AAh 0055h
Entry Cycle Base + AAAh Base + 555h 0088h
Note
Base = Base Address.
TABLE 21 SECTOR PROTECTION SCHEMES: DYB, PPB AND PPB LOCK BIT COMBINATIONS
Uniques Device PPB Lock Bit
0 = locked
1 = unlock
Sector PPB
0 = locked
1 = unlock
Sector DYB
0 = locked
1 = unlock Sector Protection Status
Any Sector 0 0 x Protected through PPB
Any Sector 0 0 x Protected through PPB
Any Sector 0 1 1 Unportected
Any Sector 0 1 0 Protected through PPB
Any Sector 1 0 x Protected through PPB
Any Sector 1 0 x Protected through PPB
Any Sector 1 1 0 Protected through PPB
Any Sector 1 1 1 Unportected
Table 21 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the
sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs are allowed. The PPB
Lock Bit can only be unlocked (reset to “1”) through a hardware reset or power cycle. See also FIG: 8.1 for
an overview of the Advanced Sector Protection feature.
TABLE 24 SECURED SILICON SECTOR PROGRAM
(LLD Function = lld_ProgramCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1
Write
Base + AAAh Base + 555h 00AAh
Unlock Cycle 2 Base + 555h Base + 2AAh 0055h
Program Setup Base + AAAh Base + 555h 0088h
Program Word Address Word Address Data Word
Note
Base = Base Address.
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TABLE 25 SECURED SILICON SECTOR EXIT
(LLD Function = lld_SecSiSectorExitCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1
Write
Base + AAAh Base + 555h 00AAh
Unlock Cycle 2 Base + 555h Base + 2AAh 0055h
Exit Cycle 3 Base + AAAh Base + 555h 0088h
Exit Cycle 4 Base + AAAh Base + 000h 0000h
Note
Base = Base Address.
TABLE 26 ABSOLUTE MAXIMUM RATINGS
Description Rating
Storage Temperature -55ºC to +125ºC
Ambient Temperature with Power Applied
Voltage with Respect to Ground
All Inputs and I/Os except as noted below (Note 1) -0.5V to VCC + 0.5V
VCC (Note 1) -0.5V to +4.0 V
VIO -0.5V to +4.0 V
A9 and ACC (Note 2) 0.5V to +12.5V
Notes
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See FIG: 11. Maximum DC voltage
on input or I/Os is VCC + 0.5 V. During voltage transitions inputs or I/Os may overshoot to VCC + 2.0 V for periods up to 20 ns. See FIG: 12.
2. Minimum DC input voltage on pins A9 and ACC is -0.5V. During voltage transitions, A9 and ACC may overshoot VSS to –2.0 V for periods of up to 20 ns. See FIG: 11. Maximum DC
voltage on pins A9 and ACC is +12.5 V, which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these
or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended
periods may affect device reliability.
TABLE 28 RECOMMENDED OPERATING
CONDITIONS
Parameter Symbol Min Max Unit
Supply Voltage VCC 3.0 3.6 V
I/O Supply Voltage VIO 3.0 3.6 V
Operating Temp. (Mil.) TA-55 +125 °C
Operating Temp. (Ind.) TA-40 +85 °C
Note: For all AC and DC specifi cations: VIO = VCC
TABLE 27 CAPACITANCE
TA = +25°C, f = 1.0MHz
Parameter Symbol Max Unit
WE# capacitance CWE TBD pF
CS# capacitance CCS TBD pF
Data I/O capacitance CI/O TBD pF
Address input capacitance CAD TBD pF
RESET# capacitance CRS TBD pF
RY/BY# CRB TBD pF
OE# capacitance COE TBD pF
This parameter is guaranteed by design but not tested.
TABLE 29 DATA RETENTION
Parameter Test Conditions Min Unit
Pattern Data
Retention Time
150°C 10 Years
125°C 20 Years
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TABLE 30 DC CHARACTERISTICS
Parameter
Symbol Parameter Description (Notes) Test Conditions Min Max Unit
ILI Input Load Current VIN = VSS to VCC
VCC = VCC max
WP/ACC 20 μA
Others 10
ILIT A9 Input Load Current VCC = VCC max; 12.5V 140 μA
ILO Output Leakage Current VOUT = VSS to VCC, VCC =VCC max 4μA
ICC1 VCC active Read Current (1) CE# =VIL, OE# = VIH, VCC = VCC max, f = 5MHz 220 mA
IIO2 VIO Non-active Output CE# =VIL, OE# = VIH 40 mA
ICC2 VCC Intra-Page Read Current (1) CE# =VIL, OE# = VIH, VCC = VCC max, f = 10MHz 40 mA
ICC3 VCC Active Erase/Program CUrrent (2, 3) CE# =VIL, OE# = VIH, VCC = VCC max 360 mA
ICC4 VCC Standby Current CE#, RESET# =VCC ±0.3V, OE# = VIH, VCC = VCC
max VIL = VSS + 0.3V/-0.1V
20 μA
ICC5 VCC Reset Current VCC = VCC max; VIL = VSS + 0.3V/-0.1V,
RESET# = VSS ±0.3V
200 μA
ICC6 Automatic Sleep Mode (4) VCC = VCC max, VIH = VCC ±0.3V,
VIL = VSS + 0.3V/-0.1V, WP#/ACC = VIH
20 μA
IACC ACC Accelerated Program Current CE# = VIL, OE# = VIH
VCC = VCC max, WP#/ACC = VHH
WP#/ACC pin 80 mA
VCC pin 320
VIL Input Low Voltage (5) -0.1 0.3 x VIO V
VIH Input High Voltage (5) 0.7 x VIO VIO + 0.3 V
VHH Voltage for Program Acceleration VCC = 2.7 - 3.6V 11.5 12.5 V
VID Voltage for Autoselect and Temporary Sector
Unportect
VCC = 2.7 - 3.6V 11.5 12.5 V
VOL Output Low Voltage (5) IOL = 100μA 0.15 x
VIO
V
VOH Output High Voltage (5) IOH = 100μA 0.85 x VIO V
VLKO Low VCC Lock-Out Voltage 2.3 2.5 V
Notes
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
3. Not 100% tested.
4. Automatic sleep mode enables the lower power mode when addresses remain stable tor tACC + 30 ns.
5. VIO = 1.65–3.6 V
6. VCC = 3 V and VIO = 3V or 1.8V. When VIO is at 1.8V, I/O pins cannot operate at 3V.
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TABLE 31 AC TEST CONDITIONS
Parameter Typ Unit
Input Pulse Levels VIL - 0, VIH = 2.5 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16 mA.
Tester Impedance Z0 = 50Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to similate a typical resistive load circuit.
ATE tester Includes jig capacitance.
TABLE 32 AC CHARACTERISTICS - READ-ONLY OPERATIONS
VCC = 3.3V ± 0.3V, -55°C ≤ TA ≤ +125°C
Parameter Symbol -110
Min Max -120
Min Max Unit
Read Cycle Time (1) tAVAV tRC 110 120 ns
Address Access Time tAVQV tACC 110 120 ns
Chip Select Access Time tELQV tCE 110 120 ns
Page Access Time (1) tPACC 110 120 ns
Output Enable to Output Valid tOLQV tOE 25 25 ns
Chip Select High to Output High Z tEHQZ tDF 20 20 ns
Output Enable High to Output High Z tGHQZ tDF 20 20 ns
Output Hold from Addresses, CS# or OE# Change, Whichever
occurs fi rst tAXQX tOH 00ns
Output Enable Hold Time (1)
Read tOEH 00ns
Toggle and Data#
Polling 10 10 ns
Chip Enable Hold Time tCEH 35 35 ns
Note:
1. Not tested.
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TABLE 33 AC CHARACTERISTICS - HARDWARE RESET (1)
Parameter Symbol Min Max Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode tready 35 μs
RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode tready 35 μs
RESET# Pulse Width tRP 35 μs
RESET# High Time Before Read tRH 200 ns
RESET# Low to Standby Mode tRPD 10 μs
RY/BY# Recovery Time tRB 0ns
Note:
1. Not tested.
TABLE 34 POWER-UP SEQUENCE TIMINGS
Parameter Description Speed Unit
tVCS Reset Low Time from rising edge of VCC (or last Reset pulse) to rising edge of RESET# 35 35 μs
tVIOS Reset Low Time from rising edge of VIO (or last Reset pulse) to rising edge of RESET# 35 35 μs
tRH Reset High Time before Read 35 200 μs
Notes
1. VIO < VCC + 200 mV.
2. VIO and VCC ramp must be synchronized during power up.
3. If RESET# is not stable for tVCS or tVIOS:
The device does not permit any read and write operations.
A valid read operation returns FFh.
A hardware reset is required.
4. VCC maximum power-up current (RST=VIL) is 20 mA.
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TABLE 35 AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
VCC = 3.3V ± 0.3V, -55°C ≤ TA ≤ +125°C
Parameter Symbol -100
Min Max -120
Min Max Unit
Write Cycle Time (3) tAVAV tWC 110 120 ns
Chip Select Setup Time (3) tELWL tCS 00ns
Write Enable Pulse Width tWLWH tWP 35 35 ns
Address Setup Time tAVWL tAS 00ns
Data Setup Time tDVWH tDS 30 30 ns
Data Hold Time tWHDX tDH 00ns
Address Hold Time tWLAX tAH 45 45 ns
Write Enable Pulse Width High (3) tWHWL tWPH 30 30 ns
Duration of Byte Programming Operation (1) tWHWH1 480 480 μs
Sector Erase (2) tWHWH2 5 5 sec
Read Recovery Time before Write (3) tGHWL 00ns
VCC Setup Time (3) tVCS 35 35 μs
Chip Programming Time (4) 200 200 sec
Address Setup Time to OE# low during toggle bit polling tASO 15 15 ns
Notes:
1. Typical value for tWHWH1 is 6μs.
2. Typical value for tWHWH2 is 0.5 sec.
3. Guaranteed by design, but not tested.
4. Typical value is 50 sec. The typical chip program time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program
times listed.
TABLE 36 AC CHARACTERISTICS - ALTERNATE CS# CONTROLLED ERASE AND PROGRAM
OPERATIONS
Parameter Description Speed
Options Unit
JEDEC Std 110 120
tVAVAV tWS Write Cycle Time (1) Min 110 120 ns
tAVWL tAS Address Setup Time Min 0 0 ns
tELAX tAH Address Hold Time Min 45 50 ns
tDVEH tDS Data Setup Time Min 30 30 ns
tEHDX tDH Data Hold Time Min 0 0 ns
tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 0 ns
tWLEL tWS WE# Setup Time Min 0 0 ns
tEHWH tWH WE# Hold Time Min 0 0 ns
tELEH tCP CS# Pulse Width Min 35 35 ns
tEHEL tCPH CS# Pulse Width High (1) Min 30 30 ns
tWHWH1 tWHWH1 Programming Operation Typ 480 480 μs
tWHWH1 tWHWH1 Accelerated Programming Operation Typ 13.5 13.5 μs
tWHWH2 tWHWH2 Sector Erase Operation Typ 0.5 0.5 sec
Note:
1. Not tested.
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TABLE 37 ERASE AND PROGRAMMING PERFORMANCE
VCC = 3.3V ± 0.3V, -55°C ≤ TA ≤ +125°C
Parameter Typ
(Note 1) Max
(Note 2) Unit Comments
Sector Erase Time 0.5 3.5 sec Excludes 00h programming prior to erasure (Note
4)
Chip Erase Time 64 256 sec
Total Write Buffer Time (Note 3) 480 μs
Excludes system level overhead (Note 5)Total Accelerated Write Buffer Programming Time (Note 3) 432 μs
Ship Program Time 123 sec
Notes
1. VIO < VCC + 200 mV.
2. VIO and VCC ramp must be synchronized during power up.
3. If RESET# is not stable for tVCS or tVIOS:
The device does not permit any read and write operations.
A valid read operation returns FFh.
A hardware reset is required.
4. VCC maximum power-up current (RST=VIL) is 20 mA.
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TABLE 38 MEMORY ARRAY COMMAND DEFINITIONS
Command
Cycles
Bus Cycles (Note 1-5)
First Second Third Fouth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (6) 1 RA RD
Reset (7) 1 XXX F0
AutoSelect
(8, 9)
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID (8) 4 555 AA 2AA 55 555 90 X01 227E X0E (8) X0F (8)
Sector Protect Verify (10) 4 555 AA 2AA 55 555 90 [SA]X02 (10)
Secure Device Verify (11) 4 555 AA 2AA 55 555 90 X03 (11)
CFI Query (12) 1 55 98
Program 4 555 AA 2AA 55 555 A0 PA PD
Write to Buffer 3 555 AA 2AA 55 SA 25 SA WC WBL PD WBL PD
Program Buffer to Flash (Confi rm) 1 SA 29
Write-to-Buffer-Abort Reset 3 555 AA 2AA 55 555 F0
Unlock Bypass
Enter 3 555 AA 2AA 55 555 20
Program (14) 2 XXX A0 PA PD
Sector Erase (14) 2 XXX 80 SA 30
Chip Erase (14) 2 XXX 80 XXX 10
Reset (15) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend/Program Suspend (16) 1 XXX B0
Erase Resume/Program Resume (17) 1 XXX 30
Secured Silicon Sector Entry 3 555 AA 2AA 55 555 88
Secured SIlicon Sector Exit (18) 4 555 AA 2AA 55 555 90 XX 00
Legend
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling
edge of the WE# or CE# pulse, whichever happens later.
Notes
1. See Table 7.1 for description of bus operations.
2. All values are in hexadecimal.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
5. Address bits AMAX:A16 are don’t cares for unlock and command cycles, unless SA
or PA required. (AMAX is the Highest Address pin.).
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the
autoselect mode, or if DQ5 goes high (while the device is providing status data).
8. See Table 7.2 for device ID values and defi nitions.
9. The fourth, fi fth, and sixth cycles of the autoselect command sequence are read
cycles.
10. The data is 00h for an unprotected sector and 01h for a protected sector. See
Autoselect for more information. This is same as PPB Status Read except that the
protect and unprotect statuses are inverted here.
11. The data value for DQ7 is “1” for a serialized, protected Secured Silicon Sector region
and “0” for an unserialized, unprotected region. See data and defi nitions.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or
CE# pulse, whichever happens fi rst.
SA = Address of the sector to be verifi ed (in autoselect mode) or erased. Address bits
Amax–A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as
PA.
WC = Word Count is the number of write buffer locations to load minus 1.
12. Command is valid when device is ready to read array data or when device is in
autoselect mode.
13. Command sequence returns device to reading array after being placed in a Write-to-
Buffer-Abort state. Full command sequence is required if resetting out of abort while
in Unlock Bypass mode.
14. The Unlock-Bypass command is required prior to the Unlock-Bypass- Program
command.
15. The Unlock-Bypass-Reset command is required to return to reading array data when
the device is in the unlock bypass mode.
16. The system can read and program/program suspend in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
17. The Erase Resume/Program Resume command is valid only during the Erase
Suspend/Program Suspend modes.
18. The Exit command returns the device to reading the array.
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TABLE 39 SECTOR PROTECTION COMMAND DEFINITIONS
Command
Cycles
Bus Cycles (Note 1-5)
First Second Third Fouth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Lock Register
Command Set Entry 3 555 AA 2AA 55 555
Program (6) 2 XXX A0 XXX DATA
Read (6) 1 00 RD
Command Set Exit (7, 8) 2 XXX 90 XXX 00
Password
Command Set Entry 3 555 AA 2AA 55 555
Password Program (9) 2 XXX A0 PWAx PWDx
Password Read (10) 4 00 PWD0 01 PWD 1 02 PWD 2 03 PWD 3
Password Unlock (10) 7 00 25 00 03 00 PWD 0 01 PWD 1 02 PWD 2 03 PWD 3
00 29
Command Set Exit (7, 8) 2 XXX 90 XXX 00
Global Non-Volatile
PPB Command Set Entry 3 555 AA 2AA 55 555
PPB Program (11, 12) 2 XXX A0 SA 00
All PPB Erase (13) 2 XXX 80 00 30
PPB Status Read (12) 1 SA RD (0)
PPB Command Set Exit (7, 8) 2 XXX 90 XXX 00
Global Volatile
Freeze
PPB Lock Cammand Set Entry 3 555 AA 2AA 55 555
PPB Lock Set (12) 2 XXX A0 XXX 00
PPB Lock Command Set Exit (7, 8) 1 XXX RD (0)
PPB Lock Command Set Exit (7, 8) 2 XXX 90 XXX 00
Volatile
DYB Command Set Entry 3 555 AA 2AA 55 555
DYB Set (11, 12) 2 XXX A0 SA 00
DYB Clear (12) 2 XXX A0 SA 01
DYB Status Read (12) 1 SA RD (0)
DYB Command Set Exit (7, 8) 2 XXX 90 XXX 00
Legend
X = Don’t care
RD(0) = Read data.
SA = Sector Address. Address bits Amax–A16 uniquely select any sector.
Notes
1. See Table 7.1 for description of bus operations.
2. All values are in hexadecimal.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
5. Address bits AMAX:A16 are don’t cares for unlock and command cycles, unless SA
or PA required. (AMAX is the Highest Address pin.)
6. All Lock Register bits are one-time programmable. Program state = “0” and the erase
state = “1.” The Persistent Protection Mode Lock Bit and the Password Protection
Mode Lock Bit cannot be programmed at the same time or the Lock Register Bits
Program operation aborts and returns the device to read mode. Lock Register bits
that are reserved for future use default to “1’s.” The Lock Register is shipped out as
PWD = Password
PWDx = Password word0, word1, word2, and word3.
Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit,
PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode Lock Bit.
“FFFF’s” before Lock Register Bit program execution.
7. The Exit command returns the device to reading the array.
8. If any Command Set Entry command was written, an Exit command must be issued
to reset the device into read mode.
9. For PWDx, only one portion of the password can be programmed per each “A0”
command.
10. Note that the password portion can be entered or read in any order as long as the
entire 64-bit password is entered or read.
11. If ACC = VHH, sector protection matches when ACC = VIH.
12. Protected State = “00h,” Unprotected State = “01h.”
13. The All PPB Erase command embeds programming of all PPB bits before erasure.
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Program Command:
Address 555h, Data A0h
Program Data to Address:
PA, PD
Unlock Cycle 1
Unlock Cycle 2
Setup Command
Program Address (PA),
Program Data (PD)
FAIL. Issue reset command
to return to read array mode.
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Ye s
Ye s
No
No
Polling Status
= Busy?
Polling Status
= Done?
Error condition
(Exceeded Timing Limits)
PASS. Device is in
read mode.
FIG: 4 SINGLE WORD PROGRAM
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Issue
Write Buffer Load Command:
Address SA, Data 25h
Load Word Count to Program
Program Data to Address:
SA, wc
Unlock Cycle 1
Unlock Cycle 2
wc = number of words – 1
Ye s
Ye s
Ye s
Ye s
Ye s
No
No
No
No
No
wc = 0?
Write Buffer
Abort Desired?
Write Buffer
Abort?
Polling Status
= Done?
Error?
FAIL. Issue reset command
to return to read array mode.
Write to a Different
Sector Address to Cause
Write Buffer Abort
PASS. Device is in
read mode.
Confirm command:
SA = 0x29h
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Write Next Word,
Decrement wc:
wc = wc – 1
RESET. Issue Write Buffer
Abort Reset Command
FIG: 5 SINGLE WORD PROGRAM
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No
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Write Additional
Sector Addresses
FAIL. Write reset command
to return to reading array.
PASS. Device returns
to reading array.
Perform Write Operation
Status Algorithm
Select
Additional
Sectors?
Unlock Cycle 1
Unlock Cycle 2
Ye s
Ye s
Ye s
Ye s
Ye s
No
No
No
No
Last Sector
Selected?
Done?
DQ5 = 1?
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Error condition (Exceeded Timing Limits)
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Poll DQ3.
DQ3 = 1?
• Each additional cycle must be written within t
SEA
timeout
• The host system may monitor DQ3 or wait t
SEA
to ensure
acceptance of erase commands
• No limit on number of sectors
• Commands other than Erase Suspend or selecting additional
sectors for erasure during timeout reset device to reading array
data
FIG: 6 SECTOR ERASE OPERATION
Notes
1. See table 12.1 on page 69 for earse command sequence.
2. See DQ3: Sector Erase Timeout State Indicator on page 39 for information on the sector erase timeout.
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Read_1
Read_2
Read_3
DQ6 Toggles between
Read_1 & Read_2
and
Read_2 & Read_3
WriteBuffer
program and
Read_1 DQ1 is
set
Read_1 DQ5 is
set
YES
NO
RETURN
WRITE ABORT
YES
YES RETURN
TIME OUT
NO
NO Read_1
Read_2
DQ2 Toggles NO
YES
RETURN
DONE
RETURN
SUSPEND
START
- DQ 6 toggles when programming
- DQ 6 and DQ 2 toggle when erasing
- DQ 2 toggles when erase suspend
- DQ 1 set when program error
- DQ 5 set when time out
FIG: 7 SECTOR ERASE OPERATION
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FIG: 8 SECTOR ERASE OPERATION
sdohteM erawtfoSsdohteM erawdraH
WP#/ACC = V
IL
(Highest or Lowest
Sector Locked)
Password Method
(DQ2)
Persistent Method
(DQ1)
Lock Register
(One Time Programmable)
PPB Lock Bit
1,2,3
64-bit Password
(One Time Protect)
1 = PPBs Unlocked
0 = PPBs Locked
Memory Array
Sector 0
Sector 1
Sector 2
Sector N-2
Sector N-1
Sector N
3
PPB 0
PPB 1
PPB 2
PPB N-2
PPB N-1
PPB N
Persistent
Protection Bit
(PPB)4,5
DYB 0
DYB 1
DYB 2
DYB N-2
DYB N-1
DYB N
Dynamic
Protection Bit
(DYB)6,7,8
6. 0 = Sector Protected,
1 = Sector Unprotected.
7. Protect effective only if PPB Lock Bit is
unlocked and corresponding PPB is “1”
(unprotected).
8. Volatile Bits: defaults to user choice upon
power-up (see ordering options).
4. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
1. Bit is volatile, and defaults to “1” on reset.
2. Programming to “0” locks all PPBs to their
current state.
3. Once programmed to “0”, requires hardware
reset to unlock.
3. N = Highest Address Sector.
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FIG: 9 PPB PROGRAM ALGORITHM
Read Byte Twice
Addr = SA0
Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
DQ5 = 1?
Ye s
Ye s
Ye s
No
No
No
Ye s
DQ6 =
Toggle?
DQ6 =
Toggle?
Read Byte.
Addr = SA
PASS
FAIL
Issue Reset
Command
Exit PPB
Command Set
DQ0 =
'0' (Pgm.)?
Read Byte Twice
Addr = SA0
No
Wait 500 µs
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FIG: 10 LOCK REGISTER PROGRAM ALGORITHM
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write
Enter Lock Register Command:
Address 555h, Data 40h
Program Lock Register Data
Address XXXh, Data A0h
Address XXXh*, Data PD
Unlock Cycle 1
Unlock Cycle 2
XXXh = Address don’t care
Program Data (PD): See text for Lock Register definitions
Caution: Lock register can only be progammed once.
PASS. Write Lock Register
Exit Command:
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Ye s
Ye s
No
No
Done?
DQ5 = 1? Error condition (Exceeded Timing Limits)
FAIL. Write rest command
to return to reading array.
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FIG: 11 LOCK REGISTER PROGRAM ALGORITHM
FIG: 12 LOCK REGISTER PROGRAM ALGORITHM
20 ns
20 n s
+0 .8 V
–0 .5 V
20 ns
–2 .0 V
20 ns
20 ns
20 ns
VCC
+2.0 V
+2.0 V
VCC
+0.5 V
Current Source
Current Source
I
OL
I
OH
D.U. T.
C= 50 pf
EF F
V~ 1.5v
(Bipolar Supply)
Z
AC TEST CIRCUIT
FIG. 13 AC TEST CIRCUIT
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A
ddresses Addresses Stabl e
t
RC
t
ACC
t
OE
t
OEH
t
CE
t
DF
t
OH
High Z
High Z
t
RH
CS #
OE #
WE #
Outputs
RESET#
R Y/BY#
Output Va lid
OV
tCEH
A
22-A3
A2-A0
Data
CS#
OE#
Aa Ab Ac Ad
Qa Qb Qc
Qd
Same Page
t
AC C
t
PA C C t
PA C C t
PA C C
FIG 14: AC WAVEFORMS FOR READ OPERATIONS
FIG 15: PAGE READ OPERATION TIMINGS
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RESET#
R Y/BY#
R Y/BY#
t
RP
t
Ready
t
Ready
CS#, OE#
t
RH
CS#, OE#
RESET#
t
RP
t
RB
FIG. 16: RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS
FIG. 17: RESET TIMINGS DURING EMBEDDED ALGORITHMS
FIG. 18: POWER-UP SEQUENCE TIMINGS
V
CC
min
V
CC
V
IO
minV
IO
CE#
RESET#
tRH
tVIOS
tVCS
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OE#
WE#
CS#
V
Data
CC
A
ddresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status D
OUT
Program Command Sequence (last tw o cycles)
R Y/BY#
t
RB
t
BUSY
t
CH
PA
FIG. 19: PROGRAM OPERATION
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. DOUT is the output of the data written to the device.
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FIG 20: ACCELERATED PROGRAM TIMING DIAGRAM
WP#/ACC
t
VHH
V
HH
Vo rV
IL IH Vo rV
IL IH
t
VHH
FIG 21: CHIP/SECTOR ERASE OPERATION TIMINGS
OE#
WE#
CS#
V
Data
CC
A
ddresses
t
DS
t
AH
t
DH
t
WP
30h
t
WHWH2
t
WC t
AS
t
WPH
t
VCS
2AAh SA VA
Read Status Data (last two cycles)
55h
t
CS
Status DOUT
Program Command Sequence (last tw o cycles)
R Y/BY#
t
RB
t
BUSY
t
CH
VA
10 for Chip Erase
555h for
chip erase
Notes:
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "write operation status")
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FIG 22: DATA# POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)
WE #
CS #
OE #
High Z
t
OE
High Z
DQ 7
DQ6–DQ0
R Y/BY#
t
BUSY
Complement Tr ue
A
ddresses VA
t
OEH
t
CS
t
CH
t
OH
t
DF
VA VA
Status Dat a
Complement
Status Dat a Tr ue
Va lid Dat a
Va lid Dat a
t
ACC
t
RC
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FIG 24: DQ2 VS. DQ6
FIG 23: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
OE#
CS#
WE #
A
ddresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Va lid Data
(first read) (second read) (stops toggling)
t
CSPH
t
AHT
t
AS
DQ6/DQ2 Va lid Data
V alid
Status
V alid
Status
V alid
Status
R Y/BY#
Enter
Erase
Erase
Erase
Enter Er ase
Susp end Pr ogr am
Era se Su spe nd
Read Era se Sus pe nd
Read
Erase
WE #
DQ 6
DQ 2
Era se
Co mplete
Era se
Su spend
Sus pe nd
Pro gram
Res ume
Em bedd ed
Era sing
NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CS# to toggle DQ2 and DQ6.
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NOTES:
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
FIG 25: SECTOR/SECTOR BLOCK PROTECT AND UNPROTECT TIMING DIAGRAM
Sector Group Protect: 150 μs
Sector Group Unprote ct :1 5m
s
1μ s
R ESET #
SA, A6 ,
A1 ,A 0
Da ta
CS #
WE #
OE #
60 h 6 0h 40 h
Va lid * V a lid * Va lid *
Stat us
Sector Group Protect/Unprote ct Ve ri fy
V
ID
V
IH
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FIG 26: ALTERNATE CS# CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS
t
GHEL
t
OE#
WS
CS#
WE#
RESET#
t
Data
DS
t
A
ddresses
AH
t
DH
t
CP
DQ7 #D
OUT
t
WC t
AS
t
CPH
PA
Data# Polling
A0 fo rp rogram
55 fo re rase
t
RH
t
WHWH1 or 2
R Y/BY#
t
WH
PD fo rp rogram
30 for sector er ase
10 for chi pe rase
555 fo rp rogram
2AA fo re rase
PA fo rp rogram
SA for sector er ase
555 for chi pe rase
t
BUSY
NOTES:
1. FIG: Indicated last two bus cycles of a program or erase operation.
2. PA = program address. SA = sector address, PD = program data.
3. DQ7 is the complement of the data written to the device. DOUT is the data written to the device.
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PACKAGE: 159 PBGA (PLASTIC BALL GRID ARRAY)
987654321
10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
22.15 (0.872) MAX
19.05 (0.750) NO
M
1.27 (0.050) NO
M
1.27 (0.050) NOM
1 1.43 (0.450) NOM
13.15 (0.518) MAX
0.61 (0.024) NOM
2.34 (0.092) MAX
15 9XØ 0.762 (0.030) NOM
BOTTOM VIEW
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
W 7 8M64 VP XXX SB X
White Electronic Designs Corp.
Flash:
Organization, 8M x 64:
User confi gurable as 2 x 8M x 32, or 4 x 8M x16
3.3V Power Supply:
Access Time (ns):
110 = 110ns
120 = 120ns
Package Type:
SB = 159 PBGA, 13mm x 22mm
Devise Grade:
M = Military -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
.
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Document Title
8Mx64 Flash 3.3V Page Mode Multi-Chip Package
Revision History
Rev # History Release Date Status
Rev 0 Initial Release June 2008 Advanced
Rev 1 Change (Pg. All)
1.1 Add detail to DC, AC and programming sections
July 2008 Advanced
Rev 2 Change (Pg. 1, 3, 25, 27, 47)
2.1 Removed 90 and 100ns access times
2.2 Added 110ns access time
October 2008 Advanced
