MC74AC175, MC74ACT175 Quad D Flip-Flop With Master Reset The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops, when MR is low. The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flip-flop's output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and Master Reset are common to all storage elements. * Outputs Source/Sink 24 mA * ACT175 Has TTL Compatible Inputs VCC 16 Q3 15 Q3 14 D3 D2 13 12 Q2 11 http://onsemi.com DIP-16 N SUFFIX CASE 648 16 1 16 1 16 Q2 10 1 CP SO-16 D SUFFIX CASE 751B TSSOP-16 DT SUFFIX CASE 948F 9 EIAJ-16 M SUFFIX CASE 966 16 1 1 2 3 4 5 6 7 MR Q0 Q0 D0 D1 Q1 Q1 8 GND ORDERING INFORMATION Device Figure 1. Pinout: 16-Lead Packages (Top View) PIN ASSIGNMENT PIN FUNCTION D0 - D3 Data Inputs CP Clock Pulse Input MR Master Reset Input Q0 - Q3 Outputs Q0 - Q3 Outputs Package Shipping MC74AC175N PDIP-16 25 Units/Rail MC74ACT175N PDIP-16 25 Units/Rail MC74AC175D SOIC-16 48 Units/Rail MC74ACT175D SOIC-16 48 Units/Rail MC74AC175DR2 SOIC-16 2500 Tape & Reel MC74ACT175DR2 SOIC-16 2500 Tape & Reel MC74AC175DT TSSOP-16 96 Units/Rail MC74ACT175DT TSSOP-16 96 Units/Rail MC74AC175DTR2 TSSOP-16 2500 Tape & Reel MC74ACT175DTR2 TSSOP-16 2500 Tape & Reel MC74AC175M EIAJ-16 50 Units/Rail DEVICE MARKING INFORMATION See general marking information in the device marking section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 2001 May, 2001 - Rev. 5 1 Publication Order Number: MC74AC175/D MC74AC175, MC74ACT175 TRUTH TABLE Inputs MR Outputs CP L H H H D X X H L X L NOTE: Qn D0 D1 D2 D3 MR Q0 Q0 Q1 Q1 Qn L H L Qn CP H L H Qn Q2 Q2 Q3 Q3 D Q H = HIGH Voltage Level, L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition of Clock Figure 2. Logic Symbol MR CP D3 D2 D Q D1 D CP Q CD Q NOTE: D CP Q CD Q3 Q3 D0 Q CP Q CD Q2 Q2 CP Q CD Q1 Q1 Q0 Q0 This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC + 0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC + 0.5 V IIN DC Input Current, per Pin 20 mA IOUT DC Output Sink/Source Current, per Pin 50 mA ICC DC VCC or GND Current per Output Pin 50 mA Tstg Storage Temperature -65 to +150 C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. http://onsemi.com 2 MC74AC175, MC74ACT175 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND) tr, tf IInput Rise Ri and d Fall F ll Time Ti (Note (N 1)) AC Devices except Schmitt Inputs Min Typ Min Unit AC 2.0 5.0 6.0 ACT 4.5 5.0 5.5 0 - VCC VCC @ 3.0 V - 150 - VCC @ 4.5 V - 40 - VCC @ 5.5 V - 25 - VCC @ 4.5 V - 10 - VCC @ 5.5 V - 8.0 - - - 140 C -40 25 85 C V V ns/V tr, tf In ut Rise and Fall Time (Note 2) Input ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH Output Current - HIGH - - -24 mA IOL Output Current - LOW - - 24 mA ns/V 1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25C TA = -40C to +85C Typ VIH VIL VOH VOL Conditions Guaranteed Limits Minimum High g Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC - 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC - 0.1 V Minimum High g Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 3.0 4.5 5.5 - - - 2.56 3.86 4.86 2.46 3.76 4.76 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 - - - 0.36 0.36 0.36 0.44 0.44 0.44 55 5.5 - 0 1 0.1 5.5 - 5.5 - Maximum Low Level Output Voltage IIN Maximum Input Leakage Current IOLD Minimum Dynamic O t t Current Output C t IOHD Unit V *VIN = VIL or VIH - 12 mA IOH - 24 mA - 24 mA IOUT = 50 A V V *VIN = VIL or VIH 12 mA IOH 24 mA 24 mA 1 0 1.0 A VI = VCC, GND - 75 mA VOLD = 1.65 V Max - -75 mA VOHD = 3.85 V Min *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. http://onsemi.com 3 IOUT = - 50 A MC74AC175, MC74ACT175 DC CHARACTERISTICS (continued) Symbol Parameter VCC (V) 74AC 74AC TA = +25C TA = -40C to +85C Typ ICC Maximum Q Quiescent Supply Current 55 5.5 - Unit Conditions Guaranteed Limits 80 8.0 VIN = VCC or GND A 80 *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. AC CHARACTERISTICS Symbol VCC* (V) Parameter 74AC 74AC TA = +25C CL = 50 pF TA = -40C to +85C CL = 50 pF Min Typ Max Min Max Unit Fig. No. fmax Maximum Clock Frequency 3.3 5.0 149 187 - - - - 139 187 - - MHz 3-3 tPLH Propagation g Delayy CP to Qn or Qn 3.3 5.0 2.0 1.5 - - 12.0 9.0 2.0 1.0 13.5 9.5 ns 3-6 tPHL Propagation g Delayy CP to Qn or Qn 3.3 5.0 2.5 1.5 - - 13.0 9.5 2.0 1.5 14.5 10.5 ns 3-6 tPLH Propagation g Delayy MR to Qn 3.3 5.0 3.0 2.0 - - 12.5 9.0 2.5 1.5 13.5 10.0 ns 3-6 tPHL Propagation g Delayy MR to Qn 3.3 5.0 3.0 2.0 - - 11.0 8.5 2.5 1.5 12.5 9.0 ns 3-6 Unit Fig. No. AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter Typ 74AC 74AC TA = +25C CL = 50 pF TA = -40C to +85C CL = 50 pF Guaranteed Minimum ts Set-up Time, HIGH or LOW Dn to CP 3.3 5.0 - - 4.5 3.0 4.5 3.0 ns 3-9 th Hold Time, HIGH or LOW Dn to CP 3.3 5.0 - - 1.0 1.0 1.0 1.0 ns 3-9 MR Pulse Width Low 3.3 5.0 - - 4.5 3.5 4.5 3.5 ns 3-6 CP Pulse Width 3.3 5.0 - - 4.5 3.5 5.0 3.5 ns 3-6 Recovery TIme MR to CP 3.3 5.0 - - 0 0 0 0 ns 3-6 tw tw trec *Voltage Range 3.3 V is 3.3 V 0.3 V. *Voltage Range 5.0 V is 5.0 V 0.5 V. http://onsemi.com 4 MC74AC175, MC74ACT175 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25C TA = -40C to +85C Typ Guaranteed Limits Unit Conditions VIH Minimum High g Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC - 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC - 0.1 V VOH Minimum High g Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 4.5 5.5 - - 3.86 4.86 3.76 4.76 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 4.5 5.5 - - 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOH 24 mA VOL Maximum Low Level Output Voltage IOUT = - 50 A *VIN = VIL or VIH - 24 mA IOH - 24 mA V IOUT = 50 A V IIN Maximum Input Leakage Current 55 5.5 - 0 1 0.1 1 0 1.0 A VI = VCC, GND ICCT Additional Max. ICC/Input 5.5 0.6 - 1.5 mA VI = VCC - 2.1 V IOLD Minimum Dynamic O t t Current Output C t 5.5 - - 75 mA VOLD = 1.65 V Max 5.5 - - -75 mA VOHD = 3.85 V Min 55 5.5 - 80 8.0 80 A VIN = VCC or GND IOHD ICC Maximum Q Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS Symbol VCC* (V) Parameter 74ACT 74ACT TA = +25C CL = 50 pF TA = -40C to +85C CL = 50 pF Min Typ Max Min Max Unit Fig. No. fmax Maximum Clock Frequency 50 5.0 175 - - 145 - MHz 3-3 tPLH Pro agation Delay Propagation CP to Qn 50 5.0 20 2.0 - 10 0 10.0 15 1.5 11 0 11.0 ns 3-6 tPHL Pro agation Delay Propagation CP to Qn 50 5.0 20 2.0 - 11 0 11.0 15 1.5 12 0 12.0 ns 3-6 tPHL Pro agation Delay Propagation MR to Qn or Qn 50 5.0 20 2.0 - 95 9.5 15 1.5 10 5 10.5 ns 3-6 *Voltage Range 5.0 V is 5.0 V 0.5 V. http://onsemi.com 5 MC74AC175, MC74ACT175 AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter 74ACT 74ACT TA = +25C CL = 50 pF TA = -40C to +85C CL = 50 pF Typ ts (H) Set-up Time, HIGH or LOW (L) Dn to CP Hold Time, HIGH or LOW Dn to CP th MR Pulse Width, LOW tw Unit Fig. No. Guaranteed Minimum 50 5.0 - 2.0 2.5 2.0 2.5 ns 3-9 50 5.0 - 10 1.0 10 1.0 ns 3-9 50 5.0 - 30 3.0 40 4.0 ns 3-6 tw CP Pulse Width, HIGH or LOW 50 5.0 - 30 3.0 35 3.5 ns 3-6 trec Recovery TIme MR to CP 50 5.0 - 0 0 ns 3-6 *Voltage Range 5.0 V is 5.0 V 0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 45.0 pF VCC = 5.0 V MARKING DIAGRAMS DIP-16 SO-16 MC74AC175N AWLYYWW AC175 AWLYWW MC74ACT175N AWLYYWW ACT175 AWLYWW A WL, L YY, Y WW, W TSSOP-16 EIAJ-16 AC 175 ALYW 74AC175 ALYW ACT 175 ALYW = Assembly Location = Wafer Lot = Year = Work Week http://onsemi.com 6 MC74AC175, MC74ACT175 PACKAGE DIMENSIONS PDIP-16 N SUFFIX 16 PIN PLASTIC DIP PACKAGE CASE 648-08 ISSUE R -A- 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C DIM A B C D F G H J K L M S L S SEATING PLANE -T- K H D M J G 16 PL 0.25 (0.010) M T A M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 SO-16 D SUFFIX 16 PIN PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MC74AC175, MC74ACT175 PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX 16 PIN PLASTIC TSSOP PACKAGE CASE948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K EEE CCC CCC EEE K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A -V- M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE DETAIL E H D LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A 0.13 (0.005) c A1 b M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 G EIAJ-16 M SUFFIX 16 PIN PLASTIC EIAJ PACKAGE CASE966-01 ISSUE O 16 DIM A B C D F G H J J1 K K1 L M 0.10 (0.004) http://onsemi.com 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 0 10 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 0 10 0.028 0.035 --0.031 MC74AC175, MC74ACT175 Notes http://onsemi.com 9 MC74AC175, MC74ACT175 Notes http://onsemi.com 10 MC74AC175, MC74ACT175 Notes http://onsemi.com 11 MC74AC175, MC74ACT175 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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