ANALOG Complete 12-Bit, 1.25 MSPS DEVICES Monolithic A/D Converter AD1671 REV.B 1.1 Scope. This specification covers the detail requirements for a complete monolithic 12-bit, 1.25 Msps A/D con- verter with an on-chip, high performance sample-and-hold amplifier (SHA) and voltage reference. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number -| AD1671SQ/883B 1.2.3 Case Outline. See outline dimension drawing for package outline: Package Description Q-28 28-Pin Cerdip 1.3 Absolute Maximum Ratings. (T, = +25C unless otherwise noted) Veco t0 ACOM 20k ccc ee eee een nee eee eeee -0.5 V to +6.5V Veg tO ACOM 2. ee eee tee eee ene nee eneee -6.5 V to +0.5 V Viogic t0 DCOM oo ce eee een e ener neee -0.5 V to +6.5 V ACOM to DCOM ... 1... te teen nee eee ne nannes -1Vw+l1Vv Voc to Viogic whe me ee we we ee eee we ee ee ree er ee eee ae 6.5 V to +6.5 Vv ENCODE to DCOM .... 2.2... eens 0.5 V to Veogic + 0.5 V REF IN, BPO/UPO to ACOM ... 1... ce eens 0.5 V to Voc +: 0.5 V AIN to ACOM 2... ee teen nee ene e en ee ee nees -11Vw+4llV Power Dissipation ... 0.2... ee ee ete ene eee eee bneeene 1000 mW Storage Temperature Range ...........0 0 cee ec ee teens 65C to +150C Lead Temperature (Soldering 10 sec)... eee ete tenes + 300C 1.5 Thermal Characteristics. Thermal Resistance 0), = 35C/W 854 = 120C/W ANALOG-TO-DIGITAL CONVERTERS 6-71 ANALOG-TO-DIGITAL CONVERTERS a AD1671SPECIFICATIONS Table 1. Design Sub Sub Limit Group | Group Test Symbol | Device | @ +25C | 1 2,3 Test Condition Units Resolution RES 1 12 12 12 Bits Integral Nonlinearity INL 1 2.5 2.5 3 All Codes Histogram +LSB Differential Nonlinearity DNL 1 ll ll 11 All Codes Histogram Bits Unipolar Offset Error Voss 1 9 9 2.5 V, 5 V Span +LSB Unipolar Offset Drift TCyos | 1 25 2.5 V, 5 V Span +ppm/C Gain Error Ag 1 0.37 0.37 Unipolar & Bipolar % FSR Gain Drift TC, 1 40 Unipolar & Bipolar +ppm/C Bipolar Zero Error Bpor 1 10 10 2.5 V, 5 V Span +LSB Bipolar Zero Drift TCypo 1 30 2.5 V, 5 V Span +ppm/C Analog Input Ranges Vin 1 2.5 2.5 2.5 Unipolar Mode Volts 5 5 5 2.5 2.5 2.5 Bipolar Mode + Volts 5 5 5 Input Resistance Run2.s 1 10 2.5 V Range MO Runs 10 5 V Range ka Input Capacitance Cw 1 10 pF Reference Voltage Vero 1 2.5 Unipolar & Bipolar v Reference Error Vror 1 25 Unipolar & Bipolar +mV Reference Drift TCyro | 1 30 Unipolar & Bipolar +ppm/C Reference Current TREF 1 2.5 Unipolar Mode mA 1 Bipolar Mode mA Power Dissipation Pp 1 750 750 750 Vec: Vez = 5.25 V mW Power Supply Current Tec 1 68 68 68 Tested Under +mA max len I 68 68 68 Static Conditions mA max Ipp 1 5 5 5 +mA max Operating Voltage Range Vee 1 4.75 V min 5.25 V max Ver 1 4.75 -V max 5.25 -V min Vop 1 4.5 V min 5.5 V max PSRR Vee 1 5 5 5 Full-Scale Change Measured | +LSB Ver 5 5 5 Vpp 5 5 5 Input Logic Levels Vi 1 2 2 2 Encode Input V min Vir. 0.8 0.8 0.8 V max Input Logic Currents In 1 10 10 10 + In 10 10 10 Logic Outputs Vou 1 2.4 2.4 2.4 low = 500 pA V min Vo. 0.4 0.4 0.4 lo. = 1.6 mA V max low 500 500 500 pA lo 1.6 1.6 1.6 mA 6-72 ANALOG-TO-DIGITAL CONVERTERS REV. B Design Sub Sub Limit Group | Group Test Symbol Device @ +25C 1 2,3 Test Condition Units Signal-to-Noise Plus Distortion SINAD 1 68 68 68 fin = 100 kHz dB min f, = 1 MHz ~0.5 dB Input Effective Number of Bits ENOB 1 11.0 Bits min Total Harmonic Distortion THD 1 75 75 75 dB max Peak Spurious of Peak Harmonic Component PS 1 77 77 77 dB max Small Signal Bandwidth bW 1 12 MHz Full Power Bandwidth BW 1 2 MHz Intermodulation Distortion > 2nd 1 75 75 75 2nd Order Products dB max = 3rd 1 75 75 75 3rd Order Products ~dB max Design Sub Sub Limit Group | Group Test Symbol Device @ +25C 9 10, 11 Test Condition Units Conversion Time Teonv 1 800 800 800 ns Sample Rate 1 1.25 1.25 1,25 MSPS max Encode Width High (Short Encode) tenc 1 20 20 20 ns min 50 50 50 ns max Encode Width Low (Long Encode) tencL 1 20 20 20 ps min DAV Pulse Width toav 1 150 150 150 ns min 300 300 300 ns max Encode Falling Edge Delay te 1 0 ns min Start New Conversion Delay tR 1 0 ns min Data and OTR Delay from top 1 20 ns min DAV Falling Edge Data and OTR Delay from tgs 1 20 ns min DAV Rising Edge 3.2.1 Functional Block Diagram and Terminal Assignments. out BPOMPO ENCODE Veg ACOM Vag Yicaic pou Vee fl . J wal vec BIT 12 (LSB) [2] 37] ACOM BIT 11 GB] 26] BPO/UPO BIT 10 fe] 25 | SHA OUT COARSE 8-8IT fens [+4 warn BITS [5 24| REF IN | 1 Bre | 6 2a] AINT ior ar7|7] AD671 za] AIN2 FLASH TOP VIEW BIT6/8 (Not to Scale) 21 | REF OUT BITS [2| [20] REF COM AD1671 arr [10] [19] ocom ons [i rt one REF COM OTR MSE oBITt-12 DAV BIT2 [ra] 7] ENCODE BIT 1 (MSB) |13 hie} OAV MsB |14 5] OTR REV. B ANALOG-TO-DIGITAL CONVERTERS 6-73 ANALOG-TO-DIGITAL CONVERTERS a AD1671 3.2.4 Microcircuit Technology Group. This circuit is covered by technology group (93). tenc ENCODE encope $k >| toav ~~ DAV DAV ton | tss BIT 1-12 DATA 0 (PREVIOUS| DATA1 MSB, OTR ) R wa om DATA 0 (PREVIOUS) + DATA1 a. Encode Pulse HIGH b, Encode Pulse LOW Figure 1. Timing Diagram 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). o-5v 47uF >" MR-820 4 L_ arr 3 MR-220 = Vee Vee [28-9 0 +5V 0.1,F SI BIT 12(LSB) ACOM BIT 11 BPO/UPO BIT 10 SHA OUT q BIT9 REF IN [24 +o q BITs AINt | 23 q BIT 7 AIN2 | 22 Wy O_ soHz = Bits REFOUT [21 }- 25V PEAK AR 0.1 pF q BITS REF COM |20 | q BIT 4 pcom 1o}-4 O.1nF q BIT 3 Vioaie |18 + BIT2 ENCODE sv tkHz BIT1(MSB) DAV CURR MSB OTR | 1 a Hi ALL RESISTORS 10k2, 1%, 1/4 WATT 6-74 ANALOG-TO-DIGITAL CONVERTERS REV. 8