LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 LMC6492 Dual/LMC6494 Quad CMOS Rail-to-Rail Input and Output Operational Amplifier Check for Samples: LMC6492, LMC6494 FEATURES 1 (Typical Unless Otherwise Noted) 2 * * * * * * * * Rail-to-Rail Input Common-Mode Voltage Range, Ensured Over Temperature Rail-to-Rail Output Swing within 20 mV of Supply Rail, 100 k Load Operates from 5V to 15V Supply Excellent CMRR and PSRR 82 dB Ultra Low Input Current 150 fA High Voltage Gain (RL = 100 k) 120 dB Low Supply Current (@ VS = 5V) 500 A/Amplifier Low Offset Voltage Drift 1.0 V/C APPLICATIONS * * * * * Automotive Transducer Amplifier Pressure Sensor Oxygen Sensor Temperature Sensor Speed Sensor DESCRIPTION The LMC6492/LMC6494 amplifiers were specifically developed for single supply applications that operate from -40C to +125C. This feature is well-suited for automotive systems because of the wide temperature range. A unique design topology enables the LMC6492/LMC6494 common-mode voltage range to accommodate input signals beyond the rails. This eliminates non-linear output errors due to input signals exceeding a traditionally limited commonmode voltage range. The LMC6492/LMC6494 signal range has a high CMRR of 82 dB for excellent accuracy in non-inverting circuit configurations. The LMC6492/LMC6494 rail-to-rail input is complemented by rail-to-rail output swing. This assures maximum dynamic signal range which is particularly important in 5V systems. Ultra-low input current of 150 fA and 120 dB open loop gain provide high accuracy and direct interfacing with high impedance sources. Connection Diagram Figure 1. 8-Pin PDIP/SOIC - Top View Figure 2. 14-Pin PDIP/SOIC - Top View 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) ESD Tolerance (3) 2000V Differential Input Voltage Supply Voltage (V+) + 0.3V, (V-) - 0.3V Voltage at Input/Output Pin - + Supply Voltage (V - V ) 16V Current at Input Pin 5 mA Current at Output Pin (4) 30 mA Current at Power Supply Pin 40 mA Lead Temp. (Soldering, 10 sec.) 260C -65C to +150C Storage Temperature Range Junction Temperature (5) (1) (2) (3) (4) (5) 150C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Human body model, 1.5 k in series with 100 pF. Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature at 150C. Output currents in excess of 30 mA over long term may adversely affect reliability. The maximum power dissipation is a function of TJ(max), JA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/JA. All numbers apply for packages soldered directly into a PC board. Operating Conditions (1) 2.5V V+ 15.5V Supply Voltage Junction Temperature Range Thermal Resistance (JA) (1) LMC6492AE, LMC6492BE -40C TJ +125C LMC6494AE, LMC6494BE -40C TJ +125C P Package, 8-Pin PDIP 108C/W D Package, 8-Pin SOIC 171C/W P Package, 14-Pin PDIP 78C/W D Package, 14-Pin SOIC 118C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. DC Electrical Characteristics Unless otherwise specified, all limits specified for TJ = 25C, V+ = 5V, V- = 0V, VCM = VO = V+/2 and RL > 1 M. Boldface limits apply at the temperature extremes Symbol VOS Parameter Conditions Input Offset Voltage TCVOS Typ (1) 0.11 Input Offset Voltage LMC6492AE LMC6492BE LMC6494AE LMC6494BE Limit (2) Limit (2) 3.0 6.0 mV 3.8 6.8 max Units V/C 1.0 Average Drift IB Input Bias Current See (3) 0.15 200 200 pA max IOS Input Offset Current See (3) 0.075 100 100 pA max RIN Input Resistance (1) (2) (3) 2 Tera >10 Typical Values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. Specified limits are dictated by tester limits and not device performance. Actual performance is reflected in the typical value. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 DC Electrical Characteristics (continued) Unless otherwise specified, all limits specified for TJ = 25C, V+ = 5V, V- = 0V, VCM = VO = V+/2 and RL > 1 M. Boldface limits apply at the temperature extremes Symbol Parameter Typ (1) Conditions LMC6492AE LMC6492BE LMC6494AE LMC6494BE Limit CIN Common-Mode (2) Limit Units (2) 3 pF Input Capacitance CMRR Common-Mode Rejection Ratio 0V VCM 15V 82 -PSRR VCM 63 60 58 65 63 60 58 65 63 dB 60 58 min 82 65 63 dB 60 58 min V- -0.3 -0.25 -0.25 V 0 0 max V+ + 0.25 V+ + 0.25 V V = 15V 0V VCM 5V +PSRR 65 + 82 + Positive Power Supply 5V V 15V, Rejection Ratio VO = 2.5V Negative Power Supply 0V V- -10V, Rejection Ratio VO = 2.5V Input Common-Mode V+ = 5V and 15V Voltage Range For CMRR 50 dB 82 V+ + 0.3 + V AV VO Large Signal Voltage Gain Output Swing RL = 2 k: (4) + V = 5V Sinking 40 min 4.7 RL = 600 to V+/2 0.3 14.7 RL = 2 k to V+/2 0.16 14.1 + RL = 600 to V /2 0.5 ISC ISC (4) (5) min V/mV 0.1 V+ = 15V V 300 4.9 V+ = 15V + Sourcing RL = 2 k to V+/2 V+ = 5V dB min Output Short Circuit Current Sourcing, VO = 0V 25 V+ = 5V Sinking, VO = 5V 22 Output Short Circuit Current Sourcing, VO = 0V 30 V+ = 15V Sinking, VO = 5V (5) 30 4.8 4.8 V 4.7 4.7 min 0.18 0.18 V 0.24 0.24 max 4.5 4.5 V 4.24 4.24 min 0.5 0.5 V 0.65 0.65 max 14.4 14.4 V 14.0 14.0 min 0.35 0.35 V 0.5 0.5 max 13.4 13.4 V 13.0 13.0 min 1.0 1.0 V 1.5 1.5 max 16 16 10 10 11 11 8 8 28 28 20 20 30 30 22 22 mA min V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V VO 11.5V. For Sinking tests, 3.5V VO 7.5V. Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 3 LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com DC Electrical Characteristics (continued) Unless otherwise specified, all limits specified for TJ = 25C, V+ = 5V, V- = 0V, VCM = VO = V+/2 and RL > 1 M. Boldface limits apply at the temperature extremes Symbol Parameter Typ (1) Conditions LMC6492AE LMC6492BE LMC6494AE LMC6494BE Limit IS Supply Current LMC6492 1.0 V+ = +5V, VO = V+/2 LMC6492 + 1.3 + V = +15V, VO = V /2 LMC6494 2.0 V+ = +5V, VO = V+/2 LMC6494 2.6 V+ = +15V, VO = V+/2 (2) Limit Units (2) 1.75 1.75 mA 2.1 2.1 max 1.95 1.95 mA 2.3 2.3 max 3.5 3.5 mA 4.2 4.2 max 3.9 3.9 mA 4.6 4.6 max AC Electrical Characteristics Unless otherwise specified, all limits specified for TJ = 25C, V+ = 5V, V- = 0V, VCM = VO = V+/2 and RL > 1 M. Boldface limits apply at the temperature extremes Symbol Parameter Conditions Typ (1) LMC6492AE LMC6492BE LMC6494AE LMC6494BE Limit (2) Limit (2) 0.7 0.7 0.5 0.5 Units SR Slew Rate See (3) 1.3 GBW Gain-Bandwidth Product V+ = 15V 1.5 MHz m Phase Margin 50 Deg Gm Gain Margin 15 dB Amp-to-Amp Isolation See (4) 150 dB Input-Referred F = 1 kHz 37 Voltage Noise VCM = 1V Input-Referred F = 1 kHz 0.06 F = 1 kHz, AV = -2 0.01 en in nV/HZ pA/HZ Current Noise T.H.D. Total Harmonic Distortion Vs min RL = 10 k, VO = -4.1 VPP F = 10 kHz, AV = -2 RL = 10 k, VO = 8.5 VPP % 0.01 V+ = 10V (1) (2) (3) (4) 4 Typical Values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. V+ = 15V. Connected as voltage follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Input referred, V+ = 15V and RL = 100 k connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 Typical Performance Characteristics VS = +15V, Single Supply, TA = 25C unless otherwise specified Supply Current vs Supply Voltage Input Current vs Temperature Figure 3. Figure 4. Sourcing Current vs Output Voltage Sourcing Current vs Output Voltage Figure 5. Figure 6. Sourcing Current vs Output Voltage Sinking Current vs Output Voltage Figure 7. Figure 8. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 5 LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = +15V, Single Supply, TA = 25C unless otherwise specified 6 Sinking Current vs Output Voltage Sinking Current vs Output Voltage Figure 9. Figure 10. Output Voltage Swing vs Supply Voltage Input Voltage Noise vs Frequency Figure 11. Figure 12. Input Voltage Noise vs Input Voltage Input Voltage Noise vs Input Voltage Figure 13. Figure 14. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = +15V, Single Supply, TA = 25C unless otherwise specified Input Voltage Noise vs Input Voltage Crosstalk Rejection vs Frequency Figure 15. Figure 16. Crosstalk Rejection vs Frequency Positive PSRR vs Frequency Figure 17. Figure 18. Negative PSRR vs Frequency CMRR vs Frequency Figure 19. Figure 20. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 7 LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = +15V, Single Supply, TA = 25C unless otherwise specified 8 CMRR vs Input Voltage CMRR vs Input Voltage Figure 21. Figure 22. CMRR vs Input Voltage VOS vs CMR Figure 23. Figure 24. VOS vs CMR Input Voltage vs Output Voltage Figure 25. Figure 26. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = +15V, Single Supply, TA = 25C unless otherwise specified Input Voltage vs Output Voltage Open Loop Frequency Response Figure 27. Figure 28. Open Loop Frequency Response Open Loop Frequency Response vs Temperature Figure 29. Figure 30. Maximum Output Swing vs Frequency Gain and Phase vs Capacitive Load Figure 31. Figure 32. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 9 LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = +15V, Single Supply, TA = 25C unless otherwise specified 10 Gain and Phase vs Capacitive Load Open Loop Output Impedance vs Frequency Figure 33. Figure 34. Open Loop Output Impedance vs Frequency Slew Rate vs Supply Voltage Figure 35. Figure 36. Non-Inverting Large Signal Pulse Response Non-Inverting Large Signal Pulse Response Figure 37. Figure 38. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = +15V, Single Supply, TA = 25C unless otherwise specified Non-Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 39. Figure 40. Non-Inverting Small Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 41. Figure 42. Inverting Large Signal Pulse Response Inverting Large Signal Pulse Response Figure 43. Figure 44. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 11 LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = +15V, Single Supply, TA = 25C unless otherwise specified 12 Inverting Large Signal Pulse Response Inverting Small Signal Pulse Response Figure 45. Figure 46. Inverting Small Signal Pulse Response Inverting Small Signal Pulse Response Figure 47. Figure 48. Stability vs Capacitive Load Stability vs Capacitive Load Figure 49. Figure 50. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = +15V, Single Supply, TA = 25C unless otherwise specified Stability vs Capacitive Load Stability vs Capacitive Load Figure 51. Figure 52. Stability vs Capacitive Load Stability vs Capacitive Load Figure 53. Figure 54. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 13 LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com APPLICATION HINTS INPUT COMMON-MODE VOLTAGE RANGE Unlike Bi-FET amplifier designs, the LMC6492/4 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage. Figure 55 shows an input voltage exceeding both supplies with no resulting phase inversion on the output. Figure 55. An Input Voltage Signal Exceeds the LMC6492/4 Power Supply Voltages with No Output Phase Inversion The absolute maximum input voltage is 300 mV beyond either supply rail at room temperature. Voltages greatly exceeding this absolute maximum rating, as in Figure 56, can cause excessive current to flow in or out of the input pins possibly affecting reliability. Figure 56. A 7.5V Input Signal Greatly Exceeds the 5V Supply in Figure 57 Causing No Phase Inversion Due to RI 14 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 Applications that exceed this rating must externally limit the maximum input current to 5 mA with an input resistor (RI) as shown in Figure 57. Figure 57. RI Input Current Protection for Voltages Exceeding the Supply Voltages RAIL-TO-RAIL OUTPUT The approximate output resistance of the LMC6492/4 is 110 sourcing and 80 sinking at Vs = 5V. Using the calculated output resistance, maximum output voltage swing can be esitmated as a function of load. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the LMC6492/4. Although the LMC6492/4 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors with even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phase margins. When high input impedances are demanded, guarding of the LMC6492/4 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High Impedance Work). The effect of input capacitance can be compensated for by adding a capacitor, Cf, around the feedback resistors (as in Figure 55 ) such that: (1) or R1 CIN R2 Cf (2) Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and LMC662 for a more detailed discussion on compensating for input capacitance. Figure 58. Cancelling the Effect of Input Capacitance CAPACITIVE LOAD TOLERANCE All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is normally included in this integrator stage. The frequency location of the dominant pole is affected by the resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate resistive load in parallel with the capacitive load (see Typical Curves). Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 15 LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 59. Figure 59. LMC6492/4 Noninverting Amplifier, Compensated to Handle Capacitive Loads PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6492/4, typically 150 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6492/4's inputs and the terminals of components connected to the op-amp's inputs, as in Figure 60. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 33 times degradation from the LMC6492/4's actual performance. If a guard ring is used and held within 5 mV of the inputs, then the same resistance of 1011 will only cause 0.05 pA of leakage current. See Figure 61 for typical connections of guard rings for standard op-amp configurations. Figure 60. Examples of Guard Ring in PC Board Layout 16 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 Inverting Amplifier Non-Inverting Amplifier Follower Figure 61. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 62. (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board). Figure 62. Air Wiring Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 17 LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Application Circuits Where: V0 = V1 + V2 - V3 - V4 (V1 + V2 (V3 + V4) to keep V0 > 0VDC Figure 63. DC Summing Amplifier (VIN 0VDC and VO VDC For (CMRR depends on this resistor ratio match) As shown: VO = 2(V2 - V1) Figure 64. High Input Z, DC Differential Amplifier Figure 65. Photo Voltaic-Cell Amplifier 18 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 If R1 = R5, R3 = R6, and R4 = R7; then AV 100 for circuit shown (R2 = 9.3k). Figure 66. Instrumentation Amplifier Figure 67. Rail-to-Rail Single Supply Low Pass Filter This low-pass filter circuit can be used as an anti-aliasing filter with the same supply as the A/D converter. Filter designs can also take advantage of the LMC6492/4 ultra-low input current. The ultra-low input current yields negligible offset error even when large value resistors are used. This in turn allows the use of smaller valued capacitors which take less board space and cost less. Figure 68. Low Voltage Peak Detector with Rail-to-Rail Peak Capture Range Dielectric absorption and leakage is minimized by using a polystyrene or polypropylene hold capacitor. The droop rate is primarily determined by the value of CH and diode leakage current. Select low-leakage current diodes to minimize drooping. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 19 LMC6492, LMC6494 SNOS724D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Rf = Rx Rf >> R1, R2, R3, and R4 Figure 69. Pressure Sensor In a manifold absolute pressure sensor application, a strain gauge is mounted on the intake manifold in the engine unit. Manifold pressure causes the sensing resistors, R1, R2, R3 and R4 to change. The resistors change in a way such that R2 and R4 increase by the same amount R1 and R3 decrease. This causes a differential voltage between the input of the amplifier. The gain of the amplifier is adjusted by Rf. Spice Macromodel A * * * * * spice macromodel is available for the LMC6492/4. This model includes accurate simulation of: Input common-model voltage range Frequency and transient response GBW dependence on loading conditions Quiescent and dynamic supply current Output swing dependence on loading conditions and many other characteristics as listed on the macromodel disk. Contact your local Texas Instruments sales office to obtain an operational amplifier spice model library disk. 20 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 LMC6492, LMC6494 www.ti.com SNOS724D - AUGUST 2000 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6492 LMC6494 Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMC6492AEM NRND SOIC D 8 95 Non-RoHS & Green Call TI Call TI -40 to 125 LMC64 92AEM LMC6492AEM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC64 92AEM LMC6492AEMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC64 92AEM LMC6492BEM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC64 92BEM LMC6492BEMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC64 92BEM LMC6494AEM NRND SOIC D 14 55 Non-RoHS & Green Call TI Call TI -40 to 125 LMC6494 AEM LMC6494AEM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494 AEM LMC6494AEMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494 AEM LMC6494BEM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494 BEM LMC6494BEMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494 BEM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMC6492AEMX/NOPB SOIC D LMC6492BEMX/NOPB SOIC LMC6494AEMX/NOPB SOIC LMC6494BEMX/NOPB SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 5.4 2.0 8.0 12.0 Q1 8 2500 330.0 12.4 6.5 D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6492AEMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6492BEMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6494AEMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMC6494BEMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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