LMC6492, LMC6494
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LMC6492 Dual/LMC6494 Quad CMOS Rail-to-Rail Input and Output Operational Amplifier
Check for Samples: LMC6492,LMC6494
1FEATURES DESCRIPTION
The LMC6492/LMC6494 amplifiers were specifically
2(Typical Unless Otherwise Noted) developed for single supply applications that operate
• Rail-to-Rail Input Common-Mode Voltage from −40°C to +125°C. This feature is well-suited for
Range, Ensured Over Temperature automotive systems because of the wide temperature
• Rail-to-Rail Output Swing within 20 mV of range. A unique design topology enables the
LMC6492/LMC6494 common-mode voltage range to
Supply Rail, 100 kΩLoad accommodate input signals beyond the rails. This
• Operates from 5V to 15V Supply eliminates non-linear output errors due to input
• Excellent CMRR and PSRR 82 dB signals exceeding a traditionally limited common-
• Ultra Low Input Current 150 fA mode voltage range. The LMC6492/LMC6494 signal
range has a high CMRR of 82 dB for excellent
• High Voltage Gain (RL= 100 kΩ) 120 dB accuracy in non-inverting circuit configurations.
• Low Supply Current (@ VS= 5V) 500 The LMC6492/LMC6494 rail-to-rail input is
μA/Amplifier complemented by rail-to-rail output swing. This
• Low Offset Voltage Drift 1.0 μV/°C assures maximum dynamic signal range which is
particularly important in 5V systems.
APPLICATIONS Ultra-low input current of 150 fA and 120 dB open
• Automotive Transducer Amplifier loop gain provide high accuracy and direct interfacing
• Pressure Sensor with high impedance sources.
• Oxygen Sensor
• Temperature Sensor
• Speed Sensor
Connection Diagram
Figure 1. 8-Pin PDIP/SOIC - Top View Figure 2. 14-Pin PDIP/SOIC - Top View
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMC6492, LMC6494
SNOS724D –AUGUST 2000–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
ESD Tolerance(3) 2000V
Differential Input Voltage ±Supply Voltage
Voltage at Input/Output Pin (V+) + 0.3V, (V−)−0.3V
Supply Voltage (V+−V−) 16V
Current at Input Pin ±5 mA
Current at Output Pin(4) ±30 mA
Current at Power Supply Pin 40 mA
Lead Temp. (Soldering, 10 sec.) 260°C
Storage Temperature Range −65°C to +150°C
Junction Temperature(5) 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Human body model, 1.5 kΩin series with 100 pF.
(4) Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature at 150°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
(5) The maximum power dissipation is a function of TJ(max),θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(max) −TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Operating Conditions(1)
Supply Voltage 2.5V ≤V+≤15.5V
Junction Temperature Range LMC6492AE, LMC6492BE −40°C ≤TJ≤+125°C
LMC6494AE, LMC6494BE −40°C ≤TJ≤+125°C
Thermal Resistance (θJA) P Package, 8-Pin PDIP 108°C/W
D Package, 8-Pin SOIC 171°C/W
P Package, 14-Pin PDIP 78°C/W
D Package, 14-Pin SOIC 118°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
DC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩ.Boldface
limits apply at the temperature extremes LMC6492AE LMC6492BE
Symbol Parameter Conditions Typ(1) LMC6494AE LMC6494BE Units
Limit(2) Limit(2)
VOS Input Offset Voltage 0.11 3.0 6.0 mV
3.8 6.8 max
TCVOS Input Offset Voltage 1.0 μV/°C
Average Drift
IBInput Bias Current See(3) 0.15 200 200 pA max
IOS Input Offset Current See(3) 0.075 100 100 pA max
RIN Input Resistance >10 Tera Ω
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) Specified limits are dictated by tester limits and not device performance. Actual performance is reflected in the typical value.
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DC Electrical Characteristics (continued)
Unless otherwise specified, all limits specified for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩ.Boldface
limits apply at the temperature extremes LMC6492AE LMC6492BE
Symbol Parameter Conditions Typ(1) LMC6494AE LMC6494BE Units
Limit(2) Limit(2)
CIN Common-Mode 3 pF
Input Capacitance
CMRR Common-Mode 0V ≤VCM ≤15V 82 65 63 dB
min
Rejection Ratio V+= 15V 60 58
0V ≤VCM ≤5V 82 65 63
60 58
+PSRR Positive Power Supply 5V ≤V+≤15V, 82 65 63 dB
Rejection Ratio VO= 2.5V 60 58 min
−PSRR Negative Power Supply 0V ≤V−≤ −10V, 82 65 63 dB
Rejection Ratio VO= 2.5V 60 58 min
VCM Input Common-Mode V+= 5V and 15V V−−0.3 −0.25 −0.25 V
Voltage Range For CMRR ≥50 dB 0 0 max
V++ 0.3 V++ 0.25 V++ 0.25 V
V+V+min
AVLarge Signal Voltage Gain RL= 2 kΩ:(4) Sourcing 300 V/mV
Sinking 40 min
VOOutput Swing V+= 5V 4.9 4.8 4.8 V
RL= 2 kΩto V+/2 4.7 4.7 min
0.1 0.18 0.18 V
0.24 0.24 max
V+= 5V 4.7 4.5 4.5 V
RL= 600Ωto V+/2 4.24 4.24 min
0.3 0.5 0.5 V
0.65 0.65 max
V+= 15V 14.7 14.4 14.4 V
RL= 2 kΩto V+/2 14.0 14.0 min
0.16 0.35 0.35 V
0.5 0.5 max
V+= 15V 14.1 13.4 13.4 V
RL= 600Ωto V+/2 13.0 13.0 min
0.5 1.0 1.0 V
1.5 1.5 max
ISC Output Short Circuit Current Sourcing, VO= 0V 25 16 16
10 10
V+= 5V Sinking, VO= 5V 22 11 11
8 8 mA
min
ISC Output Short Circuit Current Sourcing, VO= 0V 30 28 28
20 20
V+= 15V Sinking, VO= 5V(5) 30 30 30
22 22
(4) V+= 15V, VCM = 7.5V and RLconnected to 7.5V. For Sourcing tests, 7.5V ≤VO≤11.5V. For Sinking tests, 3.5V ≤VO≤7.5V.
(5) Do not short circuit output to V+, when V+is greater than 13V or reliability will be adversely affected.
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DC Electrical Characteristics (continued)
Unless otherwise specified, all limits specified for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩ.Boldface
limits apply at the temperature extremes LMC6492AE LMC6492BE
Symbol Parameter Conditions Typ(1) LMC6494AE LMC6494BE Units
Limit(2) Limit(2)
ISSupply Current LMC6492 1.0 1.75 1.75 mA
V+= +5V, VO= V+/2 2.1 2.1 max
LMC6492 1.3 1.95 1.95 mA
V+= +15V, VO= V+/2 2.3 2.3 max
LMC6494 2.0 3.5 3.5 mA
V+= +5V, VO= V+/2 4.2 4.2 max
LMC6494 2.6 3.9 3.9 mA
V+= +15V, VO= V+/2 4.6 4.6 max
AC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩ.Boldface
limits apply at the temperature extremes LMC6492AE LMC6492BE
Symbol Parameter Conditions Typ(1) LMC6494AE LMC6494BE Units
Limit(2) Limit(2)
SR Slew Rate See(3) 1.3 0.7 0.7 Vμs min
0.5 0.5
GBW Gain-Bandwidth Product V+= 15V 1.5 MHz
φmPhase Margin 50 Deg
GmGain Margin 15 dB
Amp-to-Amp Isolation See(4) 150 dB
enInput-Referred F = 1 kHz 37 nV/√HZ
Voltage Noise VCM = 1V
inInput-Referred F = 1 kHz 0.06 pA/√HZ
Current Noise
T.H.D. Total Harmonic Distortion F = 1 kHz, AV=−2 0.01
RL= 10 kΩ, VO=−4.1 VPP
F = 10 kHz, AV=−2 %
RL= 10 kΩ, VO= 8.5 VPP 0.01
V+= 10V
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) V+= 15V. Connected as voltage follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
(4) Input referred, V+= 15V and RL= 100 kΩconnected to 7.5V. Each amp excited in turn with 1 kHz to produce VO= 12 VPP.
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Typical Performance Characteristics
VS= +15V, Single Supply, TA= 25°C unless otherwise specified
Supply Current vs Input Current vs
Supply Voltage Temperature
Figure 3. Figure 4.
Sourcing Current vs Sourcing Current vs
Output Voltage Output Voltage
Figure 5. Figure 6.
Sourcing Current vs Sinking Current vs
Output Voltage Output Voltage
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
VS= +15V, Single Supply, TA= 25°C unless otherwise specified
Sinking Current vs Sinking Current vs
Output Voltage Output Voltage
Figure 9. Figure 10.
Output Voltage Swing vs Input Voltage Noise
Supply Voltage vs Frequency
Figure 11. Figure 12.
Input Voltage Noise Input Voltage Noise
vs Input Voltage vs Input Voltage
Figure 13. Figure 14.
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Typical Performance Characteristics (continued)
VS= +15V, Single Supply, TA= 25°C unless otherwise specified
Input Voltage Noise Crosstalk Rejection
vs Input Voltage vs Frequency
Figure 15. Figure 16.
Crosstalk Rejection Positive PSRR
vs Frequency vs Frequency
Figure 17. Figure 18.
Negative PSRR CMRR vs
vs Frequency Frequency
Figure 19. Figure 20.
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Typical Performance Characteristics (continued)
VS= +15V, Single Supply, TA= 25°C unless otherwise specified
CMRR vs CMRR vs
Input Voltage Input Voltage
Figure 21. Figure 22.
CMRR vs ΔVOS
Input Voltage vs CMR
Figure 23. Figure 24.
ΔVOS Input Voltage vs
vs CMR Output Voltage
Figure 25. Figure 26.
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Typical Performance Characteristics (continued)
VS= +15V, Single Supply, TA= 25°C unless otherwise specified
Input Voltage vs Open Loop
Output Voltage Frequency Response
Figure 27. Figure 28.
Open Loop Open Loop Frequency Response
Frequency Response vs Temperature
Figure 29. Figure 30.
Maximum Output Swing Gain and Phase vs
vs Frequency Capacitive Load
Figure 31. Figure 32.
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Typical Performance Characteristics (continued)
VS= +15V, Single Supply, TA= 25°C unless otherwise specified
Gain and Phase vs Open Loop Output Impedance
Capacitive Load vs Frequency
Figure 33. Figure 34.
Open Loop Output Impedance Slew Rate vs
vs Frequency Supply Voltage
Figure 35. Figure 36.
Non-Inverting Large Non-Inverting Large
Signal Pulse Response Signal Pulse Response
Figure 37. Figure 38.
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Typical Performance Characteristics (continued)
VS= +15V, Single Supply, TA= 25°C unless otherwise specified
Non-Inverting Large Non-Inverting Small
Signal Pulse Response Signal Pulse Response
Figure 39. Figure 40.
Non-Inverting Small Non-Inverting Small
Signal Pulse Response Signal Pulse Response
Figure 41. Figure 42.
Inverting Large Inverting Large Signal
Signal Pulse Response Pulse Response
Figure 43. Figure 44.
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Typical Performance Characteristics (continued)
VS= +15V, Single Supply, TA= 25°C unless otherwise specified
Inverting Large Signal Inverting Small Signal
Pulse Response Pulse Response
Figure 45. Figure 46.
Inverting Small Signal Inverting Small Signal
Pulse Response Pulse Response
Figure 47. Figure 48.
Stability vs Stability vs
Capacitive Load Capacitive Load
Figure 49. Figure 50.
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Typical Performance Characteristics (continued)
VS= +15V, Single Supply, TA= 25°C unless otherwise specified
Stability vs Stability vs
Capacitive Load Capacitive Load
Figure 51. Figure 52.
Stability vs Stability vs
Capacitive Load Capacitive Load
Figure 53. Figure 54.
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APPLICATION HINTS
INPUT COMMON-MODE VOLTAGE RANGE
Unlike Bi-FET amplifier designs, the LMC6492/4 does not exhibit phase inversion when an input voltage exceeds
the negative supply voltage. Figure 55 shows an input voltage exceeding both supplies with no resulting phase
inversion on the output.
Figure 55. An Input Voltage Signal Exceeds the
LMC6492/4 Power Supply Voltages with
No Output Phase Inversion
The absolute maximum input voltage is 300 mV beyond either supply rail at room temperature. Voltages greatly
exceeding this absolute maximum rating, as in Figure 56, can cause excessive current to flow in or out of the
input pins possibly affecting reliability.
Figure 56. A ±7.5V Input Signal Greatly
Exceeds the 5V Supply in Figure 57 Causing
No Phase Inversion Due to RI
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Applications that exceed this rating must externally limit the maximum input current to ±5 mA with an input
resistor (RI) as shown in Figure 57.
Figure 57. RIInput Current Protection for
Voltages Exceeding the Supply Voltages
RAIL-TO-RAIL OUTPUT
The approximate output resistance of the LMC6492/4 is 110Ωsourcing and 80Ωsinking at Vs= 5V. Using the
calculated output resistance, maximum output voltage swing can be esitmated as a function of load.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the
LMC6492/4.
Although the LMC6492/4 is highly stable over a wide range of operating conditions, certain precautions must be
met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors with
even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce
phase margins.
When high input impedances are demanded, guarding of the LMC6492/4 is suggested. Guarding input lines will
not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High
Impedance Work).
The effect of input capacitance can be compensated for by adding a capacitor, Cf, around the feedback resistors
(as in Figure 55 ) such that:
(1)
or R1CIN ≤R2Cf(2)
Since it is often difficult to know the exact value of CIN, Cfcan be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 and LMC662 for a more detailed discussion on compensating
for input capacitance.
Figure 58. Cancelling the Effect of Input Capacitance
CAPACITIVE LOAD TOLERANCE
All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor
is normally included in this integrator stage. The frequency location of the dominant pole is affected by the
resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate
resistive load in parallel with the capacitive load (see Typical Curves).
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Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created
by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the
unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.
With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 59.
Figure 59. LMC6492/4 Noninverting Amplifier, Compensated to Handle Capacitive Loads
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6492/4, typically 150 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining
low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though
it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination,
the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6492/4's
inputs and the terminals of components connected to the op-amp's inputs, as in Figure 60. To have a significant
effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be
connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow
between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is
normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the
input.
This would cause a 33 times degradation from the LMC6492/4's actual performance. If a guard ring is used and
held within 5 mV of the inputs, then the same resistance of 1011Ωwill only cause 0.05 pA of leakage current. See
Figure 61 for typical connections of guard rings for standard op-amp configurations.
Figure 60. Examples of Guard Ring in PC Board Layout
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Inverting Amplifier
Non-Inverting Amplifier
Follower
Figure 61. Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 62.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board).
Figure 62. Air Wiring
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Application Circuits
Where: V0= V1+ V2−V3– V4
(V1+ V2≥(V3+ V4) to keep V0> 0VDC
Figure 63. DC Summing Amplifier (VIN ≥0VDC and VO≥VDC
For
(CMRR depends on this resistor ratio match)
As shown: VO= 2(V2−V1)
Figure 64. High Input Z, DC Differential Amplifier
Figure 65. Photo Voltaic-Cell Amplifier
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If R1 = R5, R3 = R6, and R4 = R7; then
∴AV≈100 for circuit shown (R2= 9.3k).
Figure 66. Instrumentation Amplifier
Figure 67. Rail-to-Rail Single Supply Low Pass Filter
This low-pass filter circuit can be used as an anti-aliasing filter with the same supply as the A/D converter. Filter
designs can also take advantage of the LMC6492/4 ultra-low input current. The ultra-low input current yields
negligible offset error even when large value resistors are used. This in turn allows the use of smaller valued
capacitors which take less board space and cost less.
Figure 68. Low Voltage Peak Detector with Rail-to-Rail Peak Capture Range
Dielectric absorption and leakage is minimized by using a polystyrene or polypropylene hold capacitor. The
droop rate is primarily determined by the value of CHand diode leakage current. Select low-leakage current
diodes to minimize drooping.
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Rf= Rx
Rf>> R1, R2, R3, and R4
Figure 69. Pressure Sensor
In a manifold absolute pressure sensor application, a strain gauge is mounted on the intake manifold in the
engine unit. Manifold pressure causes the sensing resistors, R1, R2, R3 and R4 to change. The resistors change
in a way such that R2 and R4 increase by the same amount R1 and R3 decrease. This causes a differential
voltage between the input of the amplifier. The gain of the amplifier is adjusted by Rf.
Spice Macromodel
A spice macromodel is available for the LMC6492/4. This model includes accurate simulation of:
• Input common-model voltage range
• Frequency and transient response
• GBW dependence on loading conditions
• Quiescent and dynamic supply current
• Output swing dependence on loading conditions
and many other characteristics as listed on the macromodel disk.
Contact your local Texas Instruments sales office to obtain an operational amplifier spice model library disk.
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMC6492AEM NRND SOIC D 8 95 Non-RoHS
& Green Call TI Call TI -40 to 125 LMC64
92AEM
LMC6492AEM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC64
92AEM
LMC6492AEMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC64
92AEM
LMC6492BEM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC64
92BEM
LMC6492BEMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC64
92BEM
LMC6494AEM NRND SOIC D 14 55 Non-RoHS
& Green Call TI Call TI -40 to 125 LMC6494
AEM
LMC6494AEM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494
AEM
LMC6494AEMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494
AEM
LMC6494BEM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494
BEM
LMC6494BEMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMC6494
BEM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMC6492AEMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC6492BEMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC6494AEMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMC6494BEMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMC6492AEMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMC6492BEMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMC6494AEMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMC6494BEMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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