2.5 V to 5.5 V, Parallel Interface
Octal Voltage Output 8-/10-/12-Bit DACs
Data Sheet AD5346/AD5347/AD5348
Rev. A Document Feedback
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Technical Support www.analog.com
FEATURES
AD5346: octal 8-bit DAC
AD5347: octal 10-bit DAC
AD5348: octal 12-bit DAC
Low power operation: 1.4 mA (max) at 3.6 V
Power-down to 120 nA at 3 V, 400 nA at 5 V
Guaranteed monotonic by design over all codes
Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Readback
Buffered/unbuffered reference inputs
20 ns WR time
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit
DACs, operating from a 2.5 V to 5.5 V supply. These devices
incorporate an on-chip output buffer that can drive the output
to both supply rails, and also allow a choice of buffered or
unbuffered reference input.
The AD5346/AD5347/AD5348 have a parallel interface. CS
selects the device and data is loaded into the input registers on
the rising edge of WR. A readback feature allows the internal
DAC registers to be read back through the digital port.
The GAIN pin on these devices allows the output range to be
set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
STRING
DAC A
STRING
DAC B
STRING
DAC D
STRING
DAC E
STRING
DAC F
STRING
DAC G
STRING
DAC H
DGND
VOUTB
VOUTC
VOUTD
VOUTE
VOUTG
VOUTH
VOUTF
VDD
POWER-ON
RESET
VOUTA
VREFEF
VREFAB
PD
INTER-
FACE
LOGIC
GAIN
DB11
DB0
CS
WR
A0
A1
CLR
LDAC
.
.
.
BUF
A2
RD
VREFGH
VREFCD
AGND
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
AD5348
POWER-DOWN
LOGIC
03331-0-001
Figure 1.
1 Protected by U.S. Patent No. 5,969,657.
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .......................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 5
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 13
Functional Description .................................................................. 17
Digital-to-Analog Section ......................................................... 17
Resistor String ............................................................................. 17
DAC Reference Input ................................................................. 17
Output Amplifier ........................................................................ 17
Parallel Interface ......................................................................... 17
Power-On Reset .......................................................................... 18
Power-Down Mode .................................................................... 18
Suggested Data Bus Formats ..................................................... 19
Applications Information .............................................................. 20
Typical Application Circuits ..................................................... 20
Bipolar Operation Using the AD5346/AD5347/AD5348 ..... 20
Decoding Multiple AD5346/AD5347/AD5348s .................... 21
AD5346/AD5347/AD5348 as Digitally Programmable
Window Detectors ...................................................................... 21
Programmable Current Source ................................................ 21
Coarse and Fine Adjustment Using the
AD5346/AD5347/AD5348 ....................................................... 22
Power Supply Bypassing and Grounding ................................ 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Changes to Figure 6 .......................................................................... 8
Changes to Figure 8 .......................................................................... 9
Changes to Figure 10 ...................................................................... 10
Deleted Driving VDD from the Reference Voltage Section and
Figure 42; Renumbered Sequentially ........................................... 20
Deleted Table 9 and Table 10; Renumbered Sequentially ......... 23
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 24
11/03—Revision 0: Initial Version
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 3 of 24
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
B Version1
Parameter2 Min Typ Max Unit Test Conditions/Comments
DC PERFORMANCE3, 4
AD5346
Resolution 8 Bits
Relative Accuracy ±0.15 ±1 LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes
AD5347
Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes
AD5348
Resolution 12 Bits
Relative Accuracy ±2 ±16 LSB
Differential Nonlinearity ±0.2 ±1 LSB Guaranteed monotonic by design over all codes
Offset Error ±0.4 ±3 % of FSR
Gain Error ±0.1 ±1 % of FSR
Lower Deadband5 10 60 mV Lower deadband exists only if offset error is
negative
Upper Deadband5 10 60 mV VDD = 5 V; upper deadband exists only if VREF = VDD
Offset Error Drift6 –12
ppm of
FSR/°C
Gain Error Drift6 –5
ppm of
FSR/°C
DC Power Supply Rejection Ratio6 –60 dB ∆VDD = ±10%
DC Crosstalk6 200 μV
RL = 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;
Gain = +1
DAC REFERENCE INPUT6
VREF Input Range 1 VDD V Buffered reference mode
VREF Input Range 0.25 VDD V Unbuffered reference mode
VREF Input Impedance >10 MΩ Buffered reference mode and power-down mode
90 kΩ Gain = +1; input impedance = RDAC
45 kΩ Gain = +2; input impedance = RDAC
Reference Feedthrough –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –75 dB Frequency = 10 kHz
OUTPUT CHARACTERISTICS6
Minimum Output Voltage4, 7 0.001 V min Rail-to-rail operation
Maximum Output Voltage4, 7 VDD –
0.001
V max
DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA VDD = 5 V
16 mA VDD = 3 V
Power-Up Time 2.5 μs Coming out of power-down mode; VDD = 5 V
5 μs Coming out of power-down mode; VDD = 3 V
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 4 of 24
B Version1
Parameter2 Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS6
Input Current ±1 µA
VIL, Input Low Voltage 0.8 V VDD = 5 V ±10%
0.7 V VDD = 3 V ±10%
0.6 V VDD = 2.5 V
VIH, Input High Voltage 1.7 V VDD = 2.5 V to 5.5 V
Pin Capacitance 5 pF
LOGIC OUTPUTS6
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL 0.4 V ISINK = 200 µA
Output High Voltage, VOH VDD – 1 V ISOURCE = 200 µA
V
DD
= 2.5 V to 3.6 V
Output Low Voltage, VOL 0.4 V ISINK = 200 µA
Output High Voltage, VOH VDD –
0.5
V ISOURCE = 200 µA
POWER REQUIREMENTS
VDD 2.5 5.5 V
IDD (Normal Mode) VIH = VDD, VIL = GND
VDD = 4.5 V to 5.5 V 1 1.65 mA All DACs in unbuffered mode. In buffered mode,
V
DD
= 2.5 V to 3.6 V
0.8
1.4
mA
extra current is typically x µA per DAC,
where x = 5 µA + VREF/RDAC
IDD (Power-Down Mode) VIH = VDD, VIL = GND
VDD = 4.5 V to 5.5 V 0.4 1 µA
VDD = 2.5 V to 3.6 V 0.12 1 µA
1 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.
2 See the Terminology section.
3 Linearity is tested using a reduced code range: AD5346 (Code 8 to Code 255); AD5347 (Code 28 to Code 1023); AD5348 (Code 115 to Code 4095).
4 DC specifications tested with outputs unloaded.
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization, not production tested.
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and the offset
plus gain error must be positive.
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 5 of 24
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed
by design and characterization, not production tested.
Table 2.
B Version1
Parameter2 Min Typ Max Unit Test Conditions/Comments
Output Voltage Settling Time VREF = 2 V
AD5346 6 8 μs 1/4 scale to 3/4 scale change (40 H to C0 H)
AD5347 7 9 μs 1/4 scale to 3/4 scale change (100 H to 300 H)
AD5348 8 10 μs 1/4 scale to 3/4 scale change (400 H to C00 H)
Slew Rate 0.7 V/μs
Major Code Transition Glitch Energy 8 nV-s 1 LSB change around major carry
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 1 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3.5 nV-s
Multiplying Bandwidth 200 kHz VREF = 2 V ±0.1 V p-p; unbuffered mode
Total Harmonic Distortion –70 dB VREF = 2. V ±0.1 V p-p; frequency = 10 kHz; unbuffered mode
1 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.
2 See the Terminology section.
I
OH
I
OL
TO OUTPUT
PIN V
OH
(min) + V
OL
(max)
2
C
L
50pF
200A
200A
03331-0-002
Figure 2. Load Circuit for Digital Output Timing Specifications
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not
production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 2.
Table 3.
Parameter Limit at TMIN, TMAX Unit Test Condition/Comments
Data Write Mode (Figure 3)
t1 0 ns min CS to WR setup time
t2 0 ns min CS to WR hold time
t3 20 ns min WR pulse width
t4 5 ns min Data, GAIN, BUF setup time
t5 4.5 ns min Data, GAIN, BUF hold time
t6 5 ns min Synchronous mode. WR falling to LDAC falling.
t7 5 ns min Synchronous mode. LDAC falling to WR rising.
t8 4.5 ns min Synchronous mode. WR rising to LDAC rising.
t9 5 ns min Asynchronous mode. LDAC rising to WR rising.
t10 4.5 ns min Asynchronous mode. WR rising to LDAC falling.
t11 20 ns min LDAC pulse width
t12 10 ns min CLR pulse width
t13 20 ns min Time between WR cycles
t14 20 ns min A0, A1, A2 setup time
t15 0 ns min A0, A1, A2 hold time
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 6 of 24
Parameter Limit at TMIN, TMAX Unit Test Condition/Comments
Data Readback Mode (Figure 4)
t16 0 ns min A0, A1, A2 to CS setup time
t17 0 ns min A0, A1, A2 to CS hold time
t18 0 ns min CS to falling edge of RD
t19 20 ns min RD pulse width; VDD = 3.6 V to 5.5 V
30 ns min RD pulse width; VDD = 2.5 V to 3.6 V
t20 0 ns min CS to RD hold time
t21 22 ns max Data access time after falling edge of RD; VDD = 3.6 V to 5.5 V
30 ns max Data access time after falling edge of RD VDD = 2.5 V to 3.6 V
t22 4 ns min Bus relinquish time after rising edge of RD
30 ns max
t23 22 ns max CS falling edge to data; VDD = 3.6 V to 5.5 V
30 ns max
CS falling edge to data; VDD = 2.5 V to 3.6 V
t24 30 ns min
Time between RD cycles
t25 30 ns min
Time from RD to WR
t26 30 ns min
Time from WR to RD, VDD = 3.6 V to 5.5 V
50 ns min
Time from WR to RD, VDD = 2.5 V to 3.6 V
CS
WR
DATA,
GAIN, BUF
LDAC
1
LDAC
2
CLR
NOTES
1. SYNCHRONOUS LDAC UPDATE MODE
2. ASYNCHRONOUS LDAC UPDATE MODE
A0–A2
t
1
t
2
t
3
t
4
t
7
t
9
t
10
t
11
t
12
t
5
t
15
t
8
t
14
t
6
t
13
03331-0-003
Figure 3. Parallel Interface Write Timing Diagram
CS
A0–A2
RD
WR
DATA
t
16
t
18
t
25
t
20
t
22
t
21
t
17
t
26
t
24
t
19
t
23
03331-0-004
Figure 4. Parallel Interface Read Timing Diagram
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND –0.3 V to +7 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND –0.3 V to VDD + 0.3 V
VOUT to GND –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version)
–40°C to +105°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
38-Lead TSSOP Package
Power Dissipation (TJ max − TA)/ θJA mW
θJA Thermal Impedance 98.3°C/W
θJC Thermal Impedance 8.9°C/W
40-Lead LFCSP Package
Power Dissipation (TJ max − TA)/ θJA mW
θJA Thermal Impedance (3-layer
board) 29.6°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature 220°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those listed in the operational
sections of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. AD5346 Pin Configuration—TSSOP
LDAC
A1
A0
WR
CS
AGND
V
OUT
D
V
REF
CD
V
REF
EF
V
REF
GH
V
OUT
C
V
OUT
B
V
OUT
A
V
REF
AB
PD
V
DD
DB
0
DB
1
DB
2
CLR
GAIN
DB
7
DB
6
DB
3
DB
4
DB
5
V
OUT
H
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE TI E D TO GND.
V
OUT
G
V
OUT
F
V
OUT
E
DGND
A2
RD
BUF
AGND
V
DD
DGND
DGND
DGND
DGND
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
03331-006
8-BIT
AD5346
TOP VIEW
(No t t o Scal e)
Figure 6. AD5346 Pin Configuration—LFCSP
Table 5. AD5346 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 35 VREFGH Reference Input for DACs G and H.
2 36 VREFEF Reference Input for DACs E and F.
3 37 VREFCD Reference Input for DACs C and D.
4 38, 39 VDD Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP
package must be at the same potential.
5 40 VREFAB Reference Input for DACs A and B.
6 to 9,
11 to 14
1 to 4,
7 to 10
V
OUT
X
Output of DAC X. Buffered output with rail-to-rail operation.
10 5, 6 AGND Analog Ground. Ground reference for analog circuitry.
15,
21 to 24
11,
17 to 20
DGND Digital Ground. Ground reference for digital circuitry.
16
12
BUF
Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17 13 LDAC
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which
allows all DAC outputs to be simultaneously updated.
18 14 A0 LSB Address Pin. Selects which DAC is to be written to.
19 15 A1 Address Pin. Selects which DAC is to be written to.
20 16 A2 MSB Address Pin. Selects which DAC is to be written to.
25 to 32 21 to 28 DB0 to DB7 Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
33 29 CS Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or
with RD to read back data from a DAC.
34 30 RD Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.
35 31 WR Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.
36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VR E F.
37
33
CLR
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
38 34 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Not
applicable
41 EPAD Exposed Pad. The exposed pad must be tied to GND.
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 9 of 24
Figure 7. AD5347 Pin Configuration—TSSOP
LDAC
A1
A0
WR
CS
AGND
VOUTD
VREFCD
VREFEF
VREFGH
VOUTC
VOUTB
VOUTA
VREFAB
PD
VDD
DB2
DB3
DB4
CLR
GAIN
DB9
DB8
DB5
DB6
DB7
VOUTH
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE TI E D TO GND.
VOUTG
VOUTF
VOUTE
DGND
A2
RD
BUF
AGND
VDD
DB1
DB0
DGND
DGND
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
03331-008
10-BIT
AD5347
TOP VIEW
(No t t o Scal e)
Figure 8. AD5347 Pin Configuration—LFCSP
Table 6. AD5347 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 35 VREFGH Reference Input for DACs G and H.
2 36 VREFEF Reference Input for DACs E and F.
3 37 VREFCD Reference Input for DACs C and D.
4 38, 39 VDD Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP
package must be at the same potential.
5 40 VREFAB Reference Input for DACs A and B.
6 to 9,
11 to 14
1 to 4,
7 to 10
VOUTX Output of DAC X. Buffered output with rail-to-rail operation.
10 5, 6 AGND Analog Ground. Ground reference for analog circuitry.
15, 21 to 22 11,
17 to 18
DGND Digital Ground. Ground reference for digital circuitry.
16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17 13 LDAC Active Low Control Input. Updates the DAC registers with the contents of the input registers,
which allows all DAC outputs to be simultaneously updated.
18
14
A0
LSB Address Pin. Selects which DAC is to be written to.
19 15 A1 Address Pin. Selects which DAC is to be written to.
20 16 A2 MSB Address Pin. Selects which DAC is to be written to.
23 to 32 19 to 28 DB0 to DB9 Ten Parallel Data Inputs. DB9 Is the MSB of these ten bits.
33 29 CS Active Low Chip Select Input. Used in conjunction with WR
to write data to the parallel interface,
or with RD to read back data from a DAC.
34 30 RD Active Low Read Input. Used in conjunction with CS
to read data back from the internal DACs.
35 31 WR
Active Low Write Input. Used in conjunction with CS
to write data to the parallel interface.
36 32 GAIN
Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
37 33 CLR Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
38 34 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Not
applicable
41
EPAD
Exposed Pad. The exposed pad must be tied to GND.
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 10 of 24
TOP VIEW
(Not to Scale)
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
AD5348
LDAC
A1
A0
WR
CS
AGND
V
OUT
D
V
REF
CD
V
REF
EF
V
REF
GH
V
OUT
C
V
OUT
B
V
OUT
A
V
REF
AB
PD
V
DD
DB
4
DB
5
DB
6
CLR
GAIN
DB
11
DB
10
DB
7
DB
8
DB
9
12-BIT
V
OUT
H
V
OUT
G
V
OUT
F
V
OUT
E
DGND
A2
RD
BUF DB
2
DB
0
DB
3
DB
1
03331-0-009
Figure 9. AD5348 Pin Configuration—TSSOP
LDAC
A1
A0
WR
CS
AGND
VOUTD
VREFCD
VREFEF
VREFGH
VOUTC
VOUTB
VOUTA
VREFAB
PD
VDD
DB4
DB5
DB6
CLR
GAIN
DB11
DB10
DB7
DB8
DB9
VOUTH
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE TI E D TO GND.
VOUTG
VOUTF
VOUTE
DGND
A2
RD
BUF
AGND
VDD
DB3
DB2
DB1
DB0
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
03331-010
12-BIT
AD5348
TOP VIEW
(No t t o Scal e)
Figure 10. AD5348 Pin Configuration—LFCSP
Table 7. AD5348 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 35 VREFGH Reference Input for DACs G and H.
2 36 VREFEF Reference Input for DACs E and F.
3 37 VREFCD Reference Input for DACs C and D.
4 38, 39 VDD Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP
package must be at the same potential.
5 40 VREFAB Reference Input for DACs A and B.
6 to 9,
11 to 14
1 to 4,
7 to 10
VOUTX Output of DAC X. Buffered output with rail-to-rail operation.
10 5, 6 AGND Analog Ground. Ground reference for analog circuitry.
15 11 DGND Digital Ground. Ground reference for digital circuitry.
16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17 13 LDAC Active Low Control Input. Updates the DAC registers with the contents of the input registers,
which allows all DAC outputs to be simultaneously updated.
18 14 A0 LSB Address Pin. Selects which DAC is to be written to.
19 15 A1 Address Pin. Selects which DAC is to be written to.
20 16 A2 MSB Address Pin. Selects which DAC is to be written to.
21 to 32 17 to 28 DB0 to DB11 Twelve Parallel Data Inputs. DB11 is the MSB of these 12 bits.
33 29 CS Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface,
or with RD to read back data from a DAC.
34 30 RD Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.
35
31
WR
Active Low Write Input. Used in conjunction with
CS
to write data to the parallel interface.
36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
37 33 CLR Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
38 34 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Not
applicable
41 EPAD Exposed Pad. The exposed pad must be tied to GND.
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 11 of 24
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus code plots can be seen in Figure 14,
Figure 15, and Figure 16.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in Figure 17, Figure 18, and Figure 19.
Gain Error
This is a measure of the span error of the DAC, including any
error in the gain of the buffer amplifier. It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
and is expressed as a percentage of the full-scale range. This is
illustrated in Figure 11.
Offset Error
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
If the offset voltage is positive, the output voltage still positive at
zero input code. This is shown in Figure 12. Because the DACs
operate from a single supply, a negative offset cannot appear at
the output of the buffer amplifier. Instead, there is a code close
to zero at which the amplifier output saturates (amplifier
footroom). Below this code there is a dead band over which the
output voltage does not change. This is illustrated in Figure 13.
OUTPUT
V
OLTAGE
DAC CODE
POSITIVE
GAIN ERROR
NEGATIVE
GAIN ERROR
ACTUAL
IDEAL
03331-0-011
Figure 11. Gain Error
OUTPUT
VOLTAGE
DAC CODE
POSITIVE
OFFSET
GAIN ERROR
AND
OFFSET
ERROR
ACTUAL
IDEAL
03331-0-012
Figure 12. Positive Offset Error and Gain Error
AMPLIFIER
FOOTROOM
(~1mV)
NEGATIVE
OFFSET
OUTPUT
VOLTAGE
DAC CODE
GAIN ERROR
AND
OFFSET
ERROR
DEADBAND CODES
ACTUAL
IDEAL
NEGATIVE
OFFSET
03331-0-013
Figure 13. Negative Offset Error and Gain Error
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 12 of 24
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
DC Power-Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated, that is, LDAC is high. It is expressed in dB.
Channel-to-Channel Isolation
This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference inputs of the other DACs.
It is measured by grounding one VREF pin and applying a 10 kHz,
4 V p-p sine wave to the other VREF pins. It is expressed in dB.
Major-Code Transition Glitch Energy
This is the energy of the impulse injected into the analog output
when the DAC changes state. It is normally specified as the area
of the glitch in nV-s and is measured when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).
Digital Feedthrough
This is a measure of the impulse injected into the analog output
of the DAC from the digital input pins of the device, but it is
measured when the DAC is not being written to, CS held high.
It is specified in nV-s and is measured with a full-scale change
on the digital input pins, that is, from all 0s to all 1s and vice
versa.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-s.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC pin set
low and monitoring the output of another DAC. The energy of
the glitch is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output. It is measured in dB.
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 13 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
CODE 2501000 50 150 200
INL ERROR (LSB)
1.0
0.5
–1.0
0
–0.5
03331-0-014
TA = 25C
VDD = 5V
Figure 14. AD5346 Typical INL Plot
CODE
INL ERROR (LSB)
3
0 200 1000
400 600 800
0
–1
–2
–3
2
1
T
A
= 25C
V
DD
= 5V
03331-0-015
Figure 15. AD5347 Typical INL Plot
CODE
INL ERROR (LSB)
12
0
–4
–8
8
4
0 40001000 2000 3000
–12
T
A
= 25C
V
DD
= 5V
03331-0-016
Figure 16. AD5348 Typical INL Plot
CODE
DNL ERROR (LSB)
250100 1500 50 200
–0.1
–0.2
–0.3
0.3
0.1
0.2
0
03331-0-017
T
A
= 25C
V
DD
= 5V
Figure 17. AD5346 Typical DNL Plot
CODE
DNL ERROR (LSB)
0.4
–0.4
600400 800 1000
0
–0.6
0.6
0.2
–0.2
2000
T
A
= 25C
V
DD
= 5V
03331-0-018
Figure 18. AD5347 Typical DNL Plot
CODE
2000 3000 4000
DNL ERROR (LSB)
0.5
0
–1.0
1.0
–0.5
10000
03331-0-019
T
A
= 25C
V
DD
= 5V
Figure 19. AD5348 Typical DNL Plot
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 14 of 24
V
REF
(V)
ERROR (LSB)
0.5
0.3
0.2
0.1
0.4
–0.5
–0.4
0
–0.3
–0.2
–0.1
012345
MAX INL
MAX DNL
MIN INL
MIN DNL
03331-0-031
V
DD
= 5V
T
A
= 25C
Figure 20. AD5346 INL and DNL Error vs. VREF
TEMPERATURE (C)
ERROR (LSB)
0.5
0.2
–0.5
–40 0–204020
0
–0.2
60 80 100
–0.4
–0.3
–0.1
0.1
0.3
0.4
MAX INL
MAX DNL
MIN INL
03331-0-032
V
DD
= 5V
V
REF
= 2V
MIN DNL
Figure 21. AD5346 INL and DNL Error vs. Temperature
TEMPERATURE (C)
–1.0
03331-0-033
ERROR (% FSR)
1.0
0.5
–40 –20 0 4020
0
–0.5
8060 100
OFFSET ERROR
GAIN ERROR
V
DD
= 5V
V
REF
= 2V
Figure 22. AD5346 Offset Error and Gain Error vs. Temperature
V
DD
(V)
ERROR (% FSR)
0.2
0
–0.6 0213
–0.4
–0.2
456
–0.5
–0.3
–0.1
0.1
03331-0-034
T
A
= 25C
V
REF
= 2V
OFFSET ERROR
GAIN ERROR
Figure 23. Offset Error and Gain Error vs. VDD
SINK/SOURCE CURRENT (mA)
V
OUT
(V)
5
00213
3
456
1
2
4
03331-0-035
5V SOURCE
3V SOURCE
5V SINK 3V SINK
Figure 24. VOUT Source and Sink Current Capability
DAC CODE
I
DD
(mA)
1.0
0.8
0ZERO SCALE HALF SCALE
0.2
0.4
FULL SCALE
0.1
0.3
0.5
0.6
0.7
0.9
03331-0-036
V
DD
= 5V
T
A
= 25C
Figure 25. Supply Current vs. DAC Code
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 15 of 24
SUPPLY VOLTAGE (V)
I
DD
(mA)
1.4
1.2
02.5 3.53.0 4.0
0.4
0.8
4.5 5.0 5.5
0.2
0.6
1.0
03331-0-037
T
A
= +105C
T
A
= +25C
T
A
= –40C
V
REF
= 2V
GAIN = 1 UNBUFFERED
Figure 26. Supply Current vs. Supply Voltage
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
I
DD
POWER-DOWN (A)
T
A
= 25°C
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
DD
(V)
03331-0-038
Figure 27. Power-Down Current vs. Supply Voltage
VLOGIC (V)
I
DD
(mA)
2.5
00321 4
1.5
5
0.5
1.0
2.0
03331-0-039
T
A
= 25C
V
DD
= 5V
V
DD
= 3V
Figure 28. Supply Current vs. Logic Input Voltage
CH2
CH1
V
OUT
A
T
A
= 25°C
V
DD
= 5V
V
REF
= 5V
03331-0-040
CH1 1V, CH2 5V, TIME BASE = 1s/DIV
LDAC
Figure 29. Half-Scale Settling (¼ to ¾ Scale Code)
CH2
CH1
CH1 2V, CH2 200mV, TIME BASE = 200s/DIV
V
OUT
A
V
DD
03331-0-041
T
A
= 25°C
V
DD
= 5V
V
REF
= 2V
Figure 30. Power-On Reset to 0 V
CH1
CH2
CH1 2.00V, CH2 1.00V, TIME BASE = 20s/DIV
V
OUT
1
03331-0-042
PD
Figure 31. Exiting Power-Down to Midscale
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 16 of 24
0
3
6
9
12
15
18
21
FREQUENCY
I
DD
(mA)
0.80.6 1.0 1.2 1.4
03331-0-043
V
DD =
3V V
DD =
5V
Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V
V
OUT
(V)
2.47
2.49
2.48
2.50
1s/DIV
03331-0-044
Figure 33. AD5348 Major Code Transition Glitch Energy
FREQUENCY (Hz)
dB
10
–10
–6010 1k100 10k
–40
–30
100k 1M 10M
–50
–20
0
03331-0-045
Figure 34. Multiplying Bandwidth (Small Signal Frequency Response)
V
REF
(V)
FULL-SCALE ERROR (V)
0.02
0.01
–0.02 0213
–0.01
0
456
03331-0-046
V
DD
= 5V
T
A
= 25
C
Figure 35. Full-Scale Error vs. VREF
0
1.996
1.997
1.998
1.999
511
475
450
425
400
375
350
325
300
275
250
225
200
175
150
125
100
75
50
25
03331-0-047
Figure 36. DAC-to-DAC Crosstalk
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 17 of 24
FUNCTIONAL DESCRIPTION
The AD5346/AD5347/AD5348 are octal resistor-string DACs
fabricated by a CMOS process with resolutions of 8, 10, and 12
bits, respectively. They are written to using a parallel interface.
They operate from single supplies of 2.5 V to 5.5 V, and the
output buffer amplifiers offer rail-to-rail output swing. The gain
of the buffer amplifiers can be set to 1 or 2 to give an output
voltage range of 0 V to VREF or 0 V to 2 × VREF. The AD5346/
AD5347/AD5348 have reference inputs that may be buffered to
draw virtually no current from the reference source. The
devices have a power-down feature that reduces current
consumption to only 100 nA at 3 V.
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 37 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
Gain
D
VV N
REFOUT 2
where:
D is the decimal equivalent of the binary code, which is loaded
to the DAC register:
0 to 255 for AD5346 (8 bits)
0 to1023 for AD5347 (10 bits)
0 to 4095 for AD5348 (12 bits)
N is the DAC resolution.
Gain is the output amplifier gain (1 or 2).
V
OUT
A
(GAIN = +1 OR +2)
V
REF
AB
BUF
DAC
REGISTER
INPUT
REGISTER RESISTOR
STRING
OUTPUT
BUFFER AMPLIFIER
REFERENCE
BUFFER
03331-0-020
Figure 37. Single DAC Channel Architecture
RESISTOR STRING
The resistor string section is shown in Figure 38. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
TO OUTPUT
AMPLIFIER
R
R
R
R
R
V
REF
03331-0-021
Figure 38. Resistor String
DAC REFERENCE INPUT
The DACs operate with an external reference. The AD5346/
AD5347/AD5348 have a reference input for each pair of DACs.
The reference inputs may be configured as buffered or
unbuffered. This option is controlled by the BUF pin.
In buffered mode (BUF = 1), the current drawn from an
external reference voltage is virtually zero because the imped-
ance is at least 10 MΩ. The reference input range is 1 V to VDD.
In unbuffered mode (BUF = 0), the user can have a reference
voltage as low as 0.25 V and as high as VDD because there is no
restriction due to headroom and footroom of the reference
amplifier. The impedance is still large at typically 90 kΩ for 0 V
to VREF mode and 45 kΩ for 0 V to 2 × VREF mode.
If using an external buffered reference (such as REF192), there
is no need to use the on-chip buffer.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on VREF, GAIN, the load on VOUT, and offset error.
If a gain of +1 is selected (GAIN = 0), the output range is
0.001 V to VREF.
If a gain of +2 is selected (GAIN = +1), the output range is
0.001 V to 2 × VREF. However, because of clamping, the
maximum output is limited to VDD − 0.001 V.
The output amplifier is capable of driving a load of 2 kΩ to
GND or VDD, in parallel with 500 pF to GND or VDD. The
source and sink capabilities of the output amplifier can be seen
in Figure 24.
The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB
(at 8 bits) of 6 s with the output unloaded. See Figure 29.
PARALLEL INTERFACE
The AD5346/AD5347/AD5348 load their data as a single 8-,
10-, or 12-bit word.
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 18 of 24
Double-Buffered Interface
The AD5346/AD5347/AD5348 DACs all have double-buffered
interfaces consisting of an input register and a DAC register.
DAC data, BUF, and GAIN inputs are written to the input regis-
ter under control of the Chip Select (CS) and Write (WR) pins.
Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it. The gain and buffer control signals
are also double-buffered and are updated only when LDAC is
taken low.
This is useful if the user requires simultaneous updating of all
DACs and peripherals. The user can write to all input registers
individually and then, by pulsing the LDAC input low, all
outputs update simultaneously.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the input registers. In the case of the AD5346/
AD5347/AD5348, the part updates the DAC register only if the
input register has been changed since the last time the DAC
register was updated. This removes unnecessary crosstalk.
Clear Input (CLR)
CLR is an active low, asynchronous clear that resets the input
and DAC registers.
Chip Select Input (CS)
CS is an active low input that selects the device.
Write Input (WR)
WR is an active low input that controls writing of data to the
device. Data is latched into the input register on the rising edge
of WR.
Read Input (RD)
RD is an active low input that controls when data is read back
from the internal DAC registers. On the falling edge of RD, data
is shifted onto the data bus. Under the conditions of a high
capacitive load and high supplies, the user must ensure that the
dynamic current remains at an acceptable level, therefore
ensuring that the die temperature is within specification. The
die temperature can be calculated as
TDIE = TAMBIENT + VDD(IDD + IDYNAMIC)θJA
where:
IDYNAMI C = cvf (c = capacitance or the data bus, v = VDD, and f =
readback frequency)
Load DAC Input (LDAC)
LDAC transfers data from the input register to the DAC register,
and therefore updates the outputs. The LDAC function enables
double-buffering of the DAC data, GAIN data, and BUF. There
are two LDAC modes:
In synchronous mode, the DAC register is updated after
new data is read in on the rising edge of the WR input.
LDAC can be tied permanently low or pulsed as shown in
Figure 3.
In asynchronous mode, the outputs are not updated at the
same time that the input register is written to. When LDAC
goes low, the DAC register is updated with the contents of
the input register.
POWER-ON RESET
The AD5346/AD5347/AD5348 have a power-on reset function,
so that they power up in a defined state. The power-on state is
Normal operation
Reference input buffered
0 V to VREF output range
Output voltage set to 0 V
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
POWER-DOWN MODE
The AD5346/AD5347/AD5348 have low power consumption,
dissipating typically 2.4 mW with a 3 V supply and 5 mW with
a 5 V supply. Power consumption can be further reduced when
the DACs are not in use by putting them into power-down
mode, which is selected by taking the PD pin low.
When the PD pin is high, the DACs work normally with a typi-
cal power consumption of 1 mA at 5 V (0.8 mA at 3 V). In
power-down mode, however, the supply current falls to 400 nA
at 5 V (120 nA at 3 V) when the DACs are powered down. Not
only does the supply current drop, but the output stage is also
internally switched from the output of the amplifier, making it
open-circuit. This has the advantage that the outputs are three-
state while the part is in power-down mode, and provides a
defined input condition for whatever is connected to the outputs
of the DAC amplifiers. The output stage is illustrated in Figure 39.
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER V
OU
T
03331-0-022
Figure 39. Output Stage During Power-Down
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 19 of 24
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 s for VDD = 5 V and 5 µs when VDD
= 3 V. This is the time from a rising edge on the PD pin to when
the output voltage deviates from its power-down voltage. See
Figure 31.
SUGGESTED DATA BUS FORMATS
In many applications, the GAIN and BUF pins are hardwired.
However, if more flexibility is required, they can be included in
a data bus. This enables the user to software program GAIN,
giving the option of doubling the resolution in the lower half of
the DAC range. In a bused system, GAIN and BUF may be
treated as data inputs because they are written to the device
during a write operation and take effect when LDAC is taken
low. This means that the reference buffers and the output
amplifier gain of multiple DAC devices can be controlled using
common GAIN and BUF lines. Note that GAIN and BUF are
not read back during an RD operation.
The AD5347 and AD5348 data bus must be at least 10 and 12
bits wide, respectively, and are best suited to a 16-bit data bus
system.
Examples of data formats for putting GAIN and BUF on a
16-bit data bus are shown in Figure 40. Note that any unused
bits above the actual DAC data may be used for GAIN and BUF.
03331-0-048
DB0
DB1
DB2
DB3
DB4
DB5
DB6DB7
DB8DB9
GAIN
XX BUF
X
X = UNUSED BIT
X
DB0DB1DB2DB3DB4DB5
DB6
DB7
DB8
DB9
GAIN
XX BUF DB11 DB10
AD5347
AD5348
Figure 40. AD5347/AD5348 Data Format for Word Load with
GAIN and BUF Data on 16-Bit Bus
Table 8. AD5346/AD5347/AD5348 Truth Table
CLR LDAC CS WR RD A2 A1 A0 Function
1 1 1 X X X X X No data transfer
1 1 X 1 1 X X X No data transfer
0
X
X
X
X
X
X
X
Clear all registers
1 1 0 0
→
1 1 0 0 0 Load DAC A input register
1 1 0 0
→
1 1 0 0 1 Load DAC B input register
1 1 0 0
→
1 1 0 1 0 Load DAC C input register
1 1 0 0
→
1 1 0 1 1 Load DAC D input register
1 1 0 0
→
1 1 1 0 0 Load DAC E input register
1 1 0 0
→
1 1 1 0 1 Load DAC F input register
1 1 0 0
→
1 1 1 1 0 Load DAC G input register
1 1 0 0
→
1 1 1 1 1 Load DAC H input register
1 X 0 1 1
→
0 0 0 0 Read Back DAC Register A
1 X 0 1 1
→
0 0 0 1 Read Back DAC Register B
1 X 0 1 1
→
0 0 1 0 Read Back DAC Register C
1 X 0 1 1
→
0 0 1 1 Read Back DAC Register D
1 X 0 1 1
→
0 1 0 0 Read Back DAC Register E
1 X 0 1 1
→
0 1 0 1 Read Back DAC Register F
1 X 0 1 1
→
0 1 1 0 Read Back DAC Register G
1 X 0 1 1
→
0 1 1 1 Read Back DAC Register H
1 0 X X 1 X X X Update DAC registers
X X 0 0 0 X X X Invalid operation
X = Don’t Care
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 20 of 24
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUITS
The AD5346/AD5347/AD5348 can be used with a wide range
of reference voltages, especially if the reference inputs are
configured as unbuffered, in which case the devices offer full,
one-quadrant multiplying capability over a reference range of
0.25 V to VDD. More typically, these devices may be used with a
fixed, precision reference voltage. Figure 41 shows a typical
setup for the devices when using an external reference
connected to the reference inputs. Suitable references for 5 V
operation are the AD780, ADR381, and REF192 (2.5 V refer-
ences). For 2.5 V operation, suitable external references are the
AD589 and the AD1580 (1.2 V band gap references).
AD5346/AD5347/
AD5348
VOUT*
0.1F
VDD = 2.5V to 5.5V
VDD
GND
AD780/ADR381/REF192
WITH VDD = 5V
OR AD589/AD1580 WITH
VDD = 2.5V
VREF*
GND
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
10F
VOUT
VIN
EXT
REF
03331-0-024
Figure 41. AD5346/AD5347/AD5348 Using an External Reference
BIPOLAR OPERATION USING THE
AD5346/AD5347/AD5348
The AD5346/AD5347/AD5348 have been designed for single-
supply operation, but a bipolar output range is also possible by
using the circuit shown in Figure 42. This circuit has an output
voltage range of ±5 V. Rail-to-rail operation at the amplifier
output is achievable using an AD820, an AD8519, or an OP196
as the output amplifier.
5V
EXT
REF
GND
VOUT
R2
20k
R1
10k
R4
20k
R3
10k
±5V
+5V
–5V
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
0.1F
0.1F10F
AD820/AD8519/
OP196
VIN
GND
AD5346/AD5347/
AD5348
VOUT*
VDD
VREF*
03331-0-026
Figure 42. Bipolar Operation with the AD5346/AD5347/AD5348
The output voltage for any input code can be calculated as
follows:
VOUT = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] −
R4 × VREF/R3
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
VREF is the reference voltage input.
with:
VREF = 5 V
R1 = R3 = 10 kΩ
R2 = R4 = 20 kΩ
VDD = 5 V
GAIN = 2
VOUT = (10 × D/2N) – 5
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 21 of 24
DECODING MULTIPLE AD5346/AD5347/AD5348s
The CS pin on these devices can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same data and WR pulses, but only the CS to
one of the DACs will be active at any one time, so data will only
be written to the DAC whose CS is low.
The 74HC139 is used as a 2-line to 4-line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded address inputs are changing state.
Figure 43 shows a diagram of a typical setup for decoding
multiple devices in a system. Once data has been written
sequentially to all DACs in a system, all the DACs can be
updated simultaneously using a common LDAC line. A com-
mon CLR line can also be used to reset all DAC outputs to 0 V.
ENABLE
CODED
A
DDRESS
1G
1A
1B
V
DD
V
CC
74HC139
DGND
1Y0
1Y1
1Y2
1Y3
A0
A1
A2
WR
LDAC
CLR
DATA
INPUTS
DATA
INPUTS
DATA
INPUTS
DATA
INPUTS
DATA BUS
A0
A1
A2
WR
LDAC
CLR
CS
A0
A1
A2
WR
LDAC
CLR
CS
AD5346/AD5347
/AD5348
A0
A1
A2
WR
LDAC
CLR
CS
A0
A1
A2
WR
LDAC
CLR
CS
AD5346/AD5347
/AD5348
AD5346/AD5347
/AD5348
AD5346/AD5347
/AD5348
03331-0-027
Figure 43. Decoding Multiple DAC Devices
AD5346/AD5347/AD5348 AS DIGITALLY
PROGRAMMABLE WINDOW DETECTORS
A digitally programmable upper/lower limit detector using two
of the DACs in the AD5346/AD5347/AD5348 is shown in
Figure 44. Any pair of DACs in the device may be used, but for
simplicity the description refers to DACs A and B.
The upper and lower limits for the test are loaded to DACs A
and B which, in turn, set the limits on the CMP04. If a signal at
the VIN input is not within the programmed window, an LED
indicates the fail condition.
5V
GND
V
REF
AB V
DD
V
IN
FAIL PASS
1k1k
PASS/
FAIL
1/6 74HC05
1/2
CMP04
V
REF
0.1F10F
V
OUT
B
V
OUT
A
AD5346/AD5347/
AD5348
03331-0-028
Figure 44. Programmable Window Detector
PROGRAMMABLE CURRENT SOURCE
Figure 45 shows the AD5346/AD5347/AD5348 used as the
control element of a programmable current source. In this
example, the full-scale current is set to 1 mA. The output
voltage from the DAC is applied across the current setting
resistor of 4.7 kΩ in series with the 470 Ω adjustment
potentiometer, which gives an adjustment of about ±5%.
Suitable transistors to place in the feedback loop of the ampli-
fier include the BC107 and the 2N3904, which enable the
current source to operate from a minimum VSOURCE of 6 V. The
operating range is determined by the operating characteristics
of the transistor. Suitable amplifiers include the AD820 and the
OP295, both having rail-to-rail operation on their outputs. The
current for any digital input code and resistor value can be
calculated as follows:
mA
R
D
VGI N
REF
)2(
where:
G is the gain of the buffer amplifier (1 or 2).
D is the digital input code.
N is the DAC resolution (8, 10, or 12 bits).
R is the sum of the resistor plus adjustment potentiometer in kΩ.
VDD = 5V
5V LOAD
VSOURCE
EXT
REF
GND
VOUT
4.7k
470
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
0.1F
0.1F
10F
VIN
GND
AD5346/AD5347/
AD5348
VDD
VREF*V
OUT*
03331-0-029
Figure 45. Programmable Current Source
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 22 of 24
COARSE AND FINE ADJUSTMENT USING THE
AD5346/AD5347/AD5348
Two of the DACs in the AD5346/AD5347/AD5348 can be
paired together to form a coarse and fine adjustment function,
as shown in Figure 46. As with the window comparator
previously described, the description refers to DACs A and B.
DAC A provides the coarse adjustment, while DAC B provides
the fine adjustment. Varying the ratio of R1 and R2 changes the
relative effect of the coarse and fine adjustments. With the
resistor values shown, the output amplifier has unity gain for
the DAC A output, so the output range is 0 V to (VREF – 1 LSB).
For DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B
a range equal to 2 LSBs of DAC A.
The circuit is shown with a 2.5 V reference, but reference
voltages up to VDD may be used. The op amps indicated allow a
rail-to-rail output swing.
AD780/ADR381/REF192
WITH V
DD
= 5V
V
DD
= 5V
V
OUT
5V
EXT
REF V
OUT
V
IN
GND
GND
AD5346/AD5347/
AD5348
V
OUT
B
V
OUT
A
V
DD
V
REF
AB R1
390
R4
390
R2
51.2k
R3
51.2k
0.1F
0.1F
10F
03331-0-030
Figure 46. Coarse and Fine Adjustment
POWER SUPPLY BYPASSING AND GROUNDING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance.
The printed circuit board on which the AD5346/AD5347/AD5348
is mounted should be designed so that the analog and digital
sections are separated and are confined to certain areas of the
board. This facilitates the use of ground planes that can be
separated easily. A minimum etch technique is generally best
for ground planes because it gives the best shielding. Digital and
analog ground planes should be joined in one place only. If the
AD5346/AD5347/AD5348 is the only device requiring an
AGND-to-DGND connection, then the ground planes should
be connected at the AGND and DGND pins of the AD5346/
AD5347/AD5348. If the AD5346/AD5347/AD5348 is in a
system where multiple devices require AGND-to-DGND
connections, the connection should be made at one point only,
a star ground point that should be established as close as
possible to the AD5346/AD5347/AD5348.
The AD5346/AD5347/AD5348 should have ample supply
bypassing of 10 μF in parallel with 0.1 μF on the supply located
as close to the package as possible, ideally right up against the
device. The 10 μF capacitors are the tantalum bead type. The
0.1 μF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types that provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.
The power supply lines of the device should use the largest trace
possible to provide low impedance paths and to reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other to reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best, but not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground plane, while signal traces are placed on the solder side.
Data Sheet AD5346/AD5347/AD5348
Rev. A | Page 23 of 24
OUTLINE DIMENSIONS
38 20
191
9.80
9.70
9.60
PIN 1
SEATING
PLANE
0
.15
0
.05
0.50
BSC
1.20
MAX
0.27
0.17 0.20
0.09
8°
0°
4.50
4.40
4.30 6.40 BSC
0.70
0.60
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-BD-1
Figure 47. 38-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-38)
Dimensions shown in millimeters
0.50
BSC
BOTTOM VIEWTOP VI EW
PIN 1
INDICATOR
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
6.10
6.00 SQ
5.90
0.80
0.75
0.70
FOR PROPER CONNECTIO N OF
THE EXPOSED PAD, REFER TO
THE P IN CONF IGU RATI ON AND
FUNCTI ON DES C RIPTIONS
SECTION OF THIS DATA SHEET.
0.45
0.40
0.35
0.25 MIN
4.25
4.10 SQ
3.95
COM P LI A NT TO J E DEC STANDARDS M O-220 -WJJD.
40
1
11
20
21
30
31
10
05-06-2011-A
Figure 48. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm, Very Very Thin Quad
(CP-40-9)
Dimensions shown in millimeters
AD5346/AD5347/AD5348 Data Sheet
Rev. A | Page 24 of 24
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD5346BRU −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5346BRU-REEL7 −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5346BRUZ −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5346BRUZ-REEL −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5346BRUZ-REEL7 −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5346BCPZ −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-9
AD5347BRU −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5347BRU-REEL7 −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5347BRUZ −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5347BCPZ −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-9
AD5348BRU −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5348BRUZ −40°C to +105°C 38-Lead Thin Shrink Small Outline Package [TSSOP] RU-38
AD5348BCPZ −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-9
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D03331-0-6/15(A)