LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 LMV861/LMV862 30 MHz Low Power CMOS, EMI Hardened Operational Amplifiers Check for Samples: LMV861, LMV862 FEATURES DESCRIPTION 1 Unless Otherwise Noted, Typical Values at TA = 25C, V+ = 3.3V 2 * * * * * * * * * * * Supply Voltage 2.7V to 5.5V Supply Current (per Channel) 2.25 mA Input Offset Voltage 1 mV Max Input Bias Current 0.1 pA GBW 30 MHz EMIRR at 1.8 GHz 105 dB Input Noise Voltage at 1 kHz 8 nV/Hz Slew Rate 18 V/s Output Voltage Swing Rail-to-Rail Output Current Drive 67 mA Operating Ambient Temperature Range -40C to 125C APPLICATIONS * * * * Photodiode Preamp Weight Scale Systems Filters/Buffers Medical Diagnosis Equipment TI's LMV861 and LMV862 are CMOS input, low power op amp IC's, providing a low input bias current, a wide temperature range of -40C to +125C and exceptional performance making them robust general purpose parts. Additionally, the LMV861 and LMV862 are EMI hardened to minimize any interference so they are ideal for EMI sensitive applications. The unity gain stable LMV861 and LMV862 feature 30 MHz of bandwidth while consuming only 2.25 mA of current per channel. These parts also maintain stability for capacitive loads as large as 200 pF. The LMV861 and LMV862 provide superior performance and economy in terms of power and space usage. This family of parts has a maximum input offset voltage of 1 mV, a rail-to-rail output stage and an input common-mode voltage range that includes ground. Over an operating range from 2.7V to 5.5V the LMV861 and LMV862 provide a PSRR of 93 dB, and a CMRR of 93 dB. The LMV861 is offered in the space saving 5-Pin SC70 package, and the LMV862 in the 8-Pin VSSOP. Typical Application V R1 + NO RF RELATED DISTURBANCES PRESSURE SENSOR + - + R2 ADC + EMI HARDENED EMI HARDENED INTERFERING RF SOURCES Figure 1. EMI Hardened Sensor Application 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2013, Texas Instruments Incorporated LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Human Body Model ESD Tolerance (3) 2 kV Charge-Device Model 1 kV Machine Model 200V VIN Differential Supply Voltage Supply Voltage (VS = V+ - V-) 6V Voltage at Input/Output Pins V+ +0.4V V- -0.4V Storage Temperature Range -65C to +150C Junction Temperature (4) +150C Soldering Information (1) (2) (3) (4) Infrared or Convection (20 sec) 260C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX), JA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA . All numbers apply for packages soldered directly onto a PC board. Operating Ratings (1) Temperature Range (2) -40C to +125C Supply Voltage (VS = V+ - V-) Package Thermal Resistance (JA (2)) (1) (2) 2.7V to 5.5V 5-Pin SC70 302C/W 8-Pin VSSOP 217C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. The maximum power dissipation is a function of TJ(MAX), JA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA . All numbers apply for packages soldered directly onto a PC board. 3.3V Electrical Characteristics (1) Unless otherwise specified, all limits are guaranteed for TA = 25C, V+ = 3.3V, V- = 0V, VCM = V+/2, and RL =10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units V VOS Input Offset Voltage (4) 273 1000 1260 TCVOS Input Offset Voltage Temperature Drift (4) (5) 0.7 2.6 IB Input Bias Current (5) 0.1 10 500 IOS Input Offset Current 1 (1) (2) (3) (4) (5) 2 V/C pA pA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting distribution This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 3.3V Electrical Characteristics(1) (continued) Unless otherwise specified, all limits are guaranteed for TA = 25C, V+ = 3.3V, V- = 0V, VCM = V+/2, and RL =10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol Min (2) Typ (3) 0.2V VCM V - 1.2V 77 75 93 77 76 93 Parameter Conditions (4) + CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio (4) 2.7V V+ 5.5V, VOUT = 1V EMIRR EMI Rejection Ratio, IN+ and IN- (6) VRF_PEAK = 100 mVP (-20 dBVP), f = 400 MHz 70 VRF_PEAK = 100 mVP (-20 dBVP), f = 900 MHz 80 VRF_PEAK = 100 mVP (-20 dBVP), f = 1800 MHz 105 VRF_PEAK = 100 mVP (-20 dBVP), f = 2400 MHz 110 CMVR Input Common-Mode Voltage Range CMRR 65 dB -0.1 AVOL Large Signal Voltage Gain (7) RL = 2 k VOUT = 0.15V to 1.65V, VOUT = 3.15V to 1.65V 100 97 110 RL = 10 k VOUT = 0.1V to 1.65V, VOUT = 3.2V to 1.65V 100 98 113 VOUT Output Voltage Swing High Output Voltage Swing Low IOUT Output Short Circuit Current IS Supply Current SR Slew Rate (8) GBW m en Input Referred Voltage Noise Density in (6) (7) (8) Max (2) dB dB dB 2.1 12 14 18 LMV862, RL = 2 k to V+/2 12 16 19 LMV861, RL = 10 k to V+/2 3 4 5 LMV862, RL = 10 k to V+/2 3 6 7 LMV861, RL = 2 k to V+/2 8 12 16 LMV862, RL = 2 k to V+/2 10 14 17 LMV861, RL = 10 k to V+/2 2 4 5 LMV862, RL = 10 k to V+/2 3 7 8 Sourcing, VOUT = VCM, VIN = 100 mV 61 52 70 Sinking, VOUT = VCM, VIN = -100 mV 72 58 86 V dB LMV861, RL = 2 k to V+/2 mV from either rail mA LMV861 2.25 2.59 3.00 LMV862 4.42 5.02 5.77 mA 18 V/s Gain Bandwidth Product 30 MHz Phase Margin 70 deg Input Referred Current Noise Density AV = +1, VOUT = 1 VPP, 10% to 90% Units f = 1 kHz 8 f = 100 kHz 5 f = 1 kHz 0.015 nV/Hz pA/Hz The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/VOS). The specified limits represent the lower of the measured values for each output range condition. Number specified is the slower of positive and negative slew rates. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 3 LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 www.ti.com 3.3V Electrical Characteristics(1) (continued) Unless otherwise specified, all limits are guaranteed for TA = 25C, V+ = 3.3V, V- = 0V, VCM = V+/2, and RL =10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) ROUT Closed Loop Output Impedance CIN Common-Mode Input Capacitance 21 Differential-Mode Input Capacitance 15 THD+N Total Harmonic Distortion + Noise f = 20 MHz Typ (3) Max (2) f = 1 kHz, AV = 1, BW 500 kHz Units 80 pF 0.02 % 5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for T = 25C, V+ = 5V, V- = 0V, VCM = V+/2, and RL =10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) (4) Typ (3) Max (2) Units 273 1000 1260 V VOS Input Offset Voltage TCVOS Input Offset Voltage Temperature Drift (4) (5) 0.7 2.6 V/C IB Input Bias Current (5) 0.1 10 500 pA IOS Input Offset Current 1 (4) + 0V VCM V -1.2V 78 77 94 Power Supply Rejection Ratio (4) 2.7V V+ 5.5V, VOUT = 1V 77 76 93 EMI Rejection Ratio, IN+ and IN- (6) VRF_PEAK = 100 mVP (-20 dBVP), f = 400 MHz 70 VRF_PEAK = 100 mVP (-20 dBVP), f = 900 MHz 80 VRF_PEAK = 100 mVP (-20 dBVP), f = 1800 MHz 105 VRF_PEAK = 100 mVP (-20 dBVP), f = 2400 MHz 110 CMRR Common-Mode Rejection Ratio PSRR EMIRR CMVR Input Common-Mode Voltage Range CMRR 65 dB -0.1 AVOL Large Signal Voltage Gain (7) RL = 2 k VOUT = 0.15V to 2.5V, VOUT = 4.85V to 2.5V 103 100 111 RL = 10 k VOUT = 0.1V to 2.5V, VOUT = 4.9V to 2.5V 103 100 113 (1) (2) (3) (4) (5) (6) (7) 4 pA dB dB dB 3.9 V dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting distribution This parameter is specified by design and/or characterization and is not tested in production. The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/VOS). The specified limits represent the lower of the measured values for each output range condition. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 5V Electrical Characteristics(1) (continued) Unless otherwise specified, all limits are ensured for T = 25C, V+ = 5V, V- = 0V, VCM = V+/2, and RL =10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol VOUT Output Voltage Swing High, Output Voltage Swing Low, IOUT Output Short Circuit Current IS Typ (3) Max (2) LMV861, RL = 2 k to V+/2 13 15 19 LMV862, RL = 2 k to V+/2 13 17 20 LMV861, RL = 10 k to V+/2 3 4 5 LMV862, RL = 10 k to V+/2 3 6 7 LMV861, RL = 2 k to V+/2 10 14 18 LMV862, RL = 2 k to V+/2 12 17 20 LMV861, RL = 10 k to V+/2 3 4 5 LMV862, RL = 10 k to V+/2 3 7 8 Parameter Supply Current SR Slew Rate (8) GBW Gain Bandwidth Product m Phase Margin en Input Referred Voltage Noise Density Conditions Min (2) Sourcing, VOUT = VCM, VIN = 100 mV 90 86 150 Sinking, VOUT = VCM, VIN = -100 mV 90 86 150 2.47 2.84 3.27 LMV862 4.85 5.63 6.35 MHz 71 deg f = 1 kHz 8 f = 100 kHz 5 Input Referred Current Noise Density f = 1 kHz Closed Loop Output Impedance f = 20 MHz CIN Common-Mode Input Capacitance 20 Differential-Input Capacitance 15 (8) f = 1 kHz, AV= 1, BW 500 kHz V/s 31 ROUT Total Harmonic Distortion + Noise mA 20 in THD+N mV from either rail mA LMV861 AV = +1, VOUT = 2VPP, 10% to 90% Units nV/Hz 0.015 pA/Hz 60 0.02 pF % Number specified is the slower of positive and negative slew rates. Connection Diagram Figure 2. 5-Pin SC70 (Top View) Figure 3. 8-Pin VSSOP (Top View) Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 5 LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics At TA = 25C. RL = 10 k, V+ = 3.3V, V- = 0V, unless otherwise specified. VOS vs. VCM at V+ = 3.3V VOS vs. VCM at V+ = 5.0V 0.3 0.3 -40C 0.2 0.1 25C 0 -0.1 -0.2 25C 0 -0.1 -0.2 85C 125C -40C 0.1 VOS (mV) VOS (mV) 0.2 -0.3 85C 125C -0.3 + + V = 5.0V V = 3.3V -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -0.5 0.5 1.5 Figure 4. 3.5 VOS vs. Supply Voltage VOS vs. Temperature 150 100 -40C 0.1 50 VOS (PV) 0 3.3V 0 -50 -0.1 25C -100 85C -0.2 125C -0.3 2.5 3.0 3.5 4.0 4.5 5.0V -150 5.0 5.5 6.0 -200 -50 -25 0 25 50 75 TEMPERATURE (C) Figure 7. VOS vs. VOUT Input Bias Current vs. VCM at 25C TA = 25C IB (pA) 12 9 6 3 0 -3 -6 -9 -12 1 125 Figure 6. V = 5.0V, RL = 2k 0 100 VSUPPLY (V) + VOS (V) 5.5 200 0.2 2 3 VOUT (V) 4 5 5 4 3 2 1 0 -1 -2 -3 -4 -5 5V 3.3V -1 0 1 2 3 4 5 6 VCM (V) Figure 8. 6 4.5 Figure 5. 0.3 VOS (mV) 2.5 VCM (V) VCM (V) Figure 9. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 Typical Performance Characteristics (continued) At TA = 25C. RL = 10 k, V = 3.3V, V- = 0V, unless otherwise specified. + Input Bias Current vs. VCM at 85C Input Bias Current vs. VCM at 125C TA = 125C 50 40 30 20 10 0 -10 -20 -30 -40 -50 IBIAS (pA) IBIAS (pA) TA = 85C 5.0V 3.3V 500 400 300 200 100 0 -100 -200 -300 -400 -500 5.0V 3.3V -1 0 1 2 3 VCM (V) 4 5 6 -1 1 2 3 4 5 6 VCM (V) Figure 10. Figure 11. Supply Current vs. Supply Voltage Single LMV861 Supply Current vs. Supply Voltage Dual LMV862 3.4 6.0 125C 3.2 3.0 125C 85C 5.5 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 0 85C 2.8 2.6 2.4 25C 2.2 2.0 -40C 5.0 4.5 25C 4.0 -40C 3.5 1.8 1.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 3.0 2.5 6.0 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) Figure 12. Figure 13. 6.5 3.0 6.0 2.8 5.0V 2.6 2.4 2.2 3.3V 2.0 6.0 Supply Current vs. Temperature Dual LMV862 3.2 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 3.5 SUPPLY VOLTAGE (V) Supply Current vs. Temperature Single LMV861 5.5 5.0V 5.0 4.5 3.3V 4.0 3.5 1.8 1.6 -50 3.0 -25 0 25 50 75 100 125 3.0 -50 -25 0 25 50 75 TEMPERATURE (C) TEMPERATURE (C) Figure 14. Figure 15. 100 125 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 7 LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) At TA = 25C. RL = 10 k, V = 3.3V, V- = 0V, unless otherwise specified. + Sinking Current vs. Supply Voltage Sourcing Current vs. Supply Voltage 250 250 200 200 ISOURCE (mA) ISINK (mA) -40C 25C 150 100 85C 125C 25C 100 85C 50 50 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40C 150 6.0 2.5 3.0 4.0 4.5 6.0 Figure 17. Output Swing High vs. Supply Voltage RL = 2 k Output Swing High vs. Supply Voltage RL = 10 k 5 VOUT FROM RAIL HIGH (mV) RL = 2k 125C 15 85C 10 25C 5 0 2.5 -40C 3.0 3.5 4.0 4.5 5.0 5.5 RL = 10k 4 125C 85C 3 2 25C 1 -40C 0 2.5 6.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 18. Figure 19. Output Swing Low vs. Supply Voltage RL = 2 k Output Swing Low vs. Supply Voltage RL = 10 k 20 5 RL = 2k 125C RL = 10k 85C 125C VOUT FROM RAIL LOW (mV) VOUT FROM RAIL LOW (mV) 5.5 Figure 16. 20 15 10 25C -40C 5 0 2.5 8 5.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) VOUT FROM RAIL HIGH (mV) 3.5 125C 3.0 3.5 4.0 4.5 5.0 5.5 6.0 4 85C 3 25C 2 -40C 1 0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 20. Figure 21. Submit Documentation Feedback 5.5 6.0 Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 Typical Performance Characteristics (continued) At TA = 25C. RL = 10 k, V = 3.3V, V- = 0V, unless otherwise specified. + Output Voltage Swing vs. Load Current at V+ = 3.3V Output Voltage Swing vs. Load Current at V+ = 5.0V SINK 125C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 VOUT FROM RAIL (V) + -40C V = 3.3V 125C 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 125C 125C SOURCE 10 20 SOURCE 30 40 50 ILOAD (mA) 60 70 80 0 10 20 30 40 50 60 70 80 ILOAD (mA) Figure 23. Open Loop Frequency Response vs. Temperature Open Loop Frequency Response vs. Load Conditions 80 70 60 50 40 30 20 10 0 25C 85C 125C PHASE GAIN -40C 25C 85C 125C -40C CL = 5 pF 10k 120 105 90 75 60 45 30 15 0 GAIN (dB) Figure 22. PHASE () GAIN (dB) 0 + V = 5.0V -40C 100k 1M 10M 10k 100M 20 pF 120 5 pF 105 90 75 100 pF 60 50 pF 45 30 15 5 pF 0 80 PHASE 70 60 50 GAIN 40 30 20 10 CL = 5 pF 0 = 20 pF = 50 pF = 100 pF 100 pF 100k FREQUENCY (Hz) PHASE () VOUT FROM RAIL (V) SINK 1M 10M 100M FREQUENCY (Hz) Figure 24. Figure 25. Phase Margin vs. Capacitive Load PSRR vs. Frequency 3.3V 100 PSRR (dB) PHASE() 120 80 70 60 50 40 30 20 10 0 5.0V 80 60 40 -PSRR 3.3V 5.0V 20 +PSRR 0 + V = 3.3V, 5.0V 1 10 100 1000 100 CLOAD (pF) Figure 26. 1k 10k 100k 1M FREQUENCY (Hz) 10M Figure 27. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 9 LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) At TA = 25C. RL = 10 k, V = 3.3V, V- = 0V, unless otherwise specified. + CMRR vs. Frequency 80 DC CMRR 60 40 20 CHANNEL SEPARATION (dB) AC CMRR 100 CMRR (dB) Channel Separation vs. Frequency 160 140 120 100 80 60 + + V = 3.3V, 5.0V V = 3.3V, 5.0V 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 1k 100k 1M 10M FREQUENCY (Hz) Figure 29. Large Signal Step Response with Gain = 1 Large Signal Step Response with Gain = 10 200 mV/DIV 100 mV/DIV Figure 28. f = 1 MHz f = 1 MHz AV = +1 AV = +10 VIN = 500 mVPP VIN = 100 mVPP 100 ns/DIV 100 ns/DIV Figure 31. Small Signal Step Response with Gain = 1 Small Signal Step Response with Gain = 10 20 mV/DIV 20 mV/DIV Figure 30. f = 1 MHz f = 1 MHz AV = +1 AV = +10 VIN = 100 mVPP VIN = 10 mVPP 100 ns/DIV 100 ns/DIV Figure 32. 10 10k Figure 33. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 Typical Performance Characteristics (continued) At TA = 25C. RL = 10 k, V = 3.3V, V- = 0V, unless otherwise specified. + Slew Rate vs. Supply Voltage Input Voltage Noise vs. Frequency 30 100 28 FALLING EDGE 24 NOISE (nV/ Hz) SLEWRATE (V/s) 26 22 20 18 16 10 RISING EDGE 14 12 AV = +1 CL = 5 pF 10 2.5 3.0 3.5 1 V+ = 3.3V, 5.0V 4.0 4.5 5.0 5.5 6.0 10 100 100k Figure 34. Figure 35. THD+N vs. Frequency THD+N vs. Amplitude 1M + 0.1 BW = >500 kHz 10 + V =3.3V, VIN=320 mVPP 1 THD + N (%) 0.01 + V =5.0V, VIN=480 mVPP + V =3.3V, VIN=2.3 VPP 0.001 AV = 1x 100 AV = 1x 0.1 0.01 + V =5.0V, VIN=3.8 VPP 0.0001 V = 5.0V V = 3.3V + AV = 10x AV = 10x THD + N (%) 10k FREQUENCY (Hz) SUPPLY VOLTAGE (V) 10 1k 1k 0.001 f = 1 kHz BW = >500 kHz 10k 100k 1m 10m 100m 1 10 VOUT (VPP) FREQUENCY (Hz) Figure 36. Figure 37. ROUT vs. Frequency EMIRR IN+ vs. Power at 400 MHz 100 100 120 110 80 AV = 100x 60 1 40 0.1 AV = 10x 20 0.01 AV = 1x 0.001 100 1k 10k 100 EMIRR V_PEAK (dB) ROUT (O) 10 90 80 125C 85C 70 60 50 25C -40C 40 30 100k 1M 0 10M fRF = 400 MHz 20 -40 -30 -20 -10 0 FREQUENCY (Hz) RF INPUT PEAK VOLTAGE (dBVp) Figure 38. Figure 39. 10 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 11 LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) At TA = 25C. RL = 10 k, V = 3.3V, V- = 0V, unless otherwise specified. + EMIRR IN+ vs. Power at 1800 MHz 120 110 110 100 100 90 EMIRR V_PEAK (dB) EMIRR V_PEAK (dB) EMIRR IN+ vs. Power at 900 MHz 120 125C 85C 80 70 60 25C -40C 50 40 125C 85C 90 25C -40C 80 70 60 50 40 30 30 fRF = 900 MHz 20 -40 -30 -20 -10 0 fRF = 1800 MHz 20 -40 -30 -20 10 -10 0 RF INPUT PEAK VOLTAGE (dBVp) RF INPUT PEAK VOLTAGE (dBVp) Figure 40. Figure 41. EMIRR IN+ vs. Power at 2400 MHz EMIRR IN+ vs. Frequency 10 120 110 125C 85C EMIRRV_PEAK (dB) EMIRR V_PEAK (dB) 100 90 80 25C -40C 70 60 50 120 110 100 90 80 70 60 50 40 30 20 125C 85C 25C -40C 40 + V = 3.3V, 5.0V 30 fRF = 2400 MHz 20 -40 -30 -20 VRF PEAK == -20 dBVp V -20dBVp PEAK -10 0 10 10 RF INPUT PEAK VOLTAGE (dBVp) Figure 42. 12 100 1000 10000 FREQUENCY (MHz) Figure 43. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 APPLICATION INFORMATION INTRODUCTION The LMV861 and LMV862 are operational amplifiers with excellent specifications, such as low offset, low noise and a rail-to-rail output. These specifications make the LMV861 and LMV862 great choices for medical and instrumentation applications such as diagnosis equipment and power line monitors. The low supply current is perfect for battery powered equipment. The small packages, SC70 package for the LMV861, and the VSSOP package for the dual LMV862, make these parts a perfect choice for portable electronics. Additionally, the EMI hardening makes the LMV861 and LMV862 a must for almost all op amp applications. Most applications are exposed to Radio Frequency (RF) signals such as the signals transmitted by mobile phones or wireless computer peripherals. The LMV861 and LMV862 will effectively reduce disturbances caused by RF signals to a level that will be hardly noticeable. This again reduces the need for additional filtering and shielding. Using this EMI resistant series of op amps will thus reduce the number of components and space needed for applications that are affected by EMI, and will help applications, not yet identified as possible EMI sensitive, to be more robust for EMI. INPUT CHARACTERISTICS The input common mode voltage range of the LMV861 and LMV862 includes ground, and can even sense well below ground. The CMRR level does not degrade for input levels up to 1.2V below the supply voltage. For a supply voltage of 5V, the maximum voltage that should be applied to the input for best CMRR performance is thus 3.8V. When not configured as unity gain, this input limitation will usually not degrade the effective signal range. The output is rail-to-rail and therefore will introduce no limitations to the signal range. The typical offset is only 0.273 mV, and the TCVOS is 0.7 V/C, specifications close to precision op amps. CMRR MEASUREMENT The CMRR measurement results may need some clarification. This is because different setups are used to measure the AC CMRR and the DC CMRR. The DC CMRR is derived from VOS versus VCM. This value is stated in the tables, and is tested during production testing. The AC CMRR is measured with the test circuit shown in Figure 44. R2 1 k: + V + R1 1 k: - VIN LMV86x + R11 1 k: V BUFFER Buffer + VOUT - R12 V995: V BUFFER P1 10: Figure 44. AC CMRR Measurement Setup The configuration is largely the usually applied balanced configuration. With potentiometer P1, the balance can be tuned to compensate for the DC offset in the DUT. The main difference is the addition of the buffer. This buffer prevents the open-loop output impedance of the DUT from affecting the balance of the feedback network. Now the closed-loop output impedance of the buffer is a part of the balance. But as the closed-loop output impedance is much lower, and by careful selection of the buffer also has a larger bandwidth, the total effect is that the CMRR of the DUT can be measured much more accurately. The differences are apparent in the larger measured bandwidth of the AC CMRR. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 13 LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 www.ti.com One artifact from this test circuit is that the low frequency CMRR results appear higher than expected. This is because in the AC CMRR test circuit the potentiometer is used to compensate for the DC mismatches. So, mainly AC mismatch is all that remains. Therefore, the obtained DC CMRR from this AC CMRR test circuit tends to be higher than the actual DC CMRR based on DC measurements. The CMRR curve in Figure 45 shows a combination of the AC CMRR and the DC CMRR. AC CMRR 100 CMRR (dB) 80 DC CMRR 60 40 20 + V = 3.3V, 5.0V 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 45. CMRR Curve OUTPUT CHARACTERISTICS As already mentioned the output is rail-to-rail. When loading the output with a 10 k resistor the maximum swing of the output is typically 3 mV from the positive and negative rail. The output of the LMV861 and LMV862 can drive currents up to 70 mA at 3.3V, and even up to 150 mA at 5V. The LMV861 and LMV862 can be connected as non-inverting unity gain amplifiers. This configuration is the most sensitive to capacitive loading. The combination of a capacitive load placed at the output of an amplifier along with the amplifier's output impedance creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be under damped which causes peaking in the transfer and, when there is too much peaking, the op amp might start oscillating. The LMV861 and LMV862 can directly drive capacitive loads up to 200 pF without any stability issues. In order to drive heavier capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 46. By using this isolation resistor, the capacitive load is isolated from the amplifier's output, and hence, the pole caused by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive. VIN RISO VOUT + CL Figure 46. Isolating Capacitive Load A resistor value of around 50 would be sufficient. As an example some values are given in the following table, for 5V and an open loop gain of 111 dB. 14 CLOAD RISO 300 pF 62 400 pF 55 500 pF 50 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 When increasing the closed-loop gain the capacitive load can be increased even further. With a closed loop gain of 2 and a 27 isolation resistor, the load can be 1 nF EMIRR With the increase of RF transmitting devices in the world, the electromagnetic interference (EMI) between those devices and other equipment becomes a bigger challenge. The LMV861 and LMV862 are EMI hardened op amps which are specifically designed to overcome electromagnetic interference. Along with EMI hardened op amps, the EMIRR parameter is introduced to unambiguously specify the EMI performance of an op amp. This section presents an overview of EMIRR. A detailed description on this specification for EMI hardened op amps can be found in Application Note AN-1698. The dimensions of an op amp IC are relatively small compared to the wavelength of the disturbing RF signals. As a result the op amp itself will hardly receive any disturbances. The RF signals interfering with the op amp are dominantly received by the PCB and wiring connected to the op amp. As a result the RF signals on the pins of the op amp can be represented by voltages and currents. This representation significantly simplifies the unambiguous measurement and specification of the EMI performance of an op amp. RF signals interfere with op amps via the non-linearity of the op amp circuitry. This non-linearity results in the detection of the so called out-of-band signals. The obtained effect is that the amplitude modulation of the out-ofband signal is downconverted into the base band. This base band can easily overlap with the band of the op amp circuit. As an example Figure 47 depicts a typical output signal of a unity-gain connected op amp in the presence of an interfering RF signal. Clearly the output voltage varies in the rhythm of the on-off keying of the RF carrier. RF RF SIGNAL VOUT OPAMP (AV = 1) NO RF VOS + VDETECTED VOS Figure 47. Offset voltage variation due to an interfering RF signal EMIRR Definition To identify EMI hardened op amps, a parameter is needed that quantitatively describes the EMI performance of op amps. A quantitative measure enables the comparison and the ranking of op amps on their EMI robustness. Therefore the EMI Rejection Ratio (EMIRR) is introduced. This parameter describes the resulting input-referred offset voltage shift of an op amp as a result of an applied RF carrier (interference) with a certain frequency and level. The definition of EMIRR is given by: V * RF_PEAK EMIRRV RF_PEAK = 20 log 'V OS (c) where * * VRF_PEAK is the amplitude of the applied un-modulated RF signal (V) VOS is the resulting input-referred offset voltage shift (V) (1) The offset voltage depends quadratically on the applied RF level, and therefore, the RF level at which the EMIRR is determined should be specified. The standard level for the RF signal is 100 mVP. Application Note AN-1698 addresses the conversion of an EMIRR measured for an other signal level than 100 mVP. The interpretation of the EMIRR parameter is straightforward. When two op amps have EMIRRs which differ by 20 dB, the resulting error signals when used in identical configurations, differs by 20 dB as well. So, the higher the EMIRR, the more robust the op amp. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 15 LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 www.ti.com Coupling an RF Signal to the IN+ Pin Each of the op amp pins can be tested separately on EMIRR. In this section the measurements on the IN+ pin (which, based on symmetry considerations, also apply to the IN- pin) are discussed. In Application Note AN-1698 the other pins of the op amp are treated as well. For testing the IN+ pin the op amp is connected in the unity gain configuration. Applying the RF signal is straightforward as it can be connected directly to the IN+ pin. As a result the RF signal path has a minimum of components that might affect the RF signal level at the pin. The circuit diagram is shown in Figure 48. The PCB trace from RFIN to the IN+ pin should be a 50 stripline in order to match the RF impedance of the cabling and the RF generator. On the PCB a 50 termination is used. This 50 resistor is also used to set the bias level of the IN+ pin to ground level. For determining the EMIRR, two measurements are needed: one is measuring the DC output level when the RF signal is off; and the other is measuring the DC output level when the RF signal is switched on. The difference of the two DC levels is the output voltage shift as a result of the RF signal. As the op amp is in the unity gain configuration, the input referred offset voltage shift corresponds one-to-one to the measured output voltage shift. C2 10 F + VDD C3 100 pF RFin + R1 50: Out C4 100 pF C1 22 pF + VSS C5 10 F Figure 48. Circuit for coupling the RF signal to IN+ Cell Phone Call The effect of electromagnetic interference is demonstrated in a setup where a cell phone interferes with a pressure sensor application. The application is show in Figure 50. This application needs two op amps and therefore a dual op amp is used. The op amp configured as a buffer and connected at the negative output of the pressure sensor prevents the loading of the bridge by resistor R2. The buffer also prevents the resistors of the sensor from affecting the gain of the following gain stage. The op amps are placed in a single supply configuration. The experiment is performed on two different op amps: a typical standard op amp and the LMV862, EMI hardened dual op amp. A cell phone is placed on a fixed position a couple of centimeters from the op amps in the sensor circuit. When the cell phone is called, the PCB and wiring connected to the op amps receive the RF signal. Subsequently, the op amps detect the RF voltages and currents that end up at their pins. The resulting effect on the output of the second op amp is shown in Figure 49. 16 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 VOUT (0.5V/DIV) www.ti.com Typical Opamp LMV862 TIME (0.5s/DIV) Figure 49. Comparing EMI Robustness The difference between the two types of op amps is clearly visible. The typical standard dual op amp has an output shift (disturbed signal) larger than 1V as a result of the RF signal transmitted by the cell phone. The LMV862, EMI hardened op amp does not show any significant disturbances. This means that the RF signal will not disturb the signal entering the ADC when using the LMV862. R1 2.4 k: VDD VDD PRESSURE SENSOR + LMV862 - + R2 100: ADC LMV862 + VOUT Figure 50. Pressure Sensor Application DECOUPLING AND LAYOUT Care must be given when creating a board layout for the op amp. For decoupling the supply lines it is suggested that 10 nF capacitors be placed as close as possible to the op amp. For single supply, place a capacitor between V+ and V-. For dual supplies, place one capacitor between V+ and the board ground, and a second capacitor between ground and V-. Even with the LMV861 and LMV862 inherent hardening against EMI, it is still recommended to keep the input traces short and as far as possible from RF sources. Then the RF signals entering the chip are as low as possible, and the remaining EMI can be, almost, completely eliminated in the chip by the EMI reducing features of the LMV861 and LMV862. LOAD CELL SENSOR APPLICATION The LMV861 and LMV862 can be used for weight measuring system applications which use a load cell sensor. Examples of such systems are: bathroom weight scales, industrial weight scales and weight measurement devices on moving equipment such as forklift trucks. The following example describes a typical load cell sensor application that can be used as a starting point for many different types of sensors and applications. Applications in environments where EMI may appear would especially benefit from the EMIRR performance of the LMV861 and LMV862. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 17 LMV861, LMV862 SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 www.ti.com Load Cell Characteristics The load cell used in this example is a Wheatstone bridge. The value of the resistors in the bridge changes when pressure is applied to the sensor. This change of the resistor values will result in a differential output voltage depending on the sensitivity of the sensor, the used supply voltage and the applied pressure. The difference between the output at full scale pressure and the output at zero pressure is defined as the span of the load cell. A typical value for the span is 10 mV/V. The circuit configuration should be chosen such that loading of the sensor is prevented. Loading of the resistor bridge due to the circuit following the sensor, could result in incorrect output voltages of the sensor. Load Cell Example Figure 51 shows a typical schematic for a load cell application. It uses a single supply and has an adjustment for both positive and negative offset of the load cell. An ADC converts the amplified signal to a digital signal. The op amps A1 and A2 are configured as buffers, and are connected at both the positive and the negative output of the load cell. This is to prevent the loading of the resistor bridge in the sensor by the resistors configuring the differential op amp circuit (op amp A4). The buffers also prevent the resistors of the sensor from affecting the gain of the following gain stage. The third buffer (A3) is used to create a reference voltage, to correct for the offset in the system. Given the differential output voltage VS of the load cell, the output signal of this op amp configuration, VOUT, equals: R3 x V R3 R3 x VDD SENSE + VOUT = + 1 x VREF R1 (c) R5 R5 (2) (c) To align the pressure range with the full range of an ADC the correct gain needs to be set. To calculate the correct gain, the power supply voltage and the span of the load cell are needed. For this example a power supply of 5V is used and the span of the sensor, in this case a 125 kg sensor, is 100 mV. With the configuration as shown in Figure 51, this signal is covering almost the full input range of the ADC. With no weight on the load cell, the output of the sensor and the op amp A4 will be close to 0V. With the full weight on the load cell, the output of the sensor is 100 mV, and will be amplified with the gain from the configuration. In the case of the configuration of Figure 51 the gain is R3/R1 = 51 k/100 = 50. This will result in a maximum output of 100 mV x 50 = 5V, which covers the full range of the ADC. For further processing the digital signal can be processed by a microprocessor following the ADC, this can be used to display or log the weight on the load cell. To get a resolution of 0.5 kg, the LSB of the ADC should be smaller then 0.5 kg/125 kg = 1/1000. A 12-bit ADC would be sufficient as this gives 4096 steps. A 12-bit ADC such as the two channel 12-bit ADC122S021 can be used for this application. 18 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 VDD R5 5 k: VDD A1 - LOAD CELL + R3 5 k: R1 100: VDD LMV861 - + A4 ADC LMV861 VSENSE A2 - + R2 100: VOUT LMV861 + R4 5 k: VDD R6 80 k: P1 20 k: A3 - VREF LMV861 + R6 80 k: Figure 51. Load Cell Application IR PHOTODIODE APPLICATION The LMV861 and LMV862 are also very good choices to be used in photodiode applications, such as IR communication, monitoring, etc. The large bandwidth of the LMV861 and LM862 makes it possible to create high speed detection. This, together with the low noise, makes the LMV861 and LMV862 ideal for medical applications such as fetal monitors and bed side monitors. Another application where the LMV861 and LMV862 would fit perfectly is a bill validator, an instrument to detect counterfeit bank notes. The following example describes an application that can be used for different types of photodiode sensors and applications. IR Photodiode Example The circuit shown in Figure 53 is a typical configuration for the readout of a photodiode. The response of a photodiode to incoming light is a variation in the diode current. In many applications a voltage is required, i.e. when connecting to an ADC. Therefore the first step is to convert the diode signal current into a voltage by an I-V converter. In Figure 53 the left op amp is configured as an I-V converter, with a gain set by R1. Some types of photodiodes can have a large capacitance. This could potentially lead to oscillation. The addition of resistor R2 isolates the photodiode capacitance from the feedback loop, thereby preventing the loop from oscillating. The capacitor in between the two op amp configurations, blocks the DC component, thus removing the DC offset of the first op amp circuit, and the offset created by the ambient light entering the photodiode. The second op amp amplifies the signal to levels that can be converted to a digital signal by an ADC. To prevent floating of the input of the second op amp, resistor R5 is added. By allowing the input bias current of a few pA to flow through this resistor a stable input is ensured. In Figure 52 a sensed and amplified signal is shown from an IR source, in this case an IR remote control. The data from the ADC can then be used by a DSP or microprocessor for further processing. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 19 LMV861, LMV862 www.ti.com 1 V/DIV SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 20 s/DIV Figure 52. IR Photodiode Signal R1 100 k: R2 330: R5 1 M: VDD C1 1 nF - + LMV861 + IR Photodiode VDD VOUT LMV861 ADC VEE VEE R4 100: VEE R3 100 k: Figure 53. IR Photodiode Application 20 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 LMV861, LMV862 www.ti.com SNOSAZ5C - FEBRUARY 2008 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 19 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LMV861 LMV862 21 PACKAGE OPTION ADDENDUM www.ti.com 23-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMV861MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AEA LMV861MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AEA LMV861MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AEA LMV862MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AJ5A LMV862MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AJ5A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Oct-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMV861MG/NOPB SC70 DCK 5 LMV861MGE/NOPB SC70 DCK LMV861MGX/NOPB SC70 DCK LMV862MM/NOPB VSSOP LMV862MMX/NOPB VSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV861MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV861MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0 LMV861MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LMV862MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMV862MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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