[AK4128A]
MS1242-E-01 2011/06
- 1 -
GENERAL DESCRIPTION
The AK4128A is an 8ch digital sample rate converter (SRC). The input sample rate ranges from 8kHz to
216kHz. The output sample rate is from 8kHz to 216kHz. The AK4128A has an internal Oscillator and
does not need any external master clocks. It contributes simplifying a system configuration. The AK4128A
supports master mode and TDM data interface, enabling simultaneous input of asynchronous stereo
data. The AK4128A is suitable for the application interfacing to different sample rates such as
multi-channel high-end Car Audio Systems and DVD recorders.
FEATURES
• 8 channels input/output
• Asynchronous Sample Rate Converter
• Input Sample Rate Range (FSI): 8kHz ∼ 216kHz
• Output Sample Rate Range (FSO): 8kHz ∼ 216kHz
• Input to Output Sample Rate Ratio: 1/6 to 6
• THD+N: −130dB
• Dynamic Range: 140dB (A-weighted)
• I/F format: MSB justified, LSB justified and I2S compatible and TDM
• Oscillator for Internal Operation Clock
• Clock for Master mode: 128/256/384/512/768fso
• On-chip X’tal oscillator
• Digital De-emphasis Filter (32kHz, 44.1kHz and 48kHz)
• Soft Mute Function
• SRC Bypass mode (Master/Slave)
• μP Interface: I²C bus
• Power Supply: AVDD, DVDD1-4: 3.0 ∼ 3.6V (typ. 3.3V)
• Ta = −20 ∼ 85°C (AK4128AEQ), −40 ∼ 85°C (AK4128AVQ)
• Package: 64LQFP
8ch 216kHz / 24-Bit Asynchronous SRC
AK4128A
[AK4128A]
MS1242-E-01 2011/06
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Output
Serial
A
udio
I/F
DEM
Input
Serial
A
udio
I/F
SRC1
FIR SRC
SMUTE
+
Dither
Bypass
SRC
0.5 LSB
IBICK1
SDTI1
ILRCK1
DEM
Input
Serial
A
udio
I/F
SRC2
FIR SRC
SMUTE
+
Dither
Bypass
SRC
IBICK2
SDTI2
ILRCK2
SDTO1
SDTO2
DEM
Input
Serial
A
udio
I/F
SRC3
FIR SRC
SMUTE
+
Dither
Bypass
SRC
IBICK3
SDTI3
ILRCK3
SDTO3
DEM
Input
Serial
A
udio
I/F
SRC4
FIR SRC
SMUTE
+
Dither
Bypass
SRC
IBICK4
SDTI4
ILRCK4
SDTO4
MCKO
Clock
Div
CM2 CM1 CM0
IMCLK
Bypass
SRC
X’tal
Osc
OMCLK/XTI
XTO
OLRCK
OBICK
OBIT1
OBIT2
ODIF1
ODIF0
IDIF2
uP
I/F
SDA
SPB
CAD0
PDN
PM1
PM2
UNLOCK
A
VDD
VSS1
SCL
IDIF1
IDIF0
DEM1
DEM0
INAS
DVDD1-4
VSS2-5
SMSEMI
SMUTE
SMT1
SMT0
DITHER
0.5 LSB
0.5 LSB
0.5 LSB
Internal
OSC
Internal
Regulator REF
VD18
Figure 1. AK4128A Block Diagram (Synchronous mode INAS pin = “L”)
Output
Serial
A
udio
I/F
DEM
Input
Serial
A
udio
SRC1
FIR SRC
SMUTE +
Dither
Bypass
SRC
IBICK1
SDTI1
ILRCK1
DEM
Input
Serial
A
udio
SRC2
FIR SRC
SMUTE +
Dither
Bypass
SRC
IBICK2
SDTI2
ILRCK2
SDTO1
SDTO2
DEM
Input
Serial
A
udio
I/F
SRC3
FIR SRC
SMUTE +
Dither
Bypass
SRC
IBICK3
SDTI3
ILRCK3
SDTO3
DEM
Input
Serial
A
udio
I/F
SRC4
FIR SRC
SMUTE +
Dither
Bypass
SRC
IBICK4
SDTI4
ILRCK4
SDTO4
MCKO
Clock
Div
CM2 CM1 CM0
IMCLK
Bypass
SRC
X’tal
Osc
OMCLK/XTI
XTO
OLRCK
OBICK
OBIT1
OBIT0
SCL
0.5LSB
ODIF1
ODIF0
uP
I/F
SDA
SPB
CAD0
PDN
PM1
PM2
UNLOCK
A
VDD
VSS1
IDIF2
IDIF1
IDIF0
DEM1
DEM0
INAS
DVDD1-4
VSS2-5
SMSEMI
SMUTE
SMT1
SMT0
DITHER
I/F
I/F
0.5LSB
0.5LSB
0.5LSB
Internal
OSC
Internal
Regulator REF
VD18
Figure 2. AK4128A Block Diagram (Asynchronous mode INAS pin = “H”)
[AK4128A]
MS1242-E-01 2011/06
- 3 -
■ Compatibility with AK4126
(1) Specifications
Parameter AK4126 AK4128A
Stereo Inputs
Asynchronous Mode
Not Available
Synchronous Mode Only
Available
The INAS pin controls synchronous and
asynchronous modes.
Internal Clock Internal PLL
The PLL2-0 pins must be set
according to the PLL reference clock.
#61 pin: A pin for external devices of
PLL filter.
Internal Regulator + Internal Oscillator
PLL reference clock select is not needed since
internal oscillator generates the clock.
#61 pin: A capacitor pin for the internal regulator.
Bypass Mode Not Available Available
Controlled by CM2-0 pins or BYPS bit.
Master Mode for
Output Ports
Not Available Available
Controlled by CM2-0 pins
Maximum FSI and
FSO
192kHz 216kHz
Maximum IBICK and
OBICK Frequency
64fs 256fs
X’tal Oscillator Not Available Available
Master Clock Output Not Available Available
TDM Mode Not Available Available
Controlled by IDIF2-0 pins or IDIF2-0 bits (Input)
Controlled by TDM pin (Output)
Soft Mute All channels are controlled together. Individual Setting Available
Individual setting is available by setting SMUTE4-1
bits in serial control mode.
De-emphasis Filter All channels are controlled together. Individual Setting Available
Individual setting is available by DEM41-40,
31-30, 21-20, 11-10 bits in serial control mode.
Audio Format for
Input port.
All channels are controlled together. Individual Setting Available
Individual setting is available by IDIF42-40, 32-30,
22-20, 12-10 bits in serial control mode.
I2C Not Available Available
Parallel and Serial control modes are selected by the
SPB pin.
UNLOCK pin Detects PLL unlock. FSI:FSO Ratio Change Detect
Detects over-current/voltage of the 1.8V outputs.
[AK4128A]
MS1242-E-01 2011/06
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(2) Pins
Pin# AK4126 AK4128A
AK4128A pin 6ch mode AK4126 compatible
(PM2/1 pin = “LL”)
1 NC IBICK2 L
2 TEST0 IMCLK L
7 TST0 SDTI4 L
14 TST1 ILRCK3 L
15 TST2 IBICK3 L
16 NC ILRCK4 L
17 TST3 IBICK4 L
18 TST4 INAS L
32 TST5 PM2 L
33 NC TDM L
42 TST6 SDTO4 L
47 TEST4 OMCLK/XTI L
48 NC XTO L
49 NC MCKO L
51 TST8 CAD0 L
54 PLL2 TST1 L or H
55 PLL1 SMSEMI L or H
56 PLL0 TST2 L or H
57 TST9 SCL L
58 TST10 SDA L
59 NC SPB L
61 FILT VD18 *
63 TST11 TST3 AK4126: “Open”
AK4128A: “L”
64 NC ILRCK2 L
*: An external device is needed for the No 61 pin.
AK4126
C1
R
FILT
C2
AK4128A
VD18
1uF
Figure 3. AK4126 Figure 4. AK4128A
(Please refer to the AK4126 datasheet about external devices.)
[AK4128A]
MS1242-E-01 2011/06
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■ Ordering Guide
AK4128AEQ −20 ∼ +85°C 64pin LQFP (0.5mm pitch)
AK4128AVQ −40 ∼ +85°C 64pin LQFP (0.5mm pitch)
AKD4128A Evaluation Board for AK4128A
■ Pin Layout
MCKO
XTO
49
TST0
48
50
CAD0 51
DVDD4 52
VSS5 53
TS T1 5 4
SMSEMI 55
TS T2 5 6
SCL 57
SDA 58
SPB
OM CLK/XTI
47
OLRCK
4
6
45
44
VSS4
43
SDTO4
42
SDTO1
41
SDTO2
40
SDT O3
3
9
ODIF0
38
ILRCK4
1
IBICK2
2
IMCLK
3
ILRCK1
4
IBICK1
5
6
VSS2
7
SDTI4
8
SDTI1
9
SDTI2
10
SDTI3
11
32
31
30
29
28
27
26
25
24
23
22
PM2
OBIT1
OBIT0
PM1
DEM1
DEM0
SMT1
SMT0
PDN
DITHER
SMUTE
Top View
DVDD1
OBICK
DVDD3
ODIF1 3
7
IDIF0
12
59
AVDD 60 21 VSS3
VD18 61
VSS1 62
TS T3 63
ILRCK2 64
IDIF1
13
IDIF
2
14
ILRCK3
15
IBICK3
16
CM0
36
CM1
35
CM2
3
4
TDM
33
20
19
18
DVDD2
UNLOCK
INAS
17 IBICK4
[AK4128A]
MS1242-E-01 2011/06
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PIN / FUNCTION
No. Pin Name I/O Function
1 IBICK2 I Audio Serial Data Clock #2 Pin
When the INAS pin = “L”, this pin should be connected to VSS2-5.
2 IMCLK I Master Clock Input Pin for Input PORT
3 ILRCK1 I Input Channel Clock #1 Pin
4 IBICK1 I Audio Serial Data Clock #1 Pin
5 DVDD1 - Digital Power Supply Pin, 3.0 ∼ 3.6V
6 VSS2 - Digital Ground Pin
7 SDTI4 I Audio Serial Data Input #4 Pin
8 SDTI1 I Audio Serial Data Input #1 Pin
9 SDTI2 I Audio Serial Data Input #2 Pin
10 SDTI3 I Audio Serial Data Input #3 Pin
11 IDIF0 I Audio Interface Format #0 Pin for Input PORT (Note 2)
12 IDIF1 I Audio Interface Format #1 Pin for Input PORT (Note 2)
13 IDIF2 I Audio Interface Format #2 Pin for Input PORT (Note 2)
14 ILRCK3 I Input Channel Clock #3 Pin
When the INAS pin = “L”, this pin should be connected to VSS2-5.
15 IBICK3 I Audio Serial Data Clock #3 Pin
When the INAS pin = “L”, this pin should be connected to VSS2-5.
16 ILRCK4 I Input Channel Clock #4 Pin
When the INAS pin = “L”, this pin should be connected toVSS2-5.
17 IBICK4 I Audio Serial Data Clock #4 Pin
When the INAS pin = “L”, this pin should be connected to VSS2-5.
18 INAS I
Asynchronous Mode Select Pin.
“L”(connected to the ground): Synchronous mode.
“H”(connected to DVDD1-4) : Asynchronous mode.
19 UNLOCK O Unlock Status Pin
When the PDN pin= “L”, this pin outputs “H”.
20 DVDD2 - Digital Power Supply Pin, 3.0 ∼ 3.6V
21 VSS3 - Digital Ground Pin
22 SMUTE I Soft Mute Pin (Note 3) “H”: Soft Mute, “L”: Normal Operation
23 DITHER I Dither Enable Pin “H”: Dither ON, “L”: Dither OFF
24 PDN I
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
The AK4128A should be reset once by bringing PDN pin = “L” upon power-up.
25 SMT0 I Soft Mute Timer Select #0 Pin
26 SMT1 I Soft Mute Timer Select #1 Pin
27 DEM0 I De-emphasis Control #0 Pin (Note 4)
28 DEM1 I De-emphasis Control #1 Pin (Note 4)
29 PM1 I Channel Mode Select #1 Pin
30 OBIT0 I Bit Length Select #0 Pin for Output Data
31 OBIT1 I Bit Length Select #1 Pin for Output Data
32 PM2 I Channel Mode Select #2 Pin
33 TDM I
TDM Format Select Pin.
“L”(connected to the ground): Stereo mode.
“H”(connected to DVDD1-4) : TDM mode.
[AK4128A]
MS1242-E-01 2011/06
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No. Pin Name I/O Function
34 CM2 I Clock Select or Mode Select #2 Pin for Output PORT
35 CM1 I Clock Select or Mode Select #1 Pin for Output PORT
36 CM0 I Clock Select or Mode Select #0 Pin for Output PORT
37 ODIF1 I Audio Interface Format #1 Pin for Output PORT
38 ODIF0 I Audio Interface Format #0 Pin for Output PORT
39 SDTO3 O Audio Serial Data Output #3 Pin for Output PORT
When the PDN pin = “L”, the SDRO3 pin outputs “L”.
40 SDTO2 O Audio Serial Data Output #2 Pin for Output PORT
When the PDN pin = “L”, the SDTO2 pin outputs “L”.
41 SDTO1 O Audio Serial Data Output #1 Pin for Output PORT
When the PDN pin = “L”, the SDTO1 pin outputs “L”.
42 SDTO4 O Audio Serial Data Output #4 Pin for Output PORT
When the PDN pin = “L”, the SDRO4 pin outputs “L”.
43 VSS4 - Digital Ground Pin
44 DVDD3 - Digital Power Supply Pin, 3.0 ∼ 3.6V
45 OBICK I/ O
Audio Serial Data Clock Pin for Output PORT
When the PDN pin = “L” in master mode, the OBOCK pin outputs “L”.
46 OLRCK I/ O
Output Channel Clock Pin for Output PORT
When the PDN pin = “L” in master mode, the OBOCK pin outputs “L”.
47 OMCLK/XTI I External Master Clock Input / X’tal Input Pin
48 XTO O X’tal Output Pin
When the PDN pin = “L”, XTO outputs Hi-z.
49 MCKO O
Master Clock Output Pin
When the PM2 pin = “H” and PDN pin = “L”, the MCKO pin outputs “L”.
When the PM2 pin = “L” and PDN pin = “L”, the MCKO pin outputs Hi-z.
50 TST0 I Test Pin. This pin should be connected to VSS2-5.
51 CAD0 I Chip Address 0 pin
This pin must be connected to VSS2-5 in parallel control mode (SPB pin = “L”).
52 DVDD4 - Digital Power Supply Pin, 3.0 ∼ 3.6V
53 VSS5 - Digital Ground Pin
54 TST1 I Test Pin. This pin should be connected to VSS2-5.
55 SMSEMI I Soft Mute Semi-auto Mode Setting Pin
“H”: Semi-auto, “L”: Manual Mode
56 TST2 I Test Pin. This pin should be connected to VSS2-5.
57 SCL I
I2C Control Data Clock Pin, (when the SPB pin= “H”)
Since there is a protection diode between this pin and DVDD1-4, connect
pulled-up resister to DVDD1-4 + 0.3V or less. This pin must be connected to the
VSS2-5 in parallel control mode (PSB pin= “L”).
58 SDA I/ O
I2C Control Data In/Out put Pin, (when the SPB pin= “H”)
Since there is a protection diode between this pin and DVDD1-4, connect
pulled-up resister to DVDD1-4 + 0.3V or less. This pin must be connected to the
VSS2-5 in parallel control mode (PSB pin= “L”).
59 SPB I Parallel/Serial Control Mode Select Pin
“H”: Serial Control Mode, “L”: Parallel Control Mode
[AK4128A]
MS1242-E-01 2011/06
- 8 -
No. Pin Name I/O Function
60 AVDD - Analog Power Supply Pin, 3.0 ∼ 3.6V
61 VD18 O
Digital Power Output Pin, Typ 1.8V
When the PDN pin= “L”, the DV18 pin outputs “L”. Current must not be taken
from this pin. A 1μF (±30%; including the temperature characteristics) capacitor
should be connected between this pin and DVSS. When this capacitor is polarized,
the positive polarity pin should be connected to the VD18 pin.
62 VSS1 - Analog Ground Pin
63 TST3 I Test Pin.
This pin should be connected to VSS2-5.
64 ILRCK2 I Input Channel Clock #2 Pin
When INAS pin = “L”, this pin should be connected to VSS2-5.
Note: All input pins should not be left floating. DVDD1-4 must be connected to the same power supply.
Note 1. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD0 pin must be changed when the PDN
pin= “L”.
Note 2. In parallel control mode (SPB pin = “L”), IDIF2-0 pins control all SRC1~4 audio interface input formats.
In serial control mode (SPB pin = “H”), the setting of IDIF2-0 pins is ignored. The IDIF[12:10] bits setting is
reflected to SRC1, the IDIF[22:20] bits setting is reflected to SRC2, the IDIF[32:30] bits setting is reflected to
SRC3, and the IDIF[42:40] bits setting is reflected to SRC4.
Note 3. In parallel control mode (SPB pin = “L”), the SMUTE pin controls all SRC1~4 soft mute.
In serial control mode (SPB pin = “H”), the SUMUTE pin setting is ignored. The SMUTE1 bit setting is
reflected to SRC1, the SMUTE2 bit setting is reflected to SRC2, the SMUTE3 bit setting is reflected to SRC3,
and the SMUTE4 bit setting is reflected to SRC4.
Note 4. In parallel control mode (SPB pin= “L”), DEM1-0 pins control all SRC1~4 de-emphasis settings.
In serial control mode (SPB pin= “H”), setting of DEM1-0 pins is ignored. DEM[11:10] bits setting is reflected
to SRC1, DEM[21:20] bits setting is reflected to SRC2, DEM[31:30] bits setting is reflected to SRC3, and
DEM[41:40] bits setting is reflected to SRC4.
■ Handling of Unused Pins
The unused I/O pins should be processed appropriately as below.
Classification Pin Name Setting
IBICK2, IMCLK, SDTI3-4, ILRCK3,
IBICK3, ILRCK4, IBICK4, SMUTE,
DITHER, OMCLK/XTI, ILRCK2,
SDA, SCL, CAD0, TST0-3
These pins must be connected to VSS2-5.
Digital
UNLOCK, SDTO1-4, MCKO, XTO These pins must be open.
[AK4128A]
MS1242-E-01 2011/06
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ABSOLUTE MAXIMUM RATINGS
(VSS1-5=0V; Note 5)
Parameter Symbol min max Units
Power Supplies: Analog
Digital
AVDD
DVDD1-4
−0.3
−0.3
4.2
4.2
V
V
Input Current, Any Pin Except Supplies IIN - ±10 mA
Digital Input Voltage (Note 6) VIND −0.3 DVDD1-4+0.3 V
AK4128AEQ Ta −20 85 °C Ambient Temperature
(Power applied) (Note 7) AK4128AVQ Ta −40 85 °C
Storage Temperature Tstg −65 150 °C
Note 5. All voltages with respect to ground. VSS1-5 must be connected to the same ground.
Note 6. IMCLK, IBICK4-1, ILRCK4-1, IDIF2-0, INAS, SUMTE, DITHER, PDN, SMT1-0, DEM1-0, PM2-1, OBIT1-0,
TDM, CM2-0, ODIF1-0, SDTO4-1, OBICK, OLRCK, OMCLK/XTI, CAD0, SMSEMI, SCL, SDA and SPB
pins.
Note 7. In case that wiring density is 100%.
Note 8. DVDD1-4 pins must be connected to the same power supply.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1-5=0V; Note 5)
Parameter Symbol min typ max Units
Power Supplies:
(Note 9)
Analog
Digital
AVDD
DVDD1-4
3.0
3.0
3.3
3.3
3.6
3.6
V
V
Difference AVDD - DVDD1-4 -0.3 0 +0.3 V
Note 5. All voltages with respect to ground. VSS1-5 must be connected to the same ground.
Note 8. DVDD1-4 pins must be connected to the same power supply.
Note 9. The power up sequence between AVDD and DVDD1-4 is not critical but the PDN pin must be “L” until all power
supplies are ON, then put the PDN pin to “H”.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4128A]
MS1242-E-01 2011/06
- 10 -
SRC CHARACTERISTICS
(Ta=25°C; AVDD=DVDD1-4=3.3V; VSS1-5=0V; Signal Frequency = 1kHz; data = 24bit;
Measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.)
Parameter Symbol min typ max Units
SRC Characteristics:
Resolution 24 Bits
Input Sample Rate FSI 8 216 kHz
Output Sample Rate FSO 8 216 kHz
THD+N (Input = 1kHz, 0dBFS, Note 10)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case (FSO/FSI = 32kHz/176.4kHz)
-
-
-
-
-
−130
−124
−133
−124
-
-
-
-
-
-91
dB
dB
dB
dB
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 10)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case (FSO/FSI = 48kHz/32kHz)
Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 10)
FSO/FSI = 44.1kHz/48kHz
-
-
-
-
132
-
136
136
136
132
-
140
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Ratio between Input and Output Sample Rate FSO/FSI 1/6 6 -
Note 10. Measured by Audio Precision System Two Cascade.
POWER CONSUMPTION
(Ta= 25°C; AVDD=DVDD1-4=3.0~3.6V; VSS1-5=0V; Signal Frequency=1kHz; data=24bit; Asynchronous Input mode
(INAS pin = “H”), Output PORT: Master mode, OMCLK/XTI are input via a X’tal. PM2/1 pin = “H/L” 8ch mode, unless
otherwise specified.)
Parameter min typ max Units
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD+DVDD1-4
FSI=FSO=48kHz: AVDD=DVDD1-4=3.3V (Note 12)
FSI=FSO=192kHz: AVDD=DVDD1-4=3.3V (Note 13)
: AVDD=DVDD1-4=3.6V (Note 14)
Power down (PDN pin = “L”) (Note 11)
AVDD+DVDD1-4
42
108
109
10
-
-
164
100
mA
mA
mA
μA
Note 11. All digital input pins are held to VSS2-5.
Note 12. It is 41 [mA] (typ) when the OMCLK/XTI pin is supplied a 24.576MHz external clock and the output port is in
slave mode.
Note 13. It is 105 [mA] (typ) when the OMCLK/XTI pin is supplied a 24.576MHz external clock and the output port is in
slave mode.
Note 14. It is 106 [mA] (typ) when the OMCLK/XTI pin is supplied a 24.576MHz external clock and the output port is in
slave mode.
[AK4128A]
MS1242-E-01 2011/06
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FILTER CHARACTERISTICS
(Ta= 25°C; AVDD=DVDD1-4=3.0 ∼ 3.6V)
Parameter Symbol min typ max Units
Digital Filter
0.985 ≤ FSO/FSI ≤ 6.000 PB 0 0.4583FSI kHz
0.905 ≤ FSO/FSI < 0.985 PB 0 0.4167FSI kHz
0.714 ≤ FSO/FSI < 0.905 PB 0 0.3195FSI kHz
0.656 ≤ FSO/FSI < 0.714 PB 0 0.2852FSI kHz
0.536 ≤ FSO/FSI < 0.656 PB 0 0.2182FSI kHz
0.492 ≤ FSO/FSI < 0.536 PB 0 0.2177FSI kHz
0.452 ≤ FSO/FSI < 0.492 PB 0 0.1948FSI kHz
0.357 ≤ FSO/FSI < 0.452 PB 0 0.1458FSI kHz
0.324 ≤ FSO/FSI < 0.357 PB 0 0.1302FSI kHz
0.246 ≤ FSO/FSI < 0.324 PB 0 0.0917FSI kHz
0.226 ≤ FSO/FSI < 0.246 PB 0 0.0826FSI kHz
Passband −0.01dB
0.1667 ≤ FSO/FSI < 0.226 PB 0 0.0583FSI kHz
0.985 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI kHz
0.905 ≤ FSO/FSI < 0.985 SB 0.5021FSI kHz
0.714 ≤ FSO/FSI < 0.905 SB 0.3965FSI kHz
0.656 ≤ FSO/FSI < 0.714 SB 0.3643FSI kHz
0.536 ≤ FSO/FSI < 0.656 SB 0.2974FSI kHz
0.492 ≤ FSO/FSI < 0.536 SB 0.2813FSI kHz
0.452 ≤ FSO/FSI < 0.492 SB 0.2604FSI kHz
0.357 ≤ FSO/FSI < 0.452 SB 0.2116FSI kHz
0.324 ≤ FSO/FSI < 0.357 SB 0.1969FSI kHz
0.246 ≤ FSO/FSI < 0.324 SB 0.1573FSI kHz
0.226 ≤ FSO/FSI < 0.246 SB 0.1471FSI kHz
Stopband
0.1667 ≤ FSO/FSI < 0.226 SB 0.1020FSI kHz
Passband Ripple PR ±0.01 dB
0.985 ≤ FSO/FSI ≤ 6.000 SA 121.2 dB
0.905 ≤ FSO/FSI < 0.985 SA 121.4 dB
0.714 ≤ FSO/FSI < 0.905 SA 115.3 dB
0.656 ≤ FSO/FSI < 0.714 SA 116.9 dB
0.536 ≤ FSO/FSI < 0.656 SA 114.6 dB
0.492 ≤ FSO/FSI < 0.536 SA 100.2 dB
0.452 ≤ FSO/FSI < 0.492 SA 103.3 dB
0.357 ≤ FSO/FSI < 0.452 SA 102.0 dB
0.324 ≤ FSO/FSI < 0.357 SA 103.6 dB
0.246 ≤ FSO/FSI < 0.324 SA 103.3 dB
0.226 ≤ FSO/FSI < 0.246 SA 101.5 dB
Stopband
Attenuation
0.1667 ≤ FSO/FSI < 0.226 SA 73.2 dB
Group Delay (Note 15) GD - 64 - 1/fs
Note 15. This value is the time from the rising edge of ILRCK after SDTI data is input to rising edge of OLRCK after the
SDTI data is output, when OLRCK data corresponds with ILRCK data.
[AK4128A]
MS1242-E-01 2011/06
- 12 -
DC CHARACTERISTICS
(Ta= 25°C; AVDD=DVDD1-4=3.0 ∼ 3.6V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%DVDD1-4
-
-
-
-
30%DVDD1-4
V
V
High-Level Output Voltage
Except the SDA pin (Iout=−400μA)
Low-Level Output Voltage
Except the SDA pin (Iout=400μA)
SDA pin (Iout=3mA)
VOH
VOL
VOL
DVDD1-4 − 0.4
-
-
-
-
0.4
0.4
V
V
V
Input Leakage Current Iin - - ±10 μA
SWITCHING CHARACTERISTICS
(Ta= 25°C; AVDD=DVDD1-4=3.0 ∼ 3.6V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Crystal Oscillator Frequency fXTAL 11.2896 24.576 MHz
IMCLK Input
Frequency
Duty
fECLK
dECLK
1.024
40
50
36.864
60
MHz
%
OMCLK Input
128 FSO :
Pulse Width Low
Pulse Width High
256 FSO :
Pulse Width Low
Pulse Width High
384 FSO :
Pulse Width Low
Pulse Width High
512 FSO :
Pulse Width Low
Pulse Width High
768 FSO :
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
1.024
13
13
2.048
13
13
3.072
10
10
4.096
13
13
6.144
10
10
27.648
27.648
36.864
27.648
36.864
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MCKO Output
Frequency
Duty (Note 16)
fMCK
dMCLK
1.024
40
50
36.864
60
MHz
%
Note 16. This is a value of MCKO output duty when the master clock for output ports is supplied by a crystal oscillator.
[AK4128A]
MS1242-E-01 2011/06
- 13 -
Input PORT LRCK for Stereo Mode (ILRCK1-4)
Frequency
Duty Cycle Slave Mode
FSI
Duty
8
48
50
216
52
kHz
%
Output PORT LRCK for Stereo Mode (OLRCK)
Frequency
Slave mode
Master mode OMCLK Input 128FSO mode
Master mode OMCLK Input 256FSO mode
Master mode OMCLK Input 384FSO mode
Master mode OMCLK Input 512FSO mode
Master mode OMCLK Input 768FSO mode
Duty Cycle Slave Mode
Master Mode
FSO
FSO
FSO
FSO
FSO
FSO
Duty
Duty
8
8
8
8
8
8
48
50
50
216
216
108
96
54
48
52
kHz
kHz
kHz
kHz
kHz
kHz
%
%
Input PORT LRCK for TDM256 Mode (ILRCK1)
Asynchronous Inputs Mode (INAS pin = “L”)
Frequency
“H” time (slave mode)
“L” time (slave mode)
FSI
tLRH
tLRL
8
1/256FSI
1/256 FSI
48
kHz
ns
ns
Output PORT LRCK for TDM256 Mode (OLRCK)
Frequency
“H” time (slave mode)
“L” time (slave mode)
“H” time
(Master mode, TDM256 24bit MSB justified)
“L” time
(Master mode, TDM256 24bit I2S)
FSO
tLRH
tLRL
tLRH
tLRL
8
1/256 FSO
1/256 FSO
-
-
1/8 FSO
1/8 FSO
48
-
-
kHz
ns
ns
ns
ns
Audio Interface Timing
Input PORT ( Stereo Slave mode)
IBICK1-4 Period (FSI= 8kHz ∼ 54kHz)
(FSI=54kHz ∼ 108kHz)
(FSI=108kHz ∼ 216kHz)
IBICK1-4 Pulse Width Low
Pulse Width High
ILRCK1-4 Edge to IBICK1-4 “↑”(Note 17)
IBICK1-4 “↑” to ILRCK1-4 Edge (Note 17)
SDTI1-4 Hold Time from IBICK1-4 “↑”
SDTI1-4 Setup Time to IBICK1-4 “↑”
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/256 FSI
1/128 FSI
1/64 FSI
27
27
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input PORT (TDM256 slave mode)
IBICK1 Period
IBICK1 Pulse Width Low
Pulse Width High
ILRCK1 Edge to IBICK1 “↑” (Note 17)
IBICK1 “↑” to ILRCK1 Edge (Note 17)
SDTI1 Hold Time from IBICK1 “↑”
SDTI1 Setup Time to IBICK1 “↑”
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
81
32
32
20
20
20
10
ns
ns
ns
ns
ns
ns
ns
Output PORT ( Stereo Slave mode)
OBICK Period (FSO= 8kHz ∼ 54kHz)
(FSO= 54kHz ∼ 108kHz)
(FSO=108kHz ∼ 216kHz)
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to OBICK “↑” (Note 17)
OBICK “↑” to OLRCK Edge (Note 17)
OLRCK to SDTO1-4 (MSB) (Except I2S mode)
OBICK “↓” to SDTO1-4
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/256 FSO
1/128 FSO
1/64 FSO
27
27
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
[AK4128A]
MS1242-E-01 2011/06
- 14 -
Output PORT (TDM256 slave mode)
OBICK Period
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to OBICK “↑” (Note 17)
OBICK “↑” to OLRCK Edge (Note 17)
OBICK “↓” to SDTO1
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
81
32
32
20
20
20
ns
ns
ns
ns
ns
ns
Output PORT (Stereo Master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK Edge
OBICK “↓” to SDTO1-4
fBCK
dBCK
tMBLR
tBSD
−20
−20
64 FSO
50
20
20
Hz
%
ns
ns
Output PORT (TDM256 master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK Edge
OBICK “↓” to SDTO1
fBCK
dBCK
tMBLR
tBSD
-
-
−10
−20
256 FSO
50(Note 19)
-
-
-
10
20
Hz
%
ns
ns
Reset Timing
PDN Pulse Width (Note 18)
tPD
150
ns
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. The AK4128A can be reset by bringing the PDN pin = “L”.
Note 19. When OMCLK=512FSO. If the OMCLK=256FSO, OMCLK clock is though and output from the OBICK pin.
When OMCLK = 384FSO, dBCK= (tCLKH)/(tCLKH+1/fCLK) x100 [%] or (tCLKL)/(tCLKL+1/fCLK) x100
[%]. When OMCLK=768FSO, dBCK= (1/fCLK)/(3/fCLK) x100 [%].
OMCLK=384FSO
OMCLK=768FSO
O M C LK pin
tCLKH
tCLKL tCLKL
1/fCLK 1/fCLK
tCLKH tCLKL
1/fCLK 1/fCLK
OBI CK pin Oupu t
(TDM256
Mast er m ode)
OM C LK pin
1/fCLK
3/fCLK 3/fCLK
OB ICK pin Output
(TDM256
Mast er m ode)
1/fCLK
1/fCLK
1/fCLK
[AK4128A]
MS1242-E-01 2011/06
- 15 -
Parameter Symbol min typ max Units
Control Interface Timing (I2C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 20)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Capacitive load on bus
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
[AK4128A]
MS1242-E-01 2011/06
- 16 -
1/fCLK
OMCLK(I) VIH
VIL
1/fMCK
tMCKL
50%DVDD
tMCKH
MCKO(O)
tCLKLtCLKH
1/fECLK
tECLKL
VIH
tECLKH
IMCLK(I) VIL
dEC LK
= tECLKH (or tECLKL) x fECLK x 100
dMCLK
= tMCKH (or tMCKL) x fMCK x 100
1/FSI
LRCK1- 4(I) VIH
VIL
tLRCLtLRCH
tBCK
tBCKL
VIH
tBCKH
IBICK1 -4(I) VIL
•S tereo M ode and Slave Mode
Duty
= tLRCH (or tLRCL) x FSI x 100
1/FSI
LRCK1(I) VIH
VIL
tLRL tLRH
tBCK
tBCKL
VIH
tBCKH
IBICK1 (I) VIL
•TDM256 Mode and Slave Mode
■ Timing Diagram
Figure 5. IMCLK, OMCLK, MCKO Clock Timing
Figure 6. ILRCK1-4, IBICK1-4 Clock Timing
[AK4128A]
MS1242-E-01 2011/06
- 17 -
1/FSO
OLRCK(I) VIH
VIL
tLRCLtLRCH
tBCK
tBCKL
VIH
tBCKH
OBICK (I) VIL
• Stereo Mode an d Slav e Mode
Duty
= tLRC H (or t L RCL) x FS O x 100
1/FSO
OLRCK(I) VIH
VIL
tLRL tLRH
tBCK
tBCKL
VIH
tBCKH
OBICK (I) VIL
• TDM256 Mode and Slave Mode
1/FSO
OLRCK(O) 50%DVDD
tLRCLtLRCH
1/ fBCK
tBICKL
50% DVDD
tBICKH
OBICK(O)
• Stereo Mode and Master Mode
Duty
= tLRCH (or tLRCL) x FSO x 100
• TDM256 Mode and Master Mode
dBCK
= tBICKH(or tBICKL) x fBCK x 100
1/FSO
OLRCK(O)
24bit MSB justified
50%DVDD
tLRH
1/ fBC K
tBICKL
50% DVDD
tBICKH
OBICK(O)
dBCK
= tBICKH(or tBICKL) x fBCK x 100
1/FSO
OLRCK(O)
24bit I2S
50%DVDD
tLRL
Figure 7. OLRCK, OBICK, Clock Timing (Slave Mode)
Figure 8. OLRCK, OBICK, Clock Timing (Master Mode)
[AK4128A]
MS1242-E-01 2011/06
- 18 -
Figure 9. Input PORT Audio Interface Timing (Stereo Slave mode and TDM256 Slave Mode)
Figure 10. Output PORT Audio Interface Timing (TDM256 Slave mode & Stereo Slave mode)
tLRB
ILRCK 1 - 4
VIH
IBICK 1 - 4
VIL
VIH
VIL
tBLR
tSDS
SDTI 1 - 4
VIH
VIL
tSDH
tLRB
O LRCK
VIH
O BICK VIL
SDTO 1 - 4
50% D VDD
VIH
VIL
tBLR
tLRS
tBSD
[AK4128A]
MS1242-E-01 2011/06
- 19 -
tHIGH
SCL
SDA VIH
tLOW
tBUF
tHD:STA
tR tF
tHD:DAT tSU:DAT tSU:STA
Stop Start Start Stop
tSU:STO
VIL
VIH
VIL
tSP
OLRCK
OBICK
SDTO1-4
tBSD
tMBLR
50% DVDD
50% DVDD
50%DVDD
Figure 11. Output PORT Audio Interface Timing (TDM256 Master mode & Stereo Master mode)
tPD
PDN VIL
Figure 12. Power Down Timing
Figure 13. I2C Bus Timing
[AK4128A]
MS1242-E-01 2011/06
- 20 -
OPERATION OVERVIEW
■ Synchronous and Asynchronous Modes Setting
There are two modes of operation: asynchronous and synchronous modes. The AK4128A is set to Synchronous mode
when the INAS pin is “L” and it is set to Asynchronous mode when the INAS pin is “H”.
FSI pin Mode Data LRCK BICK
SDTI1
SDTI2
SDTI3
L Synchro
nous
SDTI4
ILRCK1
(Note 21)
IBICK1
(Note 22)
SDTI1 ILRCK1 IBICK1
SDTI2 ILRCK2 IBICK 2
SDTI3 ILRCK3 IBICK 3
H Asynchr
onous
SDTI4 ILRCK4 IBICK 4
Note 21. ILRCK2-4 pins must be connected to VSS2-5.
Note 22. IBICK2-4 pins must be connected to VSS2-5.
Table 1. Input Data Synchronous/Asynchronous Mode Setting
■ Audio Interface Format for Input PORT
The audio data format of input port is MSB first, 2’s complement format. The SDTI1, SDTI2, SDTI3 and SDTI4 are
latched on the rising edge of IBICK1, IBICK2, IBIXK3 and IBICK4 respectively.
In parallel control mode (SPB pin= “L”), IDIF2-0 pins control all audio interface formats of SRC1~4. IDIF2-0 pins must be
set during the PDN pin= “L”.
In serial control mode (SPB pin = “H”), setting of IDIF2-0 pins is ignored. IDIF[12:10] bits setting is reflected to SRC1,
IDIF[22:20] bits setting is reflected to SRC2, IDIF[32:30] bits setting is reflected to SRC3, and IDIF[42:40] bits setting is
reflected to SRC4.
IDIF[12:10] bits should be changed after all SDTO1 output codes become zero during soft mute by SMUTE1 bit = “1” or
the SMUTE pin = “H”. IDIF[22:20] bits should be changed after all SDTO2 output codes become zero during soft mute by
SMUTE2 bit = “1” or the SMUTE pin = “H”. IDIF[32:30] bits should be changed after all SDTO3 output codes become
zero during soft mute by SMUTE3 bit = “1” or the SMUTE pin = “H”. IDIF[42:40] bits should be changed after all SDTO4
output codes become zero during soft mute by SMUTE4 bit = “1” or the SMUTE pin = “H”.
TDM mode (Mode 5/6) can be set in Synchronous Inputs mode (INAS pin = “L”). Serial data for 8channels should be input
from the SDTI1 pin. In this mode, connect SDTI2-4 pins to VDD2-5 because there pins are ignored.
Asynchronous Inputs mode (INAS pin = “H”) does not support TDM mode. The AK4128A is not able to operate correctly
because of SDTI1-4 data inputs are incorrect. TDM mode is must be OFF, when using the AK4128A in asynchronous
inputs mode (INAS pin = “H”). The maximum input frequency of IBICK1-4 is 256FSI.
[AK4128A]
MS1242-E-01 2011/06
- 21 -
Mode
IDIF2
Pin
(Note 23)
IDIF1
Pin
(Note 23)
IDIF0
Pin
(Note 23)
SDTI1-4 Format ILRCK
1-4
IBICK
1-4
IBICK1-4
Freq
0 L L L 16bit, LSB justified ≥ 32FSI
1 L L H 20bit, LSB justified ≥ 40FSI
2 L H L 24bit, MSB justified ≥ 48FSI
24 or 16bit, I2S Compatible ≥ 48FSI
3 L H H 16bit, I2S Compatible 32FSI
4 H L L 24bit, LSB justified ≥ 48FSI
5 H L H TDM 24bit, MSB justified 256FSI
6 H H X TDM 24bit, I2S Compatible
Input Input
256FSI
Table 2. Input PORT Audio Interface Format (Parallel Control Mode, SPB pin= “L”) (X= Don’t care)
Note 23. In serial control mode (SPB pin = “H”), setting of IDIF2-0 pins is ignored. IDIF[12:10] bits setting is reflected to
SRC1, IDIF[22:20] bits setting is reflected to SRC2, IDIF[32:30] bits setting is reflected to SRC3, and
IDIF[42:40] bits setting is reflected to SRC4.
ILRCK
IBICK(32fs) 01102 3 9 1112131415 0 123 10109 1112131415
SDTI(i) Don't Care 1 0 15 14 13 21015 14 13 12 12Don't Care
15:MSB, 0:LSB
SDTI(i) 15 14 13 7654321015 14 13 1576543210
IBICK(64fs) 01182 3 19 20 31 0 1 2 3 1018 19 20 3117 17
Lch Data Rch Data
Figure 14. Mode 0 Timing (16bit, LSB justified)
ILRCK
IBICK(64fs) 0 1 22431012 103124
SDTI(i) Don't Care 0 8 10
19:MSB, 0:LSB
Lch Data Rch Data
19 8 Don't Care 191
12 13 1312
Figure 15. Mode 1 Timing (20bit, LSB justified)
ILRCK
IBICK(64fs) 0 1 220212431012 102220 21 312422 23 23
SDTI(i) Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 231234
Figure 16. Mode 2 Timing (24bit, MSB justified)
[AK4128A]
MS1242-E-01 2011/06
- 22 -
ILRCK
IBICK(64fs) 0122521 24 0 12 1022 2521 2422 23 233
SDTI(i) Don't C are0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 1234
Figure 17. Mode 3 Timing (24bit I2S)
ILRCK
IBICK(64fs) 0 1 22431012 10312489 89
SDTI(i) Don't Care 0 8 10
23:MSB, 0:LSB
Lch Data Rch Data
23 8 Don't Care 231
Figure 18. Mode 4 Timing (24bit, LSB justified)
Note: SDTI is identified as SDTI1, SDTI2, SDTI3 and SDTI4, ILRCK is identified as ILRCK1, ILRCK2, ILRCK3 and
ILRCK4, IBICK is identified as IBICK1, IBICK2, IBICK3 and IBICK4.
23
ILRCK1(I)
IBICK1 ( I: 25 6 FSI)
SDTI1(I) 22 0
L1
32 IBICK
256 IBICK
22 0
R1
32 IBICK
2223 2323 22 0
L2
3 2 IBICK
22 0
R2
32 IBICK
23 23 22 0
L3 22 0
R3
23 23 22 0
L4 22 0
R4
23
32 IBICK 3 2 I BICK 32 I BICK 32 I BICK
Figure 19. Mode 5 Timing (TDM, 24bit, MSB justified, SDTI2-4: Don’t care)
ILRCK1(I)
IBICK1( I: 25 6F SI)
SDTI1(I) 23 0
L1
256 IBICK
23 0
R1
2323 0
L2
23 0
R2
23 0
L3
23 0
R3
23 0
L4
23 0
R4
32 IBIC K 32 IBICK 32 IBICK 32 IBICK 32 IBICK 32 IBICK 32 IBICK 32 IBICK
Figure 20. Mode 6 Timing (TDM, I2S, SDTI2-4: Don’t care)
[AK4128A]
MS1242-E-01 2011/06
- 23 -
■ System Clock for Output PORT
The output ports work in master mode and slave mode. The CM2-0 pins select the master/slave mode.
Mode CM2
pin
CM1
pin
CM0
pin Master / Slave OMCLK/XTI
Input MCKO Output FSO FSO with
X’tal
0 L L L Master 256FSO 256FSO 8k∼108kHz 44.1~96kHz
1 L L H Master 384FSO 384FSO 8k∼96kHz 29.4~64kHz
2 L H L Master 512FSO 512FSO 8k∼54kHz 22.05~48kHz
3 L H H Master 768FSO 768FSO 8k∼48kHz 14.7~32kHz
4 H L L Slave Not used. (Note 24)OMCLK Input
Clock 8k∼216kHz -
5 H L H Master 128FSO (Note 25) 128FSO
8k∼216kHz 88.2~192kHz
6 H H L Slave(Bypass)
7 H H H Master(Bypass)
Not used. (Note 24)IMCLK Input
Clock 8k∼216kHz -
Note 24. Use for a clock input or connect to VSS2-5 pin. In Mode 4, the MCKO pin outputs “L” if the OMCLK/XTI pin is
connected to VSS2-5. When a clock is input to the OMCLK/XTI pin, the clock is through and output from the
MCKO pin. In Mode 6-7, OMCLK/XTI input is ignored internally.
Note 25. Output ports do not support TDM mode in this mode.
Table 3. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = “L”)
In serial control mode (SPB pin = “H”), the BYPS bit selects SRC bypass mode and SRC mode.
The default value of the BYPS bit is “0” (SRC mode).
Mode CM2
pin
CM1
pin
CM0
pin
BYPS
bit Master / Slave OMCLK/XTI
Input
MCKO
Output FSO FSO with
X’tal
0 L L L 0 Master 256FSO 256FSO
8∼108kHz 44.1~96kHz
1 L L H 0 Master 384FSO 384FSO
8∼96kHz 29.4~64kHz
2 L H L 0 Master 512FSO 512FSO
8∼54kHz 22.05~48kHz
3 L H H 0 Master 768FSO 768FSO 8k~48kHz 14.7~32kHz
4 H L L 0 Slave Not used. (Note 26)
OMCLK
Input
Clock
8∼216kHz -
5 H L H 0 Master 128FSO (Note 25) 128FSO
8∼216kHz 88.2~192kHz
6 H H L 0 Slave (Bypass)
7 H H H 0 Master (Bypass)
8 L L L 1 Master (Bypass)
9 L L H 1 Master (Bypass)
10 L H L 1 Master (Bypass)
11 L H H 1 Master (Bypass)
12 H L L 1 Slave (Bypass)
13 H L H 1 Master (Bypass)
14 H H L 1 Slave (Bypass)
15 H H H 1 Master (Bypass)
Not used. (Note 26)
IMCLK
Input
Clock
8∼216kHz -
Note 26. Use for a clock input or connect to VSS2-5 pin. In Mode 4, the MCKO pin outputs “L” if the OMCLK/XTI pin is
connected to VSS2-5. When a clock is input to the OMCLK/XTI pin, the clock is through and output from the
MCKO pin. In Mode 6-15, OMCLK/XTI input is ignored internally.
Table 4. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = “H”)
[AK4128A]
MS1242-E-01 2011/06
- 24 -
(1) Master Mode
The OLRCK pin and OBICK pin are output pins in master mode. Master clock is supplied from the OMCLK/XTI pin. The
clock for the OMCLK/XTI pin can be generated by the following methods: Connect a crystal oscillator between the
OMCLK/XTI and XTO pins, or input a clock to the OMCLK/XTI pin. In bypass mode, the MCKO pin outputs IMCLK
data.
a. X’tal
XTI
XTO AK4128A
460kΩ
C
C
(typ)
Note: Refer to Table 5 for the capacitor and resistor values of the X’tal oscillator.
Figure 21. X’tal Mode
Nominal Frequency [MHz] 11.2896 12.288 24.576
Equivalent Series Resistance R1[Ω] max 60
External Capacitance C[pF] max 15
Table 5. Equivalent Series Resistor and External Capacitor for External X’tal Oscillator
In X’tal mode at 256FSO OMCLK input, FSO ranges from 44.1kHz to 96kHz.
In X’tal mode at 384FSO OMCLK input, FSO ranges from 29.4kHz to 64kHz.
In X’tal mode at 512FSO OMCLK input, FSO ranges from 22.05kHz to 48kHz.
In X’tal mode at 768FSO OMCLK input, FSO ranges from 14.7kHz to 32kHz.
In X’tal mode at 128FSO OMCLK input, FSO ranges from 88.2kHz to 192kHz.
b. External Clcok
- Note: Do not input the clock over DVDD1-4.
XTI
XTO AK4128A
460kΩ
External
Clock
(typ)
Figure 22. External Clock (OMCLK) mode
(2) Slave Mode
The OLRCK pin and OBICK pin are input pins in slave mode.
The OMCLK/XTI pin
is pulled down when
the PDN pin= “L”.
[AK4128A]
MS1242-E-01 2011/06
- 25 -
(3) SRC Bypass Mode
SRC bypass mode can be set in Synchronous inputs mode (INAS pin = “L”). Asynchronous inputs mode (INAS pin = “H”)
does not supports SRC bypass mode, so that the data is not transferred correctly on SDTI1→SDTO1, SDTI2→SDTO2,
SDTI3→SDTO3 and SDTI4→SDTO4 lines. In Asynchronous inputs mode (INAS pin = “H”), the AK4128A should be
used in SRC mode.
When the AK4128A is in slave mode, SDTI1-4 data are input by the ILRCK1 and IBICK1 clocks in SRC bypass mode
(Table 2). The SDTI1-4 data are output from the OLRCK and OBICK pins in a format shown in Table 6 and Table 7.
IBICK and OBICK must be synchronized but the phase is not critical. ILRCK and OLRCK must be synchronized but the
phase is not critical.
Output
Serial
udio
I/F
DEM
Input
Serial
A
udio
I/F
SRC1
FIR SRC
SMUTE
+
Dither
Bypass
SRC
0.5 LSB
IBICK1
SDTI1
ILRCK1
DEM
Input
Serial
A
udio
I/F
SRC2
FIR SRC
SMUTE
+
Dither
Bypass
SRC
IBICK2
SDTI2
ILRCK2
SDTO1
SDTO2
DEM
Input
Serial
A
udio
I/F
SRC3
FIR SRC
SMUTE
+
Dither
Bypass
SRC
IBICK3
SDTI3
ILRCK3
SDTO3
DEM
Input
Serial
A
udio
I/F
SRC4
FIR SRC
SMUTE
+
Dither
Bypass
SRC
IBICK4
SDTI4
ILRCK4
SDTO4
MCKO
Clock
Div
CM2 CM1 CM0
IMCLK
Bypass
SRC
X’tal
Osc
OMCLK/XTI
XTO
OLRCK
OBICK
OBIT1
OBIT2
ODIF1
ODIF0
IDIF2
uP
I/F
SDA
SPB
CAD0
PDN
PM1
PM2
UNLOCK
A
VDD
VSS1
SCL
IDIF1
IDIF0
DEM1
DEM0
INAS
DVDD1-4
VSS2-5
SMSEMI
SMUTE
SMT1
SMT0
DITHER
0.5 LSB
0.5 LSB
0.5 LSB
Internal
OSC
Internal
Regulator REF
VD18
Figure 23. Bypass Mode in Slave Mode (Synchronous mode INAS pin = “L”)
[AK4128A]
MS1242-E-01 2011/06
- 26 -
When the AK4128A is in master mode, SDTI1-4 data are input by the ILRCK1 and IBICK1 clocks in SRC bypass mode
(Table 2). The SDTI1-4 output data are output by the ILRCK1 and IBICK1 clocks in a format shown in Table 6 and Table
7. The ILRCK1 clock bypasses the SRC and it is output from the OLRCK pin. The IBICK1 clock bypasses the SRC and it
is output from the OBICK pin.
Output
Serial
udio
I/F
DEM
Input
Serial
A
udio
I/F
SRC1
FIR SRC
SMUTE
+
Dither
Bypass
SRC
0.5 LSB
IBICK1
SDTI1
ILRCK1
DEM
Input
Serial
A
udio
I/F
SRC2
FIR SRC
SMUTE
+
Dither
Bypass
SRC
IBICK2
SDTI2
ILRCK2
SDTO1
SDTO2
DEM
Input
Serial
A
udio
I/F
SRC3
FIR SRC
SMUTE
+
Dither
Bypass
SRC
IBICK3
SDTI3
ILRCK3
SDTO3
DEM
Input
Serial
A
udio
I/F
SRC4
FIR SRC
SMUTE
+
Dither
Bypass
SRC
IBICK4
SDTI4
ILRCK4
SDTO4
MCKO
Clock
Div
CM2 CM1 CM0
IMCLK
Bypass
SRC
X’tal
Osc
OMCLK/XTI
XTO
OLRCK
OBICK
OBIT1
OBIT2
ODIF1
ODIF0
IDIF2
uP
I/F
SDA
SPB
CAD0
PDN
PM1
PM2
UNLOCK
A
VDD
VSS1
SCL
IDIF1
IDIF0
DEM1
DEM0
INAS
DVDD1-4
VSS2-5
SMSEMI
SMUTE
SMT1
SMT0
DITHER
0.5 LSB
0.5 LSB
0.5 LSB
Internal
OSC
Internal
Regulator REF
VD18
Figure 24. Bypass Mode in Master Mode (Synchronous mode INAS pin = “L”)
[AK4128A]
MS1242-E-01 2011/06
- 27 -
■ Audio Interface Format for Output PORT
The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2’s
complement format. The SDTO1-4 is clocked out on the falling edge of OBICK. Select the audio interface format for
output port when the PDN pin = “L”. If the AK4128A is in slave mode at bypass mode, IBICK1 and OBICK must be
synchronized but the phase is not critical. ILRCK1 and OLRCK must be synchronized but the phase is not critical. The
audio interface format of SDTO1, SDTO2, SDTO3 and SDTO4 are controlled together by ODIF1-0 pins, OBIT1-0 pins
and TDM pin. Output ports become TDM mode when the TDM pin = “H”. In TDM mode, the SDTI1 pin outputs serial
data for 8channels and the SDTI2-4 pins output “L”.
Mode TDM pin ODIF1 pin ODIF0 pin SDTO1-4 Format
0 L L L LSB justified
1 L L H Reserved
2 L H L MSB justified
3 L H H I2S Compatible
4 H L L Reserved
5 H L H Reserved
6 H H L TDM256 mode 24bit MSB justified
7 H H H TDM256 mode 24bit I2S Compatible
Table 6. Output PORT Audio Interface Format 1
OBICK Frequency
Mode TDM
pin
Master / Slave
setting
OBIT1
pin
OBIT0
pin
SDTO
1-4
OLRC
K OBICK MSB justified,
I2S
LSB
justified
0 L L 16bit
≥ 32FSO
1 L H 18bit
≥ 36FSO
2 H L 20bit
≥ 40FSO
3
Slave
(CM2-0 = “HLL”
or “HHL”)
H H 24bit
Input Input
≥ 48FSO
64FSO
4 L L 16bit
5 L H 18bit
6 H L 20bit
7
L
Master
(Not CM2-0 =
“HLL”/“HHL”) H H 24bit
Output Output 64FSO
8
9
10
11
Slave
(CM2-0 = “HLL”
or “HHL”)
* *
TDM256
mode
24bit
Input Input 256FSO
12
13
14
15
H
Master
(Not CM2-0 =
“HLL”/“HHL”)
* *
TDM256
mode
24bit
Output Output 256FSO
Table 7. Output PORT Audio Interface Format 2
(* The data length for 1channel is 24bit fixed in TDM mode. The OBIT1-0 pin settings are ignored. Connect these pins to
VSS2-5.)
[AK4128A]
MS1242-E-01 2011/06
- 28 -
OLRCK
OBICK(64fs) 0 1
Lch Data Rch Data
89
SDTO(O) 15:MSB, 0:LSB
SDTO(O) 17:MSB, 0:LSB
SDTO(O) 19:MSB, 0:LSB
SDTO(O) 23:MSB, 0:LSB
1
012 13 141110 16 1715 20 21 22 2923 3130
10 9 81115 14 2 1 0
10 9 81115 14 2 1 017 16
10 9 81115 14 2 1 017 1619 18
10 9 81115 14 2 1 017 1619 1821 2023 22
12 13 14118 9 10 16 1715 20 21 22 2923 3130 0 1 2
10 9 21115 14 018
2815 14 11 0117 16 10 9
2815 14 9 0117 1619 18 11 10
2815 11 10 9 0117 1619 1821 2023 22 14
Figure 25. Stereo Mode LSB justified Timing
OLRCK
OBICK(64fs) 0 1 2
Lch Data Rch Data
34
SDTO(O)
SDTO(O)
SDTO(O)
SDTO(O) 23:MSB, 0:LSB
34
15:MSB, 0:LSB
17:MSB, 0:LSB
19:MSB, 0:LSB
32148765 010 921 2023 22
321465 017 1619 18
321415 14 017 16
15 14 13 12 2 1 0
32148765 010 921 2023 22
321465 017 1619 18
321415 14 017 16
15 14 13 12 2 1 0
031 1 2 031 1 2
191817 2413 14 1615 20 21 2322 191817 2413 14 1615 20 21 2322
23 22
19 18
17 16
15 14
Figure 26. Stereo Mode MSB Justified Timing
OLRCK
OBICK(64fs) 012
Lch Data Rch Data
34
SDTO(O)
SDTO(O)
SDTO(O)
SDTO(O) 23:MSB, 0:LSB
34
15:MSB, 0:LSB
17:MSB, 0:LSB
19:MSB, 0:LSB
012 031 1 2191817 2414 1615 20 21 2322 191817 2414 1615 20 21 2322
23
19
17
1515 14 13 12 2 1 0
321415 14 017 16
321465 017 1619 18
32148765 010 921 2023 22
15 14 13 12 2 1 0
321415 14 017 16
321465 017 1619 18
32148765 010 921 2023 22
Figure 27. Stereo Mode I2S Compatible Timing
Note: SDTO is identified as SDTO1, SDTO2, SDTO3 and SDTO4.
[AK4128A]
MS1242-E-01 2011/06
- 29 -
23
O
BICK(O) (25 6F SO )
SDTO 1 (O) 22 0
L1
32OBICK
25 6 OBI CK
22 0
R1
32OBICK
2223 2323 22 0
L2
32OBICK
22 0
R2
32OBICK
23 23 22 0
L3
22 0
R3
23 23 22 0
L4
22 0
R4
23
O
LRCK(O) 1/ 8FSO
32OBICK 32OBICK 32O BICK 32OBICK
Figure 28. TDM 256 mode 24bit MSB justified Timing at Master Mode. (SDTO2-4: “L” outputs)
23
OLRCK(I)
OBICK(I) (2 56FS O)
S
DTO 1 (O) 22 0
L1
32 OBICK
256 OBICK
22 0
R1
32 OBICK
2223 2323 22 0
L2
32 OBICK
22 0
R2
32 OBICK
23 23 22 0
L3
22 0
R3
23 23 22 0
L4
22 0
R4
23
min. 1/ 256FSO
32 OBICK 32 OBICK 32 OBICK 32 OBICK
Figure 29. TDM 256 mode 24bit MSB justified Timing at Slave Mode. (SDTO2-4: “L” outputs)
OBI CK (O: 256FSO)
SDTO 1 (O) 23 0
L1
32 OBICK
256 OBICK
23 0
R1
32 OBICK
2323 0
L2
32 OBICK
23 0
R2
32 OBICK
23 0
L3
23 0
R3
23 0
L4
23 0
R4
OLRCK(O ) 1/8FSO
32 OBICK 32 OBICK 32 OBICK 32 OBICK
Figure 30. TDM 256 mode 24bit I2S Compatible Timing at Master Mode (SDTO2-4: “L” outputs)
OLRCK(I)
OBI C K ( I: 256FSO)
SDTO 1 ( O ) 23 0
L1
32 OBICK
256 OBICK
23 0
R1
3 2 OBICK
2323 0
L2
32 OBICK
23 0
R2
32 OBICK
23 0
L3 23 0
R3 23 0
L4 23 0
R4
32 OBICK 32 OBICK 32 OBICK 32 OBICK
min. 1/ 256FSO
Figure 31. TDM 256 mode 24bit I2S Compatible Timing at Slave Mode (SDTO2-4: “L” outputs)
[AK4128A]
MS1242-E-01 2011/06
- 30 -
■ 6/4channel Mode
The AK4128A has 6-channel and 4-channel modes to reduce power supply current when not using all eight channels.
When the PM2 and PM1 pins are set to “L/L”, six channels (SDTI1Æ SDTO1, SDTI2 Æ SDTO2 and SDTI3 Æ SDTO3)
are powered-up and the other two channels (SDTI4 Æ SDTO4) are powered-down (“L” output). When the PM2 and PM1
pins are set to “L/H”, four channels (SDTI1Æ SDTO1 and SDTI2 Æ SDTO2) are powered-up and the other four channels
(SDTI3 Æ SDTO3 and SDTI4 Æ SDTO4) are powered-down (“L” output). In 6-channel and 4-channel modes, the X’tal
oscillator circuit and the MCKO output are powered-down and the XTO pin and MCKO pin output Hi-z.
PM2
pin
PM1
pin
PDN
pin Mode X’tal Oscillator XTI pin XTO pin MCKO pin
L L L Pull down to VSS2-5 (note)
L L H
6-channel
mode Power-down Input Hi-z
L H L Pull down to VSS2-5 (note)
L H H
4-channel
mode Power-down Input Hi-z
Hi-z
H L L Power-down Pull down to VSS2-5 (note) Hi-z L
H L H
8-channel
mode Normal operation Input Output Normal operation
H H L - - - -
H H H
Not
available - - - -
Note: Pull down (460kΩ typ.) to VSS2-5.
Table 8. Channel Mode Setting
■ Soft Mute Operation
1. Manual Mode
The soft mute operation is performed in the digital domain of the SRC output. SRC1-4 soft mutes are controlled together by
the SMUTE pin in parallel control mode (SPB pin = “L”). In serial control mode (SPB pin = “H”), setting of the SMUTE
pin is ignored. SRC1 reflects SMUTE1 bit setting, SRC2 reflects SMUTE2 bit setting, SRC3 reflects SMUTE3 bit setting,
and SRC4 reflects SMUTE4 bit setting.
When the SMUTE pin goes “H” or SMUTE1-4 bits becomes “1”, all the outputs data are attenuated by −∞ during 1024
OLRCK cycles (@ SMT1 pin = “L” and SMT0 pin = “L”). When the SMUTE pin goes “L” or SMUTE1-4 bits becomes
“0”the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 OLRCK cycles (@ SMT1 pin =
“L” and SMT0 pin = “L”). If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and
returned to 0dB by the same cycles. The soft mute is effective for changing the signal source without stopping the signal
transmission. Soft mute cycle is set by SMT1-0 pins. SMT1-0 pins must not be changed during soft mute transition.
SMT1pin SMT0 pin Period FSO=48kHz FSO=96kHz FSO=192kHz
L L 1024/fso 21.3ms 10.7ms 5.3ms
L H 2048/fso 42.7ms 21.3ms 10.7ms
H L 4096/fso 85.3ms 42.7ms 21.3ms
H H 8192/fso 170.7ms 85.3ms 42.7ms
Table 9. Soft Mute Cycle Setting (Parallel Mode)
[AK4128A]
MS1242-E-01 2011/06
- 31 -
SM U T E pin,
SM U T E1-4 b it
Attenuation
0dB
-∞
(1) (2)
SDT O
(1)
All “0” co de
Note: SDTO is identified as SDTO1, SDTO2, SDTO3 and SDTO4.
(1) The soft mute cycle is selected by SMT1-0 pins. (Table 9) The output data is attenuated by −∞ during the soft mute
cycle.
(2) If the soft mute is cancelled before attenuating to −∞, the attenuation is discontinued and returned to 0dB by the same
clock cycles.
Figure 32. Soft Mute Function (Manual Mode) 2. Semi-Auto Mode
When power down of the AK4128A is released (PDN pin = “L” → “H”) with the SMSEMI pin= “H”, the AK4128A enters
semi-auto mode. In this mode, soft mute is cancelled automatically 4410/FSO after a rising edge of PDN (100ms
@FSO=44.1kHz). The soft mute is ON after releasing power down if the SMUTE pin = “H”. The SMSEMI pin must be set
during the PDN pin = “L”.
PDN pi n
Atte nuatio n
0dB
-∞
SDT O
4410/fso
(1)
SMUTE pin Don’t care “L”
“L”
All “0” code
(2)
Note: SDTO is identified as SDTO1, SDTO2, SDTO3 and SDTO4.
(1) The output data is attenuated by −∞ during the soft mute cycle (Table 9)
(2) When it is 0dB by a soft mute release after 4410/FSO, it is able to mute or release the mute by the soft mute cycle in
Table 9.
Figure 33. Soft Mute Function (Semi-Auto Mode)
[AK4128A]
MS1242-E-01 2011/06
- 32 -
■ Dither
The AK4128A includes a dither circuit. The dither circuit adds a dither signal after the lowest bit of all the output data set
by the OBIT1-0 pins when the DITHER pin = “H”, regardless of SRC and SRC bypass modes. If the output bit is 24bit
length in SRC bypass mode, the output code does not change by the DITHER pin setting.
■ De-emphasis Filter
The AK4128A includes a digital de-emphasis filter (tc = 50/15μs) by an IIR filter. This filter corresponds to three
frequencies (32kHz, 44.1kHz and 48kHz). In parallel control mode (SPB pin = “L”), de-emphasis setting of SRC1-4 are
controlled together by DEM1-0 pins. In serial control mode (PSB pin = “H”), the setting of DEM1-0 pins is ignored. SRC1
reflects the DEM[11:10] bits setting, SRC2 reflects the DEM[21:20] bits setting, SRC3 reflects the DEM[31:30] bits
setting, and SRC4 reflects the DEM[41:40] bits setting.
DEM11pin DEM10 pin Mode(SDTI1-4)
L L 44.1kHz
L H OFF
H L 48kHz
H H 32kHz
Table 10. De-emphasis Filter Setting (Parallel Control Mode (SPB pin= “L”))
DEM11bit DEM10 bit Mode(SDTI1)
L L 44.1kHz
L H OFF
H L 48kHz
H H 32kHz
Table 11. De-emphasis Filter Setting for SDTI1 (Serial Control Mode (SPB pin = “H”))
DEM21 bit DEM20 bit Mode(SDTI2)
L L 44.1kHz
L H OFF
H L 48kHz
H H 32kHz
Table 12. De-emphasis Filter Setting for SDTI2 (Serial Control Mode (SPB pin= “H”))
DEM31 bit DEM30 bit Mode(SDTI3)
L L 44.1kHz
L H OFF
H L 48kHz
H H 32kHz
Table 13. De-emphasis Filter Setting for SDTI3 (Serial Control Mode (SPB pin = “H”))
DEM41 bit DEM40 bit Mode(SDTI4)
L L 44.1kHz
L H OFF
H L 48kHz
H H 32kHz
Table 14. De-emphasis Filter Setting for SDTI4 (Serial Control Mode (SPB pin = “H”))
[AK4128A]
MS1242-E-01 2011/06
- 33 -
■ Regulator
The AK4128A has an internal regulator which suppresses the voltage to 1.8V from DVDD1-4 voltage. The generated 1.8V
power is used as power supply for internal circuit. When over-current is flowed to the regulator output, over-current
detection circuit works. When over-voltage is flowed to the regulator output, over-voltage detection circuit works. The
regulator block is powered-down and the AK4128A becomes reset state when over-current detection circuit or
over-voltage detection circuit is operated. The AK4128A does not return to normal operation without a reset by the PDN
pin when these detection circuits are worked. When over-current or over-voltage is detected, the PDN pin should be
brought into “L” at once, and should be set to “H” again to recover normal operation.
The UNLOCK pin indicate the internal status of the device, and outputs “L” in SRC normal operation, and outputs “H”
when over-current or over-voltage are detected.
■ System Reset
Bringing the PDN pin = “L” sets the AK4128A power-down mode and initializes the digital filters. The AK4128A should
be reset once by bringing the PDN pin = “L” upon power-up. When PDN pin = “L”, the SDTO1-4 output is “L”. It takes
23ms (max) for SDTO output enable after power-down state is released by a clock input. Until then, the SDTO1-4 outputs
“L”. The internal SRC circuit is powered-up on an edge of ILRCK1-4 after a power-up time period of the internal
regulator. (SDTO is identified as SDTO1, SDTO2, TDTO3 and SDTO4. SDTI is identified as SDTI1, SDTI2, SDTI3 and
SDTI4.)
Figure 34. System Reset 1
Case 1: System Rese t with clock inp u ts
Exte rnal clocks
(Input port)
SDTI
Don’t care
SDTO4
(Int ernal st at e) Power-down Normal
operation
Normal data
Input Clocks 1
Exte r n al clocks
(Ou tput port)
Don’t care
Don’t care
PDN
Power-down
Don’t care
Don’t care
Don’t care
“0” d at a
Normal
operation
23ms(max)
Normal data
PD
Input Data 1
Output Clocks 1
In put Clo ck s 2
In put Data 2
Output Clocks 2
“0” data “0” d at a
UNLOCK
23ms(max)
(1)
SDTO3 Normal data “0” d at aNormal data
“0” data “0” data
SDTO2 Normal data “0” da taNormal data
“0” data “0” data
SDTO1 Normal data “0” d at aNormal data
“0” data “0” d at a
(1)
[AK4128A]
MS1242-E-01 2011/06
- 34 -
Figure 35. System Reset 2
Note 27. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD0 pin must be changed when the PDN
pin= “L”.
Note 28. The UNLOCK pin outputs “H” when the PDN pin= “L”. SRC data is output from SDTO1-4 pins, which
corresponds to the each sampling frequency ratio detected SRC, after a rising edge “↑” of PDN if the internal
regulator is in normal operation. In 8-channel mode, the UNLOCK pin outputs “L” when sampling frequency
ratio detection is completed at all SRC’s. The UNLOCK pin keeps outputting “H” if there is one SRC which does
not finished sampling frequency ratio detection.
Note 29. (1) is the total time of “Internal circuit power-up + FSO/FSI ratio detection + Clock detection + Internal circuit
group delay”.
Note 30. (2) is the total time of “FSO/FSI ratio detection + Clock detection + Internal circuit group delay”.
Case 2 : System Reset withou t clock in puts
E xtern al cl ock s
(Input port)
SDTI
SDTO4
(Internal state) Power-down Normal
operation
21ms(max)
Nor mal data
(No Clock)
E xtern al cl ock s
(Output port)
PDN
Power-down
Don ’t ca re
Don ’t ca re
Don ’t ca re
“0” data
Internal Circuit
Power-up T ime
Input Clocks
Input Data
Output Clocks
“0” data
(Don’t care)
(Don’t care)
ILRCK1-4
Input wait (2)
SDTO3 Normal data “0” data
“0” da ta
SDTO2 Normal data “0” data
“0” data
SDTO1 Normal data “0” data
“0” data
UNLOCK
[AK4128A]
MS1242-E-01 2011/06
- 35 -
■ Internal Reset Function for Clock Change
Clock change timing is shown in Figure 36 and Figure 37. SDTO is identified as SDTO1, SDTO2, SDTO3 and SDTO4.
When changing the clock, the AK4128A should be reset by the PDN pin in parallel control mode and it should be reset by
the PDN pin or RSTN bit in serial control mode (Figure 36). SDTO means SDTO1-4 in this figure.
(3) Power-down
External clock
s
(Input port
or Output port )
Clocks 1
SDTO
(Int erna l st a t e) Normal operation Nor m al operation
Clocks 2 Don’t ca re
max 23ms
S MUTE (Note32,
recommended) 1024/FSO
Att.Level 0dB
-∞dB
Normal data Normal data
1024/FSO
PDN p i n
Note 31
Note 31. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI more than 1024/fs (GD) before
the PDN pin changes to “L”. It makes the data on SDTO remain as “0”.
Note 32. SMUTE can also remove the clicking noise (Note 31).
Note 33. (3) is the total time of “Internal circuit power-up + FSO/FSI ratio detection + Internal circuit group delay”.
Figure 36. Clock Change Sequence in Parallel Control Mode (SPB pin = “L”)
Note 34. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI from GD before the PDN pin
changes to “L”. It makes the data on SDTO remain as “0”.
Note 35. SMUTE can also remove the unknown data at Note 26
Note 36. The digital block except serial control interface and registers is powered-down. The internal oscillator and
regulator are not powered-down.
Note 37. (4) is the total time of “0.5/FSI+8/FSI(O)+156/FSO” or “1.5/FSI+8/FSI(O)+156/FSO”. (FSI(O) is lower
frequency between FSI and FSO).
Figure 37. Clock Change Sequence in Serial Control Mode (SPB pin = “H”)
Reset (Note 28)
E xternal clock s
(I nput port or Output port) Clocks 1
SDTO
(Internal st at e) Normal operati on Normal operation
Cl oc ks 2 Don’t care
S MUT E (Note35, re commended) 1024/FSO
Att.Level 0dB
-∞dB
Normal data Norma l data
1024/FSO
RST N bit
Note 34
(4)
[AK4128A]
MS1242-E-01 2011/06
- 36 -
1. When the frequency of ILRCKx (x=1, 2, 3, 4) at input port is changed without a reset by the PDN pin or RSTN bit.
When the difference of internal oscillator (min. 59.4 MHz, typ. 73.5 MHz) clock number in one ILRCKx cycle
between before an ILRCKx frequency change (FSO/FSI ratio is stabilized) and after the change is more than ±100
for 8cycles, an internal reset is made automatically and sampling frequency ratio detection is executed again.
SDTOx outputs “L” when the internal reset is made, and SRC data is output after “0.5/FSI+8/FSI(O)+156/FSO or
1.5/FSI+8/FSI(O)+156/FSO” (FSI(O) is lower frequency between FSI and FSO).
If the difference of internal oscillator clock number in one ILRCKx cycle between before an ILRCKx frequency
change and after the change is less than ±100 or more than ±100 but shorter than 8cycles, the internal reset is not
executed. In both cases; when ILRCKx frequency is changed immediately without transition time or with transition
time which is not long enough for an internal reset, it takes 5148/FSO (max. 643.5ms @FSO=8kHz) (Note 38)to
output normal SRC data. Distorted data may be output until normal SRC output.
When ILRCKx is stopped, an internal reset is executed automatically. It takes “0.5/FSI+8/FSI(O)+156/FSO or
1.5/FSI+8/FSI(O)+156/FSO” (FSI(O) is lower frequency between FSI and FSO) [s] to output normal SRC data
after ILRCKx is input again.
2. When the frequency of OLRCK at output port is changed without a reset by the PDN pin or RSTN bit.
When the difference of internal oscillator clock number in one OLRCK cycle between before an OLRCK frequency
change (FSO/FSI ratio is stabilized) and after the change is more than ±100 for 8cycles, an internal reset is made
automatically and sampling frequency ratio detection is executed again. SDTOx (x=1, 2, 3, 4)outputs “L” when the
internal reset is made, and SRC data is output after “0.5/FSI+8/FSI(O)+156/FSO or 1.5/FSI+8/FSI(O)+156/FSO”
(FSI(O) is lower frequency between FSI and FSO).
If the difference of internal oscillator clock number in one OLRCK cycle between before an OLRCK frequency
change and after the change is less than ±100 or more than ±100 but shorter than 8cycles, the internal reset is not
executed. It takes 5148/FSO (max. 643.5ms @FSO=8kHz) (Note 38) to output normal SRC data. Distorted data
may be output until normal SRC output.
When OLRCK is stopped, an internal reset is executed automatically. It takes “0.5/FSI+8/FSI(O)+156/FSO or
1.5/FSI+8/FSI(O)+156/FSO” (FSI(O) is lower frequency between FSI and FSO) [s] to output normal SRC data
after ILRCKx is input again.
Note 38. When FSO=8kHz and FSO/FSI ratio is changed from 1/6 to 1/5.99. It is 160.9ms when FSO=32kHz and FSO/fSI
ratio is changed from 1/6 to 1/5.99.
[AK4128A]
MS1242-E-01 2011/06
- 37 -
■ Internal Status Pin
The UNLOCK pin indicates internal status of the device. This pin outputs “H” when the PDN pin = “L”. SRC data is output
from SDTO1-4 pins, which corresponds to the each sampling frequency ratio detected SRC, after a rising edge “↑” of PDN
if the internal regulator is in normal operation. In 8-channel mode, the UNLOCK pin outputs “L” when sampling frequency
ratio detection is completed at all SRC’s (SRC1-4). The UNLOCK pin keeps outputting “H” if there is one SRC which
does not finished sampling frequency ratio detection.
In 6-channel mode, the UNLOCK pin outputs “L” when sampling frequency ratio detection is completed at SRC1-3. It
keeps outputting “H” if there is one SRC which does not finish sampling frequency ratio detection.
In 4-channel mode, the UNLOCK pin outputs “L” when sampling frequency ratio detection is completed at SRC1-2. It
keeps outputting “H” if there is one SRC which does not finish sampling frequency ratio detection.
When over-current/voltage is flowed at the internal regulator, the UNLCOK pin outputs “H”. An OR’ed result of the flags
between over-current/voltage detection at the internal regulator and SRC sampling frequency detection complete is output
from this pin.
Figure 38. Internal Flags and UNLOCK pin Output
In parallel control mode, if the AK4128A is set in SRC bypass mode by CM2-0 pins during the PDN pin = “L” and
powered-up, the UNLOCK pin outputs “L” after the power-up time of the internal regulator (max. 1.4ms) from a rising
edge “↑” of the PDN pin. In serial control mode, if BYPS bit is set to “1”while RSTN bit = “0”, the UNLOCK pin
immediately outputs “L” after the register writing.
Over-Current/Vo ltage Limit Flag
(“L” Norm al, “H” Over-Curre nt/Voltage detect)
SRC Samplin g Frequen c y Ratio Complete Flag
UNLOCK pin
[AK4128A]
MS1242-E-01 2011/06
- 38 -
■ Serial Control Interface
The AK4128A supports fast-mode I2C-bus system (max: 400kHz). Pull-up resistors at SDA and SCL pins should be
connected to (DVDD1-4 + 0.3)V or less voltage.
1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4128A recognizes the START condition, the device interfaced to the bus waits of the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device
pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by
the master device.
1-1. Data validity
The data on the SDA line must be stable during a HIGH period of the clock. The HIGH or LOW state of the data line can
only be changed when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
A
LLOWED
Figure 39. Data Transfer
1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from the
START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
S
SCL
SDA
STOP CONDITIONSTART CONDITION
Figure 40. START and STOP conditions
[AK4128A]
MS1242-E-01 2011/06
- 39 -
1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitter will release the SDA
line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so
that that it remains stable “L” during “H” period of this clock pulse. The AK4128A generates an acknowledge after each
byte is received.
In read mode, the slave, the AK4128A transmits eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue
transmitting data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP
condition.
SCL FROM
MASTER
acknowledge
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
1 98
START
CONDITION
Clock pulse
for acknowle dge
not acknowledge
Figure 41. Acknowledge on the I2C-bus
1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after a START condition. If the
transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the
SDA line.
The first six bits of the slave address are fixed as “001001”. The next (seventh) bit is CAD0 (device address bits). It is “0”
when the CAD0 pin = “L”, and “1” when the CAD pin = “H”. This bit identifies the specific device on the bus. When the
slave address is input, the matched device generates an acknowledge and executes a command. The eighth bit (R/W bit) of
the first byte defines whether the master requests a write or read condition. A “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
0 0 1 0 0 1 CAD0 R/W
Figure 42. The First Byte
[AK4128A]
MS1242-E-01 2011/06
- 40 -
2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4128A.
After receipt of a start condition and the first byte, the AK4128A generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4128A. The format is MSB first, and
first 6bits must be fixed to “0”.
0 0 0 0 0 0 A1 A0
(*: Don’t care)
Figure 43. The Second Byte
After receipt the second byte, the AK4128A generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7 D6 D5 D4 D3 D2 D1 D0
Figure 44. Byte structure after the second byte
The AK4128A is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4128A generates an acknowledge, and awaits the next data again. The master can
transmit more than one word instead of terminating the write cycle after the first data word is transferred. After the receipt
of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically.
If the address exceeds 03H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous
data will be overwritten.
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
A
ddress
A
C
K
R egister
A
ddress(n) Data(n)
P
S
T
O
P
Data (n +x)
A
C
K
Data(n+1)
Figure 45. WRITE Operation
[AK4128A]
MS1242-E-01 2011/06
- 41 -
3. READ Operations
Set R/W bit = “1” for the READ operation of the AK4128A.
After transmission of the data, the master can read next address’s data by generating an acknowledge instead of terminating
the write cycle after the receipt of the first data word. After the receipt of each data, the internal address counter is
incremented by one, and the next data is taken into next address automatically. If the address exceeds 03H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The AK4128A supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
3-1. CURRENT ADDRESS READ
The AK4128A contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”.
After receipt of the slave address with R/W bit set to “1”, the AK4128A generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generate the stop condition, the AK4128A discontinues transmission.
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
A
ddress
A
C
K
Data(n) Data(n+1)
P
S
T
O
P
Data (n +x)
A
C
K
Data(n+2)
Figure 46. CURRENT ADDRESS READ
3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with
the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues a start condition, slave address (R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4128A generates an acknowledge, 1byte data and increments the internal address counter by one. If the
master does not generate an acknowledge but generate the stop condition, the AK4128A discontinues transmission.
SDA
S
T
A
R
T
A
C
K
A
C
K
S S
S
T
A
R
T
Slave
A
ddress Word
A
ddress(n) Slave
A
ddress
A
C
K
Data(n)
A
C
K
P
S
T
O
P
Data (n+x)
A
C
K
Data(n+1)
Figure 47. RANDOM READ
[AK4128A]
MS1242-E-01 2011/06
- 42 -
■ Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Reset & Mute SMUTE4 SMUTE3 SMUTE2 SMUTE1 0 BYPS 0 RSTN
01H De-emphasis DEM41 DEM40 DEM31 DEM30 DEM21 DEM20 DEM11 DEM10
02H Input Audio Data Format 1 0 IDIF22 IDIF21 IDIF20 0 IDIF12 IDIF11 IDIF10
03H Input Audio Data Format 2 0 IDIF42 IDIF41 IDIF40 0 IDIF32 IDIF31 IDIF30
Note 39. All register values are initialized by the PDN pin = “L”.
Note 40. Writing to the address 00H ~ 03H are inhabited. The addresses defined as 0 must contain “0” data. BYPS bit and
IDIF12-10, 22-20, 32-30, 42-40 bits should be written when RSTN bit = “0”.
Note 41. I2C access becomes valid after 1.4ms (max) from PDN pin “↑”.
■ Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Reset & Mute SMUTE4 SMUTE3 SMUTE2 SMUTE1 0 BYPS 0 RSTN
R/W R/W R/W R/W R/W RD R/W RD R/W
Default 0 0 0 0 0 0 0 1
RSTN: Digital Reset Control
0: Reset
1: Reset Release (default)
When this bit is set to “0”, some digital blocks of the AK4128A are powered-down. In this case SRC1-4
can not operate. Control register settings are not initialized because I²C serial control interface and
control register blocks are not powered-down. Control register writings are available. The internal
oscillator for the clocks, the regulator and the reference voltage generation circuit are not powered-down.
BYPS: Bypass Mode Control
0: SRC Mode (default)
1: SRC Bypass Mode
Refer to Table 3.
SMUTE1: SRC1 Soft Mute Control
0: Soft Mute Release (default)
1: Soft Mute
In serial control mode (SPB pin= “H”), the SMUTE pin setting is ignored. SRC1 reflects the SMUTE1
bit setting.
SMUTE2: SRC2 Soft Mute Control
0: Soft Mute Release (default)
1: Soft Mute
In serial control mode (SPB pin= “H”), the SMUTE pin setting is ignored. SRC2 reflects the SMUTE2
bit setting.
SMUTE3: SRC3 Soft Mute Control
0: Soft Mute Release (default)
1: Soft Mute
In serial control mode (SPB pin= “H”), the SMUTE pin setting is ignored. SRC3 reflects the SMUTE3
bit setting.
[AK4128A]
MS1242-E-01 2011/06
- 43 -
SMUTE4: SRC4 Soft Mute Control
0: Soft Mute Release (default)
1: Soft Mute
In serial control mode (SPB pin= “H”), the SMUTE pin setting is ignored. SRC4 reflects the SMUTE4
bit setting.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H De-emphasis DEM41 DEM40 DEM31 DEM30 DEM21 DEM20 DEM11 DEM10
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 1 0 1 0 1 0 1
DEM11/10: SRC1 De-emphasis Control
Default: “01” De-emphasis=OFF
DEM21/20: SRC2 De-emphasis Control
Default: “01” De-emphasis=OFF
DEM31/30: SRC3 De-emphasis Control
Default: “01” De-emphasis=OFF
DEM41/40: SRC4 De-emphasis Control
Default: “01” De-emphasis=OFF
In serial control mode (SPB pin= “H”), the setting of DEM1-0 pins is ignored. The DEM[11:10] bits setting is
reflected to SRC1, the DEM[21:20] bits setting is reflected to SRC2, the DEM[31:30] bits setting is reflected to
SRC3, and the DEM[41:40] bits setting is reflected to SRC4.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Input Audio Data Format 1 0 IDIF22 IDIF21 IDIF20 0 IDIF12 IDIF11 IDIF10
R/W RD R/W R/W R/W RD R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Input Audio Data Format 2 0 IDIF42 IDIF41 IDIF40 0 IDIF32 IDIF31 IDIF30
R/W RD R/W R/W R/W RD R/W R/W R/W
Default 0 0 0 0 0 0 0 0
IDIF12/11/10: SRC1 Audio Data Interface Mode Select for Input Ports
Default: “000” Mode 0 (Refer Table 2)
IDIF22/21/20: SRC2 Audio Data Interface Mode Select for Input Ports
Default: “000” Mode 0 (Refer Table 2)
IDIF32/31/30: SRC3 Audio Data Interface Mode Select for Input Ports
Default: “000” Mode 0 (Refer Table 2)
IDIF42/41/40: SRC4 Audio Data Interface Mode Select for Input Ports
Default: “000” Mode 0 (Refer Table 2)
In serial control mode (SPB pin = “H”), the setting of IDIF2-0 pins is ignored. The IDIF[12:10] bits setting is
reflected to SRC1, the IDIF[22:20] bits setting is reflected to SRC2, the IDIF[32:30] bits setting is reflected to
SRC3, and the IDIF[42:40] bits setting is reflected to SRC4.
[AK4128A]
MS1242-E-01 2011/06
- 44 -
SYSTEM DESIGN
Figure 48 and Figure 49 shows the system connection diagram. An evaluation board is available which demonstrates
application circuits, the optimum layout, power supply arrangements and measurement results.
• Parallel Control Mode (SPB pin = “L”).
•Synchronous Mode (INAS pin = “L”).
• OMCLK/XTI Input = X’tal mode
• Input PORT: Slave mode, IBICK1 lock mode (64FSI), 24 bit MSB justified
• Output PORT: Slave mode, 24 bit MSB justified
• Dither = OFF, DEM=OFF, PM2/1 pin= “H/L” (8ch mode)
C1= 0.1μF
C2=10μF
C3=1μF± 30%
IBICK21
2
3
4
5
6
7
8
9
10
11
IMCLK
ILRCK1
IBICK1
DVDD1
VSS2
SDTI4
SDTI1
SDTI2
SDTI3
IDIF0
Top View
ILRCK2
64 63 62
TST3
VSS1
61 60 58 5759 55 5456 53
VD18
AVDD
SPB
SDA
SCL
TST2
SMSEMI
TST1
VSS5
12 IDIF1
13 IDIF2
14 ILRCK3
15 IBICK3
16 ILRCK4
52
DVDD4
51
CAD0
50
TST0
49
MCKO
IBICK4
17
INAS
18
UNLOCK
19
DVDD2
20
VSS3
21
SMUTE
22
DITHER
23
PDN
24
SMT0
25
SMT1
26
DEM0
27
DEM1
28
PM1
29
OBIT0
30
OBIT1
31
PM2
32
44
43
42
41
40
39
38
37
36
35
34
33
DVDD3
VSS4
SDTO4
SDTO1
SDTO2
SDTO3
ODIF0
ODIF1
CM0
CM1
CM2
TDM
45OBICK
46OLRCK
47XTI/OMCLK
48XTO
DSP1
uP
3.3V
C2
C1
C1
C1
+
+
DSP2
C1
C1
C2
+
C2
FSI
64FSI
FSO
64FSO
C3+
CC
Notes:
- All digital input pins should be not left floating.
- VSS1 -5 must be connected to the same ground plane.
- DVDD1-4 pins must be connected to the same power supply.
- Connect a 1μF (± 30%; including temperature characteristics) capacitor between the VD18 pin and DVSS. When
this capacitor is polarized, the positive polarity pin should be connected to the VD18 pin.
- Refer to Table 5 for the equivalent series resistance R1 and capacitance C values of the X’tal oscillator.
Figure 48. Typical Connection Diagram (Parallel Control Mode)
[AK4128A]
MS1242-E-01 2011/06
- 45 -
• Serial Control Mode (SPB pin = “H”).
•Asynchronous Inputs Mode (INAS pin = “H”).
• OMCLK/XTI Input= 256FSO, X’tal
• Input PORT: Slave mode, IBICK1~4 lock mode (64FSI)
Input Audio Interface Format can be set by registers.
• Output PORT: Master mode, 24 bit MSB justified.
• Dither = OFF, De-emphasis filter can be set by registers. PM2/1 pin= “H/L” (8ch mode)
C1= 0.1μF
C2=10μF
C3=1μF± 30%
Notes:
- All digital input pins should be not left floating.
- VSS1 -5 must be connected to the same ground plane.
- DVDD1-4 pins must be connected to the same power supply.
- Connect a 1μF (± 30%; including temperature characteristics) capacitor between the VD18 pin and DVSS. When
this capacitor is polarized, the positive polarity pin should be connected to the VD18 pin.
- Refer to Table 5 for the equivalent series resistance R1 and capacitance C values of the X’tal oscillator.
Figure 49. Typical Connection Diagram (Serial Control Mode)
IBICK21
2
3
4
5
6
7
8
9
10
11
IMCLK
ILRCK1
IBICK1
DVDD1
VSS2
SDTI4
SDTI1
SDTI2
SDTI3
IDIF0
Top View
ILRCK2
64 63 62
TST3
VSS1
61 60 58 5759 55 5456 53
VD18
AVDD
SPB
SDA
SCL
TST2
SMSEMI
TST1
VSS5
12 IDIF1
13 IDIF2
14 ILRCK3
15 IBICK3
16 ILRCK4
52
DVDD4
51
CAD0
50
TST0
49
MCKO
IBICK4
17
INAS
18
UNLOCK
19
DVDD2
20
VSS3
21
SMUTE
22
DITHER
23
PDN
24
SMT0
25
SMT1
26
DEM0
27
DEM1
28
PM1
29
OBIT0
30
OBIT1
31
PM2
32
44
43
42
41
40
39
38
37
36
35
34
33
DVDD3
VSS4
SDTO4
SDTO1
SDTO2
SDTO3
ODIF0
ODIF1
CM0
CM1
CM2
TDM
45OBICK
46OLRCK
47XTI/OMCLK
48XTO
DSP1
uP
3.3V
C2
C1
C1
C1
+
+
DSP5
C1
C1
C2
+
C2
FSI
64FSI
FSO
64FSO
DSP2
DSP3
DSP4
C3
+
CC
[AK4128A]
MS1242-E-01 2011/06
- 46 -
1. Grounding and Power Supply Decoupling
The AK4128A requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and
DVDD1-4 are supplied separately, the power up sequence is not critical. VSS1-5 must be connected to the same
ground plane. Decoupling capacitors should be as near to the AK4128A as possible, with the small value ceramic
capacitor being the nearest.
2. Jitter Tolerance
Figure 50 shows the jitter tolerance to ILRCK1-4 and IBICK. The jitter quantity is defined by the jitter frequency and the
jitter amplitude shown in Figure 50. When the jitter amplitude is 0.02Uipp or less, the AK4128A operates normally
regardless of the jitter frequency.
Figure 50. Jitter Tolerance
(1) Normal Operation
(2) There is a possibility that the output data is lost.
Note
▪ Y axis is the jitter amplitude of ILRCK1-4 just before THD+N degradation starts.
1UI (Unit Interval) is one cycle of IBICK. When FSI = 48kHz, 1[UIpp]=1/48kHz=20.8μs
A
[AK4128A]
MS1242-E-01 2011/06
- 47 -
3. Digital Filter Response Example
Table 15 shows the examples of digital filter response performed by the AK4128A.
Ratio FSO/FSI [kHz] Passband [kHz] Stopband [kHz] Stopband
Attenuation [dB] Gain [dB]
4.000 192/48.0 22.000 26.000 −121.2 −0.01@ 20k
1.000 48.0/48.0 22.000 26.000 −121.2 −0.01@ 20k
0.919 44.1/48.0 20.000 24.100 −121.4 −0.01@ 20k
0.725 32.0/44.1 14.088 17.487 −115.3 −0.01@ 14.5k
0.667 32.0/48.0 13.688 17.488 −116.9 −0.19@ 14.5k
0.544 48.0/88.2 19.250 26.232 −114.6 −0.03@ 20k
0.500 48.0/96.0 20.900 27.000 −100.2 −0.01@ 20k
0.500 44.1/88.2 19.202 24.806 −100.2 −0.08@ 20k
0.459 44.1/96.0 18.700 25.000 −103.3 −0.23@ 20k
0.363 32.0/88.2 12.863 18.665 −102.0 −0.75@ 14.5k
0.333 32.0/96.0 12.500 18.900 −103.6 −1.07@ 14.5k
0.250 48.0/192.0 17.600 30.200 −104.0 −0.18@ 20k
0.250 44.1/176.4 16.170 27.746 −104.0 −1.34@ 20k
0.230 44.1/192.0 15.860 28.240 −103.3 −1.40@ 20k
0.167 32.0/192.0 11.200 19.600 −73.2 −2.97@ 14.5k
0.181 32.0/176.4 10.278 17.987 −73.2 −7.88@ 14.5k
0.167 8/48.0 2.800 4.900 −73.2 −2.97@ 3.625k
0.181 8/44.1 2.5695 4.4968 −73.2 −7.88@ 3.625k
Table 15. Digital Filter Example
4. I2C bus Connection
SCL and SDA pins should be connected to DVDD1-4 through the resistor based on I2C standard. As there is a protection
between each pin and DVDD1-4, the pulled up voltage must be DVDD1-4 or lower (Figure 51).
VSS2-5
DVDD1-4
AK4128A
+3.3V
S
DA pin
Figure 51. SDA pin output
[AK4128A]
MS1242-E-01 2011/06
- 48 -
PACKAGE
12.0
10.0
32
33
48
49
64
1 16
17
0.2±0.1 0.10 M
0.5
12.0
0.10 0.50
±
0.25
0°~10°
Max 1.85
1.40 0.00~0.25
0.09~0.25
64pin LQFP(Unit: mm)
■ Material & Lead finish
Package molding compound: Epoxy, Halogen (bromine and chlorine) free
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
[AK4128A]
MS1242-E-01 2011/06
- 49 -
MARKING (AK4128AEQ)
1
AKM
AK4128AEQ
XXXXXXX
XXXXXXX: Date code identifier
MARKING (AK4128AVQ)
1
AKM
AK4128AVQ
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[AK4128A]
MS1242-E-01 2011/06
- 50 -
Date (YY/MM/DD) Revision Reason Page Contents
10/09/13 00 First Edition
11/06/02 01 Description
Addition
4 ■ Compatibility with AK4126
(2) Pins: No. 63-pin was added.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
REVISION HISTORY