Package Footprint
Package Height
DBV (SOT23-5)
OPA171-Q1
www.ti.com
SBOS556 –JUNE 2011
36V, SINGLE-SUPPLY, GENERAL-PURPOSE
OPERATIONAL AMPLIFIER
Check for Samples: OPA171-Q1
1FEATURES DESCRIPTION
The OPA171-Q1 is a 36V, single-supply, low-noise
•Qualified for Automotive Applications operational amplifier with the ability to operate on
•Supply Range: +2.7V to +36V, ±1.35V to ±18V supplies ranging from +2.7V (±1.35V) to +36V
•Low Noise: 14nV/√Hz (±18V). This device is available in micro-packages
•Low Offset Drift: ±0.3µV/°C (typ) and offer low offset, drift, and bandwidth with low
quiescent current. The single, dual, and quad
•RFI Filtered Inputs versions all have identical specifications for maximum
•Input Range Includes the Negative Supply design flexibility.
•Input Range Operates to Positive Supply Unlike most op amps, which are specified at only one
•Rail-to-Rail Output supply voltage, the OPA171-Q1 is specified from
•Gain Bandwidth: 3MHz +2.7V to +36V. Input signals beyond the supply rails
•Low Quiescent Current: 475µA per Amplifier do not cause phase reversal. The OPA171-Q1 is
•High Common-Mode Rejection: 120dB (typ) stable with capacitive loads up to 300pF. The input
can operate 100mV below the negative rail and within
•Low Input Bias Current: 8pA 2V of the top rail during normal operation. Note that
•Industry-Standard Package: these devices can operate with full rail-to-rail input
–5-Pin Small Outline Transistor [SOT 100mV beyond the top rail, but with reduced
(SOT-23) - DBV] Package performance within 2V of the top rail.
The OPA171-Q1 op amp is specified from –40°C to
APPLICATIONS +125°C.
•Tracking Amplifier in Power Modules
•Merchant Power Supplies
•Transducer Amplifiers
•Bridge Amplifiers
•Temperature Measurements
•Strain Gauge Amplifiers
•Precision Integrators
•Battery-Powered Instruments
•Test Equipment
Product Family
DEVICE PACKAGE
OPA171-Q1 SOT (SOT-23) - DBV
Smallest Packaging for 36V Op Amp
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
5
4
V+
-IN
OUT
V-
+IN
OPA171-Q1
SBOS556 –JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DBV PACKAGE: OPA171-Q1
SOT23-5
(TOP VIEW)
ORDERING INFORMATION(1)
ORDERABLE PART
TAPACKAGE NUMBER TOP-SIDE MARKING
–40°C to 125°C SOT (SOT-23) –DBV Reel of 3000 OPA171AQDBVRQ1 OULQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. OPA171-Q1 UNIT
Supply voltage ±20 V
Voltage (V–)–0.5 to (V+) + 0.5 V
Signal input terminals Current ±10 mA
Output short circuit(2) Continuous
Operating temperature –55 to +150 °C
Storage temperature –65 to +150 °C
Junction temperature +150 °C
Human body model (HBM) 4 kV
ESD ratings: Charged device model (CDM) 500 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Short-circuit to ground, one amplifier per package.
THERMAL INFORMATION OPA171-Q1
THERMAL METRIC(1) DBV (SOT-23) UNITS
5 PINS
θJA Junction-to-ambient thermal resistance 277.3
θJC(top) Junction-to-case(top) thermal resistance 193.3
θJB Junction-to-board thermal resistance 121.2 °C/W
ψJT Junction-to-top characterization parameter 51.8
ψJB Junction-to-board characterization parameter 109.5
θJC(bottom) Junction-to-case(bottom) thermal resistance n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2Copyright ©2011, Texas Instruments Incorporated
OPA171-Q1
www.ti.com
SBOS556 –JUNE 2011
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA=–40°C to +125°C.
At TA= +25°C, VS= +2.7V to +36V, VCM = VOUT = VS/2, and RLOAD = 10kΩconnected to VS/2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input offset voltage VOS 0.25 ±1.8 mV
Over temperature 0.3 ±2 mV
Drift dVOS/dT 0.3 ±2(1) µV/°C
vs power supply PSRR VS= +4V to +36V 1 ±3µV/V
Channel separation, dc dc 5 µV/V
INPUT BIAS CURRENT
Input bias current IB±8±15 pA
Over temperature ±3.5 nA
Input offset current IOS ±4 pA
Over temperature ±3.5 nA
NOISE
Input voltage noise f = 0.1Hz to 10Hz 3 µVPP
f = 100Hz 25 nV/√Hz
Input voltage noise density enf = 1kHz 14 nV/√Hz
INPUT VOLTAGE
Common-mode voltage range(2) VCM (V–)–0.1V (V+) –2V V
VS=±2V, (V–)–0.1V <VCM <(V+) –2V 90 104 dB
Common-mode rejection ratio CMRR VS=±18V, (V–)–0.1V <VCM <(V+) –2V 104 120 dB
INPUT IMPEDANCE
Differential 100 || 3 MΩ|| pF
1012Ω||
Common-mode 6 || 3 pF
OPEN-LOOP GAIN
Open-loop voltage gain AOL VS= +4V to +36V, (V–) + 0.35V <VO<(V+) –0.35V 110 130 dB
FREQUENCY RESPONSE
Gain bandwidth product GBP 3.0 MHz
Slew rate SR G = +1 1.5 V/µs
To 0.1%, VS=±18V, G = +1, 10V step 6 µs
Settling time tSTo 0.01% (12 bit), VS=±18V, G = +1, 10V step 10 µs
Overload recovery time VIN ×Gain >VS2µs
Total harmonic distortion + noise THD+N G = +1, f = 1kHz, VO= 3VRMS 0.0002 %
OUTPUT
Voltage output swing from rail VORL= 10kΩ, AOL ≥110dB (V–) + 0.35 (V+) –0.35 V
Short-circuit current ISC +25/–35 mA
Capacitive load drive CLOAD See Typical Characteristics pF
Open-loop output resistance ROf = 1MHz, IO= 0A 150 Ω
POWER SUPPLY
Specified voltage range VS+2.7 +36 V
Quiescent current per amplifier IQIO= 0A 475 595 µA
Over temperature IO= 0A 650 µA
TEMPERATURE
Specified range –40 +125 °C
Operating range –55 +150 °C
(1) Not production tested.
(2) The input range can be extended beyond (V+) –2V up to V+. See the Typical Characteristics and Application Information sections for
additional information.
Copyright ©2011, Texas Instruments Incorporated 3
OPA171-Q1
SBOS556 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
Table 1. Characteristic Performance Measurements
DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage Drift Distribution Figure 2
Offset Voltage vs Temperature Figure 3
Offset Voltage vs Common-Mode Voltage Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5
Offset Voltage vs Power Supply Figure 6
IBand IOS vs Common-Mode Voltage Figure 7
Input Bias Current vs Temperature Figure 8
Output Voltage Swing vs Output Current (Maximum Supply) Figure 9
CMRR and PSRR vs Frequency (Referred-to Input) Figure 10
CMRR vs Temperature Figure 11
PSRR vs Temperature Figure 12
0.1Hz to 10Hz Noise Figure 13
Input Voltage Noise Spectral Density vs Frequency Figure 14
THD+N Ratio vs Frequency Figure 15
THD+N vs Output Amplitude Figure 16
Quiescent Current vs Temperature Figure 17
Quiescent Current vs Supply Voltage Figure 18
Open-Loop Gain and Phase vs Frequency Figure 19
Closed-Loop Gain vs Frequency Figure 20
Open-Loop Gain vs Temperature Figure 21
Open-Loop Output Impedance vs Frequency Figure 22
Small-Signal Overshoot vs Capacitive Load (100mV Output Step) Figure 23,Figure 24
No Phase Reversal Figure 25
Positive Overload Recovery Figure 26
Negative Overload Recovery Figure 27
Small-Signal Step Response (100mV) Figure 28,Figure 29
Large-Signal Step Response Figure 30,Figure 31
Large-Signal Settling Time (10V Positive Step) Figure 32
Large-Signal Settling Time (10V Negative Step) Figure 33
Short-Circuit Current vs Temperature Figure 34
Maximum Output Voltage vs Frequency Figure 35
Channel Separation vs Frequency Figure 36
4Copyright ©2011, Texas Instruments Incorporated
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.1
1.2
1.3
2
OffsetVoltageDrift( V/ C)m °
PercentageofAmplifiers(%)
25
20
15
10
5
0
1
DistributionTakenFrom110Amplifiers
1.5
1.7
1.9
1.8
1.6
1.4
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-100
0
100
200
300
400
500
600
700
800
900
1000
1200
OffsetVoltage( V)m
PercentageofAmplifiers(%)
16
14
12
10
8
6
4
2
0
-200
1100
DistributionTakenFrom3500Amplifiers
600
400
200
0
200
400
600
800
-
-
-
-
OffsetVoltage( V)m
-75 -50 -25 0 25 150
Temperature( C)°
50 12510075
5TypicalUnitsShown
1000
800
600
400
200
0
200
400
600
800
1000
-
-
-
-
-
V ( V)m
OS
-20 -15 -10 -5 0 5 10 15 20
V (V)
CM
V = 18.1V-
CM
10TypicalUnitsShown
10000
8000
6000
4000
2000
0
2000
4000
6000
8000
10000
-
-
-
-
-
V ( V)m
OS
15.5 16 16.5 17 17.5 18 18.5
V (V)
CM
10TypicalUnitsShown
Normal
Operation V =+18.1V
CM
350
250
150
50
50
150
250
350
-
-
-
-
V ( V)m
OS
0 2 4 6 8 16 20
V (V)
SUPPLY
V = 1.35Vto 18V
10TypicalUnitsShown
±
SUPPLY ±
18141210
OPA171-Q1
www.ti.com
SBOS556 –JUNE 2011
TYPICAL CHARACTERISTICS
VS=±18V, VCM = VS/2, RLOAD = 10kΩconnected to VS/2, and CL= 100pF, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT DISTRIBUTION
Figure 1. Figure 2.
OFFSET VOLTAGE vs TEMPERATURE OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
Figure 3. Figure 4.
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
(Upper Stage) OFFSET VOLTAGE vs POWER SUPPLY
Figure 5. Figure 6.
Copyright ©2011, Texas Instruments Incorporated 5
IB+
IB-
IOS
10000
1000
100
10
1
0
InputBiasCurrent(pA)
-75 -50 -25 0 25 150
Temperature( C)°
50 12510075
IB
IOS
18
OutputVoltage(V)
0 2 4 6 8 16
OutputCurrent(mA)
10 12 14
17
16
15
14.5
-14.5
-15
-16
-17
-18
- °40 C
+25 C°
+85 C°
+125 C°
140
120
100
80
60
40
20
0
Common-ModeRejectionRatio(dB),
Power-SupplyRejectionRatio(dB)
1 10 100 1k 10k 10M
Frequency(Hz)
100k 1M
+PSRR
-PSRR
CMRR
30
20
10
0
10
20
30
-
-
-
Common-ModeRejectionRatio( V/V)m
-75 -50 -25 0 25 150
Temperature( C)°
50 12510075
V =2.7V
S
V =4V
S
V =36V
S
OPA171-Q1
SBOS556 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VS=±18V, VCM = VS/2, RLOAD = 10kΩconnected to VS/2, and CL= 100pF, unless otherwise noted.
IBAND IOS vs COMMON-MODE VOLTAGE INPUT BIAS CURRENT vs TEMPERATURE
Figure 7. Figure 8.
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT CMRR AND PSRR vs FREQUENCY
(Maximum Supply) (Referred-to Input)
Figure 9. Figure 10.
CMRR vs TEMPERATURE PSRR vs TEMPERATURE
Figure 11. Figure 12.
6Copyright ©2011, Texas Instruments Incorporated
1 V/divm
Time(1s/div)
1000
100
10
1
VoltageNoiseDensity(nV/ )ÖHz
1 10 100 1k 10k 1M
Frequency(Hz)
100k
0.01
0.001
0.0001
0.00001
TotalHarmonicDistortion+Noise(%)
10 100 1k 10k 20k
Frequency(Hz)
TotalHarmonicDistortion+Noise(dB)
V =3V
BW=80kHz
OUT RMS
G=+1,R =10kW
L
G= 1,R =2k- W
L
-80
-100
-120
-140
0.1
0.01
0.001
0.0001
0.00001
TotalHarmonicDistortion+Noise(%)
0.01 0.1 1 10 20
OutputAmplitude(V )
RMS
-80
TotalHarmonicDistortion+Noise(dB)
BW=80kHz
G=+1,R =10kW
L
G= 1,R =2k- W
L
-100
-120
-140
0.65
0.6
0.55
0.5
0.45
0.4
0.35
I (mA)
Q
-75 -50 -25 0 25 150
Temperature( C)°
1251007550
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
I (mA)
Q
0 4 8 12 16 36
SupplyVoltage(V)
32282420
SpecifiedSupply-VoltageRange
OPA171-Q1
www.ti.com
SBOS556 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
VS=±18V, VCM = VS/2, RLOAD = 10kΩconnected to VS/2, and CL= 100pF, unless otherwise noted.
INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
0.1Hz TO 10Hz NOISE FREQUENCY
Figure 13. Figure 14.
THD+N RATIO vs FREQUENCY THD+N vs OUTPUT AMPLITUDE
Figure 15. Figure 16.
QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE
Figure 17. Figure 18.
Copyright ©2011, Texas Instruments Incorporated 7
180
135
90
45
0
45-
Gain(dB)
1 10 100 1k 10k 10M
Frequency(Hz)
1M100k
Phase
Gain
Phase( )°
180
135
90
45
0
-45
25
20
15
10
5
0
5
10
15
20
-
-
-
-
Gain(dB)
10k 100M
Frequency(Hz)
1M100k 10M
G=10
G=1
G= 1-
3
2.5
2
1.5
1
0.5
0
A ( V/V)m
OL
-75 150
Temperature( C)°
-25-50 0
5TypicalUnitsShown
125100755025
V =2.7V
S
V =4V
S
V =36V
S
1M
100k
10k
1k
100
10
1
1m
Z ( )W
O
1 10 100 1k 10k 10M
Frequency(Hz)
100k 1M
50
45
40
35
30
25
20
15
10
5
0
Overshoot(%)
0 100 200 300 400 500 600 700 800 900 1000
CapacitiveLoad(pF)
+18V
-18V
ROUT
CL
OPA171
RL
G=+1
R =0W
OUT
R =25W
OUT
R =50W
OUT
R =10kW
L
50
45
40
35
30
25
20
15
10
5
0
Overshoot(%)
0 100 200 300 400 500 600 700 800 900 1000
CapacitiveLoad(pF)
OPA171
R =
I10kW
ROUT
CL
RF=10kW
+18V
-18V
G= 1-
R =0W
OUT
R =25W
OUT
R =50W
OUT
OPA171-Q1
SBOS556 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VS=±18V, VCM = VS/2, RLOAD = 10kΩconnected to VS/2, and CL= 100pF, unless otherwise noted.
OPEN-LOOP GAIN AND PHASE vs FREQUENCY CLOSED-LOOP GAIN vs FREQUENCY
Figure 19. Figure 20.
OPEN-LOOP GAIN vs TEMPERATURE OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Figure 21. Figure 22.
SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD
(100mV Output Step) (100mV Output Step)
Figure 23. Figure 24.
8Copyright ©2011, Texas Instruments Incorporated
Output
Output
Time(100 s/div)m
5V/div
+18V
-18V
37VPP
SineWave
( 18.5V)±
OPA171
Time(5 s/div)m
5V/div
VIN
VOUT
2kW
20kW
VIN
VOUT
OPA171
G= 10-
+18V
-18V
Time(5 s/div)m
5V/div
VIN
VOUT
2kW
20kW
VIN
VOUT
OPA171
G= 10-
+18V
-18V
20mV/div
Time(1 s/div)m
+18V
-18V CL
RL
OPA171
G=+1
R =10k
C =100pF
W
L
L
Time(20 s/div)m
20mV/div
+18V
-18V
R 2kW
F=
R 2kW
I=
CL
OPA171
G= 1-
C =100pF
L
2V/div
Time(5 s/div)m
G=+1
R =10k
C =100pF
W
L
L
OPA171-Q1
www.ti.com
SBOS556 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
VS=±18V, VCM = VS/2, RLOAD = 10kΩconnected to VS/2, and CL= 100pF, unless otherwise noted.
NO PHASE REVERSAL POSITIVE OVERLOAD RECOVERY
Figure 25. Figure 26.
SMALL-SIGNAL STEP RESPONSE
NEGATIVE OVERLOAD RECOVERY (100mV)
Figure 27. Figure 28.
SMALL-SIGNAL STEP RESPONSE
(100mV) LARGE-SIGNAL STEP RESPONSE
Figure 29. Figure 30.
Copyright ©2011, Texas Instruments Incorporated 9
Time(4 s/div)m
2V/div
G= 1
R =10k
C =100pF
-
W
L
L
10
8
6
4
2
0
2
4
6
8
10
-
-
-
-
-
DFromFinalValue(mV)
0 36
Time( s)m
84 28 3224201612
12-BitSettling
( 1/2LSB= 0.024%)± ±
G= 1-
10
8
6
4
2
0
2
4
6
8
10
-
-
-
-
-
DFromFinalValue(mV)
0 36
Time( s)m
84 28 3224201612
12-BitSettling
( 1/2LSB= 0.024%)± ±
G= 1-
50
45
40
35
30
25
20
15
10
5
0
I (mA)
SC
-75 -50 -25 0 25 150
Temperature( C)°
50 125
I ,Source
SC
10075
I ,Sink
SC
15
12.5
10
7.5
5
2.5
0
OutputVoltage(V )
PP
10k 100k 1M 10M
Frequency(Hz)
V = 15V±
S
V = 5V±
S
V = 1.35V±
S
Maximumoutputvoltagewithout
slew-rateinduceddistortion.
-60
70
80
90
100
110
120
-
-
-
-
-
-
ChannelSeparation(dB)
10 100 1k 10k 100k
Frequency(Hz)
OPA171-Q1
SBOS556 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VS=±18V, VCM = VS/2, RLOAD = 10kΩconnected to VS/2, and CL= 100pF, unless otherwise noted.
LARGE-SIGNAL SETTLING TIME
LARGE-SIGNAL STEP RESPONSE (10V Positive Step)
Figure 31. Figure 32.
LARGE-SIGNAL SETTLING TIME
(10V Negative Step) SHORT-CIRCUIT CURRENT vs TEMPERATURE
Figure 33. Figure 34.
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY
Figure 35. Figure 36.
10 Copyright ©2011, Texas Instruments Incorporated
Output
Output
Time(100 s/div)m
5V/div
+18V
-18V
37VPP
SineWave
( 18.5V)±
OPA171
OPA171-Q1
www.ti.com
SBOS556 –JUNE 2011
APPLICATION INFORMATION
The OPA171-Q1 operational amplifier provides high This device can operate with full rail-to-rail input
overall performance, making it ideal for many 100mV beyond the top rail, but with reduced
general-purpose applications. The excellent offset performance within 2V of the top rail. The typical
drift of only 2µV/°C provides excellent stability over performance in this range is summarized in Table 2.
the entire temperature range. In addition, the device
offers very good overall performance with high PHASE-REVERSAL PROTECTION
CMRR, PSRR, and AOL. As with all amplifiers, The OPA171-Q1 has an internal phase-reversal
applications with noisy or high-impedance power protection. Many op amps exhibit a phase reversal
supplies require decoupling capacitors close to the when the input is driven beyond its linear
device pins. In most cases, 0.1µF capacitors are common-mode range. This condition is most often
adequate. encountered in noninverting circuits when the input is
driven beyond the specified common-mode voltage
OPERATING CHARACTERISTICS range, causing the output to reverse into the opposite
The OPA171-Q1 is specified for operation from 2.7V rail. The input of the OPAx171 prevents phase
to 36V (±1.35V to ±18V). Many of the specifications reversal with excessive common-mode voltage.
apply from –40°C to +125°C. Parameters that can Instead, the output limits into the appropriate rail. This
exhibit significant variance with regard to operating performance is shown in Figure 37.
voltage or temperature are presented in the Typical
Characteristics.
GENERAL LAYOUT GUIDELINES
For best operational performance of the device, good
printed circuit board (PCB) layout practices are
recommended. Low-loss, 0.1µF bypass capacitors
should be connected between each supply pin and
ground, placed as close to the device as possible. A
single bypass capacitor from V+ to ground is
applicable to single-supply applications.
COMMON-MODE VOLTAGE RANGE
The input common-mode voltage range of the Figure 37. No Phase Reversal
OPAx171 series extends 100mV below the negative
rail and within 2V of the top rail for normal operation.
Table 2. Typical Performance Range
PARAMETER MIN TYP MAX UNIT
Input Common-Mode Voltage (V+) –2 (V+) + 0.1 V
Offset voltage 7 mV
vs Temperature 12 µV/°C
Common-mode rejection 65 dB
Open-loop gain 60 dB
GBW 0.7 MHz
Slew rate 0.7 V/µs
Noise at f = 1kHz 30 nV/√Hz
Copyright ©2011, Texas Instruments Incorporated 11
5kW
OPA171
10mAmax
V+
VIN
VOUT
IOVERLOAD
50
45
40
35
30
25
20
15
10
5
0
Overshoot(%)
0 100 200 300 400 500 600 700 800 900 1000
CapacitiveLoad(pF)
+18V
-18V
ROUT
CL
OPA171
RL
G=+1
R =0W
OUT
R =25W
OUT
R =50W
OUT
R =10kW
L
50
45
40
35
30
25
20
15
10
5
0
Overshoot(%)
0 100 200 300 400 500 600 700 800 900 1000
CapacitiveLoad(pF)
OPA171
R =
I10kW
ROUT
CL
RF=10kW
+18V
-18V
G= 1-
R =0W
OUT
R =25W
OUT
R =50W
OUT
OPA171-Q1
SBOS556 –JUNE 2011
www.ti.com
CAPACITIVE LOAD AND STABILITY or even the output pin. Each of these different pin
functions have electrical stress limits determined by
The dynamic characteristics of the OPA171-Q1 have the voltage breakdown characteristics of the
been optimized for commonly encountered operating particular semiconductor fabrication process and
conditions. The combination of low closed-loop gain specific circuits connected to the pin. Additionally,
and high capacitive loads decreases the phase internal electrostatic discharge (ESD) protection is
margin of the amplifier and can lead to gain peaking built into these circuits to protect them from
or oscillations. As a result, heavier capacitive loads accidental ESD events both before and during
must be isolated from the output. The simplest way to product assembly.
achieve this isolation is to add a small resistor (for
example, ROUT equal to 50Ω) in series with the These ESD protection diodes also provide in-circuit,
output. Figure 38 and Figure 39 illustrate graphs of input overdrive protection, as long as the current is
small-signal overshoot versus capacitive load for limited to 10mA as stated in the Absolute Maximum
several values of ROUT. Also, refer to Applications Ratings.Figure 40 shows how a series input resistor
Bulletin AB-028 (SBOA015), available for download may be added to the driven input to limit the input
from the TI website for details of analysis techniques current. The added resistor contributes thermal noise
and application circuits. at the amplifier input and its value should be kept to a
minimum in noise-sensitive applications.
Figure 40. Input Current Protection
An ESD event produces a short duration,
high-voltage pulse that is transformed into a short
duration, high-current pulse as it discharges through
a semiconductor device. The ESD protection circuits
Figure 38. Small-Signal Overshoot versus are designed to provide a current path around the
Capacitive Load (100mV Output Step) operational amplifier core to prevent it from being
damaged. The energy absorbed by the protection
circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit,
the ESD protection components are intended to
remain inactive and not become involved in the
application circuit operation. However, circumstances
may arise where an applied voltage exceeds the
operating voltage range of a given pin. Should this
condition occur, there is a risk that some of the
internal ESD protection circuits may be biased on,
and conduct current. Any such current flow occurs
through ESD cells and rarely involves the absorption
device.
If there is an uncertainty about the ability of the
supply to absorb this current, external zener diodes
may be added to the supply pins. The zener voltage
Figure 39. Small-Signal Overshoot versus must be selected such that the diode does not turn
Capacitive Load (100mV Output Step) on during normal operation.
ELECTRICAL OVERSTRESS However, its zener voltage should be low enough so
that the zener diode conducts if the supply pin begins
Designers often ask questions about the capability of to rise above the safe operating supply voltage level.
an operational amplifier to withstand electrical
overstress. These questions tend to focus on the
device inputs, but may involve the supply voltage pins
12 Copyright ©2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 26-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA171AQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA171-Q1 :
•Catalog: OPA171
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA171AQDBVRQ1 SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Mar-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA171AQDBVRQ1 SOT-23 DBV 5 3000 202.0 201.0 28.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Mar-2012
Pack Materials-Page 2
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